Cascaded amplifier with dynamic matrix bias and signal amplification method thereof

Abstract

The invention relates to a spliced amplifier with dynamic matrix bias and a signal amplification method thereof. A cascode amplifier includes a cascode amplifier, a cascode amplifier, a dynamic matrix voltage generator, and a load. The common source amplifier includes a first metal oxide semiconductor transistor (MOST) of a first type to receive a first input signal and output a first current to a first drain node according to a substrate voltage applied to a substrate of the first MOST. The common-gate amplifier includes a second MOST of the first type for receiving the first current from the first drain node and outputting a second current to the second drain node according to the first gate voltage. The dynamic matrix voltage generator is configured to receive a first input signal and output a matrix voltage. The load is to establish a third drain voltage at the third drain node in response to a second current through the DC path between the second drain node and the third drain node.

Description

Technical Field

[0001] This disclosure document relates to amplifiers, and particularly to cascode amplifiers with dynamic body bias. Background Art

[0002] Those skilled in the art of this technology can understand the terms and basic concepts related to microelectronics used in this disclosure document, such as "voltage", "current", "signal", "differential", "single-ended", "capacitance", "inductance", "resistance", "transistor", "metal-oxide semiconductor transistor (MOST)", "P-type metal-oxide semiconductor transistor (PMOST)", "N-type metal-oxide semiconductor transistor (NMOST)", "alternating current (AC)", "direct current (DC)", "DC coupling", "AC coupling", "source", "gate", "drain", "body", "node", "ground node", "power supply node", "bias", "cascode", "common-source amplifier", "common-gate amplifier", "load", "impedance", and "cascode amplifier". When such terms and basic concepts are used in this disclosure document, they are obvious to those skilled in the art, so their details are not elaborated here.

[0003] Those skilled in the art of this technology can recognize the resistor symbol, the inductor symbol, and the MOST symbols for PMOST and NMOST, and can identify the "source" terminal, "gate" terminal, "drain" terminal, and "body" terminal of the MOST. For the sake of brevity, in the description of the MOST in this disclosure document, the "source terminal" is simplified to "source", the "gate terminal" is simplified to "gate", the "drain terminal" is simplified to "drain", and the "body terminal" is simplified to "body". The MOST has a threshold voltage and conducts when the gate-source voltage is greater than the threshold voltage; the threshold voltage of the MOST is affected by the voltage of its body, and this phenomenon is called the "body effect".

[0004] Those skilled in the art can read the schematic diagram of a circuit including resistors, capacitors, inductors, NMOSTs, and PMOSTs, and there is no need to describe in detail how the transistors, resistors, inductors, or capacitors in the schematic diagram are connected to another transistor, resistor, inductor, or capacitor.

[0005] The cascode amplifier includes a cascade composed of a common-source amplifier and a common-gate amplifier. The common-source amplifier is embodied by a first NMOST, and the common-gate amplifier is embodied by a second NMOST. The source of the first NMOST is connected to the ground node, thus embodying the common-source amplifier. The gate of the second NMOST is connected to the bias node of a substantially stable voltage, thus embodying the common-gate amplifier. The first NMOST converts the input voltage (received from its gate) into an internal current (output via its drain), and the second NMOST relays the internal current (received from its source) into an output current (output via its drain), thereby generating an output voltage across the load connected to the drain of the second NMOST. It is desirable that a change in the input voltage can cause a proportional change in the output voltage. However, in practice, the change in the output voltage may not be proportional to the change in the input voltage, especially when the change in the input voltage is large. This situation is inevitable because: First, the NMOST follows the square law, and the current at the drain is approximately proportional to the square of the difference between the gate-source voltage and the threshold voltage. Second, the NMOST is subject to channel-length modulation, where the current at the drain is modulated by the drain-source voltage.

[0006] Therefore, a method for improving the linearity of the cascode amplifier is highly desirable. Summary of the Invention

[0007] The objective of this disclosure is to use dynamic body biasing technology to improve the linearity of the cascode amplifier.

[0008] Another objective of this disclosure is to use dynamic body biasing technology to improve the power efficiency of the cascode amplifier.

[0009] In one embodiment, a cascode amplifier includes a common-source amplifier, a common-gate amplifier, a dynamic body voltage generator, and a load. The common-source amplifier includes a first metal-oxide semiconductor transistor (MOST) of a first type for receiving a first input signal and outputting a first current to a first drain node in accordance with a body voltage applied to a body of the first MOST. The common-gate amplifier includes a second MOST of the first type for receiving the first current from the first drain node and outputting a second current to a second drain node in accordance with a first gate voltage. The dynamic body voltage generator is for receiving the first input signal and outputting the body voltage. The load is for establishing a third drain voltage at a third drain node in response to the second current through a DC path between the second drain node and a third drain node. Wherein the dynamic body voltage generator includes a third MOST of a second type and a resistor, the third MOST is for outputting a dynamic current in accordance with the first input signal, and the resistor is for establishing the body voltage in response to the dynamic current. In a further embodiment, the cascode amplifier further includes a dynamic gate voltage generator for receiving the first input signal and outputting the first gate voltage.

[0010] In one embodiment, a signal amplification method includes: receiving a first input signal; converting the first input signal into a first current directed to a first drain node by using a common-source amplifier including a first MOST of a first type, wherein a source, a gate, a drain, and a body of the first MOST of the first type are respectively connected to a first DC node, the first input signal, the first drain node, and a body voltage; relaying the first current into a second current directed to a second drain node by using a first common-gate amplifier including a second MOST of the first type, wherein a source, a gate, and a drain of the second MOST of the first type are respectively connected to the first drain node, a first gate voltage, and the second drain node; adjusting the body voltage by using a third MOST of a second type configured in a common-source amplifier topology to receive an AC coupling of the first input signal and output the body voltage; and establishing a third drain voltage at the third drain node by directing the second current through a DC path to the third drain node and terminating the third drain node with a load, wherein the load includes an inductor for providing a DC coupling between the third drain node and a second DC node. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] To make the above and other objects, features, advantages and embodiments of the present disclosure more apparent and understandable, the description of the drawings is as follows:

[0012] Figure 1 A schematic diagram of a cascode amplifier shown according to an embodiment of the present disclosure document; and

[0013] Figure 2Flowchart of a signal amplification method shown according to an embodiment of the present disclosure document.

[0014] Symbol Explanation

[0015] 100: Stacked amplifier

[0016] 110: Dynamic substrate voltage generator

[0017] 111: PMOST

[0018] 112: AC coupling capacitor

[0019] 113: First resistor

[0020] 114: Second resistor

[0021] 120: Dynamic gate voltage generator

[0022] 121: Diode

[0023] 122: Resistor

[0024] 123: Capacitor

[0025] 210, 220, 230, 240, 250: Steps

[0026] C1: First capacitor

[0027] CGA1: First common-gate amplifier

[0028] CGA2: Second common-gate amplifier

[0029] CN: Neutralization capacitor

[0030] CSA1: Common-source amplifier

[0031] DL1: Dotted line

[0032] DN1: First drain node

[0033] DN2: Second drain node

[0034] DN3: Third drain node

[0035] GN1: First gate node

[0036] GN2: Second gate node

[0037] GN3: Third gate node

[0038] I1: First current

[0039] I2: Second current

[0040] I3: Third current

[0041] I b : Output current

[0042] L1: First inductor

[0043] LD1: Load

[0044] NM1: First NMOST

[0045] NM2: Second NMOST

[0046] NM3: Third NMOST

[0047] V b : Substrate voltage

[0048] V d1 : First drain voltage

[0049] V d3 : Third drain voltage

[0050] V dc1 : First DC bias node

[0051] V dc2 : Second DC bias node

[0052] V DD1 : First power supply node

[0053] V DD2 : Second power supply node

[0054] V g1 : First gate voltage

[0055] V g2 : Second gate voltage

[0056] V g3 : Third gate voltage

[0057] V i : First input signal

[0058] V ’ i : Second input signal

[0059] V SS : Ground node Detailed implementation manner

[0060] The present invention relates to a stacked amplifier. Although several exemplary embodiments that are considered to be advantageous modes of implementing the present invention are described in this specification, it should be understood that the present invention can be implemented in various ways and is not limited to the specific examples described below or the specific ways of implementing any features of such examples. In other instances, existing details are not shown or described in order to avoid obscuring various embodiments of the present invention.

[0061] In this disclosure, "DC" represents direct current, and "AC" represents alternating current. A DC voltage represents a substantially stable voltage. An AC voltage represents a voltage that varies over time in an oscillatory manner and also represents a dynamic voltage. Generally, a voltage signal includes a DC component and an AC component; the former is substantially stable and remains fixed within a specific time interval, while the latter is dynamic and can vary over time within a specific time interval. Hereinafter, for the sake of brevity, the swing of the AC component in the voltage signal is simply referred to as the "AC (alternating current) swing".

[0062] A DC node is a node with a substantially stable voltage. In this disclosure, "V DD " is a first special DC node referred to as the power supply node, and "V SS " is a second special DC node referred to as the ground node. When there are more than two power supply nodes, "V DD1 " represents the first power supply node, and "V DD2 " represents the second power supply node. The first power supply node "V DD1 " and the second power supply node "V DD2 " can have the same fixed voltage level or different fixed voltage levels.

[0063] A common-source amplifier is embodied by a MOST. This MOST is used to receive an input voltage at its gate and output an output current via its drain, where its source is connected to a DC node.

[0064] A common-gate amplifier is embodied by a MOST. This MOST is used to receive an input current at its source and output an output current via its drain, where its gate is connected to a bias node, and the voltage of this bias node is equal to a substantially fixed bias voltage.

[0065] A stacked amplifier is a cascade of a common-source amplifier and a common-gate amplifier, where the output current of the common-source amplifier is the input current of the common-gate amplifier.

[0066] A circuit is a collection of transistors, capacitors, inductors, resistors, and / or other electronic devices interconnected in a specific manner to embody a specific function. A network is a collection of one or more circuits to embody a specific function.

[0067] In this disclosure, "circuit node" is abbreviated as "node" because its meaning is clear from the perspective of microelectronics and will not cause confusion.

[0068] In this disclosure, a signal is a voltage that can change levels over time. The (voltage) level of a signal at a certain moment represents the state of the signal at that moment.

[0069] Please refer to Figure 1 , Figure 1 FIG. shows a stacked amplifier 100 according to various embodiments. As will be described below, the specific elements shown in Figure 1 are optionally employed and are not necessary for the broader embodiments of the present invention.

[0070] As Figure 1 shown, a stacked amplifier 100 according to an embodiment of the present disclosure includes: a common-source amplifier CSA1 including a first NMOST NM1 for receiving a first input signal V i and outputting a first current I1 to a first drain node DN1 according to a substrate voltage V b ; a dynamic substrate voltage generator 110 for generating a substrate voltage V i in response to the first input signal V b ; a first common-gate amplifier CGA1 including a second NMOST NM2 for receiving the first current I1 via the first drain node DN1 and outputting a second current I2 to a second drain node DN2 according to a first gate voltage V g1 at a first gate node GN1; and a load LD1 including a first inductor L1 and a first capacitor C1 connected in parallel for establishing a third drain voltage V d3 at a third drain node DN3 in response to the second current I2 passing through a DC path between the second drain node DN2 and the third drain node DN3, where the third drain voltage V d3 is the output voltage of the stacked amplifier 100.

[0071] In a first embodiment of the DC path, the third drain node DN3 is directly connected to the second drain node DN2, so the two nodes are shorted together. In other words, Figure 1The dashed line DL1 therein is a physical connection between the second drain node DN2 and the third drain node DN3. That is, the DC path includes a short circuit embedded between the second drain node DN2 and the third drain node DN3. In a second embodiment of the DC path, the dashed line DL1 is disconnected, and a second common-gate amplifier CGA2, which includes a third NMOST NM3, is added and embedded between the second drain node DN2 and the third drain node DN3 to transmit a second current I2 as a third current I3 directed to the third drain node DN3 according to a second gate voltage V g2 at the second gate node GN2.

[0072] The purpose of the dynamic substrate voltage generator 110 is to make the substrate voltage V i higher when the first input signal V b has a large AC swing. The dynamic substrate voltage generator 110 includes a PMOST 111, an AC coupling capacitor 112, a first resistor 113, and a second resistor 114. The PMOST 111 is configured in a common-source amplifier topology, where the first input signal V i is coupled to its gate at the third gate node GN3 via the AC coupling capacitor 112, the substrate voltage V b is output from its drain, and its source is connected to a first power supply node V DD1 . The first resistor 113 is used as the load of the PMOST 111. The second resistor 114 is used to provide a DC coupling between the first DC bias node V dc1 and the gate of the PMOST 111 to establish a third gate voltage V g3 , where the third gate voltage V g3 includes a DC part equal to the voltage level of the first DC bias node V dc1 and an AC part proportional to the AC part of the first input signal V i . In terms of circuit structure and function, the dynamic substrate voltage generator 110 is clear to those skilled in the art and will not be further explained in detail herein.

[0073] When the AC part of the first input signal V i is large, the third gate voltage V g3 will have a large swing, which will cause the output current I b of the PMOST 111 to have a large average level due to the current square law relationship associated with MOS transistors. Therefore, the substrate voltage V bThe average level will become relatively high, and due to the "body effect", the first NMOST NM1 has a lower threshold voltage and a higher overdrive voltage; therefore, the first NMOST NM1 will actually be severely biased into the class-A region to handle a larger input swing, and thus becomes more linear. The concepts of "class-A region" and "MOST severely biased into the class-A region can handle a larger input swing and is more linear" can be understood by those skilled in the art, and thus will not be further explained in detail here. Generally speaking, the biasing condition of the common-source amplifier CSA1 is dynamically adjusted according to the body effect based on the first input signal V i and thus when the AC swing of the first input signal V i is relatively large, the common-source amplifier CSA1 will be severely biased into the class-A region. Biasing the transistor into the severe class-A region can obtain a higher linearity at the cost of higher power consumption; however, the first NMOST NM1 will only be biased into the severe class-A region when the AC swing of the first input signal V i is relatively large, so the higher power consumption will only occur when a larger AC swing needs to be processed. Contrary to biasing the common-source amplifier CSA1 severely into the class-A region regardless of the AC swing of the first input signal V i , the common-source amplifier CSA1 will only be severely biased into the class-A region when the AC swing of the first input signal V i is relatively large, and thus a higher power supply efficiency can be achieved.

[0074] In the appended claims of the present disclosure, the output current I b is described as a "dynamic current" because its average level is dynamically adjusted according to the AC swing of the first input signal V i .

[0075] The first common-gate amplifier CGA1 is used to provide reverse isolation and reduce the feedback from the second drain node DN2 to the first drain node DN1, and when the second common-gate amplifier CGA2 is added, the reverse isolation effect can be further improved and the feedback from the third drain node DN3 to the second drain node DN2 can be reduced. The concepts of "reverse isolation" and "common-gate amplifier is good at providing reverse isolation" can be understood by those skilled in the art, and thus will not be further explained in detail here.

[0076] Figure 1The cascode amplifier 100 shown is an example of a single-ended circuit; this is merely an example and not a limitation. By adding a replicated circuit of the cascode amplifier 100 and applying input signals that are complementary to each other (where the DC parts are the same and the AC parts are inverted with respect to each other) thereto, an example of a differential circuit can be constructed. This is obvious to those skilled in the art, and thus will not be further explained in detail herein.

[0077] Please refer to Figure 1 . The purpose of the first capacitor C1 is to resonate with the first inductor L1 at the frequency of the first input signal V i to exhibit a high impedance, thereby increasing the AC swing of the third drain voltage V d3 . However, the first capacitor C1 is optionally employed, and if the parasitic capacitance at the third drain node DN3 is easily sufficient to resonate with the first inductor L1, the first capacitor C1 may not be required.

[0078] In a further embodiment, the cascode amplifier 100 includes a neutralization capacitor CN for coupling the second input signal V ’ i to the first drain node DN1, wherein the second input signal V ’ i is an inverted signal of the first input signal V i . The common-source amplifier CSA1 is an inverting amplifier that makes the first drain voltage V d1 at the first drain node DN1 an inverted signal of the first input signal V i . Since the second input signal V ’ i is an inverted signal of the first input signal V i , the phase of coupling the second input signal V ’ i to the first drain node DN1 via the neutralization capacitor CN will be in phase with the phase of amplifying the first input signal V i to the first drain node DN1 via the common-source amplifier CSA1. However, the coupling via the neutralization capacitor CN itself is linear; thus, the overall linearity is improved.

[0079] In a further embodiment, the cascode amplifier 100 further includes a dynamic gate voltage generator 120 for receiving the first input signal V i and outputting a first gate voltage V g1 . The purpose of the dynamic gate voltage generator 120 is to boost the first gate voltage V i when the AC swing of the first input signal V g1, so that the first NMOST NM1 has a large headroom at its drain to mitigate the linearity degradation caused by channel length modulation. The dynamic gate voltage generator 120 is a peak detector including a diode 121, a resistor 122, and a capacitor 123, where "V dc2 " represents the second DC bias node; the structure and function of the peak detector are well known in the art and thus will not be further explained in detail here. When the AC swing of the first input signal V i is larger, its peak voltage will be higher, and the average voltage of the first gate voltage V g1 will be higher, making the average voltage of the first drain voltage V d1 become higher, and the common-source amplifier CSA1 becomes more linear due to having a larger headroom to provide a larger AC swing.

[0080] For any given circuit including NMOSTs and / or PMOSTs, if all NMOSTs are replaced by PMOSTs, all PMOSTs are replaced by NMOSTs, all power supply nodes are replaced by ground nodes, and all ground nodes are replaced by power supply nodes, the function of the circuit will remain the same; in other words, NMOSTs and PMOSTs are replaced with each other, and power supply nodes and ground nodes are replaced with each other. Therefore, in the appended claims of this disclosure, NMOSTs and PMOSTs are not explicitly specified; instead, "the first type of MOST" and "the second type of MOST" are explicitly specified; in one embodiment, "the first type of MOST" and "the second type of MOST" represent NMOSTs and PMOSTs respectively; in another embodiment, "the first type of MOST" and "the second type of MOST" represent PMOSTs and NMOSTs respectively. Similarly, power supply nodes and ground nodes are not explicitly specified; instead, "the first DC node" and "the second DC node" are used.

[0081] As Figure 2As shown in the flowchart, the method according to an embodiment of the present disclosure document includes: (step 210) receiving a first input signal; (step 220) converting the first input signal into a first current directed to a first drain node using a common-source amplifier including a first MOST of a first type, wherein the source, gate, drain, and substrate of the first MOST of the first type are respectively connected to a first DC node, the first input signal, the first drain node, and a substrate voltage; (step 230) relaying the first current into a second current directed to a second drain node using a first common-gate amplifier including a second MOST of the first type, wherein the source, gate, and drain of the second MOST of the first type are respectively connected to the first drain node, a first gate voltage, and the second drain node; (step 240) adjusting the substrate voltage using a third MOST of a second type configured in a common-source amplifier structure to receive an AC coupling of the first input signal and output the substrate voltage; and (step 250) establishing a third drain voltage at the third drain node by directing the second current to the third drain node via a DC path and terminating the third drain node with a load (i.e., using the load as the tail end of the third drain node), wherein the load includes an inductor for providing a DC coupling between the third drain node and a second DC node).

[0082] Those skilled in the art can easily understand that various changes and modifications can be made to the devices and methods in the present disclosure document without departing from the inspiration of the present disclosure document. Therefore, the present disclosure document should not be construed as being limited only by the scope and boundaries of the appended claims.

Claims

1. A stacked amplifier, comprising: a common source amplifier comprising a first metal oxide semiconductor transistor of a first type, configured to receive a first input signal and output a first current to a first drain node according to a body voltage applied to a body of the first metal oxide semiconductor transistor of the first type; a common-gate amplifier, comprising a second metal oxide semiconductor transistor of the first type, configured to receive the first current from the first drain node and output a second current to a second drain node according to a first gate voltage; a dynamic substrate voltage generator, configured to receive the first input signal and output the substrate voltage; and a load for establishing a third drain voltage at the third drain node in response to the second current passing through a DC path between the second drain node and a third drain node, The dynamic base voltage generator includes a third metal oxide semiconductor transistor of a second type and a first resistor. The third metal oxide semiconductor transistor is used to output a dynamic current according to the first input signal, and the first resistor is used to establish the base voltage in response to the dynamic current.

2. The cascade amplifier of claim 1, wherein the load is a resonant network configured to have a high impedance at a frequency of the first input signal.

3. The cascade amplifier as claimed in claim 2, wherein the load comprises an inductor, and the inductor is used to provide a DC coupling between the third drain node and a second DC node.

4. The cascade amplifier as claimed in claim 3, further comprising a capacitor connected in parallel with the inductor.

5. The cascade amplifier as claimed in claim 1, wherein a gate of the third MOS transistor of the second type is coupled to the first input signal via an AC coupling capacitor and is DC coupled to a first bias node via a second resistor.

6. The cascaded amplifier as claimed in claim 1, wherein the DC path comprises a short circuit, and the short circuit is embedded between the second drain node and the third drain node.

7. The cascade amplifier as described in claim 1, wherein the DC path includes a second common-gate amplifier, the second common-gate amplifier includes a fourth metal oxide semiconductor transistor of the first type, and is used to relay the second current into a third current directed to the third drain node according to a second gate voltage.

8. The cascade amplifier as claimed in claim 1, further comprising a neutralizing capacitor for coupling a second input signal to the first drain node, wherein the second input signal is an inverted signal of the first input signal.

9. The cascade amplifier as claimed in claim 1, further comprising a dynamic gate voltage generator for outputting the first gate voltage according to an AC swing of the first input signal.

10. A signal amplification method, comprising: receiving a first input signal; converting the first input signal into a first current directed to a first drain node by using a common source amplifier including a first metal oxide semiconductor transistor of a first type, wherein a source, a gate, a drain and a bulk of the first metal oxide semiconductor transistor of the first type are respectively connected to a first DC node, the first input signal, the first drain node and a bulk voltage; relaying the first current into a second current directed to a second drain node by using a first common-gate amplifier including a second metal oxide semiconductor transistor of the first type, wherein a source, a gate, and a drain of the second metal oxide semiconductor transistor of the first type are connected to the first drain node, a first gate voltage, and the second drain node, respectively; adjusting the bulk voltage by using a third metal oxide semiconductor transistor of a second type configured in a common source amplifier structure to receive an AC coupling of the first input signal and output the bulk voltage; and A third drain voltage is established at the third drain node by directing the second current to a third drain node via a DC path and terminating the third drain node with a load, wherein the load includes an inductor for providing a DC coupling between the third drain node and a second DC node.

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