Coding method and communication device

Abstract

The invention provides a coding method and a communication device, mainly aims at a pre-transformation polar code, provides a plurality of modes for generating a pre-transformation code word based on a shift register, and can obtain better error correction performance of a PC-polar code. In addition, the processing modes of the message bit, the check bit and the frozen bit in the polar code are more uniform, and the description complexity is low. The output of the shift register not only supports the pre-transformed code word to be a non-system code, but also supports the pre-transformed code word to be a system code. The performance of the pre-transformation polar code is further improved through the combination of the shift registers in various forms, the tap number, the tap direction and the feedback mode.

Description

Technical Field

[0001] This application relates to the field of channel coding, and more specifically, to a coding method and a communication device. Background Art

[0002] Performing pre-transformed encoding before polar encoding can improve the code spectrum of the polar code and enhance the error correction performance of the polar code. Among them, cyclic redundancy check (CRC) encoding, parity check (PC) encoding, and convolutional encoding all belong to the upper triangular pre-transformations that can improve the code spectrum of the polar code. The pre-transformed polar code of the fifth generation (5G) system is a PC-polar code. The PC-polar code generates a pre-transformed encoding codeword based on a shift register with single-tap feedback. However, the PC parity check relationship that can be generated by this single-tap feedback shift register is simple, and the improvement of the code spectrum is limited. In addition, the turbo code of Long Term Evolution (LTE) is also a convolutional codeword generated based on a shift register. In this technology, the feedback method is single-tap feedback after reading along the taps, and the error correction performance is limited.

[0003] Therefore, how to further improve the error correction performance of the polar code is an urgent problem to be solved. Summary of the Invention

[0004] This application provides a coding method and a communication device, which can improve the error correction performance of the polar code and improve the code spectrum.

[0005] In a first aspect, a coding method is provided. This method can be executed by a first communication device, components in the first communication device (such as a processor, a chip, a chip system, a hardware circuit, etc.), or a logic module or software that can implement all or part of the functions of the first communication device. The method includes: obtaining an input sequence; performing pre-transformed encoding on the input sequence according to a shift register to obtain an output sequence; performing polar encoding on the output sequence to obtain a codeword sequence; where the shift register corresponds to at least two taps, the directions of the at least two taps are for writing, the positions of the at least two taps are determined by a pre-transformed encoding polynomial, and the coefficients of the lowest power term and the highest power term of the pre-transformed encoding polynomial are both 1; if the current position of the input sequence corresponds to a dynamic frozen bit, the output of the shift register is related to the value in the Lth register in the shift direction of the shift register, and the Lth register is the register corresponding to the highest power term of the pre-transformed encoding polynomial, and L is an integer greater than or equal to 1.

[0006] In this technical solution, the input sequence is pre-transformed and encoded according to a shift register, and the shift register has at least two taps, and the directions of the at least two taps are for writing. Since the directions of the taps are for writing, the shift register can be immediately updated based on the values on the taps. Therefore, the update of the values in the shift register has no delay, and the error correction performance of the PC-polar code can be improved.

[0007] Combined with the first aspect, in some implementation manners of the first aspect, the value in the L-th register is related to the values in the previous L-1 registers.

[0008] In this implementation manner, the taps are in a feedforward manner. The output of the shift register is related to the value in the L-th register, and the value in the L-th register is obtained by shifting the values in the previous L-1 registers, and the code has stronger checking ability. In addition, in the feedforward manner, the value in the L-th register is related to a part of the message bits before the current position in the input sequence.

[0009] Combined with the first aspect, in some implementation manners of the first aspect, if the current position of the input sequence is a message bit, the value in the first register in the shift register is updated to the exclusive OR of the value in the first register and the value of the first tap corresponding to the first register, the value of the first tap is the input of the shift register, and the first register is any register in the shift register.

[0010] Combined with the first aspect, in some implementation manners of the first aspect, the value in the L-th register is related to all the message bits before the current position in the input sequence.

[0011] In this implementation manner, the taps are in a feedback manner. The shift register has a longer memory length. Based on this shift register for pre-transformation encoding and cascading with the polar code, better code spectrum performance can be obtained.

[0012] Combined with the first aspect, in some implementation manners of the first aspect, if the current position of the input sequence is a message bit, the value of the first register in the shift register is updated to: the exclusive OR value of the value in the first register and the value of the corresponding first tap, the value of the first tap is the exclusive OR value of the feedback input value and the message bit at the current position, and the first register is any register in the shift register.

[0013] In combination with the first aspect, in some implementations of the first aspect, if the current position of the input sequence corresponds to a message bit, the output of the shift register is related to the value in the L-th register in the shift direction of the shift register; or, if the current position of the input sequence corresponds to a frozen bit, the output of the shift register is 0.

[0014] In this implementation, the pre-transform coding is a non-systematic code. Whether the current position of the input sequence is a message bit or a dynamic frozen bit, the output is from a fixed position of the shift register, such as from the last register (i.e., the L-th register) in the shift direction of the shift register. The description of message bits and dynamic frozen bits is more unified, and the description complexity is low.

[0015] In combination with the first aspect, in some implementations of the first aspect, if the current position of the input sequence corresponds to a message bit, the output of the shift register is the input of the shift register; or if the current position of the input sequence corresponds to a frozen bit, the output of the shift register is 0.

[0016] In this implementation, the pre-transform coding is a systematic code. On the basis of obtaining the beneficial technical effect that the direction of obtaining the tap is writing, the decoding complexity can also be reduced.

[0017] In combination with the first aspect, in some implementations of the first aspect, the length L of the shift register is a prime number.

[0018] In combination with the first aspect, in some implementations of the first aspect, L is 5 or 7; if L is 7, the number of taps corresponding to the shift register does not exceed 5; or, if L is 5, the number of taps corresponding to the shift register does not exceed 3.

[0019] In this implementation, the design of the length L of the shift register and the design of the number of taps corresponding to the shift register can balance the coding complexity and the error correction performance of the code.

[0020] In combination with the first aspect, in certain implementations of the first aspect, the shift register corresponds to at least two taps, the directions of the at least two taps are for writing, the positions of the at least two taps are determined by a pre-transform coding polynomial, and the coefficients of the lowest-degree term and the highest-degree term of the pre-transform coding polynomial are both 1, including: the shift register corresponds to two tap groups, and the directions of the taps in at least one of the two tap groups are for writing; the positions of the taps in the first tap group among the two tap groups are determined by a first pre-transform coding polynomial, and the positions of the taps in the second tap group among the two tap groups are determined by a second pre-transform coding polynomial; the coefficients of the lowest-degree term and the highest-degree term of each of the first pre-transform coding polynomial and the second pre-transform coding polynomial are both 1.

[0021] In this implementation, the shift register has both feed-forward taps and feedback taps. Combining feed-forward and feedback, and having the direction of at least one group of taps among the feed-forward taps and the feedback taps for writing can improve the code spectrum performance or improve the error-checking ability of the code.

[0022] In combination with the first aspect, in certain implementations of the first aspect, the directions of the taps in the first tap group are for writing, and the directions of the taps in the second tap group are for reading; if the current position of the input sequence corresponds to a message bit, the value in the first register in the shift register is updated to: the exclusive-OR value of the value in the first register and the value of the first tap corresponding to the first register, the value of the first tap is the exclusive-OR value of the feedback input and the message bit at the current position, the feedback input is the exclusive-OR value of the values of the taps corresponding to the power terms with coefficients greater than 0 in the second pre-transform coding polynomial, and the first register is any register in the shift register.

[0023] In this implementation, the shift register is of the type with feed-forward and feedback, and the feed-forward method is multi-tap writing, and the feedback method is multi-tap reading, having a larger memory length. Based on this, pre-transform coding is performed and cascaded with a polar code, which can further improve the code spectrum performance.

[0024] In combination with the first aspect, in certain implementations of the first aspect, the direction of the taps in the first tap group is write, and the direction of the taps in the second tap group is write; if the current position of the input sequence corresponds to a message bit, the value in the first register of the shift register is updated to: the XOR value of the value in the first register, the value of the first tap corresponding to the first register, and the value of the second tap, where the value of the first tap or the value of the second tap is the XOR value of the input of the shift register and the feedback input, and the feedback input is the output of the shift register, where the first tap belongs to the first tap group and the second tap belongs to the second tap group.

[0025] In this implementation, the shift register is of the type with feedforward and feedback, and the feedforward method is multi-tap write, and the feedback method is also multi-tap write. The feedback bit is used as the output bit, which has a lower correlation with the current input bit, and the pre-transformed coded word is more random.

[0026] In combination with the first aspect, in certain implementations of the first aspect, if the current position of the input sequence corresponds to a message bit, the output of the shift register is related to the value of the L-th register in the shift direction of the shift register; or, if the current position of the input sequence corresponds to a frozen bit, the output of the shift register is 0.

[0027] In this implementation, the pre-transform coding is a non-systematic code. Whether the current position of the input sequence is a message bit or a dynamic frozen bit, the output is from a fixed position of the shift register. The description of message bits and dynamic frozen bits is more unified, and the description complexity is low.

[0028] In combination with the first aspect, in certain implementations of the first aspect, if the current position of the input sequence corresponds to a message bit, the output of the shift register is the input of the shift register; or, if the current position of the input sequence corresponds to a frozen bit, the output of the shift register is 0.

[0029] In this implementation, the pre-transform coding is a systematic code. On the basis of obtaining the beneficial technical effect that the direction of the taps is write, the decoding complexity can also be reduced.

[0030] In combination with the first aspect, in certain implementations of the first aspect, the direction of the taps in the first tap group is read, and the direction of the taps in the second tap group is write; if the current position in the input sequence corresponds to a message bit, the value in the first register of the shift register is updated to: the XOR value of the value in the first register and the value of the first tap corresponding to the first register, where the first tap belongs to the second tap group, and the first register is any register in the shift register.

[0031] In this implementation, the shift register is of the type with feedforward and feedback, and the feedforward method is multi-tap readout, and the feedback method is multi-tap write. The output of the shift register is related to the values in multiple registers, and the error-checking ability is stronger.

[0032] Combined with the first aspect, in some implementations of the first aspect, if the current position of the input sequence corresponds to a message bit, the output of the shift register is related to the values of the taps in the first tap group; or, if the current position of the input sequence corresponds to a frozen bit, the output of the shift register is 0.

[0033] Combined with the first aspect, in some implementations of the first aspect, if the current position of the input sequence corresponds to a message bit, the output of the shift register is related to the values of the taps in the first tap group, and the output of the shift register is related to the values of the taps in the first tap group, including: if the current position of the input sequence corresponds to a message bit, the output of the shift register is the exclusive OR value of the values of the taps corresponding to the power terms with coefficients greater than 0 in the first pre-transform coding polynomial.

[0034] Combined with the first aspect, in some implementations of the first aspect, if the current position of the input sequence corresponds to a message bit, the output of the shift register is the input of the shift register; or, if the current position of the input sequence corresponds to a frozen bit, the output of the shift register is 0.

[0035] Combined with the first aspect, in some implementations of the first aspect, the value of the tap in the second tap group is the exclusive OR value of the input of the shift register and the feedback input, and the feedback input is the value in the L-th register in the shift direction of the shift register.

[0036] Second aspect, a coding method is provided, which can be executed by a first communication device, components in the first communication device (e.g., a processor, a chip, a chip system, a hardware circuit, etc.), or a logic module or software capable of implementing all or part of the functions of the first communication device. The method includes: obtaining an input sequence; performing pre-transform coding on the input sequence according to a shift register to obtain an output sequence; performing polar coding on the output sequence to obtain a codeword sequence; wherein, the shift register corresponds to at least two taps, the directions of the at least two taps are readout, the positions of the at least two taps are determined by a pre-transform coding polynomial, and the coefficients of the lowest power term and the highest power term of the pre-transform coding polynomial are both 1; if the current position of the input sequence corresponds to a dynamic frozen bit, the output of the shift register is related to the value in the L-th register in the shift direction of the shift register, and the L-th register is the register corresponding to the highest power of the pre-transform coding polynomial, and L is an integer greater than or equal to 1.

[0037] In the technical solution, the shift register corresponds to at least two taps, and the directions of the at least two taps are readout. When the direction of the tap is readout as opposed to being written, the readout taps XOR the values in the registers corresponding to the pre-transform coding polynomial coefficients and then use the result as the output or feedback input of the shift register. The value of the output or feedback input of the obtained shift register is the XOR value of the values in all relevant shift registers, which can improve the code spectrum and enhance the error correction performance.

[0038] Combined with the second aspect, in some implementation manners of the second aspect, the output of the shift register is the XOR value of the input of the shift register and the value of the first tap among the at least two taps, and the first tap is the tap corresponding to the power term with a coefficient greater than 0 in the pre-transform coding polynomial.

[0039] In this implementation manner, the taps corresponding to the shift register are feed-forward taps and the direction is readout. The output of the shift register is related to the value in the shift register corresponding to the pre-transform coding polynomial.

[0040] Combined with the second aspect, in some implementation manners of the second aspect, the output of the shift register is the XOR value of the input of the shift register and the feedback input, and the feedback input is the XOR value of the at least two taps.

[0041] In this implementation manner, the taps corresponding to the shift register are feedback taps and the direction is readout. The feedback input of the shift register is related to the value in the shift register corresponding to the pre-transform coding polynomial. The information of the feedback input is more comprehensive than the case of the writing direction, which can improve the code spectrum.

[0042] In combination with the second aspect, in some implementations of the second aspect, the shift register corresponds to at least two taps, the directions of the at least two taps are for reading, the at least two taps are determined by a pre-transform coding polynomial, and the coefficients of the lowest power term and the highest power term of the pre-transform coding polynomial are both 1, including:

[0043] The shift register corresponds to two tap groups, and the directions of the taps in the two tap groups are both for reading; the positions of the taps in the first tap group of the two tap groups are determined by a first pre-transform coding polynomial, and the positions of the taps in the second tap group of the two tap groups are determined by a second pre-transform coding polynomial; the coefficients of the lowest power term and the highest power term of each of the first pre-transform coding polynomial and the second pre-transform coding polynomial are both 1;

[0044] Moreover, the output of the shift register is the exclusive OR value of the first input and the values of the taps in the first tap group; the first input is the exclusive OR value of the input of the shift register and the feedback input, and the feedback input is the exclusive OR value of the taps in the second tap group.

[0045] In this implementation, the taps corresponding to the shift register include feedforward taps and feedback taps, and the directions of the taps are both for reading. The feedback input and output values of the shift register are both the results of synthesizing the values in the shift register corresponding to the current taps, which can improve the code spectrum.

[0046] In a third aspect, a communication device is provided, and the communication device has the function of implementing the method of the first aspect or the second aspect, or the method in any possible implementation manner of the first aspect or the second aspect. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more units corresponding to the above functions.

[0047] In a fourth aspect, the present application provides a communication device, including at least one processor, the at least one processor is coupled to at least one memory, the at least one memory is used to store a computer program or instruction, and the at least one processor is used to call and run the computer program or instruction from the at least one memory, so that the communication device executes the method of the first aspect or any possible implementation manner thereof, or executes the method of the second aspect or any possible implementation manner thereof.

[0048] Fifth aspect, the present application provides a communication device, including a communication interface and a circuit. The communication interface is configured to receive an input sequence and input the input sequence into the circuit; the circuit is configured to perform pre-transform coding on the input sequence to obtain an output sequence; the communication interface is further configured to output the output sequence. Optionally, the circuit may be configured to perform polar coding on the output sequence to obtain a codeword sequence. At this time, the communication interface is configured to output the codeword sequence.

[0049] As an example, the communication devices in the third aspect to the fifth aspect are coding devices, such as encoders.

[0050] Sixth aspect, the present application provides a computer-readable storage medium, in which computer program code or instructions are stored. When the computer instructions are run on a computer, the methods in the first aspect or any possible implementation manner thereof are implemented, or the methods in the second aspect or any possible implementation manner thereof are implemented.

[0051] Seventh aspect, the present application provides a computer program product, which includes computer program code or instructions. When the computer program code or instructions are run on a computer, the methods in the first aspect or any possible implementation manner thereof are implemented, or the methods in the second aspect or any possible implementation manner thereof are implemented.

[0052] Eighth aspect, the present application provides a wireless communication system, including a communication device in any one of the third aspect to the fifth aspect. Description of the Drawings

[0053] Figure 1 Schematic diagram of a single-tap feedback shift register adopted by 5G polar.

[0054] Figure 2 Schematic diagram of the communication system process.

[0055] Figure 3 Schematic flowchart of the coding method provided by the present application.

[0056] Figure 4 Schematic diagram of the pre-transform coding output of non-systematic code for feedforward poly RSB RHS, right shift, and writing from taps.

[0057] Figure 5 Another equivalent schematic diagram of the pre-transform coding output of non-systematic code for feedforward poly RSB RHS, right shift, and writing from taps.

[0058] Figure 6Schematic diagram of the pre-transform coding output with feed-forward poly MSB RHS, right shift, and writing from taps being the systematic code.

[0059] Figure 7 Schematic diagram of the shift register with feedback poly MSB RHS, right shift, and writing from taps.

[0060] Figure 8 Schematic diagram of the shift register with feed-forward taps for writing and feedback taps for reading.

[0061] Figure 9 Schematic diagram of the shift register with feed-forward taps for reading and feedback taps for writing.

[0062] Figure 10 Shift register with both feed-forward taps and feedback taps for writing.

[0063] Figure 11 Schematic diagram of the shift register with feed-forward taps for reading.

[0064] Figure 12 Schematic diagram of the shift register with feedback taps for reading.

[0065] Figure 13 Schematic diagram of the shift register with both feed-forward taps and feedback taps in the direction of reading.

[0066] Figures 14 to 22 Performance simulation diagram of various shift registers provided by this application.

[0067] Figure 23 Schematic structural diagram of a communication device provided by this application.

[0068] Figure 24 Schematic structural diagram of another communication device provided by this application.

[0069] Figure 25 Schematic structural diagram of yet another communication device provided by this application. Specific implementation manners

[0070] Next, the technical solutions in this application will be described in conjunction with the accompanying drawings.

[0071] To facilitate the understanding of the technical solutions in this application, relevant concepts or technologies involved in the embodiments will be briefly introduced first.

[0072] Performing upper triangular pre-transform coding before polar coding can improve the code spectrum of the polar code and enhance the error correction performance of the polar code. CRC coding, PC coding, and convolutional coding all belong to this type of upper triangular pre-transform that can improve the code spectrum of the polar code.

[0073] In 5G, when 12 ≤ k ≤ 19, the control channel coding adopts the combination of PC coding and CRC coding as the pre-transform coding strategy, where k is the information length. When k ≥ 20, CRC coding is adopted as the pre-transform coding strategy to further improve the performance of the Polar code.

[0074] Figure 1 It is a schematic diagram of the shift register adopted by PC-polar in NR. The NR PC-polar code uses a shift register with a length of 5 to implement the pre-transform coding, as Figure 1 shown. If the current position is a message bit, after XORing the current bit with the value in the leftmost shift register, store it in the leftmost shift register, and use the currently input message bit as the bit at the current position, then the register circulates and shifts; if the current position is a parity bit, take out the value in the leftmost shift register as the parity bit, then the register circulates and shifts to the left; if the current position is a frozen bit, directly output zero as the bit at the current position, then the register circulates and shifts to the left.

[0075] The pseudocode and its annotations for pre-transform polar coding based on the shift register in the NR standard are as follows:

[0076]

[0077] The pre-transformed codeword u is then subjected to polar coding to obtain the output d = [d0 d1 d2... d N-1 , d = uG N .

[0078] As described above, the PC-polar code in the NR standard generates the pre-transform coding codeword based on a single-tap feedback shift register. Among them, the form of the shift register is a feedback shift register; the direction of the tap is for writing; the number of taps is single-tap; the shift direction of the shift register is to the left; the positions of the feedback tap and the output tap are both at the end (the leftmost) of the moving direction; and the shift register input bit can only be used at the message position; when the current position is the parity position, the shift register output bit is used. The moving timing logic of the shift register is to read at time t and write at time t + 1. The PC check relationship that such a single-tap feedback shift register can generate is simple, and the improvement of the code spectrum is limited. In addition, the processing methods of message bits, parity bits, and frozen bits are not unified, and the description complexity is high.

[0079] The LTE-turbo code also uses a shift register to generate the convolutional codeword. However, this coding method is independently used as a channel coding strategy, without cascaded coding with the polar code, and the error correction performance directly used for the pre-transform coding of the polar code is uncertain.

[0080] To this end, the present application provides an encoding method. Specifically for pre-transformed polar codes, multiple ways of generating pre-transformed codewords based on shift registers are proposed, which can achieve better error correction performance than NR PC-polar codes. In addition, the processing methods for message bits, parity bits, and frozen bits in polar codes are more unified, and the description complexity is low. The output of the shift register supports both non-systematic pre-transformed codewords and systematic transformed codewords. Multiple forms of shift registers and combinations of tap numbers, tap directions, and feedback methods further improve the performance of pre-transformed polar codes.

[0081] Figure 2 It is a schematic diagram of the communication system process. As shown in Figure 2 , the technical solution of the present application mainly relates to the part of channel coding. Channel coding is located between source coding and modulation. It is responsible for channel encoding the bits generated by the source, and after modulation, the transmitting end sends the modulated symbols through a noisy channel to the receiving end. After demodulation at the receiving end, channel decoding is performed. Channel decoding is located between demodulation and source decoding and is responsible for recovering the source bit stream.

[0082] Figure 3 It is a schematic flowchart of the encoding method 300 provided by the present application. The method 300 can be executed by a first communication device, components in the first communication device (such as a chip, a chip system, or a circuit, etc.), or a logic module or software that can implement all or part of the functions of the first communication device. As an example, the first communication device can be an encoding device. The following will be described by taking the encoding device as an example.

[0083] 310. The encoding device obtains an input sequence.

[0084] 320. The encoding device performs pre-transformed encoding on the input sequence according to the shift register to obtain an output sequence.

[0085] Here, the input sequence refers to the input sequence of the pre-transformed encoding, and the output sequence refers to the output sequence of the pre-transformed encoding.

[0086] 330. The encoding device performs polar encoding on the output sequence to obtain a codeword sequence.

[0087] The encoding device further performs polar encoding on the output sequence of the pre-transformed encoding. Through steps 310 to 330, the encoding device performs cascaded encoding of pre-transformed encoding and polar encoding to obtain a codeword sequence.

[0088] Among them, the pre-transform coding is performed based on a shift register. The shift register corresponds to at least two taps, the directions of the at least two taps are for writing, the positions of the at least two taps are determined by a pre-transform coding polynomial, and the coefficients of the lowest power term and the highest power term of the pre-transform coding polynomial are both 1. If the current position of the input sequence corresponds to a dynamic frozen bit, the output of the shift register is related to the value in the L-th register in the shift direction of the shift register. Among them, the L-th register is the register corresponding to the highest power term of the pre-transform coding polynomial, and L is an integer greater than or equal to 1.

[0089] The length of the shift register is L, and L generally equals the highest power of the pre-transform coding polynomial. For example, if the highest power of the pre-transform coding polynomial is 1, at this time, L = 1, and there is only one register. For another example, if the pre-transform coding polynomial is 1 + D + D 3 , the highest power of the pre-transform coding polynomial is 3, at this time, L = 3, so there are three registers. Among them, D corresponds to the first register, and D 3 corresponds to the third register. It should be understood that D 2 corresponds to the second register, but since the coefficient of D 2 in this pre-coding polynomial is 0, therefore, the tap corresponding to the second register does not exist. Regarding the taps corresponding to the shift register (such as read taps and / or write taps), they will be described in the following embodiments for the specific structure of the shift register. In the pseudo-code provided in the following embodiments, it is assumed that the highest power of the pre-transform coding polynomial is L, so there are L shift registers. Among them, y0 represents the value in the first register, and y1 represents the value in the second register. And so on, y L-1 represents the value in the L-th register.

[0090] In addition, the shift register corresponds to at least two taps. When the at least two taps are two taps, they should be the taps corresponding to the lowest power term and the highest power term respectively.

[0091] In the embodiments of the present application, L is a prime number. As an example, L equals 5 or 7. If L equals 7, the number of taps (feed-forward taps or feedback taps) corresponding to the shift register does not exceed 5. If L equals 5, the number of taps (feed-forward taps or feedback taps) corresponding to the shift register does not exceed 3. It should be understood that if the shift register is of the type with both feed-forward and feedback, when L equals 7, the number of feed-forward taps and feedback taps respectively does not exceed 5; if L equals 5, the number of feed-forward taps and feedback taps respectively does not exceed 3. The design of the value of L and the number of taps is to balance the pre-transform coding complexity and the decoding performance. The description of the number of taps is also applicable in the following embodiments, and will not be repeated below.

[0092] In addition, the dynamic freezing bit may refer to a check bit.

[0093] In method 300, at least two taps corresponding to the shift register may correspond to a pre-transform coding polynomial, such as a feed-forward polynomial or a feedback polynomial; alternatively, the at least two taps correspond to two pre-transform coding polynomials, such as a feed-forward polynomial and a feedback polynomial. Specific examples are described below.

[0094] In addition, in the embodiments of the present application, the shift direction of the shift register may be left shift or right shift, which is not limited. In the following embodiments, right shift is used as an example for illustration.

[0095] In the embodiments of the present application, the pre-transform coding polynomial takes the poly polynomial as an example, and the most significant bit (MSB) of the poly polynomial is located on the right hand side (RHS) of the polynomial, that is, poly MSB RHS. Alternatively, the poly polynomial may also have the most significant bit located on the left hand side (LHS), poly MSB LHS. In the following embodiments, poly MSB RHS is used as an example for illustration.

[0096] Example 1

[0097] Feed-forward + poly MSB RHS + right shift + write from tap

[0098] Figure 4 FIG. is a schematic diagram of the pre-transform coding output that is non-systematic for feed-forward poly MSB RHS, right shift, and write from tap.

[0099] The sequence of the pre-transform input (simplified as the input sequence in the embodiment) is the message sequence v0, v1, v2,..., v to be encoded K-1 , and the output sequence is u0, u1, u2,..., u N-1 , N is the length of the polar code mother code, and the relationship between the input sequence and the output sequence is determined according to the shift register and the pre-transform coding polynomial.

[0100] As Figure 4 , in this example, the structure of the pre-transform coding is a feed-forward shift register, the number of registers is L, the tap positions are determined according to the polynomial g(D) = 1 + g1D + g2D 2 +... + g m D m is determined, and the tap direction is write. The number L of the shift registers generally equals the highest power of the polynomial g(D). For example, the polynomial g(D) = 1 + D + D 3, the polynomial coefficients are g0 = 1, g1 = 1, g2 = 0, g3 = 1 respectively, the highest power m = 3, and the number L of corresponding registers is also equal to 3.

[0101] From the perspective of timing, g0 corresponds to the tap at the current moment, g1 corresponds to the tap at the moment 1 before the current moment, that is, the moment after passing through one register; g2 corresponds to the tap at the moment 2 before the current moment, that is, the moment after passing through two registers; similarly, gm corresponds to the tap at the moment after passing through m registers. In the feedforward shift register, represents the exclusive OR operation in the binary field, represents the binary switch, and the coefficient g of the polynomial g(D) i when taking 0, is closed, indicating that there is no tap at the i-th moment; otherwise is open, indicating that there is a tap at the i-th moment.

[0102] Figure 4 The structure shown in is the pre-transform coding as a non-systematic code. It can be seen that if the pre-transform coding is a non-systematic code, the output of the shift register has nothing to do with the set to which the current position of the input sequence belongs. Specifically, regardless of whether the current position belongs to the message bit set or the dynamic frozen bit set, the output of the shift register is read from the last register in the shift direction of the shift register.

[0103] As described above, the length of the shift register is L, so the last register in the shift direction is the L-th register. Therefore, if the current position of the input sequence corresponds to the message bit or the dynamic frozen bit set, the output of the shift register is related to the value in the L-th register in the shift direction of the shift register. The value in the L-th register is obtained by right-shifting the values in the first register to the (L - 1)-th register. In addition, if the current position of the input sequence corresponds to the frozen bit, the output of the shift register is 0.

[0104] If the pre-transform coding uses a non-systematic code, although the decoding complexity of the shift register is slightly higher, the output of the shift register is more unified and the description complexity is lower.

[0105] Another structure equivalent to the pre-transform coding structure in Figure 4 is shown in Figure 5 as shown. Figure 5 It is another schematic diagram of the pre-transform coding output as a non-systematic code with feedforward as poly MSBRHS, right-shifting, and writing from the tap. It should be understood that Figure 5 and Figure 4 The pre-transform coding processes shown are essentially equivalent and will not be elaborated.

[0106] Figure 6Schematic diagram of the pre-transform coding output that is a feedforward poly MSB RHS, right-shifted, and written from the taps, which is a systematic code.

[0107] If the pre-transform coding is a systematic code, the output of the shift register is related to the set to which the current position of the input sequence belongs. Specifically, if the current position belongs to the message bit set, the output of the shift register is the input at the current position; if the current position belongs to the dynamic frozen bit set, the output of the shift register is read from the last register in the shift direction of the shift register.

[0108] Before starting the coding, the values in the L shift registers need to be initialized. For example, the value of each register is initialized to 0.

[0109] In the case where the pre-transform coding is a non-systematic code or a systematic code, if the current position of the input sequence is a frozen bit (such as the positions of puncturing and shortening), the output of the shift register is 0.

[0110] In Example 1, for the case of a non-systematic code, the pseudocode is as follows:

[0111]

[0112]

[0113] In Example 1, for the case of a systematic code, the pseudocode is as follows:

[0114]

[0115] It can be seen from the above pseudocode that in Example 1, if the current position of the input sequence corresponds to a message bit, the value in the first register of the shift register is updated to: the exclusive OR value of the value in the first register and the value of the first tap corresponding to the first register. Among them, the value of the first tap is the input of the shift register. In the feedforward mode of Example 1, the input of the shift register is also the message bit at the current position. Here, the first register can refer to any one of the registers in the first register.

[0116] In the above pseudocode, the process of obtaining the message bit set I, the dynamic frozen (DF) bit set, and the positions of the frozen bits (such as puncturing or shortening) is as follows:

[0117] (1) Obtain the reliability sequence of the mother code length and perform rate matching, starting from remove the positions of puncturing and / or shortening to obtain the reliability sequence after rate matching whose length is N minus the number of punctured bits and / or shortened bits.

[0118] For example, the mother code length N = 32, Rate matching requires puncturing 2 bits, and the length of the reliability sequence after puncturing is 30.

[0119] (2) Select the positions with the highest reliability in the sequence and denote them as the set where K represents the information bit length. is a construction parameter required for selecting message bits, indicating the number of bits sacrificing reliability when selecting message bits, or in other words, the number of pre-frozen bits.

[0120] For example, K = 11, Select the positions with the highest reliability in the reliability sequence to obtain the set

[0121] (3) The remaining positions in the sequence form the frozen bit set F.

[0122] For example, the frozen bit set F = {3, 4, 5, 6, 7, 8, 9, 17, 10, 18, 11, 19, 13, 21, 25}, and the length is 15.

[0123] (4) Calculate the minimum row weight in the set and denote it as w min , then freeze at most positions with row weight equal to w in the set min in descending order of reliability. If the number of positions with row weight equal to w in the set min is less than , then continue to pre-freeze at positions with row weight equal to 2w min until there are positions pre-frozen in the set as PC bits.

[0124] For example, the minimum row weight of is 8, and the positions with row weight 8 and the highest reliability in

[0125] (5) Obtain the dynamic frozen bit set DF, where the set DF is the set formed by adding the PC positions to the set F.

[0126] The set DF = {3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 17, 18, 19, 21, 23, 25, 26, 27, 29}, with a length of 19.

[0127] (6) Obtain the message bit set I, where the message bit set is the set after removing the set DF, with a size of K.

[0128] I = {12, 20, 14, 15, 22, 16, 24, 28, 30, 31, 32}.

[0129] The process of obtaining the message bit set I, the dynamic frozen bit set DF, and the frozen bit set DF provided here is applicable in other embodiments below and will not be repeated hereinafter.

[0130] In Example 1, the type of the shift register is the feedforward type, and the feedforward method is multi-tap writing, where the number of taps (or feedforward taps) is greater than or equal to 1, and the shift register outputs at the end of its shift direction.

[0131] In addition, as introduced in Example 1, there is no restriction on the rule of how to use the shift register to output bits in this example. For example, it can be read from the shift register when the current position is the message position and the dynamic frozen position (in the case of non-systematic code after pre-transform coding), or it can be read from the register only when the current position is the dynamic frozen position (in the case of systematic code for pre-transform coding). Therefore, the codeword after pre-transform coding can be a systematic code or a non-systematic code. In the following examples, non-systematic code is used as an example for illustration.

[0132] Example 2

[0133] Feedback + poly MSB RHS + right shift + write from taps

[0134] Figure 7 Schematic diagram of a multi-tap shift register with feedback.

[0135] In this example, the input sequence of the pre-transform coding is the message sequence to be encoded v0, v1, v2,..., v K-1 , and the output sequence is u0, u1, u2,..., u N-1 , where N is the length of the polar code mother code, and the relationship between the input sequence and the output sequence is determined according to the shift register and the polynomial. The structure of the pre-transform coding is a shift register with feedback, the number of registers is L, and the tap positions are determined according to the polynomial q(D) = 1 + q1D + q2D 2 +...+ q m D mIt is determined that the tap direction is for writing. The number L of shift registers generally equals the highest power of the polynomial q(D). For example, for the polynomial q(D) = 1 + D 2 + D 3 , the polynomial coefficients are q0 = 1, q1 = 0, q2 = 1, q3 = 1 respectively, the highest power m = 3, and the number L of the corresponding registers also equals 3.

[0136] Looking at the timing, q0 corresponds to the tap at the current moment; q1 corresponds to the tap at 1 moment before the current moment; q2 corresponds to the tap at 2 moments before the current moment; similarly, q m corresponds to the tap at the moment after passing through m registers. In the shift register, represents the exclusive OR operation over the binary field, represents the binary switch. When the coefficient q i of the polynomial q(D) takes 0, it is closed, indicating that there is no tap at the i-th moment; otherwise it is open, indicating that there is a tap at the i-th moment.

[0137] In Example 2, parameters are used in the process of obtaining the message bit set I, the dynamic frozen bit set DF, and the positions of the frozen bits (such as shortening or puncturing). This parameter The specific values in Example 2 can refer to one or more groups of values shown in Table 1 below.

[0138] Below is also given a pre-transform coding polynomial in Example 2. This pre-transform coding polynomial can be given in the form of Table 2.

[0139] In Table 1 and Table 2, the parameter E is involved, representing the transmitted code length, which is the code length after rate matching. Specifically, it can refer to the length of the sequence to be decoded obtained in the decoding device after the encoding device performs operations such as polar coding, rate matching, modulation, or frequency conversion on the message bits and then transmits them through the wireless transmission environment. Among them, in Table 1 or Table 2, "-1" means: when the current K, the situation corresponding to E is meaningless. The pre-transform coding polynomial taking 0 means not performing the pre-transform coding operation.

[0140] The following Table 1 and Table 2 describe or store in tabular form multiple groups of corresponding relationships of the pre-transform coding polynomials under different K and E. It can be understood that in specific implementations, there can be other description or storage forms, and it may not be necessary to have all groups of corresponding relationships. In one implementation, it can include one or several groups of corresponding relationships in Table 1 or 2 below. For example, it includes the corresponding relationships of the first 16 rows in Table 1. The following Table 1 and Table 2 describe or store in tabular form multiple groups of corresponding relationships of the pre-transform coding polynomials under different K and E. It can be understood that in specific implementations, there can be other description or storage forms, and it may not be necessary to have all groups of corresponding relationships. In one implementation, it can include one or several groups of corresponding relationships in Table 1 or 2 below. For example, it includes the corresponding relationships of the first 16 rows in Table 1.

[0141] Table 1

[0142]

[0143]

[0144] Table 2

[0145]

[0146] The values of K from 1 to 16 are given in Table 1. Since the code rate R = K / E is usually less than 1, the value of E is usually greater than K. In addition, if the length of the mother code is 32, the value of E is less than or equal to 32. In practice, considering the case of rate matching with repetition, the value of E can also be greater than 32. However, for the ultra-short code, the length of the mother code corresponding to E is less than or equal to 32. Therefore, in this application, the values of E from K + 1 to 32 (so the values of E are from 2 to 32) are taken as examples. The values of K from 1 to 16 and the corresponding PC polynomials for the values of E from 2 to 32 are given in Table 1.

[0147] Determine the Figure 7 tap q0 to q m in Example 2 according to the PC polynomial. The specific method is as follows: Convert PCpoly from decimal to binary sequence, q m is on the rightmost side, q0 is on the leftmost side, and take the values of q0 to q m to determine the switch of the tap. For example, if PC poly = 97, its corresponding binary sequence is [1000011], from the highest bit to the lowest bit, q6 = 1, q5 = 1, q4 = 0, q3 = 0, q2 = 0, q1 = 0, q0 = 1.

[0148] Among them, q4 to q1 are all zero, indicating that there is no write tap at the moments corresponding to q4 to q1. And there are write taps at the current moment corresponding to q0 and the moments corresponding to q6 to q5. Therefore, at the moments corresponding to these coefficients equal to 1, the value written on the write tap will be XORed with the value in the corresponding register and then written back to the register.

[0149] PC poly = 97 is one of the polynomials with a relatively high occurrence frequency among the numerous PC polynomials selected based on the technical solution of this application. Considering that a finite number of PC polynomials are used to be compatible with various situations, PCpoly = 97 can be used as the PC polynomial.

[0150] In one implementation, the pre-transform coding in Example 2 is a non-systematic code, such as Figure 7As shown. If the pre-transform coding is a non-systematic code, the output of the shift register is independent of the set to which the current position of the input sequence belongs. Specifically, regardless of whether the current position belongs to the message bit set or the dynamic frozen bit set, the output of the shift register is read from the last register in the shift direction of the shift register. This last register is also the L-th register in the shift direction. In addition, in Example 2, due to the introduction of feedback, the value in the L-th register is related to the message bits before the current position in the input sequence.

[0151] In another implementation, the pre-transform coding in Example 2 can be a systematic code. If the pre-transform coding is a systematic code, the output of the shift register is related to the set to which the current position of the input sequence belongs. Specifically, if the current position corresponds to a message bit, the output of the shift register is the input of the shift register, that is, the output of the shift register is the message bit at the current position; if the current position corresponds to a frozen bit, the output of the shift register is 0.

[0152] The pseudocode of Example 2 is as follows:

[0153]

[0154] It can be seen from the above pseudocode that in Example 2, if the current position of the input sequence corresponds to a message bit, the value in the first register in the shift register is updated to: the exclusive OR value of the value in the first register and the value of the first tap corresponding to the first register. Among them, the value of the first tap is the exclusive OR value of the feedback input of the shift register and the message bit at the current position. The first register can refer to any register in the shift register. Among them, the first tap corresponds to Figure 7 any one of the write taps ( Figure 7 shows the structure of the shift register with q0 = 1). For example, q0 to q m each correspond to a write tap (since q0 = 1, the tap corresponding to q0 is not shown in the form of a binary switch in Figure 7 , which is equivalent to the write tap at the current moment corresponding to q0 existing). According to the examples in Table 1 and Table 2 above, the coefficients of some terms of the pre-transform coding polynomial may be zero, and a zero coefficient indicates that there is no write tap at the corresponding moment. For example, in the example of the above PC poly = 97, taking poly RHS as an example, q m is on the far right, q0 is on the far left, and the binary sequence corresponding to 97 is [1000011]. Therefore, q6 = 1, q5 = 1, q4 = 0, q3 = 0, q2 = 0, q1 = 0, q0 = 1. It can be seen that q4 to q1 are all zero, so there is no write tap at the moments corresponding to q4 to q1.

[0155] It can be seen that the type of the shift register in Example 2 is feedback, and the feedback method is multi-tap writing. The number of feedback taps is greater than or equal to 1. The output of the shift register is at the rightmost side in the shift direction of the shift register. For example, Figure 7 the value of the end register shown in

[0156] is the exclusive OR value of the feedback input. Compared with Example 1, the register in Example 2 has a larger memory length, and has better performance in enhancing the code spectrum after the pre-transform coding and the polar code are cascaded.

[0157] The present application also provides an example in which at least two taps corresponding to the shift register come from two tap groups, which can also improve the code spectrum performance.

[0158] In the example involving two tap groups, the direction of at least one of the taps in the two tap groups is writing. For example, the direction of the taps in one of the two tap groups is writing, or the direction of the taps in both groups is writing. Wherein, the two tap groups include a first tap group and a second tap group. The positions of the taps in the first tap group are determined by a first pre-transform coding polynomial, and the positions of the taps in the second tap group are determined by a second pre-transform coding polynomial. In addition, the coefficients of the lowest power term and the highest power term of each of the first pre-transform coding polynomial and the second pre-transform coding polynomial are both 1.

[0159] The implementation of the two tap groups will be described below in conjunction with some specific examples.

[0160] Example 3

[0161] Feedforward tap writing + feedback tap reading + poly MSB RHS + right shift

[0162] Figure 8 is a schematic diagram of a shift register with feedforward taps for writing and feedback taps for reading. As Figure 8 , the direction of the taps in the first tap group is writing, and the direction of the taps in the second tap group is reading. The taps in the first tap group are feedforward taps, and the positions of the feedforward taps are determined by the first pre-transform coding polynomial g(D) = 1 + g1D + g2D 2 +... + g m D m determined. In this example, the first pre-transform coding polynomial can also be referred to as a feedforward polynomial. The taps in the second tap group are feedback taps, and the positions of the feedback taps are determined by the second pre-transform coding polynomial q(D) = 1 + q1D + q2D2 +...+q m D m Sure.

[0163] It can be seen that the structure of the pre-transform coding is a shift register with feedback taps and feedforward taps. In this example, the length L of the shift register can be equal to the maximum of the power of the feedforward polynomial g(D) and the feedback polynomial q(D). For example, the feedback polynomial q(D) = 1 + D 2 +D 3 , the polynomial coefficients are q0=1, q1=0, q2=1, q3=1, and the highest power is 3; the feedforward polynomial g(D)=1+D+D 5 , the polynomial coefficients are g0=1, g1=1, g2=0, g3=0, g4=0, g5=1, and the highest power is 5, then the length of the shift register L=5.

[0164] From the timing point of view, q0 (or g0) corresponds to the tap at the current moment, q1 (or g1) corresponds to the tap at one moment before the current moment; q2 (or g2) corresponds to the tap at two moments before the current moment; similarly, q m (or g m ) corresponds to the tap after passing through m registers. represents the exclusive-or operation on a binary field, For a binary switch, the polynomial q(D) = 1 + q1D + q2D 2 +...+q m D m The coefficient q i When 0 is taken, is off (when there is no tap at the i-th moment), otherwise is open (there is a tap at the i-th moment), and the coefficients of the polynomial g(D) have similar meanings and are not repeated here.

[0165] Similarly, the input sequence of the pre-transform coding is the message sequence to be encoded v0, v1, v2, ..., v K-1 , the output sequence is u0, u1, u2, ..., u N-1 , N is the mother code length of the polar code. The relationship between the input sequence and the output sequence is determined by the shift register and the feedback polynomial q(D) and the feedforward polynomial g(D).

[0166] Before starting encoding, the values ​​in the L shift registers need to be initialized, for example, the value of each register is initialized to 0.

[0167] In one implementation, the pre-transform coding is a non-systematic code. In this case, the output of the shift register is independent of the set to which the current position of the input sequence belongs. Specifically, regardless of whether the current position belongs to the message bits, the output is taken from a fixed position in the shift register. For example, the output is taken from the last register in the shift direction of the shift register, as shown in Figure 8 the u shown in i = z i .

[0168] In another implementation, the pre-transform coding is a systematic code. In this case, the output of the shift register is related to the set to which the current position of the input sequence belongs. For example, if the current position of the input sequence belongs to the set of message bits, the output of the pre-transform coding is the input of the pre-transform coding, u i = v i . If the current position of the input sequence belongs to the set of dynamic frozen bits, the value read from the last register in the shift direction of the shift register is used as the output of the pre-transform coding, u i = z i .

[0169] For either non-systematic or systematic codes, if the current position of the input sequence corresponds to a frozen bit, the output of the pre-transform coding is 0.

[0170] The pseudo-code for Example 3 is as follows:

[0171]

[0172] As can be seen from the pseudo-code, if the direction of the taps in the first tap group is write, the direction of the taps in the second tap group is read, and the current position of the input sequence corresponds to a message bit, the value in the first register in the shift register is updated to: the exclusive OR value of the value in the first register and the value of the first tap corresponding to the first register. Among them, the value of the first tap is the exclusive OR value of the feedback input of the shift register and the message bit at the current position. The feedback input of the shift register is the exclusive OR value of the values of the taps corresponding to the power terms with coefficients greater than 0 in the second pre-transform coding polynomial. The first register is any register in the shift register.

[0173] Compared with Example 2, Example 3 adds feedforward on the basis of feedback, and changes the direction of the feedback taps in Example 2, with a larger memory length, and has a better code spectrum enhancement effect after cascading the pre-transform coding and the polar code.

[0174] Example 4

[0175] Feedforward reads from the taps, feedback writes to the taps, polyMSB RHS+ right shift

[0176] Figure 9Figure 1 is a schematic diagram of a shift register with a feedforward tap for reading and a feedback tap for writing. Figure 9 The taps in the first tap group are in the direction of reading, and the taps in the second tap group are in the direction of writing. The taps in the first tap group are feedforward taps, and the positions of the feedforward taps are determined by the first pre-transform coding polynomial g(D)=1+g1D+g2D 2 +...+g m D m In this example, the first pre-transform coding polynomial can also be called a feedforward polynomial. The taps in the second tap group are feedback taps, and the position of the feedback taps is determined by the second pre-transform coding polynomial q(D)=1+q1D+q2D 2 +...+q m D m The second pre-transform coding polynomial may also be referred to as a feedback polynomial.

[0177] In this example, the structure of the pre-transform coding is a shift register with a feedforward tap and a feedback tap. The length of the shift register is L, which is equal to the maximum power of the polynomial g(D) and the polynomial q(D).

[0178] From the timing point of view, q0 (or g0) corresponds to the tap at the current moment, q1 (or g1) corresponds to the tap at one moment before the current moment; q2 (or g2) corresponds to the tap at two moments before the current moment; similarly, q m (or g m ) corresponds to the tap after passing through m registers. represents the exclusive-or operation on a binary field, For a binary switch, the polynomial q(D) = 1 + q1D + q2D 2 +...+q m D m The coefficient q i When 0 is taken, is off (when there is no tap at the i-th moment), otherwise is open (there is a tap at the i-th moment), and the coefficients of the polynomial g(D) have similar meanings and are not repeated here.

[0179] In one implementation, the pre-transformation code is a non-systematic code, and if the current position of the input sequence corresponds to a message bit, the output of the shift register is related to the value of the tap in the first tap group (i.e., the feedforward tap group). Specifically, the output of the shift register is the exclusive OR value of the tap value corresponding to the power term with a coefficient greater than 0 in the first pre-transformation coding polynomial.

[0180] In another implementation, the pre-transform coding is a systematic code. If the current position of the input sequence corresponds to a message bit, the output of the shift register is related to the set to which the current position belongs. For example, if the current position of the input sequence belongs to the set of message bits, the output of the shift register is the input of the shift register, u i = v i .

[0181] In addition, for non-systematic codes or systematic codes, if the current position of the input sequence belongs to the set of frozen bits, the output of the shift register is 0.

[0182] In Example 4, the value of the tap in the second tap group (i.e., the feedback tap group) is the exclusive OR value of the input of the shift register and the feedback input of the shift register, and the feedback input is the value in the L-th register in the shift direction of the shift register.

[0183] The pseudocode of Example 4 can be as follows:

[0184]

[0185]

[0186] It can be seen from the above pseudocode that for the structure where the tap direction in the first tap group in Example 4 is readout and the tap direction in the second tap group is write, if the current position in the input sequence corresponds to a message bit, the value in the first register of the shift register is updated to: the exclusive OR value of the value in the first register and the value of the first tap corresponding to the first register, the first tap belongs to the second tap group, and the first register is any register in the shift register.

[0187] The type of register in Example 4 is feedforward + feedback. Compared with the feedforward method in Example 3, in Example 4, it is multi-tap readout, and the feedback method is multi-tap write. The number of feedforward taps or feedback taps is greater than or equal to 1.

[0188] Different from the fact that the output of the pre-transform coding in Example 3 is only related to the value stored in one register of the shift register, the output of the pre-transform coding in Example 4 is related to the values stored in multiple registers of the shift register. Therefore, the error-checking ability is stronger.

[0189] Example 5

[0190] Feedforward tap write + feedback tap write + poly MSB RHS + right shift

[0191] Figure 10 It is a shift register where both the feedforward tap and the feedback tap are for writing. Such as Figure 10, the directions of the taps in both the first tap group and the second tap group are for writing. The taps in the first tap group are feedforward taps, and the positions of the feedforward taps are determined by the first pre-transform coding polynomial g(D) = 1 + g1D + g2D 2 +... + g m D m . In this example, the first pre-transform coding polynomial can also be called the feedforward polynomial. The taps in the second tap group are feedback taps, and the positions of the feedback taps are determined by the second pre-transform coding polynomial q(D) = 1 + q1D + q2D 2 +... + q m D m . The second pre-transform coding polynomial can also be called the feedback polynomial.

[0192] In this example, the pre-transform coding is based on a shift register where both the feedforward taps and the feedback taps are for writing. After combining the feedforward polynomial and the feedback polynomial, they are all written from the taps after the input bits are XORed with the feedback bits, and read from the last register in the shift direction of the shift register.

[0193] For the descriptions of the feedforward polynomial, the feedback polynomial, and the polynomial coefficients, reference can be made to the descriptions in other examples above, and will not be elaborated here.

[0194] The pseudocode of Example 5 can be as follows:

[0195]

[0196]

[0197] From the above pseudocode, it can be seen that for the structure where the taps in both tap groups in Example 5 are used for writing, if the current position of the input sequence corresponds to a message bit, the value in the first register in the shift register is updated to: the XOR value of the value in the first register, the value of the first tap corresponding to the first register, and the value of the second tap. Among them, the value of the first tap or the value of the second tap is the XOR value of the input and the feedback input of the shift register. Here, the feedback input of the shift register is the output of the shift register. Here, the first tap belongs to the first tap group and is a feedforward tap. The second tap belongs to the second tap group and is a feedback tap.

[0198] Compared with Example 4, in Example 5, the feedforward method becomes multi-tap writing, and the feedback method is also multi-tap writing, and the number of taps is greater than or equal to 1.

[0199] It should be noted that after combining the feedforward polynomial and the feedback polynomial in Example 5, in terms of the feedback effect, it is similar to Example 2, that is, the input of the shift register is XORed with the feedback input of the shift register and then written from the taps, and output from the last register in the shift direction of the shift register.

[0200] In Examples 3 to 5 above, the taps of at least one of the two tap groups are used for writing. An embodiment is also provided below in which the taps of a shift register are all used for reading.

[0201] Specifically, the shift register corresponds to at least two taps, and the directions of the at least two taps are for reading. The positions of the at least two taps are determined by a pre-transform coding polynomial, and the coefficients of the lowest power term and the highest power term of the pre-transform coding polynomial both take the value of 1. In addition, if the current position of the input sequence of the pre-transform coding corresponds to a dynamic freeze bit, the output of the shift register is related to the value in the L-th register based on the shift direction of the shift register. Among them, the L-th register is the register corresponding to the highest power term of the pre-transform coding polynomial, and L is an integer greater than or equal to 1. The following will be illustrated with Examples 6 to 8.

[0202] Example 6

[0203] Feedforward + poly MSB RHS + right shift + read from tap

[0204] Figure 11 It is a schematic diagram of a shift register with a feedforward tap for reading. Figure 11 The pre-transform coding in it is based on a shift register with a feedforward tap. Among them, the position of the feedforward tap is based on a pre-transform coding polynomial (which can also be called a feedforward polynomial) g(D) = 1 + g1D + g2D 2 +... + g m D m Determined. For the pre-transform coding polynomial g(D), see the description in Example 1, which will not be elaborated here. Different from Example 1, in Example 6, the direction of the tap is for reading.

[0205] In Figure 6 The output of the shift register is the exclusive OR value of the input of the shift register and the value of the first tap. The first tap is the tap corresponding to the power term with a coefficient greater than 0 in the pre-transform coding polynomial.

[0206] Example 7

[0207] Feedback + poly MSB RHS + right shift + read from tap

[0208] Figure 12 It is a schematic diagram of a shift register with a feedback tap for reading. Figure 12 The pre-transform coding in it is based on a shift register with a feedback tap. Among them, the position of the feedback tap is based on a pre-transform coding polynomial q(D) = 1 + q1D + q2D 2 +... + q m D mDetermined. For the pre-transform coding polynomial q(D), refer to the description in Example 2, which will not be elaborated here. Different from Example 2, in Example 7, the direction of the taps is readout.

[0209] In Example 7, the output of the shift register is the exclusive OR value of the input of the shift register and the feedback input of the shift register, where the feedback input is the exclusive OR value of at least two taps corresponding to the shift register.

[0210] Example 8

[0211] Feedback + poly MSB RHS + right shift + readout from taps

[0212] Figure 13 It is a schematic diagram of a shift register where the directions of both the feedforward taps and the feedback taps are readout. Figure 13 In it, the pre-transform coding is based on a shift register with feedforward taps and feedback taps. Among them, the positions of the feedforward taps are determined based on the pre-transform coding polynomial g(D) = 1 + g1D + g2D 2 +... + g m D m and correspond to the first tap group; the positions of the feedback taps are determined based on the pre-transform coding polynomial q(D) = 1 + q1D + q2D 2 +... + q m D m and correspond to the second tap group. For the pre-transform coding polynomials g(D) and q(D), refer to the description in Example 3, which will not be elaborated here. Different from Example 3, in Example 8, the directions of both the feedforward taps and the feedback taps are readout.

[0213] In Example 8, the output of the shift register is the exclusive OR value of the first input and the values of the taps in the first tap group. The first input is the exclusive OR value of the input of the shift register and the feedback input of the shift register, and the feedback input is the exclusive OR value of the values of the taps in the second tap group.

[0214] Figures 14 to 22Performance simulation results of the encoding method provided by this application. Among them, "nestedLTE-RM FHT" in the legend represents the performance of the existing LTE-RM code, "nested PC-polar SCL8 searched RateMatchingand PC" represents the performance of the existing nested PC-Polar code, the star line of "NR seq&RM ADminMetric PC-Polar fulChkSCL8 Non-Nested" represents the case-by-case performance, and the triangle line of "NR seq&RM ADminMetric PC-PolarfulChk SCL8 Non-Nested" represents the case-by-case performance of feedback, poly MSB RHS, right shift, and writing from taps. It can be seen from the performance simulation diagram that the solution provided by this application has better performance at high code rates (corresponding to small E values). In addition, within the entire value range of E, compared with the fast Hadamard transform (FHT), the decoding complexity of the solution of this application is lower, and the performance remains basically unchanged or even better.

[0215] The encoding method provided by this application has been described in detail above. Next, the communication device provided by this application will be introduced.

[0216] As Figure 23 , this application provides a communication device 1000.

[0217] The communication device 1000 can be an encoding device or a device applied to an encoding device that can implement the corresponding functions of the encoding device in the method embodiments of this application. For example, a chip, a chip system, or a circuit, etc.

[0218] Optionally, the communication device 1000 includes a processing module 1001. The processing module can be a processor, a processing board, a processing unit, or a processing device, etc. The processing module 1001 is used to perform pre-transform encoding on the input sequence to obtain an output sequence. Optionally, the processing module 1001 is further used to perform polar encoding on the output sequence of the pre-transform encoding to obtain a codeword sequence. The specific process can refer to the detailed description of the method embodiments and will not be elaborated here.

[0219] Optionally, the communication device 1000 further includes a communication module 1002. The communication module can also be referred to as a transceiver module, a transceiver, a transceiver, or a transceiver device, etc., and is used to perform receiving (or input) and / or sending (or output) operations. For example, the communication module 1002 can be used to obtain the input sequence of the pre-transform encoding, output the output sequence of the pre-transform encoding, or output the codeword sequence after concatenated encoding, etc.

[0220] In some embodiments, the foregoing communication module and / or processing module may be implemented by virtual modules. For example, the processing module may be implemented by a software functional unit or a virtual device, and the communication module may be implemented by a software function or a virtual device. Alternatively, the processing module or the communication module may also be implemented by a physical device. For example, if the device is implemented by a chip / circuit (such as an integrated circuit, an application-specific circuit, a logic circuit, etc.). The communication module may be an input / output circuit and / or a communication interface, and perform input operations (corresponding to the foregoing receiving operations) and output operations (corresponding to the foregoing sending operations); the processing module is an integrated processor or a microprocessor or a circuit (such as an integrated circuit, a logic circuit, etc.).

[0221] The division of modules in this application is illustrative, merely a logical function division. In actual implementation, there may be other division methods. In addition, in each example of this application, each functional module may be integrated in a processor, or may exist separately physically, or two or more modules may be integrated in one module. The above integrated module may be implemented in the form of hardware or in the form of a software functional module.

[0222] As Figure 24 , this application also provides a communication device 1100. The communication device 1100 includes at least one processor 1110, which implements the functions of the encoding device described in the foregoing method embodiments.

[0223] Optionally, the processor 1110 is coupled to a memory. The memory may be located within the communication device, or the memory may be integrated with the processor, or the memory may also be located outside the communication device. The communication device 1100 may further include at least one memory 1120. The memory 1120 stores necessary computer programs, instructions, or data, etc. in any one of the foregoing method embodiments; the processor 1110 may execute the computer programs, instructions, or data, etc. stored in the memory 1120 to complete the encoding method in any of the foregoing embodiments.

[0224] Optionally, the communication device 1100 may further include a communication interface 1130. The communication device 1100 may interact with other devices through the communication interface 1130. Exemplarily, the communication interface 1130 may be a transceiver, a circuit, a bus, a module, a pin, or other types of interfaces.

[0225] The coupling in this application is an indirect coupling or communication connection between devices, units or modules, which can be electrical, mechanical or other forms, and is used for information interaction between devices, units or modules. The processor 1110 may cooperate with the memory 1120 and the communication interface 1130. In this application, the specific connection medium between the above-mentioned processor 1110, memory 1120 and communication interface 1130 is not limited.

[0226] As Figure 25 , this application also provides a chip (or chip system). The chip (or chip system) 30 may include a circuit 31 and an input / output interface 32. The circuit 31 may be a logic circuit, an integrated circuit, etc., and the input / output interface 32 may also be an input / output circuit or an interface circuit, which can input information (or receive information) and output information (or send information). Optionally, the chip system may be composed of chips, or may include chips and other discrete devices. The chip 30 can be used to execute the methods performed by the encoding device in the embodiments of this application.

[0227] In addition, this application also provides a computer-readable storage medium, in which computer instructions are stored. When the computer instructions are run on a computer, the operations and / or processes performed by the encoding device in the method embodiments of this application are executed.

[0228] This application also provides a computer program product, which includes computer program code or instructions. When the computer program code or instructions are run on a computer, the operations and / or processes performed by the encoding device in the method embodiments of this application are executed.

[0229] In addition, this application also provides a chip, which includes a processor. The memory for storing computer programs is provided independently of the chip, and the processor is used to execute the computer programs stored in the memory, so that the operations and / or processes performed by the encoding device in any one of the method embodiments are executed. Further, the chip may further include a communication interface. The communication interface may be an input / output interface or an interface circuit, etc. Further, the chip may further include a memory, which stores the code and / or instructions required for the chip to execute the encoding method of this application.

[0230] This application provides a communication system, including the encoding device in the embodiments of this application, and the encoding device is used to implement the steps 310-330 of the above method embodiments. In some embodiments, the encoding device is as Figure 23 or Figure 24 a communication device with corresponding encoding functions in Figure 25 or a chip used to implement the encoding method of the embodiments of this application in

[0231] In each embodiment of the present application, "a plurality of" includes two or more.

[0232] Those of ordinary skill in the art can realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0233] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the systems, devices, and units described above can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated herein.

[0234] In several embodiments provided by the present application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division, and there can be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces. The indirect couplings or communication connections of the devices or units can be in electrical, mechanical, or other forms.

[0235] The units described as separate components may or may not be physically separated. The components shown as units may or may not be physical units, that is, they can be located in one place, or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0236] In addition, the functional units in each embodiment of the present application can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit.

[0237] When the above-mentioned functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of this application. The aforementioned storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical discs that can store program codes.

Claims

1. A coding method, characterized in that, Including: Obtain an input sequence; Perform pre-transform coding on the input sequence according to a shift register to obtain an output sequence; Perform polar coding on the output sequence to obtain a codeword sequence; Wherein, The shift register corresponds to at least two taps, the directions of the at least two taps are for writing, the positions of the at least two taps are determined by a pre-transform coding polynomial, and the coefficients of the lowest power term and the highest power term of the pre-transform coding polynomial are both 1; If the current position of the input sequence corresponds to a dynamic frozen bit, the output of the shift register is related to the value in the L-th register in the shift direction of the shift register, and the L-th register is the register corresponding to the highest power term of the pre-transform coding polynomial, and L is an integer greater than or equal to 1.

2. The method according to claim 1, wherein The value in the L-th register is related to the values in the previous L-1 registers.

3. The method according to claim 2, wherein If the current position of the input sequence is a message bit, the value in the first register in the shift register is updated to the exclusive OR of the value in the first register and the value of the first tap corresponding to the first register, and the value of the first tap is the input of the shift register, and the first register is any register in the shift register.

4. The method according to claim 1, wherein The value in the L-th register is related to all the message bits before the current position in the input sequence.

5. The method according to claim 4, characterized in that If the current position of the input sequence is a message bit, the value of the first register in the shift register is updated to: the exclusive OR value of the value in the first register and the value of the corresponding first tap, and the value of the first tap is the exclusive OR value of the feedback input value and the message bit at the current position, and the first register is any register in the shift register.

6. The method according to any one of claims 1-5, characterized in that If the current position of the input sequence corresponds to a message bit, the output of the shift register is related to the value in the L-th register in the shift direction of the shift register; or, If the current position of the input sequence corresponds to a frozen bit, the output of the shift register is 0.

7. The method according to any one of claims 1-5, characterized in that If the current position of the input sequence corresponds to a message bit, the output of the shift register is the input of the shift register; or If the current position of the input sequence corresponds to a frozen bit, the output of the shift register is 0.

8. The method according to any one of claims 1 to 7, characterized in that, The length L of the shift register is a prime number.

9. The method according to claim 8, wherein The L is 5 or 7; If L is 7, the number of taps corresponding to the shift register does not exceed 5; or, If L is 5, the number of taps corresponding to the shift register does not exceed 3.

10. The method according to claim 1, wherein The shift register corresponds to at least two taps, the directions of the at least two taps are for writing, the positions of the at least two taps are determined by a pre-transform coding polynomial, and the coefficients of the lowest power term and the highest power term of the pre-transform coding polynomial are both 1, including: The shift register corresponds to two tap groups, and the taps in at least one of the two tap groups are for writing; The positions of the taps in the first tap group of the two tap groups are determined by a first pre-transform coding polynomial, and the positions of the taps in the second tap group of the two tap groups are determined by a second pre-transform coding polynomial; The coefficients of the lowest-degree term and the highest-degree term of each of the first pre-transform coding polynomial and the second pre-transform coding polynomial are both 1.

11. The method according to claim 10, characterized in that, The direction of the taps in the first tap group is writing, and the direction of the taps in the second tap group is reading; If the current position of the input sequence corresponds to a message bit, the value in the first register of the shift register is updated to: the exclusive OR value of the value in the first register and the value of the first tap corresponding to the first register, where the value of the first tap is the exclusive OR value of the feedback input and the message bit at the current position, and the feedback input is the exclusive OR value of the values of the taps corresponding to the power terms with coefficients greater than 0 in the second pre-transform coding polynomial, and the first register is any one of the registers in the shift register.

12. The method according to claim 10, characterized in that, The direction of the taps in the first tap group is writing, and the direction of the taps in the second tap group is writing; If the current position of the input sequence corresponds to a message bit, the value in the first register of the shift register is updated to: the exclusive OR value of the value in the first register and the values of the first tap and the second tap corresponding to the first register, where the value of the first tap or the value of the second tap is the exclusive OR value of the input of the shift register and the feedback input, and the feedback input is the output of the shift register, where the first tap belongs to the first tap group and the second tap belongs to the second tap group.

13. The method according to claim 11 or 12, characterized in that, If the current position of the input sequence corresponds to a message bit, the output of the shift register is related to the value of the L-th register in the shift direction of the shift register; or, If the current position of the input sequence corresponds to a frozen bit, the output of the shift register is 0.

14. The method according to claim 11 or 12, characterized in that, If the current position of the input sequence corresponds to a message bit, the output of the shift register is the input of the shift register; or, If the current position of the input sequence corresponds to a frozen bit, the output of the shift register is 0.

15. The method according to claim 10, wherein The direction of the taps in the first tap group is reading, and the direction of the taps in the second tap group is writing; If the current position in the input sequence corresponds to a message bit, the value in the first register of the shift register is updated to: the exclusive OR value of the value in the first register and the value of the first tap corresponding to the first register, where the first tap belongs to the second tap group, and the first register is any one of the registers in the shift register.

16. The method according to claim 15, wherein If the current position of the input sequence corresponds to a message bit, the output of the shift register is related to the value of the taps in the first tap group; or, If the current position of the input sequence corresponds to a frozen bit, the output of the shift register is 0.

17. The method according to claim 16, wherein If the current position of the input sequence corresponds to a message bit, the output of the shift register is related to the value of the taps in the first tap group, and the output of the shift register is related to the value of the taps in the first tap group, including: If the current position of the input sequence corresponds to a message bit, the output of the shift register is the exclusive OR value of the tap values corresponding to the power terms with coefficients greater than 0 in the first pre-transform coding polynomial.

18. The method according to claim 15, wherein If the current position of the input sequence corresponds to a message bit, the output of the shift register is the input of the shift register; or, If the current position of the input sequence corresponds to a frozen bit, the output of the shift register is 0.

19. The method according to any one of claims 15 - 18, characterized in that, The value of the tap in the second tap group is the exclusive OR value of the input of the shift register and the feedback input, and the feedback input is the value in the L-th register in the shift direction of the shift register.

20. A communication device, characterized in that, Comprising: A communication module for obtaining an input sequence; A processing module for: Performing pre-transform coding on the input sequence according to a shift register to obtain an output sequence; and, Performing polar coding on the output sequence to obtain a codeword sequence; Wherein, the shift register corresponds to at least two taps, the directions of the at least two taps are for writing, the positions of the at least two taps are determined by a pre-transform coding polynomial, and the coefficients of the lowest power term and the highest power term of the pre-transform coding polynomial are both 1; If the current position of the input sequence corresponds to a dynamic frozen bit, the output of the shift register is related to the value in the L-th register in the shift direction of the shift register, and the L-th register is the register corresponding to the highest power term of the pre-transform coding polynomial, and L is an integer greater than or equal to 1.

21. A communication device, characterized in that, Comprising a communication interface and a circuit, The communication interface is used for receiving an input sequence and inputting the input sequence to the circuit; the communication interface is also used for outputting a codeword sequence output by the circuit; The circuit is used for implementing the method according to any one of claims 1-19.

22. A communication device, characterized in that, Comprising: A processor, the processor is coupled to a memory, and the processor is used for executing a computer program or instruction stored in the memory to implement the method according to any one of claims 1-19.

23. A computer-readable storage medium, characterized in that, Computer instructions are stored in the computer-readable storage medium, and when the computer instructions are run on a computer, the method according to any one of claims 1-19 is implemented.

24. A computer program product, characterized in that, The computer program product includes computer program code or instructions, and when the computer program code or instructions are run on a computer, the method according to any one of claims 1-19 is implemented.

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