System and method for multi-level switch firmware combination memory resource allocation

Abstract

The invention discloses a system and a method for allocating memory resources of a multi-level exchanger firmware combination, which relate to the technical field of computers, and are characterized in that a first hardware resource on a peripheral interconnection link is read when a server is started, and when the first hardware resource comprises exchangers, a second hardware resource connected with each exchanger is identified; the identification result of the second hardware resource connected with each exchanger is transmitted to firmware of the corresponding exchanger, the firmware allocates a first memory resource for the exchanger and the second hardware resource, and resource allocation is carried out on the second hardware resource connected with the exchanger through the firmware of the exchanger; according to the embodiment of the invention, the system does not need to sequentially read each peripheral interconnection device for resource allocation, and only needs to read the memory resource allocation set in the firmware of the switch, so that the starting time of the server can be optimized, the reallocation of the memory resources can be avoided when the server is started, and the service life of the server is prolonged. And the stationarity and the stability of memory resource allocation are further ensured.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular, to a system and method for allocating memory resources of a multi-level switch firmware combination. Background Art

[0002] Intelligent network cards are widely used in various architecture servers in data centers to offload data processing functions related to the CPU (Central Processing Unit) of the server, which is not suitable for the server, to a programmable hardware chip for execution, reducing the consumption of the CPU. However, since there are many devices inside the intelligent network card, these devices all need to use memory resources and need to preferentially use some memory resources. However, some intelligent network card devices will contain a Switch chip inside. Other PCI (Peripheral Component Interconnect) devices are connected under the Switch chip. At this time, memory resources also need to be allocated. In addition, the motherboard or PCI device card of the server will also contain a similar Switch chip. The same Switch chip and the PCI devices below it also need resources.

[0003] Related technologies reserve resources when the server starts. However, since the server may involve many Switch chips and the levels of the Switch chips cannot be fixed, it is impossible to predict which specific Switch chip needs to reserve resources. Therefore, it takes a lot of time to identify and traverse the Switch chips on the PCI link for resource reservation, resulting in a significant extension of the server startup time. Summary of the Invention

[0004] The present invention provides a system and method for allocating memory resources of a multi-level switch firmware combination, so as to at least solve the problem that the server startup time is relatively long caused by the memory resource allocation method in related technologies.

[0005] The present invention provides a system for allocating memory resources of a multi-level switch firmware combination, including: at least one processing circuit of the server, at least one processing circuit is connected to at least one peripheral interconnect link, and at least one processing circuit is used for: executing a reading engine, and the reading engine reads the first hardware resources on the current peripheral interconnect link when the server starts; propagating the read data of the first hardware resources to an identification engine, and the identification engine identifies the read data. If the first hardware resources include at least one of a single-level switch and a multi-level switch, then identify the second hardware resources connected to each switch; propagating the identification results of the second hardware resources connected to each switch to the firmware of the corresponding switch, and the firmware allocates the first memory resources for the switch and the second hardware resources based on the identification results of the second hardware resources.

[0006] The present invention also provides a server, including the system for allocating memory resources of the multi-level switch firmware combination described above.

[0007] The present invention also provides a method for allocating memory resources of a multi-level switch firmware combination, including: at least one processing circuit connected by at least one peripheral interconnect link, wherein the at least one processing circuit is configured to: execute a reading engine, and the reading engine reads first hardware resources on the current peripheral interconnect link when the server starts up; propagate the read data of the first hardware resources to an identification engine, and the identification engine identifies the read data. If the first hardware resources include at least one of a single-level switch and a multi-level switch, then identify the second hardware resources connected to each switch; propagate the identification results of the second hardware resources connected to each switch to the firmware of the corresponding switch, and the firmware allocates first memory resources for the switch and the second hardware resources based on the identification results of the second hardware resources.

[0008] The present invention also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of the method for allocating memory resources of the multi-level switch firmware combination described above are implemented.

[0009] The present invention also provides a computer program product, including a computer program. When the computer program is executed by a processor, the steps of the method for allocating memory resources of the multi-level switch firmware combination described above are implemented.

[0010] Through the present invention, the first hardware resources on the peripheral interconnect link can be read when the server starts up. When the first hardware resources include at least one of a single-level switch and a multi-level switch, the second hardware resources connected to each switch are identified, and the identification results of the second hardware resources connected to each switch are propagated to the firmware of the corresponding switch. The firmware allocates first memory resources for the switch and the second hardware resources based on the identification results of the second hardware resources. By using the firmware of the switch to allocate resources for the second hardware resources connected thereto, there is no need for the system to sequentially read each peripheral interconnect device for resource allocation, and only the memory resource allocation set in the firmware of the switch needs to be read. The firmware is used to allocate memory resources for the switch and the hardware resources connected to the switch, so that the startup duration of the server can be optimized, and the reallocation of memory resources during server startup can be avoided, thereby ensuring the fixity and stability of memory resource allocation. Therefore, the technical problem in the related art that the memory resource allocation method results in a longer server startup time can be solved. Description of the Drawings

[0011] To more clearly illustrate the embodiments of the present invention, the following will briefly introduce the drawings required for the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0012] Figure 1 Schematic diagram of the memory resource allocation system for the multi - level switch firmware combination provided by the embodiment of the present invention; Figure 2 Schematic diagram of the link of the single - level switch provided by the embodiment of the present invention; Figure 3 Schematic diagram of the link of the multi - level switch provided by the embodiment of the present invention; Figure 4 Schematic diagram of the physical connection of the server motherboard provided by the embodiment of the present invention; Figure 5 Schematic diagram of the structure of the data processor provided by the embodiment of the present invention; Figure 6 Flowchart of the method for memory resource allocation of the multi - level switch firmware combination provided by the embodiment of the present invention; Figure 7 Component execution connection diagram of the memory resource allocation system for the multi - level switch firmware combination during the server startup phase provided by the embodiment of the present invention; Figure 8 Flowchart of the memory resource allocation during the server startup phase provided by the embodiment of the present invention; Figure 9 Flowchart of reading the firmware setting parameters of the switch on the peripheral interconnect link provided by the embodiment of the present invention; Figure 10 Component execution connection diagram of the memory resource allocation system for the multi - level switch firmware combination when the server enters the operating system phase provided by the embodiment of the present invention; Figure 11 Flowchart of the memory resource allocation when the server enters the operating system phase provided by the embodiment of the present invention. Detailed implementation manners

[0013] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, rather than all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

[0014] It should be noted that in the description of the present invention, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present invention are used to distinguish similar objects, rather than to describe a specific order or sequence.

[0015] An embodiment of the present invention provides a system for allocating memory resources of a multi-level switch firmware combination.

[0016] As Figure 1 shown, the system 10 for allocating memory resources of the multi-level switch firmware combination includes at least one processing circuit 11 of a server.

[0017] Among them, at least one processing circuit 11 of the server is connected to at least one peripheral interconnect link, and at least one processing circuit 11 is used for: executing a reading engine, and the reading engine reads the first hardware resources on the current peripheral interconnect link when the server starts; propagating the read data of the first hardware resources to an identification engine, and the identification engine identifies the read data. If the first hardware resources include at least one of a single-layer switch and a multi-level switch, then identify the second hardware resources connected to each switch; propagate the identification results of the second hardware resources connected to each switch to the firmware of the corresponding switch, and the firmware allocates the first memory resources for the switch and the second hardware resources based on the identification results of the second hardware resources.

[0018] The peripheral interconnect link in the embodiment of the present invention may be a PCI link; the processing circuit 11 is the circuit where the CPU processor is located, and it can issue instructions for control through BIOS (Basic Input Output System); the first hardware resources may include peripheral interconnect devices (PCI devices), switches, etc., and the switch may be a Switch chip; a single-layer switch is connected to other devices below it, rather than a switch; a multi-level switch is a switch connected to at least one other switch below it, and it is a hierarchical structure; the second hardware resources may include PCI devices, peripheral interconnect ports (PCI ports), etc. The link connection of the single-layer switch is as Figure 2 shown, and the link connection of the multi-level switch is as Figure 3 shown.

[0019] As the functions of the server continue to be enriched, the number of devices to be connected is increasing day by day, such as multiple intelligent network cards, high-performance graphics cards, large-capacity storage devices, etc. However, due to the limited number of root ports of the peripheral interconnect links of the server CPU, more peripheral interconnect devices cannot be connected. Therefore, a switch needs to be introduced to expand the number of peripheral interconnect interfaces. The peripheral interconnect interfaces also need to be physically connected to the interconnect devices. In short, the server motherboard directly links multiple peripheral interconnect links, as well as multiple device links such as the peripheral interconnect devices, switches, and peripheral interconnect ports linked on the links. The physical connection of the server motherboard is as Figure 4 shown. Memory resources need to be reserved for all these hardware resources. Therefore, when the server starts up, it takes too much time to allocate resources, resulting in an extended server startup time and low startup efficiency.

[0020] Therefore, in the embodiment of the present invention, the first hardware resources on the peripheral interconnect link can be read when the server starts up. When the first hardware resources include at least one of a single-layer switch and a multi-layer switch, the second hardware resources connected to each switch are identified, and the identification results of the second hardware resources connected to each switch are propagated to the firmware FW of the corresponding switch. Based on the identification results of the second hardware resources, the firmware allocates the first memory resources for the switch and the second hardware resources. By using the firmware of the switch to allocate resources for the second hardware resources connected to it, there is no need for the server to read each peripheral interconnect device in sequence for resource allocation. It only needs to read the memory resource allocation set in the firmware of the switch. By implementing the memory resource allocation for the switch and the hardware resources connected to the switch through the firmware, the startup duration of the server can be optimized, and the reallocation of memory resources during server startup can be avoided, thereby ensuring the fixity and stability of the memory resource allocation.

[0021] In addition, it should be noted that the processing circuit 11 in the startup stage of the server in the embodiment of the present invention is controlled by the BIOS.

[0022] In the embodiment of the present invention, the firmware is used to: if the second hardware resources include peripheral interconnect devices, allocate the first memory resources to the peripheral interconnect devices according to the target settings of the firmware; if the second hardware resources include peripheral interconnect ports, allocate the first memory resources to the peripheral interconnect ports when the peripheral interconnect ports need to support the hot-plug function.

[0023] Among them, the target settings are the memory resource allocations pre-set for the peripheral interconnect devices in the firmware of the switch; the hot-plug function is the Hotplug function, and the hot-plug function allows devices to be plugged in or removed at any time when the server is running.

[0024] It can be understood that when the embodiment of the present invention includes a peripheral interconnect device in the second hardware resource, the first memory resource is allocated to the peripheral interconnect device according to the target setting of the firmware. When the second hardware resource includes a peripheral interconnect port and the peripheral interconnect port needs to support the hot-plug function, the first memory resource is allocated to the peripheral interconnect port. Since the hot-plug function allows devices to be connected or removed at any time while the server is running, resulting in changes in memory resource requirements, the embodiment of the present invention can allocate the first memory resource to the peripheral interconnect port when the peripheral interconnect port needs to support the hot-plug function, so as to dynamically allocate and manage the memory resources according to the actual situation of the device and avoid resource conflicts with other devices.

[0025] In the embodiment of the present invention, the allocation engine is used to: when a peripheral interconnect port is connected to the current peripheral interconnect link, if the peripheral interconnect port is a target port, allocate the first memory resource to the peripheral interconnect port.

[0026] Among them, the target type is a specific type of PCI port, such as the connection ports of a graphics card, a network card, and a storage controller. These ports have specific and immediate requirements for memory resources.

[0027] It can be understood that when a target port is connected to the current peripheral interconnect link in the embodiment of the present invention, the first memory resource is allocated to the peripheral interconnect port to avoid resource conflicts between other devices and the device connected to this port, and ensure that the device connected to the target port can work normally and stably.

[0028] Specifically, during the PCI enumeration stage, the BIOS continues to determine whether the current PCI link without a Switch chip is a specific PCI port (i.e., the target port). If it is a specific PCI port, 32-bit memory resource reservation is performed; if it is not a specific PCI port and there is a PCI Switch chip, the BIOS no longer enables the Hotplug function for the upstream and downstream ports of the Switch chip. The PCI device resource allocation for the upstream and downstream ports of the Switch chip is mainly based on the settings in the Switch firmware FW, and the BIOS only reads the actual memory resource sizes required for the upstream and downstream ports of the Switch chip and the PCI devices.

[0029] In the embodiment of the present invention, at least one processing circuit 11 is used to: if the first hardware resource includes a peripheral interconnect device, propagate the read data to the allocation engine, and the allocation engine allocates the first memory resource to the peripheral interconnect device.

[0030] It can be understood that when the first hardware resource includes a peripheral interconnect device in the embodiment of the present invention, the read data is propagated to the allocation engine, and the allocation engine allocates the first memory resource to the peripheral interconnect device to normally allocate 32-bit resources for the peripheral interconnect device.

[0031] In an embodiment of the present invention, at least one processing circuit 11 is configured to: execute a reading engine, where the reading engine reads the identifier of a peripheral interconnect device; propagate the identifier of the peripheral interconnect device to an identification engine, and the identification engine identifies whether the peripheral interconnect device is a data processor based on the identifier; when the peripheral interconnect device is a data processor, an allocation engine allocates first memory resources according to the resource size of the data processor.

[0032] The identifier is used to identify the type of the peripheral interconnect device, and the identifier may be a DID (Device ID) and a VID (Vendor ID).

[0033] Since a DPU (Data Processing Unit) usually has specific memory resource requirements, the embodiment of the present invention can read the identifier of the peripheral interconnect device, identify whether the peripheral interconnect device is a DPU through the identifier, so as to adopt different memory allocation strategies for the peripheral interconnect device. When the peripheral interconnect device is not a DPU, memory resources are normally allocated to it. If it is a DPU device, memory resources are allocated to the peripheral interconnect device according to the resource size of the DPU to ensure the normal operation of the DPU device.

[0034] It should be noted that a DPU is a dedicated processor that provides virtualization services for data center infrastructure such as network, storage, security, and management around data processing. It is a computing architecture composed of a CPU based on architectures such as ARM / X86 and dedicated hardware acceleration engines such as ASIC (Application-Specific Integrated Circuit) / NP (Network Processor) / FPGA (Field Programmable Gate Array), forming an entity that provides virtualization functions and requires sufficient resources to support the operation of complex services. Therefore, resources need to be reserved. The structure of the DPU is as Figure 5 shown. Currently, DPU products have been widely used in various architecture servers in data centers (usually in the form of smart network cards), including but not limited to X86 architecture and ARM architecture, etc. However, regardless of the architecture of the server, when applying a smart network card, resource reservation for the smart network card needs to be carried out in advance because there are many devices inside the smart network card, such as physical or virtual devices such as network port devices, virtual network cards, and storage devices SSD, etc. These devices all need to use memory resources and some memory resources are prioritized. For example, 32-bit memory resources need to be highly prioritized. Therefore, resource reservation for the DPU needs to be carried out in advance to ensure that various devices can obtain the required memory resources and operate normally.

[0035] Among them, it is determined whether it is a data processor based on the identifier. Specifically, the DID and VID of the peripheral interconnection device can be recognized. If the DID and VID exist in the identifier information list of the pre-set data processor, it is determined that the peripheral interconnection device is a data processor; otherwise, it is not a data processor.

[0036] Specifically, when the server starts up, the BIOS confirms whether the current device is a DPU device by reading the DID and VID of each PCI device during the PCI enumeration stage of the DXE (Driver Execution Environment) phase. If it is not, 32-bit memory resources are normally allocated. If it is a DPU device, 32-bit resource reservation is performed according to the known 32-bit resource size of the DPU. At the same time, when the PCI link physically connected to the current DPU counts the 32-bit resources required by other PCI devices, the MMIO (Memory - Mapped I / O) 32-bit resources reserved by the DPU are accumulated. At the same time, the BIOS enables the hot-plug function of the PCI configuration space of the bridge of the PCI link physically connected to the DPU, that is, the Hotplug function is turned on.

[0037] For example, the CPU of the server has multiple PCI links. Among them, a DPU device is connected to PCI link A, and several other ordinary PCI devices (including PCI device A and PCI device B) are also connected. There is a PCI link bridge on PCI link A for connecting the CPU and the devices on PCI link A. According to the known 32-bit memory resource size of the DPU device, for example, 200MB of MIMO32 resources are reserved for it. At the same time, the 32-bit memory resources required by PCI device A and PCI device B on PCI link A are also counted. For example, PCI device A needs 30MB and PCI device B needs 15MB. Then the total 32-bit memory resources required by PCI link A are 200 + 30 + 15 = 245MB.

[0038] In the embodiment of the present invention, the firmware sets the hot-plug function for the upstream and downstream ports of the switch that has already been allocated the first memory resource.

[0039] It can be understood that the firmware of the embodiment of the present invention sets the hot-plug function for the upstream and downstream ports of the switch that has already been allocated the first memory resource. By enabling the hot-plug function, the required memory resources can be automatically allocated to the device when it is inserted, and these resources can be automatically recycled when the device is removed, realizing dynamic management of resources, improving resource utilization rate, and avoiding waste of resources.

[0040] For example, assume there is a Switch chip (named Switch X) in the server, which is connected to multiple PCI devices. Some of these devices need to support hot-plugging functions, including: The downstream port 1 of Switch X (i.e., the downstream port) is connected to a high-speed network card device A that supports hot-plugging, and the downstream port 2 is connected to an ordinary storage device B (which does not support hot-plugging). The upstream port of Switch X is connected to the upper-level PCI link and ultimately leads to the CPU. According to the requirements of device A, it needs 32MB of memory resources for packet caching and processing during normal operation.

[0041] The FW of SwitchX will reserve 32MB of memory space in the memory resource allocation table for the downstream port 1 where device A is located. This ensures that during the hot-plugging process of device A, whether it is inserted or removed, the system can provide stable memory resource support for it, avoiding device malfunction due to memory allocation problems.

[0042] At the same time, the FW of Switch X will enable the Hotplug function of the PCI configuration space of the downstream port 1. When device A is inserted into the downstream port 1 of Switch X, the Hotplug function is triggered. Switch X will allocate the previously reserved 32MB of memory resources to device A according to the rules pre-set in the FW. At the same time, Switch X will report the access information of device A to the system, including device type, required resources, etc., for the system to perform corresponding configuration and management. When device A is removed, the Hotplug function of the downstream port 1 will notify Switch X to reclaim the 32MB of memory resources allocated to device A and mark it as available for other devices to use.

[0043] In addition to the downstream port, the FW of Switch X will also enable the Hotplug function of the PCI configuration space of the upstream port (upstream port). When device A is inserted or removed, in addition to Switch X itself performing resource management, the Hotplug function of the upstream port will pass the hot-plugging event of device A to the upper-level PCI link. After receiving this event, the upper-level link will make adjustments according to the overall resource status of the system. For example, if the insertion of device A causes memory resource tension in the system, the upper-level link may notify other devices to appropriately adjust resource usage or request more memory resources from the upper-level system to ensure the stable operation of the entire system.

[0044] In an embodiment of the present invention, at least one processing circuit 11 is used to: start an allocation engine, and the allocation engine sets a hot-plug function for a peripheral interconnect link where a switch that has already been allocated a first memory resource is located.

[0045] It can be understood that embodiments of the present invention can set a hot-plug function for the peripheral interconnect link of a switch that has already been allocated the first memory resource, so as to achieve dynamic allocation and recycling of resources, improve the utilization rate of memory resources, and avoid waste of memory resources.

[0046] In addition, it should be noted that the hot-plug function of the peripheral interconnect link can only be set by the BIOS. Since the BIOS has the highest authority and priority in initializing and configuring hardware during the system startup process, only the BIOS can enable the hot-plug function of the PCI link bridge. This can ensure that the hot-plug function is correctly initialized when the system starts and works in coordination with other parts of the system, avoiding compatibility issues or system failures.

[0047] In embodiments of the present invention, at least one processing circuit 11 is configured to: when the identification engine polls all peripheral interconnect links, the first hardware resource, and the second hardware resource, execute a startup engine to start the operating system of the server.

[0048] It can be understood that when the identification engine of the embodiments of the present invention polls all peripheral interconnect links, the first hardware resource, and the second hardware resource, it executes a startup engine to start the operating system of the server and enter the next stage of memory resource allocation.

[0049] In summary, the process of allocating the first memory resource during the startup phase of the server in embodiments of the present invention is as follows.

[0050] 1. When the server starts, the BIOS confirms whether the current device is a DPU device by reading the DID and VID of each PCI device during the PCI enumeration phase in the DXE stage. If it is not, 32-bit memory resources are normally allocated; if it is a DPU device, 32-bit resource reservation is performed according to the known 32-bit resource size of the DPU. At the same time, when the PCI link physically connected to the current DPU counts the 32-bit resources required by other PCI devices, the MMIO 32-bit resources reserved by the DPU are accumulated. At the same time, the BIOS enables the hot-plug function, that is, the Hotplug function, of the PCI configuration space of the bridge of the PCI link physically connected to the DPU. 2. During the PCI enumeration stage, the BIOS continues to determine whether the current PCI link without a Switch chip is a specific PCI port. If it is, 32-bit memory resource reservation is performed; if not and there is a PCI Switch chip, the BIOS no longer enables the Hotplug function for the upstream and downstream ports of the Switch chip. The PCI device resource allocation for the upstream and downstream ports of the Switch chip is mainly based on the settings in the Switch FW. The BIOS only reads the actual memory resource sizes required for the upstream and downstream ports of the Switch chip and the PCI devices. At the same time, the BIOS enables the Hotplug function for the PCI configuration space of the PCI link of the Switch chip scanned during the PCI enumeration stage of DXE because the enabling setting of the PCI link bridge can only be performed by the BIOS; 3. The FW of the Switch chip needs to reserve the memory resource sizes for the PCI ports that need to support the hot-plug function under the Switch. At the same time, the Hotplug function for the PCI configuration space of the upstream and downstream ports where the Switch chip reserves memory resources is enabled. All Switch chips in the server perform resource reservation and Hotplug function enabling according to this method; 4. Poll all PCI link bridges and the corresponding Switch chips and their devices under the PCI link in sequence according to steps 1 and 2. After polling all the PCI links and Switch chips of all CPUs, continue to start and enter the operating system.

[0051] The embodiments of the present invention can flexibly adapt to the memory resource requirements of different types of peripheral interconnect devices, switches, and peripheral interconnect ports, avoid insufficient memory resource allocation for devices, which may cause the devices to malfunction, and at the same time improve the utilization rate of memory resources, avoid waste of memory resources, and thus enhance the overall performance and stability of the server.

[0052] For example, assume that the server currently has two CPUs, namely CPU1 and CPU2. Each CPU is connected to multiple PCI links, and different devices and Switch chips are connected to the links. There is device A (non-DPU) and device B (DPU) on PCI link 1 of CPU1, and there is a specific port A. The downstream port of Switch chip 1 on link 1 is connected to devices C and D. The FW sets that device C requires 16MB and device D requires 8MB of memory resources, and device C supports the hot-plug function. Then the following steps are specifically executed: 1. The server starts, and the BIOS enters the PCI enumeration in the DXE phase. The BIOS reads the DID and VID of device A, confirms that it is not a DPU, and normally allocates 32-bit memory resources for it. It reads the DID and VID of device B, determines that it is a DPU, and assumes that device B requires 32M of 32-bit memory resources. The BIOS reserves it for device B. At the same time, when link 1 is counting the resource requirements of other devices, the 32MB resources reserved for device B are added. The BIOS also enables the Hotplug function of the PCI configuration space of the bridge of the PCI link physically connected to device B.

[0053] 2. If there is no Switch chip on link 1 and there is a specific PCI port A, the BIOS reserves 32-bit memory resources for port A. If there is a Switch chip 1 on link 1, the BIOS no longer enables the Hotplug function for the upstream and downstream ports of Switch1. Instead, it reads the FW of Switch1 to obtain the actual memory resource sizes required for its upstream and downstream ports and the connected PCI devices. For example, the downstream port of Switch0 is connected to devices C and D, and the FW sets that device C requires 16MB and device D requires 8MB of memory resources. The BIOS records this information. At the same time, the BIOS enables the Hotplug function for the PCI configuration space of the PCI link where Switch1 is located.

[0054] 3. The FW of Switch1 reserves memory resources for the PCI ports that need to support the hot-plug function below it. Assume that the downstream port 1 of Switch1 is connected to device C, which supports hot plugging. The FW reserves 16MB of memory for it and enables the Hotplug function for the PCI configuration spaces of downstream port 1 and the upstream port. All Switch chips in the server, such as Switch1, Switch2, etc., operate in this way.

[0055] 4. Check all PCI link bridges, Switch chips, and their devices of CPU1 and CPU2 in sequence. For example, check PCI link 2 of CPU1 and repeat the above operations for device identification, resource reservation, and hot-plug function setting. After polling all the PCI links and Switch chips of all CPUs, the server continues to start and enters the operating system.

[0056] In an embodiment of the present invention, at least one processing circuit 11 is configured to: after the server enters the operating system, execute a reading engine that reads the memory allocation function of the server; and an allocation engine that reallocates the first memory resources of the server according to the memory allocation function.

[0057] Among them, the memory allocation function is used to determine whether resource reallocation is required. The memory allocation function can be identified from the Grub parameters of the operating system, which is PCI=realloc.

[0058] Since the resource requirements of the server may change during the operating system startup phase, in the embodiments of the present invention, after the server enters the operating system, the memory allocation function of the server is read to determine whether the first memory resource needs to be reallocated.

[0059] In addition, it should be noted that the processing circuit in the embodiments of the present invention during the operating system startup phase of the server can be the operating system, that is, all operations during the operating system startup phase are executed by the BIOS.

[0060] In the embodiments of the present invention, at least one processing circuit 11 is used to: before reallocating the first memory resource of the server according to the memory allocation function, execute a reading engine, and the reading engine reads the reallocation requirements of the server; an allocation engine, according to the reallocation requirements and the memory allocation function, reallocates the first memory resource of the server.

[0061] It can be understood that the embodiments of the present invention can determine whether the first memory resource of the server needs to be reallocated according to the reallocation requirements and the memory allocation function.

[0062] In the embodiments of the present invention, if the reading engine does not read the reallocation requirements of the server, the allocation engine deletes the memory allocation function and retains the allocation parameters of the first memory resource in the server startup phase.

[0063] It can be understood that when the embodiments of the present invention do not read the reallocation requirements of the server, the memory allocation function is deleted so as not to reallocate the memory resources when the server enters the operating system, and the allocation parameters of the first memory resource in the server startup phase are retained.

[0064] Specifically, when the server enters the operating system, the Grub interface of the operating system defaults to adding the PCI=realloc parameter to the Grub parameters. If it is not necessary to reallocate the memory resources allocated by the BIOS under the system at this time, this parameter is removed in the Grub file; if it is necessary to reallocate the memory resources allocated by the BIOS at this time, this parameter is retained, and at this time the operating system will reallocate all PCI resources of the server.

[0065] In the embodiments of the present invention, at least one processing circuit 11 is used to: execute a scanning engine, and the scanning engine scans all the peripheral interconnect links of the server; propagate the scanning data of the scanning engine to an identification engine, and the identification engine identifies the scanning data. If it is identified that the current peripheral interconnect link, the first hardware resource connected to the current peripheral interconnect link, and the switch connected to the current peripheral interconnect link enable the hot plug function, the first memory resource allocated to the current peripheral interconnect link in the server startup phase is retained.

[0066] It can be understood that the embodiments of the present invention can execute a scanning engine, propagate the scanning data of the scanning engine to an identification engine, the identification engine identifies the scanning data, when the current peripheral interconnect link, the first hardware resource connected to the current peripheral interconnect link, and the switch connected to the current peripheral interconnect link are identified, the hot-plug function is enabled, indicating that the device may change dynamically, then the first memory resource allocated to the current peripheral interconnect link during the server startup phase is retained to ensure that the device can work properly when accessing or removing, and the memory resources are reasonably allocated.

[0067] In the embodiments of the present invention, the identification engine is used for: if the current peripheral interconnect link, the first hardware resource connected to the current peripheral interconnect link, and the switch connected to the current peripheral interconnect link are identified, the hot-plug function is turned off, and the allocation engine reallocates the first memory resource of the server according to the memory allocation function.

[0068] It can be understood that when the hot-plug function of the current peripheral interconnect link, the first hardware resource connected to the current peripheral interconnect link, and the switch connected to the current peripheral interconnect link is turned off in the embodiments of the present invention, the first memory resource already allocated at server startup or the device that cannot allocate the first memory resource is reallocated to achieve flexible allocation of memory resources to meet new memory resource allocation requirements.

[0069] In the embodiments of the present invention, the identification engine is used for: if the current peripheral interconnect link is idle, or the switch connected to the current peripheral interconnect link is idle, then stop allocating the first memory resource of the server.

[0070] It can be understood that when the current peripheral interconnect link is empty or the switch connected to the current peripheral interconnect link is idle in the embodiments of the present invention, then stop allocating the first memory resource of the server, retain these resources for other more needed tasks or processes, improve the overall utilization rate of memory resources, and enable the server to operate more efficiently.

[0071] In the embodiments of the present invention, at least one processing circuit 11 is used for: executing a scanning engine, the scanning engine scans the current peripheral interconnect link level; propagating the scanning data of the scanning engine to an identification engine, the identification engine identifies the scanning data, if the current peripheral interconnect link level is N, then the number of times of reallocating the first memory resource is N + 1; the allocation engine allocates the first memory resource according to the number of reallocations.

[0072] Since the peripheral interconnect link of the server may have a multi-layer structure, such as Figure 4As shown, the embodiments of the present invention can scan the current peripheral interconnect link level. If a physical connection of the data exchanger occurs during the scanning process, continue scanning until all data exchangers at all levels are scanned and the final number of levels is counted. If the number of levels is N, the number of times of resource reallocation is counted as N + 1. After scanning the levels, reallocate resources to the scanned levels. By counting the number of levels and the number of reallocations, it can provide a basis for subsequent resource reallocation to ensure the accuracy of resource reallocation.

[0073] In the embodiments of the present invention, at least one processing circuit 11 is used to: execute a reading engine, and the reading engine reads the second memory resource of the server; propagate the remaining resources of the second memory resource to an identification engine, and the identification engine identifies whether the remaining resources are less than a resource threshold; propagate the identification result of the identification engine to an allocation engine, and when the remaining resources are less than the resource threshold, the allocation engine stops allocating the first memory resource of the hardware resources at the current level or the next level.

[0074] Among them, the resource threshold can be set according to specific circumstances, such as 4G.

[0075] It can be understood that the embodiments of the present invention can identify the second memory resource to optimize the allocation of the first memory resource. When the remaining resources of the second memory resource are less than the resource threshold, it indicates that the current memory resources are insufficient, and the allocation of the first memory resource of the hardware resources at the current level or the next level is stopped to improve the rationality and effectiveness of memory resource allocation.

[0076] In the embodiments of the present invention, the allocation engine is used to: if any firmware of the multi-level exchanger does not support the hot plug function, reallocate the first memory resource of the peripheral interconnect link where the firmware that does not support the hot plug function is located; if all firmwares of the multi-level exchanger support the hot plug function, retain the allocation parameters of the first memory resource at the server startup stage.

[0077] It can be understood that in the embodiments of the present invention, if any firmware of the multi-level exchanger does not support the hot plug function, reallocate the first memory resource of the peripheral interconnect link where the firmware that does not support the hot plug function is located, so that the memory resources can better adapt to the link that does not support hot plug, avoid problems caused by the mismatch between the resource allocation related to hot plug and the actual hardware capabilities, and make the memory resource allocation more reasonable. Release some of the memory resources reserved for the hot plug function for other more needed places, improving the overall utilization efficiency of memory resources; when all firmwares of the multi-level exchanger support the hot plug function, retain the allocation parameters of the first memory resource at the server startup stage to more flexibly adapt to the dynamic changes of the device, and can avoid system performance fluctuations or configuration errors that may be caused by frequent adjustment of memory allocation, maintaining the overall performance and stability of the server.

[0078] Specifically, the embodiments of the present invention can perform detailed resource reallocation according to the device conditions and hot-plug function status of each level, improve the rationality and effectiveness of resource allocation, and avoid resource conflicts and uneven distribution among devices at multiple levels. Specifically: The purpose of resource allocation is to provide memory resources for the connected peripheral interconnection devices to support their operation. Therefore, if there are no peripheral interconnection devices under the peripheral interconnection link at the current level, it is meaningless to allocate memory resources to this peripheral interconnection link, which will cause resource waste. Therefore, no resource allocation is performed on the bridge at the current level, or the hot-plug function of the data switch is turned off, indicating that there will be no device insertion or removal operations on the current data switch. The first memory resource reserved during the startup phase will not be used due to the access or removal of devices. Therefore, the reserved first memory resource is released and allocated to other devices later to improve the resource utilization rate; If there are peripheral interconnection devices under the peripheral interconnection link at the current level, in order to enable these devices to operate normally, resource allocation is performed on the peripheral interconnection devices. If the hot-plug function of the data switch bridge is turned on, indicating that there may be device access or removal operations, resource allocation is not performed on the peripheral interconnection devices, and they are used according to the resource size set during the server startup phase to avoid device failures or data loss caused by reallocating resources; If there are peripheral interconnection devices and devices at the next level under the peripheral interconnection link at the current level, resource allocation is performed on the peripheral interconnection devices to ensure normal operation of the devices, and it is determined whether there are peripheral interconnection devices on the peripheral interconnection link at the next level to further determine whether resources need to be allocated to the devices at the next level, so as to achieve reasonable resource allocation for the entire hierarchical structure; If there are no peripheral interconnection devices connected to the peripheral interconnection link at the next level and the hot-plug function is turned off, it means that there will be no new device access or removal, so there is no need to allocate resources to this bridge to avoid resource waste. If there are peripheral interconnection devices on the peripheral interconnection link at the next level, in order to ensure the normal operation of these devices, memory resources need to be allocated to them to meet the operation requirements of the devices, or the hot-plug function at the next level is turned on, indicating that there may be device insertion or removal operations, so there is no need to reallocate the first memory resource; After resource allocation and judgment are performed on the peripheral interconnection links and devices at all levels, when the resource reallocation of the (N + 1)th layer is completed, it indicates that the resource allocation work of the entire server system has been completed. Ending the resource allocation can allow the system to enter a stable operation state, avoid unnecessary resource allocation operations, and improve the efficiency and stability of the system.

[0079] Specifically, the specific operations of the embodiments of the present invention after the server enters the operating system are as follows: 1. When the server enters the operating system, the Grub interface of the operating system defaults to adding the PCI=realloc parameter to the Grub parameters. If it is not necessary to reallocate the memory resources allocated by the BIOS under the system at this time, then this parameter is removed in the Grub file; if it is necessary to reallocate the memory resources allocated by the BIOS under the system at this time, then this parameter is retained, and at this time the operating system will reallocate all PCI resources of the server; when the system driver scans that the Hotplug function of the PCI configuration space of the PCI bridge and the Switch chip under the PCI bridge and the downstream port of the Switch chip is enabled, the resources reserved by this device at BIOS startup are retained at this time. If the Hotplug function of the PCI configuration space of the PCI bridge and the Switch chip under the PCI bridge and the downstream port of the Switch chip is disabled, the operating system will reallocate the resources already allocated by the BIOS in the DXE stage or the devices that cannot allocate 32-bit memory resources. If there is no device on the PCI bridge or the Switch chip and the downstream port of the Switch chip of the PCI link and the Hotplug function is disabled, then there is no need to allocate 32-bit memory resources. In this way, it can be ensured that the PCI devices under the system can normally obtain 32-bit memory resources and meet the usage conditions under special requirements.

[0080] 2. When reallocating resources under the operating system, it is necessary to scan the PCI bridge devices of each PCI link. Here, only one PCI link is used as an example for elaboration.

[0081] First, scan the hierarchy of the current PCI link. If a physical connection to a Switch is encountered during the scan, continue the scan until all Switch chips at all hierarchies have been scanned, and then count the final number of hierarchies. If the number of hierarchies is N, count the number of times of resource reallocation as N + 1. After scanning the hierarchies, the system will reallocate resources to the scanned hierarchies. If there are no PCI terminal devices under the bridge of the first hierarchy, this bridge will not be allocated resources, or if the Hotplug function is not enabled, the reserved resources will be released. If there are PCI terminal devices under the bridge of the first hierarchy, these terminal devices will be allocated resources. If the Hotplug function of the Switch chip bridge is enabled, the operating system will not allocate resources to this PCI device, and it can be used according to the resource size set at BIOS startup. If there are both PCI terminal devices and a lower-level bridge device under the bridge of the first hierarchy, resources need to be allocated to the PCI terminal devices and it is necessary to determine whether there are PCI terminal devices on the next-level bridge. If there are no terminal devices on the next-level bridge and the Hotplug function of the PCI configuration space of the next-level bridge is disabled, this bridge does not need to be allocated resources. If there are PCI terminal devices under the next-level bridge, resources will be allocated to the next-level bridge, or if the Hotplug function of the lower-level bridge is enabled, the system does not need to reallocate resources to this Switch, and it can be used according to the memory resources allocated at BIOS startup. Perform resource allocation for N + 1 layers in this way until the 32-bit resource allocation is completed.

[0082] When the resource allocation of all PCI devices on the server is completed, if the 4G memory resources meet all the current PCI devices, there is no problem. If there is a shortage of 4G memory resources, and when the 32-bit memory resources have been allocated to the PCI devices identified at the current hierarchy and there are no more memory resources available, the remaining PCI devices at the current hierarchy or the Switch bridge chips and PCI devices at the next hierarchy will not be allocated resources. If in the FW of the multi-hierarchy Switch chips on the PCI link, the FW of any one node's Switch chip does not support the Hotplug function, the system layer will reallocate resources for this PCI link. If in the FW of the multi-hierarchy Switch chips on the PCI link, the FW of each Switch chip hierarchy supports the Hotplug function, resources will be reserved according to the resource size obtained from the BIOS allocation at server startup and no resource reallocation will be performed.

[0083] For example, assume that there is a CPU in the server, which is connected to two PCI links (Link A and Link B). Link A contains a PCI bridge, and under the bridge is connected a Switch chip (Switch A). The downstream ports of Switch A are connected to three PCI terminal devices (Device A1, Device A2, and Device A3). Link B contains a PCI bridge, and under the bridge are connected two Switch chips (Switch B1 and Switch B2). The downstream port of Switch B1 is connected to Device C1, and the downstream port of Switch C2 is connected to Device D1 and Device D3.

[0084] When the server starts up, the BIOS enumerates and allocates resources for PCI devices in the DXE phase. 32-bit memory resources are allocated for the devices on Link A and Link B, and the Hotplug functions of some devices and bridges are enabled. For example, 512MB of resources are reserved for Device A1, 256MB for Device A2, and 128MB for Device A3; 384MB of resources are reserved for Device B1, 256MB for Device B2, and 192MB for Device B3. At the same time, the Hotplug functions of the PCI bridge on Link A, the upstream and downstream ports of Switch A are enabled; the Hotplug functions of the PCI bridge on Link B, the upstream and downstream ports of Switch B1 and Switch B2 are also enabled.

[0085] When the server enters the operating system, the PCI=realloc parameter is added by default in the Grub interface. Assume that it is desired to have the system reallocate the memory resources allocated by the BIOS, so this parameter is retained.

[0086] The system driver scans that the Hotplug function of the PCI configuration space of the PCI bridge on Link A, Switch A and its downstream ports is enabled, so the resources reserved for Devices A1, A2, and A3 during BIOS startup are retained and not reallocated; assume that during the scanning process, it is found that the Hotplug function of the PCI configuration space of a certain downstream port of Switch B2 is disabled, and the operating system will reallocate the resources already allocated by the BIOS in the DXE phase on Link B or the devices that cannot be allocated 32-bit memory resources.

[0087] The system scans the hierarchy of Link B and finds that there are two layers of Switch chips (Switch B1 and Switch B2), so the hierarchy number N = 2, and the number of times of resource reallocation is counted as N + 1 = 3 times.

[0088] First allocation (first layer: PCI bridge): Since there are two subordinate bridge devices, Switch B1 and Switch B2, under the PCI bridge of Link B, no resource allocation is performed for the PCI bridge. Second allocation (second layer: Switch B1 and Switch B2): There is a PCI terminal device C1 under Switch B1, and resource allocation is performed for device C1. Since the Hotplug function of Switch B1 is enabled, the operating system does not re-allocate the resources of Switch B1 and uses them according to the resource size allocated at BIOS startup. Third allocation (third layer: no more subordinate bridges): Since it has reached the last layer and there are no more subordinate bridges, resource allocation for devices B2 and B3 is completed.

[0089] Assume that the total sum of the 32-bit memory resources required by all PCI devices exceeds 4G. When allocating the resources of Link B, after allocating resources for devices C1 and D1, it is found that the remaining memory resources are insufficient to allocate for device D2, then device D3 will not be allocated resources; assume that the FW of Switch B1 supports the Hotplug function, but the FW of Switch B2 does not support the Hotplug function, the system layer will re-allocate the resources of Link B. If the FWs of both Switch B1 and Switch B2 support the Hotplug function, then resource reservation is performed according to the resource size obtained from the BIOS allocation at server startup and no resource re-allocation is performed.

[0090] Generally speaking, since the smart network card device requires 32-bit memory addresses and the 32-bit memory address resources of the server are limited and the maximum capacity is 4GB, it is necessary to reserve resources for the smart network card in advance. At the same time, due to the limited number of Rootports of the PCI link of the CPU and unable to accommodate more PCI devices, a Switch chip is introduced to expand the number of PCI interfaces. However, the expanded PCI interfaces also need to be physically connected to PCI devices and resources need to be reserved. Therefore, in the present invention, the BIOS reserves resources by identifying PCI interfaces or fixing PCI interfaces without connected devices at server startup. At the same time, it is necessary to enable the Hotplug function of the Switch chip and the PCI link bridge where the Switch chip is located. For Switch chips that are not used and PCI interfaces that do not require special fixing, there is no need to reserve resources and there is no need to set and enable the Hotplug function of the Switch chip and the PCI link bridge where the Switch chip is located, just turn it off.

[0091] When the server starts, the operating system also allocates resources to all devices of the server. The resource allocation includes both resource reservation allocation and the allocation of currently identified device resources. If there are too many devices when the current device starts, it will cause some device resources to be unable to be effectively allocated, that is, the 32-bit resources of 4G cannot meet the total device demand exceeding the limit of 4G, which will cause some devices to be unusable. If all the PCI link devices of the current server are directly connected to the PCI end bridge of the CPU, there is no need to worry about the shortage of 4G resources. However, if the PCI link passes through multiple levels of Switch chips or multiple PCI root bridges to connect multiple PCI Switches, there will be a problem of insufficient Switch resource reservation, which will cause the devices under the system to not work properly, especially DPU and devices that need to support the hot-plug function. To solve the problem that due to excessive resource reservation and in the system, DPU devices or hot-plug devices cannot be used in the system, the present invention realizes the problem of reallocating resources under the system by adding the pci=realloc parameter to the Grub file when the system starts. At the same time, if the Hotplug function of the Switch bridge and the Rootport of the PCI link where it is located is enabled, no memory resource reallocation will be performed. If the Hotplug function of the Switch bridge and the Rootport of the PCI link where it is located is disabled, all memory resources will be reallocated to ensure the reasonable utilization of memory resources. In this way, when the server starts and enters the operating system, the system will reallocate the MMIO32 memory resources of the entire PCI link of the server according to the closing situation of the Hotplug function attribute of the PCI link and the Grub parameter settings.

[0092] However, when there are too many Switch chips in the PCI link, the BIOS will consume too much time for resource allocation when the server starts due to the excessive number of Switch chips. At this time, in order to optimize the server startup time and ensure the fixed resource allocation of each Switch chip, the present invention sets the resources and Hotplug function of the Switch chip in the FW of the Switch chip. When the BIOS starts, it only needs to read the resource size allocated by the Switch chip without reserving resources and setting the Hotplug function for the Switch chip and the PCI ports of the downstream ports again. However, the Hotplug function of the PCI link needs to be enabled by the BIOS startup setting.

[0093] The system 10 for allocating memory resources in the firmware combination of a multi-level switch according to an embodiment of the present invention can read the first hardware resources on the peripheral interconnect link when the server starts. When the first hardware resources include at least one of a single-level switch and a multi-level switch, it identifies the second hardware resources connected to each switch and propagates the identification results of the second hardware resources connected to each switch to the firmware of the corresponding switch. Based on the identification results of the second hardware resources, the firmware allocates the first memory resources for the switch and the second hardware resources. By using the firmware of the data switch to allocate resources for the second hardware resources connected to it, there is no need for the system to sequentially read each peripheral interconnect device for resource allocation. It only needs to read the memory resource allocation set in the firmware of the switch. By implementing memory resource allocation for the switch and the hardware resources connected to the switch through the firmware, the startup duration of the server can be optimized, and the reallocation of memory resources during server startup can be avoided, thus ensuring the fixity and stability of memory resource allocation.

[0094] An embodiment of the present invention further provides a server, including the system for allocating memory resources in the firmware combination of the multi-level switch described above.

[0095] An embodiment of the present invention further provides a method for allocating memory resources in the firmware combination of a multi-level switch.

[0096] As Figure 6 shown, the method for allocating memory resources in the firmware combination of the multi-level switch includes the following steps: In step S101, at least one processing circuit connected by at least one peripheral interconnect link is used, where the at least one processing circuit is used to: execute a reading engine, and the reading engine reads the first hardware resources on the current peripheral interconnect link when the server starts; It can be understood that an embodiment of the present invention can use at least one processing circuit connected by at least one peripheral interconnect link. The at least one processing circuit is used to execute a reading engine, and the reading engine reads the first hardware resources on the current peripheral interconnect link when the server starts, so as to perform subsequent memory resource allocation.

[0097] In step S102, the read data of the first hardware resources is propagated to an identification engine, and the identification engine identifies the read data. If the first hardware resources include at least one of a single-level switch and a multi-level switch, it identifies the second hardware resources connected to each switch.

[0098] It can be understood that an embodiment of the present invention can propagate the read data of the first hardware resources to an identification engine, and the identification engine identifies the read data. If the first hardware resources include at least one of a single-level switch and a multi-level switch, it identifies the second hardware resources connected to each switch to achieve reasonable memory resource allocation for the switch when there is a switch in the peripheral interconnect link.

[0099] In step S103, the recognition result of the second hardware resource connected to each switch is propagated to the firmware of the corresponding switch. Based on the recognition result of the second hardware resource, the firmware allocates the first memory resource for the switch and the second hardware resource.

[0100] It can be understood that the embodiments of the present invention can recognize the second hardware resource connected to each switch, and propagate the recognition result of the second hardware resource connected to each switch to the firmware of the corresponding switch. Based on the recognition result of the second hardware resource, the firmware allocates the first memory resource for the switch and the second hardware resource. By using the firmware of the data switch to allocate resources for the second hardware resource connected thereto, there is no need for the system to sequentially read each peripheral interconnect device for resource allocation, and only the memory resource allocation set in the firmware of the switch needs to be read. The firmware is used to allocate memory resources for the switch and the hardware resources connected to the switch, thereby optimizing the startup duration of the server, and avoiding the reallocation of memory resources during server startup, and further ensuring the fixity and stability of memory resource allocation.

[0101] It should be noted that for the description of the features in the embodiments corresponding to the method of multi-level switch firmware combined memory resource allocation, reference can be made to the relevant description of the embodiments corresponding to the system of multi-level switch firmware combined memory resource allocation, which will not be elaborated here one by one.

[0102] According to the method of multi-level switch firmware combined memory resource allocation proposed by the embodiments of the present invention, when the server starts up, the first hardware resource on the peripheral interconnect link can be read. When the first hardware resource includes at least one of a single-level switch and a multi-level switch, the second hardware resource connected to each switch is recognized, and the recognition result of the second hardware resource connected to each switch is propagated to the firmware of the corresponding switch. Based on the recognition result of the second hardware resource, the firmware allocates the first memory resource for the switch and the second hardware resource. By using the firmware of the data switch to allocate resources for the second hardware resource connected thereto, there is no need for the server to sequentially read each peripheral interconnect device for resource allocation, and only the memory resource allocation set in the firmware of the switch needs to be read. The firmware is used to allocate memory resources for the switch and the hardware resources connected to the switch, thereby optimizing the startup duration of the server, and avoiding the reallocation of memory resources during server startup, and further ensuring the fixity and stability of memory resource allocation.

[0103] Next, a specific embodiment is used to describe the process of multi-level switch firmware combined memory resource allocation according to the embodiments of the present invention. The BIOS or the operating system controls the processing circuit, and the processing circuit performs specific operations, specifically including: 1. Server startup stage.

[0104] During the server startup phase, the execution connection relationships among the components of the multi-level switch firmware combined memory resource allocation system are as follows Figure 7 shown. During the server startup phase, the BIOS control processing circuit is in charge, which is equivalent to the BIOS performing the memory resource allocation operation during the server startup phase. Specifically: The execution engine reads the first hardware resources (including peripheral interconnect devices, single-level switches, multi-level switches, etc.), the second hardware resources connected to the switches (including peripheral interconnect ports, peripheral interconnect devices, etc.), and the identifiers of the peripheral interconnect devices; the recognition engine receives the data read by the execution engine, generates corresponding recognition results, and transmits the recognition results to the allocation engine and the firmware; the allocation engine allocates the first memory resources according to the recognition results of the first hardware resources such as peripheral interconnect devices and peripheral interconnect ports and sets the hot-plug function, and the firmware allocates the first memory resources for the corresponding switches and the second hardware resources connected to the switches according to the recognition results of the switches in the first hardware resources and sets the hot-plug function; after the first memory resource allocation is completed, the startup engine is executed, and the startup engine starts the operating system of the server.

[0105] The following combines Figure 7 the execution connection relationship diagram among the components during the startup phase shown below to describe the specific execution process of the memory resource allocation during the server startup phase. The process is as follows Figure 8 shown, including: 1. When the server starts up, the BIOS confirms whether the current device is a DPU device by reading the DID and VID of each PCI device during the PCI enumeration phase of the DXE phase. If it is not, 32-bit memory resources are normally allocated; if it is a DPU device, 32-bit resource reservation is performed according to the known 32-bit resource size of the DPU; at the same time, when the PCI link physically connected to the current DPU counts the 32-bit resources required by other PCI devices, the MMIO 32-bit resources reserved by the DPU are accumulated. At the same time, the BIOS enables the hot-plug function, that is, turns on the Hotplug function, of the PCI configuration space of the bridge of the PCI link physically connected to the DPU.

[0106] 2. During the PCI enumeration phase, the BIOS continues to determine whether the current PCI link without a Switch chip is a specific PCI port. If it is, 32-bit memory resource reservation is performed. If it is not and there is a PCI Switch chip, the BIOS no longer enables the Hotplug function for the upstream and downstream ports of the Switch chip. The PCI device resource allocation for the upstream and downstream ports of the Switch chip is mainly based on the settings in the Switch FW. The BIOS only reads the actual memory resource sizes required for the upstream and downstream ports of the Switch chip and the PCI devices. At the same time, the BIOS enables the Hotplug function for the PCI configuration space of the PCI link of the Switch chip scanned during the PCI enumeration phase of DXE because the enabling setting of the PCI link bridge can only be performed by the BIOS.

[0107] Among them, after the BIOS determines that there is a Switch chip in the PCI link, the process of reading the FW firmware parameters of the Switch chip is as Figure 9 shown. The BIOS only needs to read the actual memory resource sizes required for the upstream and downstream ports of the Switch chip and the PCI devices. At the same time, the BIOS enables the Hotplug function for the PCI configuration space of the PCI link of the Switch chip scanned during the PCI enumeration phase of DXE. The FW of the Switch chip reserves the memory resource sizes for the PCI ports that need to support the hot-plug function under the Switch. At the same time, the Hotplug function for the PCI configuration spaces of the upstream and downstream ports where the Switch chip reserves memory resources is enabled. All Switch chips in the server perform resource reservation and Hotplug function enabling according to this method.

[0108] 3. Poll all PCI links and the corresponding Switch chips and their devices under the PCI links in sequence according to steps 1 and 2. After polling all the PCI links and Switch chips of all CPUs, continue to start and enter the operating system.

[0109] II. Server entering the operating system phase.

[0110] The execution connection relationships among the various components of the multi-level switch firmware combined memory resource allocation system during the server entering the operating system phase are as Figure 10As shown, the operating system control processing circuit of the server, which is equivalent to the stage of the server entering the operating system, performs the reallocation of the first memory resource by the operating system. Specifically: the execution reading engine reads the memory allocation function of the server and reads whether there is a need for memory resource reallocation; the allocation engine deletes the memory allocation function (i.e., does not reallocate memory resources) or reallocates the first memory resource according to the result of the memory resource reallocation requirement read by the reading engine; after recognizing the instruction to reallocate the first memory resource, the scanning engine is executed. The scanning engine is used for the hierarchical structure of the peripheral interconnect link, hardware resources, setting of the hot-plug function, etc., and transmits the scanned data to the recognition engine; the recognition engine is used to recognize the scanned data and transmit it to the allocation engine; the allocation engine reallocates the first memory resource.

[0111] The following combines Figure 10 the execution connection relationship diagram among the components in the startup stage shown to describe the specific execution process of the memory resource allocation in the stage of the server entering the operating system. The process is as Figure 11 shown, including: 1. When the server enters the operating system, the Grub interface of the operating system defaults to adding the PCI=realloc parameter to the Grub parameters. If there is no need to reallocate the memory resources allocated by the BIOS under the system at this time, this parameter is removed in the Grub file; if there is a need to reallocate the memory resources allocated by the BIOS under the system at this time, this parameter is retained, and at this time the operating system will reallocate all PCI resources of the server; when the system driver scans that the PCI configuration space Hotplug function of the PCI bridge and the Switch chips under the PCI bridge and the downstream ports of the Switch chips is enabled, the resources reserved by this device at the BIOS startup are retained at this time. If the PCI configuration space Hotplug function of the PCI bridge and the Switch chips under the PCI bridge and the downstream ports of the Switch chips is disabled, the operating system will reallocate the resources already allocated by the BIOS in the DXE stage or the devices that cannot allocate 32-bit memory resources. If there are no devices on the PCI bridge or the Switch chips and the downstream ports of the Switch chips of the PCI link and the Hotplug function is disabled, there is no need to allocate 32-bit memory resources. In this way, it can be ensured that the PCI devices under the system can normally obtain 32-bit memory resources and meet the usage conditions under special requirements; 2. When reallocating resources under the operating system, it is necessary to scan the PCI bridge devices of each PCI link. Here, only one PCI link is taken as an example for illustration; first, scan the hierarchy of the current PCI link. If a physical connection of the Switch is encountered during the scanning process, continue the scanning until all levels of Switch chips are scanned and the final number of levels is counted. If the number of levels is N, the number of times of reallocating resources is counted as N + 1; after scanning the levels, the system reallocates resources to the scanned levels. If there is no PCI terminal device under the bridge of the first level, this bridge will not be allocated resources, or if the Hotplug function is not enabled, the reserved resources will be released; If there is a PCI terminal device under the bridge of the first level, resources will be allocated to this terminal device. If the Hotplug function of the Switch chip bridge is enabled, the operating system will not allocate resources to this PCI device, and it can be used according to the resource size set at BIOS startup; If there is a PCI terminal device and a lower-level bridge device under the bridge of the first level, it is necessary to allocate resources to the PCI terminal device and determine whether there is a PCI terminal device on the next-level bridge. If there is no terminal device on the next-level bridge and the Hotplug function of the PCI configuration space of the next-level bridge is turned off, this bridge does not need to be allocated resources. If there is a PCI terminal device under the next-level bridge, resources will be allocated to the next-level bridge, or if the Hotplug function of the lower-level bridge is enabled, the system does not need to reallocate resources for this Switch, and it can be used according to the memory resources allocated at BIOS startup. In this way, resource allocation is carried out for N + 1 levels until 32-bit resource allocation is completed; When the resource allocation of all PCI devices of the server is completed, if the 4G memory resources meet all the current PCI devices, there is no problem. If the 4G memory resources are insufficient, when the 32-bit memory resources are allocated to the PCI devices identified at the current level and there is no memory resource available for allocation, the remaining PCI devices at the current level or the Switch bridge chips and PCI devices at the next level will not be allocated resources; if in the FW of the multi-level Switch chips of the PCI link, the FW of any one node's Switch chip does not support the Hotplug function, the system layer will reallocate resources for this PCI link. If in the FW of the multi-level Switch chips of the PCI link, the FW of each Switch chip level supports the Hotplug function, resources will be reserved according to the resource size obtained by the BIOS allocation at server startup and no resource reallocation will be performed.

[0112] In summary, for the method of allocating memory resources for the multi-level switch firmware combination of the present invention, when the server starts up, the BIOS is used to determine whether there is a Switch chip on the PCI link. If not, the PCI devices on the PCI link are directly judged, especially the DPU or specific PCI devices are actively identified, and the Hotplug function of the PCI configuration space of the bridge on the PCI link where the DPU and specific devices are located is enabled. For the normally identified PCI devices, resource allocation is performed in the normal mode and the Hotplug function of the PCI link where they are located is turned off. However, for specific ports of the PCI link, resources are reserved and the Hotplug function of the PCI link is enabled, while other PCI links are not allocated resources and the corresponding Hotplug functions of the PCI links are turned off. When there is a PCI link Switch chip, it is judged whether the downstream ports of the Switch chip need to reserve resources to support the hot-plug function under the system and there are no PCI devices, or there are PCI devices on the downstream ports.

[0113] When the above two situations occur, the Hotplug functions of the upstream and downstream ports of the Switch chip and the PCI configuration space of the PCI link bridge are set to be enabled. If there are no special requirements, the Hotplug function of the Switch chip is turned off to facilitate re-allocation of resources under the system. In this way, the PCI devices of other PCI link bridges are polled in turn until all are completed and the system boots into the operating system interface.

[0114] Since the above operations are performed by the BIOS, it affects the server startup time and cannot guarantee accuracy when there are too many Switch chips. Therefore, it is adjusted that if there is a PCI Switch chip, the BIOS directly reads the memory resource sizes of the upstream and downstream ports of the Switch chip FW and allocates them. Because the upstream and downstream ports of the Switch chip FW have been set to enable Hotplug and are managed by the Switch chip FW, at this time, there is no need for the BIOS to set the Hotplug functions of the upstream and downstream ports of the Switch chip. The BIOS needs to enable the Hotplug function of the PCI link bridge where the Switch chip is located. This method is convenient and fast, and improves the resource allocation efficiency.

[0115] After the server enters the operating system, if there is no need for the system to reallocate memory resources, the PCI=realloc parameter will be removed. If needed, the PCI=realloc parameter will be set in the Grub parameters using the default settings. Therefore, the operating system will reallocate memory resources. Even if the BIOS has completed the memory resource allocation (such as the 32-bit memory resource allocation), the system will still perform a new memory resource allocation. Because the memory resources are limited and the location information of the DPU and specific PCI devices cannot be fixed, according to the function of the parameters, the PCI devices recognized later will have no resources available for allocation because the memory resources have already been allocated. However, the PCI links with the Hotplug function enabled do not need to reallocate memory resources.

[0116] At the same time, the system will scan the Switch level. If there is an N-level Switch chip, an N+1 times resource reallocation scheme will be performed on the Switch chip. And the Hotplug function must be enabled for the upstream and downstream ports of each Switch chip and the bridge of the PCI link where the Switch chip is located. If the Hotplug function of any node in the entire link is not enabled, resource reallocation will be performed. If all are enabled, the memory resources allocated during BIIOS startup will be used for allocation; when reallocating memory resources, with the scanned Switch level being N and the scan times being N+1, 32-bit memory resources will be allocated to the PCI devices starting from N+1. When the N+1 memory resource allocation is completed, the PCI devices at the N level will be allocated resources until all devices of the PCI link bridge have completed resource allocation. If there is a shortage of 32-bit memory resources, the memory resource allocation for the Switch chips and PCI devices at the subsequent levels will be abandoned; therefore, the BIOS defaults to enabling the Hotplug function for the PCI link where the DPU and specific PCI devices are located, and enabling the Hotplug function for the upstream and downstream ports of the Switch chips of the PCI link and the PCI link bridge, to prevent the system from reallocating again and causing the DPU and specific PCI devices to be unable to be used normally. If the Hotplug function where the DPU and specific PCI devices are located is turned off and the DPU device has exhausted the 32-bit memory resources, it will cause the resources of the DPU and specific PCI devices to be released and unable to meet the memory resource requests during normal use. Therefore, problems such as the DPU being unable to display or the functions of the DPU or specific PCI devices being unable to be used normally will occur. Through the above settings, it can be ensured that the DPU and specific PCI devices can be used normally at any time without worrying about resource problems causing the DPU to be unable to be used.

[0117] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0118] An embodiment of the present invention also provides a computer-readable storage medium, in which a computer program is stored, and the computer program is configured to execute the steps in any one of the method embodiments for allocating memory resources of the multi-level switch firmware combination when running.

[0119] In an exemplary embodiment, the above computer-readable storage medium may include, but is not limited to: USB flash drive, read-only memory (ROM for short), random access memory (RAM for short), mobile hard disk, magnetic disk or optical disc and other media that can store computer programs.

[0120] An embodiment of the present invention also provides a computer program product, the computer program product includes a computer program, and when the computer program is executed by a processor, it implements the steps in any one of the method embodiments for allocating memory resources of the multi-level switch firmware combination.

[0121] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed in this article can be implemented by electronic hardware, computer software or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.

[0122] The above has introduced in detail a method for allocating memory resources provided by the present invention. Specific examples are used in this article to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. It should be pointed out that for those of ordinary skill in the art of this technology, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

Claims

1. A system for allocating memory resources of a multi - level switch firmware combination, characterized in that, Comprising: At least one processing circuit of the server, the at least one processing circuit being connected to at least one peripheral interconnect link, the at least one processing circuit being configured to: Execute a reading engine, the reading engine reading a first hardware resource on the current peripheral interconnect link when the server starts up; Propagate the read data of the first hardware resource to an identification engine, the identification engine identifying the read data, and if the first hardware resource includes at least one of a single-layer switch and a multi-layer switch, identifying a second hardware resource connected to each switch; Propagate the identification result of the second hardware resource connected to each switch to the firmware of the corresponding switch, and the firmware allocates a first memory resource for the switch and the second hardware resource based on the identification result of the second hardware resource.

2. The system for allocating memory resources of the multi-level switch firmware combination according to claim 1, characterized in that, The firmware is configured to: If the second hardware resource includes a peripheral interconnect device, allocate a first memory resource for the peripheral interconnect device according to the target setting of the firmware; If the second hardware resource includes a peripheral interconnect port, allocate a first memory resource for the peripheral interconnect port when the peripheral interconnect port needs to support the hot-plug function.

3. The system for allocating memory resources of the multi-level switch firmware combination according to claim 1, wherein The at least one processing circuit is configured to: If the first hardware resource includes a peripheral interconnect device, propagate the read data to an allocation engine, and the allocation engine allocates a first memory resource for the peripheral interconnect device.

4. The system for allocating memory resources of the multi-level switch firmware combination according to claim 3, wherein The at least one processing circuit is configured to: Execute a reading engine, the reading engine reading an identifier of the peripheral interconnect device; Propagate the identifier of the peripheral interconnect device to an identification engine, and the identification engine identifies whether the peripheral interconnect device is a data processor based on the identifier; The allocation engine allocates a first memory resource according to the resource size of the data processor when the peripheral interconnect device is a data processor.

5. The system for allocating memory resources of the multi-level switch firmware combination according to claim 3, characterized in that The allocation engine is configured to: When a peripheral interconnect port is connected to the current peripheral interconnect link, if the peripheral interconnect port is a target port, allocate a first memory resource for the peripheral interconnect port.

6. The system for allocating memory resources of the multi-level switch firmware combination according to any one of claims 1-5, characterized in that, The firmware sets the hot-plug function for the upstream and downstream ports of the switch that has been allocated the first memory resource.

7. The system for allocating memory resources of the multi-level switch firmware combination according to any one of claims 1-5, characterized in that, The at least one processing circuit is configured to: Start an allocation engine, and the allocation engine sets the hot-plug function for the peripheral interconnect link where the switch that has been allocated the first memory resource is located.

8. The system for allocating memory resources of the multi-level switch firmware combination according to claim 1, wherein The at least one processing circuit is configured to: When the identification engine polls all peripheral interconnect links, the first hardware resource, and the second hardware resource, execute a startup engine, and the startup engine starts the operating system of the server.

9. The system for allocating memory resources of the multi-level switch firmware combination according to claim 8, wherein The at least one processing circuit is configured to: After the server enters the operating system, execute the reading engine, and the reading engine reads the memory allocation function of the server; An allocation engine reallocates the first memory resource of the server according to the memory allocation function.

10. The system for allocating memory resources of the multi-level switch firmware combination according to claim 8, wherein, The at least one processing circuit is configured to: Before reallocating the first memory resource of the server according to the memory allocation function, execute the reading engine, and the reading engine reads the reallocation requirement of the server; The allocation engine reallocates the first memory resource of the server according to the reallocation requirement and the memory allocation function.

11. The system for allocating memory resources of the multi-level switch firmware combination according to claim 9, wherein If the reading engine does not read the reallocation requirement of the server, the allocation engine deletes the memory allocation function and retains the allocation parameters of the first memory resource in the server startup phase.

12. The system for allocating memory resources of the multi-level switch firmware combination according to claim 9, wherein, The at least one processing circuit is configured to: Execute a scanning engine that scans all the peripheral interconnect links of the server; Propagate the scanning data of the scanning engine to an identification engine that identifies the scanning data. If it identifies that the current peripheral interconnect link, the first hardware resource connected to the current peripheral interconnect link, and the switch connected to the current peripheral interconnect link enable the hot plug function, then retain the first memory resource allocated to the current peripheral interconnect link in the server startup phase.

13. The system for allocating memory resources of the multi-level switch firmware combination according to claim 12, characterized in that, The identification engine is configured to: If it identifies that the current peripheral interconnect link, the first hardware resource connected to the current peripheral interconnect link, and the switch connected to the current peripheral interconnect link disable the hot plug function, the allocation engine reallocates the first memory resource of the server according to the memory allocation function.

14. The system for allocating memory resources of the multi-level switch firmware combination according to claim 12, wherein The identification engine is configured to: If it identifies that the current peripheral interconnect link is idle, or the switch connected to the current peripheral interconnect link is idle, then stop allocating the first memory resource of the server.

15. The system for allocating memory resources of a multi-level switch firmware combination according to any one of claims 9-14, characterized in that, The at least one processing circuit is configured to: Execute a scanning engine that scans the current peripheral interconnect link level; Propagate the scanning data of the scanning engine to an identification engine that identifies the scanning data. If the current peripheral interconnect link level is N, the number of reallocations of the first memory resource is N + 1; The allocation engine allocates the first memory resource according to the number of reallocations.

16. The system for allocating memory resources of the multi-level switch firmware combination according to claim 15, wherein, The at least one processing circuit is configured to: Execute a reading engine that reads the second memory resource of the server; Propagate the remaining resources of the second memory resource to the identification engine that identifies whether the remaining resources are less than a resource threshold; Propagate the identification result of the identification engine to the allocation engine, and the allocation engine stops allocating the first memory resource of the hardware resource at the current level or the next level when the remaining resources are less than the resource threshold.

17. The system for allocating memory resources of the multi-level switch firmware combination according to claim 16, wherein, The allocation engine is configured to: If any firmware of the multi-level switch does not support the hot plug function, reallocate the first memory resource of the peripheral interconnect link where the firmware that does not support the hot plug function is located; If all the firmware of the multi-level switch supports the hot plug function, retain the allocation parameters of the first memory resource in the server startup phase.

18. A server, characterized in that, A system including the multi-level switch firmware combination memory resource allocation according to any one of claims 1 to 17.

19. A method for allocating memory resources of a multi-level switch firmware combination, characterized in that, Comprising: At least one processing circuit connected by at least one peripheral interconnect link, wherein the at least one processing circuit is configured to: Execute a reading engine that reads the first hardware resource on the current peripheral interconnect link when the server starts up; Propagate the read data of the first hardware resource to the recognition engine, and the recognition engine recognizes the read data. If the first hardware resource includes at least one of a single-layer switch and a multi-layer switch, recognize the second hardware resource connected to each switch; Propagate the recognition result of the second hardware resource connected to each switch to the firmware of the corresponding switch, and the firmware allocates the first memory resource for the switch and the second hardware resource based on the recognition result of the second hardware resource.

20. A computer-readable storage medium, characterized in that, A computer program is stored in the computer-readable storage medium, wherein when the computer program is executed by a processor, the steps of the method for allocating combined memory resources of the multi-layer switch firmware as described in claim 19 are implemented.

21. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, the steps of the method for allocating combined memory resources of the multi-layer switch firmware as described in claim 19 are implemented.

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