Display device

Abstract

A display device includes: a substrate including a display area in which a plurality of sub-pixels are disposed and a non-display area located outside the display area and including a pad area, and having a first groove in the non-display area; a first inorganic layer disposed on the substrate, extending from the display area to the non-display area, and having a second groove in the non-display area, the second groove being closer to the display area than the first groove; an organic layer disposed on a portion of the first inorganic layer in the non-display area, and filling the second groove; the second inorganic layer extends from the display area to the non-display area, is arranged on the first inorganic layer to cover the organic layer, and extends into the first groove; and a third inorganic layer, which extends from the display area to the non-display area, is disposed on the second inorganic layer, and extends into the first groove.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0195451, filed on December 28, 2023, which is incorporated herein by reference in its entirety for all purposes as if fully set forth herein. Technical field

[0003] Embodiments of the present disclosure relate to a display device. Background art

[0004] The display panel of a display device may include a display area for displaying an image and a non - display area for not displaying an image. Various structures, circuits, and interconnections may be provided in the non - display area (also referred to as the "bezel") of the display panel. Due to this fact, it is not easy to reduce the bezel of the display panel.

[0005] In addition, when the display panel is designed to reduce the bezel, the possibility of cracks appearing in the display panel increases, which may cause moisture penetration and lead to panel defects. Summary of the invention

[0006] Embodiments of the present disclosure may provide a display device that can prevent moisture penetration while achieving a narrow bezel.

[0007] Embodiments of the present disclosure may provide a display device that can prevent layer lifting phenomenon while achieving a narrow bezel.

[0008] A display device according to an embodiment of the present disclosure may include: a substrate including a display area in which a plurality of sub - pixels are disposed and a non - display area located outside the display area and including a pad area, and having a first groove in the non - display area; a first inorganic layer disposed on the substrate, extending from the display area to the non - display area, and having a second groove in the non - display area, the second groove being closer to the display area than the first groove; an organic layer disposed on a part of the first inorganic layer in the non - display area and filling the second groove; a second inorganic layer extending from the display area to the non - display area, disposed on the first inorganic layer to cover the organic layer, and extending into the interior of the first groove; and a third inorganic layer extending from the display area to the non - display area, disposed on the second inorganic layer, and extending into the interior of the first groove.

[0009] The display device according to an embodiment of the present disclosure may further include a touch insulating layer that extends from the display area to the non-display area, is disposed on the third inorganic layer, and overlaps with the organic layer.

[0010] The first inorganic layer may include at least one inorganic layer for forming a transistor.

[0011] The display device according to an embodiment of the present disclosure may further include: a light-emitting element disposed between the first inorganic layer and the second inorganic layer in the display area; and a encapsulation layer on the light-emitting element. The second inorganic layer and the third inorganic layer may be included in the encapsulation layer.

[0012] In the display device according to an embodiment of the present disclosure, the first inorganic layer may include a first insulating layer on the substrate; and a second insulating layer on the first insulating layer. The second groove may correspond to a hole formed in the second insulating layer.

[0013] The display device according to an embodiment of the present disclosure may further include a barrier metal disposed on the first insulating layer.

[0014] Both ends of the barrier metal may be located between the first insulating layer and the second insulating layer, and a portion between both ends of the barrier metal may overlap with the second groove.

[0015] The display device according to an embodiment of the present disclosure may include: a substrate including a display area for displaying an image and a non-display area that is an area outside the display area, and having a first groove in the non-display area; a first inorganic layer disposed on the substrate, extending from the display area to the non-display area, and having a second groove in the non-display area, the second groove being closer to the display area than the first groove; a planarization layer on the first inorganic layer; an organic layer disposed on a part of the first inorganic layer in the non-display area and filling the second groove; a light-emitting element on the planarization layer; a first inorganic encapsulation layer (corresponding to the above-mentioned second inorganic layer) on the light-emitting element; an organic encapsulation layer on the first inorganic encapsulation layer; and a second inorganic encapsulation layer (corresponding to the above-mentioned third inorganic layer) on the organic encapsulation layer.

[0016] The first inorganic encapsulation layer may extend from the display area to the non-display area, may be disposed on the first inorganic layer to cover the organic layer, and may extend into the interior of the first groove.

[0017] The second inorganic encapsulation layer may extend from the display area to the non-display area, may be disposed on the second inorganic layer, and may extend into the interior of the first groove.

[0018] The display device according to an embodiment of the present disclosure may further include a touch insulation layer that extends from the display area to the non-display area, is disposed on the second inorganic encapsulation layer, and overlaps with the organic layer.

[0019] According to an embodiment of the present disclosure, a display device may be provided that can prevent moisture penetration while achieving a narrow bezel.

[0020] According to an embodiment of the present disclosure, a display device may be provided that can prevent layer lifting while achieving a narrow bezel.

[0021] According to an embodiment of the present disclosure, by having a narrow bezel structure, the weight reduction of the display device can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 is a system configuration diagram of a display device according to an embodiment of the present disclosure.

[0023] Figure 2 shows a display panel according to an embodiment of the present disclosure.

[0024] Figure 3 shows a substrate of a display panel according to an embodiment of the present disclosure.

[0025] Figure 4 is a cross-sectional view of a display panel according to an embodiment of the present disclosure.

[0026] Figure 5 and Figure 6 are cross-sectional views of some bezel regions having a narrow bezel structure and a moisture penetration prevention structure in a display panel according to an embodiment of the present disclosure.

[0027] Figures 7 to 9 is an example of the structure of an organic layer for forming a narrow bezel structure and a moisture penetration prevention structure in a display panel according to an embodiment of the present disclosure.

[0028] Figure 10 and Figure 11 are examples of the structure of a first groove for forming a narrow bezel structure and a moisture penetration prevention structure in a display panel according to an embodiment of the present disclosure.

[0029] Figure 12A cross-sectional view of another border area having a narrow border structure and a moisture-proof penetration structure in a display panel according to an embodiment of the present disclosure. Detailed implementation manners

[0030] Now, embodiments of the present disclosure will be described in detail, and examples thereof can be shown in the drawings. In the following description, the same elements will be denoted by the same reference numerals, although they are shown in different drawings. In addition, in the following description of the present disclosure, when the detailed description of known functions and configurations incorporated herein may obscure the subject matter of the present disclosure, the detailed description of the known functions and configurations incorporated herein will be omitted. It should be noted that unless otherwise specifically stated, the terms "comprising", "having", "including", etc. used in the specification and claims should not be construed as being limited to the devices listed thereafter. When an indefinite article or a definite article is used in reference to a singular noun, such as "a", "an", and "the", this may include the plural of the noun, unless otherwise specifically stated.

[0031] In addition, when describing the components of the present disclosure, terms such as first, second, A, B, (a), and (b) may be used. These are only for the purpose of distinguishing one component from another, but do not limit the substance, order, sequence, or quantity of the components.

[0032] When referring to the first element being "connected or coupled", "contacting or overlapping" with the second element, etc., it should be interpreted that not only can the first element be "directly connected or coupled" or "directly contacting or overlapping" with the second element, but also a third element can be "inserted" between the first and second elements, or the first and second elements can be "connected or coupled", "contacting or overlapping", etc. with each other via a fourth element. Here, another component may be included in at least one of at least two components that are "connected", "coupled", or "linked" to each other.

[0033] In the description of the time flow relationship of components, operation methods, or manufacturing methods, in the case of describing the front-back relationship in terms of time or the front-back relationship in terms of process, such as "after", "behind", "next", or "before", unless "immediately" or "directly" is used, non-consecutive cases may be included.

[0034] In the case of referring to the numerical value of a component or its corresponding information (such as level, etc.), even if there is no separate explicit description, the numerical value or its corresponding information can be interpreted as including an error range that may be caused by various factors (such as process variables, internal or external shocks, noise, etc.).

[0035] Hereinafter, various embodiments of the disclosed technology will be described in detail with reference to the drawings.

[0036] Figure 1It is a system configuration diagram of the display device 100 according to an embodiment of the present disclosure.

[0037] Reference Figure 1 , according to an embodiment of the present disclosure, the display device 100 may include a display panel 110 and a display driving circuit as components for displaying an image. The display driving circuit as a circuit for driving the display panel 110 may include a data driving circuit 120, a gate driving circuit 130, and a display controller 140.

[0038] The display panel 110 may include a substrate SUB and a plurality of sub-pixels SP provided on the substrate SUB.

[0039] The substrate SUB of the display panel 110 may include a display area DA capable of displaying an image and a non-display area NDA located outside the display area DA.

[0040] The plurality of sub-pixels SP for displaying an image may be provided in the display area DA, and the non-display area NDA may include a pad area located in a first direction starting from the display area DA.

[0041] In the display panel 110 according to an embodiment of the present disclosure, the non-display area NDA may be very small. In this specification, the non-display area NDA may also be referred to as a "bezel".

[0042] For example, the non-display area NDA may include a first non-display area located outside the display area DA in a first direction, a second non-display area located outside the display area DA in a second direction different from the first direction, a third non-display area located outside the display area DA in a direction opposite to the first direction, and a fourth non-display area located outside the display area DA in a direction opposite to the second direction. One or two of the first to fourth non-display areas may include a pad area connected or bonded to the data driving circuit 120. Two or three of the first to fourth non-display areas that do not include the pad area may be very small in size. For example, the first non-display area may include the pad area, and the second non-display area, the third non-display area, and the fourth non-display area may be very small in size.

[0043] Again, for example, the boundary area between the display area DA and the non-display area NDA may be curved, so that the non-display area NDA may be located below the display area DA. In this case, when a user views the display device 100 from the front, the user may hardly see or not see the non-display area NDA. For the user, the display device 100 may appear to be borderless.

[0044] Various types of signal lines for driving the plurality of sub-pixels SP may be provided on the substrate SUB of the display panel 110.

[0045] The display device 100 according to an embodiment of the present disclosure may be a liquid crystal display device or the like, or may be a self-emissive display device in which the display panel 110 emits light by itself. When the display device 100 according to an embodiment of the present disclosure is a self-emissive display device, each of the plurality of sub-pixels SP may include a light-emitting element.

[0046] For example, the display device 100 according to an embodiment of the present disclosure may be an organic light-emitting display device that uses an organic light-emitting diode (OLED) to implement a light-emitting element. As another example, the display device 100 according to an embodiment of the present disclosure may be an inorganic light-emitting display device in which an inorganic-based light-emitting diode is used to implement a light-emitting element. As still another example, the display device 100 according to an embodiment of the present disclosure may be a quantum dot display device in which quantum dots are used as self-luminous semiconductor crystals to implement a light-emitting element.

[0047] The structure of each of the plurality of sub-pixels SP may vary according to the type of the display device 100. For example, when the display device 100 is a self-emissive display device in which each sub-pixel SP emits light by itself, each sub-pixel SP may include a self-luminous emission element, at least one transistor, and at least one capacitor.

[0048] For example, various types of signal lines may include a plurality of data lines DL that transmit data signals (also referred to as data voltages or image signals) and a plurality of gate lines GL that transmit gate signals (also referred to as scan signals).

[0049] For example, the plurality of data lines DL and the plurality of gate lines GL may cross each other. Each of the plurality of data lines DL may be set to extend in a first direction, and each of the plurality of gate lines GL may be set to extend in a second direction. The first direction may be a column direction, and the second direction may be a row direction. Alternatively, the first direction may be a row direction, and the second direction may be a column direction. Hereinafter, for ease of explanation, it will be described as an example that each of the plurality of data lines DL is set along the column direction, and each of the plurality of gate lines GL is set along the row direction.

[0050] A data driving circuit 120, which is a circuit for driving the plurality of data lines DL, may output data signals to the plurality of data lines DL.

[0051] The data driving circuit 120 may receive digital-type image data DATA from the display controller 140, may convert the received image data DATA into an analog-type data signal, and may output the data signal to the plurality of data lines DL.

[0052] For example, the data driving circuit 120 may be connected to the display panel 110 by a tape automated bonding (TAB) method, may be connected to a bonding pad of the display panel 110 by a chip on glass (COG) or chip on panel (COP) method, or may be connected to the display panel 110 by being implemented by a chip on film (COF) method.

[0053] The data driving circuit 120 may be connected to one side (e.g., the upper side or the lower side) of the display panel 110. In contrast, depending on the driving method, the panel design method, etc., the data driving circuit 120 may be connected to both sides (e.g., the upper side and the lower side) of the display panel 110, or may be connected to at least two sides among the four sides of the display panel 110.

[0054] The data driving circuit 120 may be connected to the outside of the display area DA of the display panel 110, but in contrast, may be disposed in the display area DA of the display panel 110.

[0055] The gate driving circuit 130, which is a circuit for driving a plurality of gate lines GL, may output a gate signal to the plurality of gate lines GL.

[0056] A first gate voltage corresponding to a conduction level voltage, a second gate voltage corresponding to a turn-off level voltage, and various gate driving control signals GCS may be provided to the gate driving circuit 130, a gate signal may be generated, and the generated gate signal may be provided to the plurality of gate lines GL.

[0057] In the display device 100 according to an embodiment of the present disclosure, the gate driving circuit 130 may be embedded in the display panel 110 in a gate in panel (GIP) type. When the gate driving circuit 130 is of the gate in panel (GIP) type, the gate driving circuit 130 may be formed on the substrate SUB of the display panel 110 during the manufacturing process of the display panel 110.

[0058] In the display device 100 according to an embodiment of the present disclosure, the gate driving circuit 130 may be disposed in the display area DA of the display panel 110. For example, the gate driving circuit 130 may be disposed in a first partial area (e.g., the left area or the right area in the display area DA) in the display area DA. Again, for example, the gate driving circuit 130 may be disposed in a first partial area (e.g., the left area or the right area in the display area DA) and a second partial area (e.g., the right area or the left area in the display area DA) in the display area DA. Still again, for example, the gate driving circuit 130 may be disposed by being distributed throughout the display area DA.

[0059] In the present disclosure, the gate driving circuit 130 in the gate-in-panel (GIP) type embedded display panel 110 is referred to as the "in-panel gate circuit".

[0060] The display controller 140, as a device for controlling the data driving circuit 120 and the gate driving circuit 130, can control the driving timing for multiple data lines DL and the driving timing for multiple gate lines GL.

[0061] The display controller 140 can provide a data driving control signal DCS to the data driving circuit 120 to control the data driving circuit 120, and can provide a gate driving control signal GCS to the gate driving circuit 130 to control the gate driving circuit 130.

[0062] The display controller 140 can receive input image data from the host system 150 and can provide the image data to the data driving circuit 120 based on the input image data.

[0063] The display controller 140 can be implemented as a component separate from the data driving circuit 120, or can be implemented as an integrated circuit by being integrated with the data driving circuit 120.

[0064] The display controller 140 can be a timing controller used in general display technologies, can be a control device including a timing controller and capable of further performing other control functions, can be a control device different from the timing controller, or can be a circuit in the control device. The display controller 140 can be implemented by various circuits or electronic components, such as an integrated circuit (IC), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), and a processor.

[0065] The display controller 140 can be mounted on a printed circuit board, a flexible printed circuit, etc., and can be electrically connected to the data driving circuit 120 and the gate driving circuit 130 through a printed circuit board, a flexible printed circuit, etc.

[0066] The display controller 140 can transmit signals to and receive signals from the data driving circuit 120 according to at least one predetermined interface. For example, the interface can include a low voltage differential signaling (LVDS) interface, an EPI (embedded clock point-to-point interface), a serial peripheral interface (SPI), etc.

[0067] To further provide a touch sensing function as well as an image display function, the display device 100 according to an embodiment of the present disclosure can include a touch sensor and a touch sensing circuit 160. The touch sensing circuit 160 detects whether a touch event has occurred on a touch object (such as a finger or a pen) or detects the touch position by sensing the touch sensor.

[0068] The touch sensing circuit 160 may include a touch driving circuit 170 and a touch controller 180. The touch driving circuit 170 generates and outputs touch sensing data by driving and sensing a touch sensor, and the touch controller 180 can use the touch sensing data to detect the occurrence of a touch event or detect a touch position.

[0069] The touch sensor may include a plurality of sensor electrodes. The touch sensor may also include a plurality of touch lines for electrically connecting the plurality of sensor electrodes and the touch driving circuit 170.

[0070] The touch sensor may exist outside the display panel 110 in the form of a touch panel, or may exist inside the display panel 110. When the touch sensor exists outside the display panel 110 in the form of a touch panel, the touch sensor may be referred to as an external type. When the touch sensor is of the external type, the touch panel and the display panel 110 may be separately manufactured and coupled during the assembly process. The external touch panel may include a substrate for the touch panel and a plurality of sensor electrodes on the substrate for the touch panel.

[0071] When the touch sensor exists inside the display panel 110, the touch sensor may be formed on the substrate SUB together with signal lines and electrodes related to display driving during the process of manufacturing the display panel 110.

[0072] The touch driving circuit 170 may generate touch sensing data by providing a touch driving signal to at least one of the plurality of sensor electrodes and sensing at least one of the plurality of sensor electrodes.

[0073] The touch sensing circuit 160 may perform touch sensing in a self - capacitance sensing mode or a mutual - capacitance sensing mode.

[0074] When the touch sensing circuit 160 performs touch sensing in a self - capacitance sensing mode, the touch sensing circuit 160 may perform touch sensing based on the capacitance between each sensor electrode and a touch object (e.g., a finger, a pen, etc.). According to the self - capacitance sensing method, each of the plurality of sensor electrodes can be used as both a driving sensor electrode and a sensing sensor electrode. The touch driving circuit 170 may drive all or some of the plurality of sensor electrodes, and may sense all or some of the plurality of sensor electrodes.

[0075] When the touch sensing circuit 160 performs touch sensing in a mutual - capacitance sensing mode, the touch sensing circuit 160 may perform touch sensing based on the capacitance between sensor electrodes. According to the mutual - capacitance sensing method, the plurality of sensor electrodes are divided into driving sensor electrodes and sensing sensor electrodes. The touch driving circuit 170 may drive the driving sensor electrodes and sense the sensing sensor electrodes.

[0076] The touch driving circuit 170 and the touch controller 180 included in the touch sensing circuit 160 may be implemented as separate devices, or may be implemented as a single device. In addition, the touch driving circuit 170 and the data driving circuit 120 may be implemented as separate devices, or may be implemented as a single device.

[0077] The display device 100 may further include a power supply circuit or the like that supplies various types of power to the display driving circuit and / or the touch sensing circuit 160.

[0078] The display device 100 according to an embodiment of the present disclosure may be a mobile terminal, such as a smart phone and a tablet computer, or monitors or televisions (TVs) of various sizes. However, the display device 100 according to an embodiment of the present disclosure is not limited thereto, and may be various types and various sizes of displays capable of displaying information or images.

[0079] The display device 100 according to an embodiment of the present disclosure may further include electronic devices such as a camera (image sensor) and sensors. For example, the sensor may be a sensor that detects an object or a human body by receiving light such as infrared light, ultrasonic waves, and ultraviolet light.

[0080] Figure 2 A display panel 110 according to an embodiment of the present disclosure is shown.

[0081] Reference Figure 2 , the display panel 110 may include a substrate SUB on which a plurality of sub-pixels SP are disposed and an encapsulation layer 200 above the substrate SUB. The encapsulation layer 200 may also be referred to as an encapsulation substrate or an encapsulation portion.

[0082] Reference Figure 2 , in the case where the display device 100 according to an embodiment of the present disclosure is a self-emitting display device, each of the plurality of sub-pixels SP disposed on the substrate SUB may include a light-emitting element ED and a sub-pixel circuit SPC for driving the light-emitting element ED.

[0083] Reference Figure 2 , the sub-pixel circuit SPC may include a plurality of pixel driving transistors for driving the light-emitting element ED and at least one capacitor. In the present disclosure, the sub-pixel circuit SPC may drive the light-emitting element ED by providing a driving current to the light-emitting element ED at a predetermined timing. The light-emitting element ED may be driven by the driving current to emit light.

[0084] The plurality of pixel driving transistors may include a driving transistor DT for driving the light-emitting element ED and a scanning transistor ST that is turned on or off according to a scanning signal SC.

[0085] The driving transistor DT can supply a driving current to the light-emitting element ED.

[0086] The scanning transistor ST can be configured to control the electrical state of a corresponding node in the sub-pixel circuit SPC or control the state or operation of the driving transistor DT.

[0087] At least one capacitor can include a storage capacitor Cst for maintaining a constant voltage during a frame.

[0088] In order to drive the sub-pixel SP, a data signal VDATA as an image signal, a scanning signal SC as a gate signal, etc. can be applied to the sub-pixel SP. In addition, in order to drive the sub-pixel SP, a common pixel driving voltage including a first common driving voltage VDD and a second common driving voltage VSS can be applied to the sub-pixel SP.

[0089] The light-emitting element ED can include an anode AND, an intermediate layer EL, and a cathode CAT. The intermediate layer EL can be disposed between the anode AND and the cathode CAT.

[0090] In the case where the light-emitting element ED is an organic light-emitting element, the intermediate layer EL can include a light-emitting layer EML, a first common intermediate layer COM1 between the anode AND and the light-emitting layer EML, and a second common intermediate layer COM2 between the light-emitting layer EML and the cathode CAT. The first common intermediate layer COM1 and the second common intermediate layer COM2 can be collectively referred to as the common intermediate layer EL_COM.

[0091] The light-emitting layer EML can be disposed in each sub-pixel SP, and the common intermediate layer EL_COM can be commonly disposed in a plurality of sub-pixels SP.

[0092] The light-emitting layer EML can be disposed in each light-emitting region, and the common intermediate layer EL_COM can be commonly disposed in a plurality of light-emitting regions and non-light-emitting regions.

[0093] For example, the first common intermediate layer COM1 of the common intermediate layer EL_COM can include a hole injection layer (HIL) and a hole transport layer (HTL). The second common intermediate layer COM2 of the common intermediate layer EL_COM can include an electron transport layer (ETL) and an electron injection layer (EIL).

[0094] The hole injection layer can inject holes from the anode AND into the hole transport layer, the hole transport layer can transport the holes to the light-emitting layer EML, the electron injection layer can inject electrons from the cathode CAT into the electron transport layer, and the electron transport layer can transport the electrons to the light-emitting layer EML.

[0095] For example, the cathode CAT can be electrically connected to the second common driving voltage line VSSL. The second common driving voltage VSS, which is a common pixel driving voltage, can be applied to the cathode CAT through the second common driving voltage line VSSL. The anode AND can be directly or indirectly (through another transistor) electrically connected to the first node N1 of the driving transistor DT of each sub-pixel SP. In the present disclosure, the second common driving voltage VSS can also be referred to as the "reference voltage", and the second common driving voltage line VSSL can also be referred to as the "reference voltage line".

[0096] For example, the anode AND can be a pixel electrode provided in each sub-pixel SP, and the cathode CAT can be a common electrode commonly provided in a plurality of sub-pixels SP. For another example, the cathode CAT can be a pixel electrode provided in each sub-pixel SP, and the anode AND can be a common electrode commonly provided in a plurality of sub-pixels SP. Hereinafter, for the sake of explanation, it is assumed that the anode AND is a pixel electrode and the cathode CAT is a common electrode.

[0097] Each light-emitting element ED can be configured with an overlapping portion of the anode AND, the light-emitting layer EML in the intermediate layer EL, and the cathode CAT. A predetermined light-emitting region can be formed by each light-emitting element ED. For example, the light-emitting region of each light-emitting element ED can include the overlapping portion of the anode AND, the light-emitting layer EML in the intermediate layer EL, and the cathode CAT.

[0098] For example, the light-emitting element ED can be an organic light-emitting diode (OLED), an inorganic-based light-emitting diode (LED), or a quantum dot light-emitting element. For example, when the light-emitting element ED is an organic light-emitting diode (OLED), the intermediate layer EL in the light-emitting element ED can include an intermediate layer EL containing an organic material.

[0099] The driving transistor DT can be a driving transistor for supplying a driving current to the light-emitting element ED. The driving transistor DT can be connected between the first common driving voltage line VDDL and the light-emitting element ED.

[0100] The driving transistor DT can have a first node N1, a second node N2, and a third node N3. The first node N1 can be electrically connected to the light-emitting element ED, the second node N2 can be applied with a data signal VDATA, and the third node N3 can be applied with the first common driving voltage VDD from the first common driving voltage line VDDL.

[0101] In the driving transistor DT, the second node N2 may be a gate node, the first node N1 may be a source node or a drain node, and the third node N3 may be a drain node or a source node. Hereinafter, for ease of explanation, it will be described as an example that in the driving transistor DT, the second node N2 is a gate node, the first node N1 is a source node, and the third node N3 is a drain node.

[0102] Figure 2 The scanning transistor ST included in the sub-pixel circuit SPC shown may be a switching transistor that transmits a data signal VDATA as an image signal to the second node N2 serving as the gate node of the driving transistor DT.

[0103] The scanning transistor ST may be turned on and off by a scanning signal SC (the scanning signal SC is applied as a gate signal through a scanning line SCL, and the scanning line SCL is a type of gate line GL), and thus can control the electrical connection between the second node N2 of the driving transistor DT and the data line DL. The drain electrode or source electrode of the scanning transistor ST may be electrically connected to the data line DL, the source electrode or drain electrode of the scanning transistor ST may be electrically connected to the second node N2 of the driving transistor DT, and the gate electrode of the scanning transistor ST may be electrically connected to the scanning line SCL.

[0104] The storage capacitor Cst may be electrically connected between the first node N1 and the second node N2 of the driving transistor DT. The storage capacitor Cst may include a first capacitor electrode and a second capacitor electrode. The first capacitor electrode is electrically connected to the first node N1 of the driving transistor DT or corresponds to the first node N1 of the driving transistor DT, and the second capacitor electrode is electrically connected to the second node N2 of the driving transistor DT or corresponds to the second node N2 of the driving transistor DT.

[0105] The storage capacitor Cst may not be a parasitic capacitor (e.g., Cgs or Cgd) that is an internal capacitor that may exist between the first node N1 and the second node N2 of the driving transistor DT, but an external capacitor intentionally designed outside the driving transistor DT.

[0106] Each of the driving transistor DT and the scanning transistor ST may be an n-type transistor or a p-type transistor.

[0107] The display panel 110 may have a top emission structure or a bottom emission structure.

[0108] When the display panel 110 has a top emission structure, at least a part of the sub-pixel circuit SPC may overlap at least a part of the light-emitting element ED in the vertical direction. Therefore, the area of the light-emitting region may increase, and the aperture ratio may increase.

[0109] When the display panel 110 has a bottom emission structure, the sub-pixel circuit SPC may not overlap with the light-emitting element ED in the vertical direction.

[0110] As Figure 2 shown, the sub-pixel circuit SPC may have a 2T (transistor) 1C (capacitor) structure including two transistors DT, ST, and one capacitor CST. Depending on the situation, the sub-pixel circuit SPC may further include at least one transistor and may further include at least one capacitor.

[0111] For example, the sub-pixel circuit SPC may have an 8T1C structure including eight transistors and one capacitor. Again, for example, the sub-pixel circuit SPC may have a 6T2C structure including six transistors and two capacitors. Still again, for example, the sub-pixel circuit SPC may have a 7T1C structure including seven transistors and one capacitor.

[0112] The type and number of gate signals provided to the sub-pixel SP and the type and number of gate lines may vary according to the structure of the sub-pixel circuit SPC. In addition, the type and number of common pixel driving voltages provided to the sub-pixel SP may vary according to the structure of the sub-pixel circuit SPC.

[0113] Since the circuit elements in each sub-pixel SP (in particular, the light-emitting element ED implemented by an organic light-emitting diode (OLED) including an organic material) are vulnerable to external moisture or oxygen, an encapsulation layer 200 may be provided to prevent external moisture or oxygen from penetrating into the circuit elements (in particular, the light-emitting element ED). The encapsulation layer 200 may be configured in various shapes to prevent the light-emitting element ED from contacting moisture or oxygen.

[0114] Referring Figure 2 to, in order to sense a user's touch, the display device 100 according to an embodiment of the present disclosure may include a touch sensor layer TSL including a plurality of sensor electrodes; a touch driving circuit 170 configured to sense the plurality of sensor electrodes; and a touch controller 180 configured to use the sensing result (touch sensing data) of the touch driving circuit 170 to determine whether a touch event has occurred and the touch coordinates.

[0115] The touch sensor layer TSL may be embedded in the display panel 110. For example, the touch sensor layer TSL may be disposed on the encapsulation layer 200 in the display panel 110.

[0116] The display panel 110 may further include a plurality of touch pads TP electrically connected to the touch driving circuit 170, and a plurality of touch wiring interconnections TL for electrically connecting a plurality of sensor electrodes included in the touch sensor layer TSL to the plurality of touch pads TP connected to the touch driving circuit 170.

[0117] Meanwhile, the display device 100 according to an embodiment of the present disclosure may have an extremely narrow bezel structure, in which the non-display area NDA of the display panel 110 is very small or almost non-existent.

[0118] Hereinafter, the extremely narrow bezel structure of the display panel 110 of the display device 100 according to an embodiment of the present disclosure will be described.

[0119] Figure 3 The substrate SUB of the display panel 110 according to an embodiment of the present disclosure is shown.

[0120] Reference Figure 3 , the substrate SUB of the display panel 110 according to an embodiment of the present disclosure may include a display area DA where an image can be displayed and a non-display area NDA where an image is not displayed.

[0121] Reference Figure 3 , the non-display area NDA may include a first non-display area NDA1 located in a first direction from the display area DA, a second non-display area NDA2 located in a second direction from the display area DA, a third non-display area NDA3 located in a direction opposite to the first direction from the display area DA, and a fourth non-display area NDA4 located in a direction opposite to the second direction from the display area DA. For example, the first direction may be the column direction (Y-axis direction), and the second direction intersecting the first direction may be the row direction (X-axis direction).

[0122] Reference Figure 3 , the first non-display area NDA1 may include a pad area PA in which a plurality of pads are provided.

[0123] In the pad area PA, a plurality of pads electrically connected to the driving circuit may be provided. A plurality of driving circuits or printed circuit boards may be electrically connected. For example, the plurality of pads may include a plurality of display pads and a plurality of touch pads. A plurality of data lines DL, a first common driving voltage line VDDL, and a second common driving voltage line VSSL may be electrically connected to the plurality of display pads. A plurality of touch wiring interconnections TL may be electrically connected to the plurality of touch pads.

[0124] Reference Figure 3, the first non-display area NDA1 may further include a bending area BA. In this case, the substrate SUB may be a flexible substrate. Optionally, the first non-display area NDA1 may not include the bending area BA.

[0125] Reference Figure 3 , the display panel 110 may further include a ground interconnect disposed in the non-display area NDA of the substrate SUB. The ground interconnect may be disposed from a point of the pad area PA, via the second non-display area NDA2, the third non-display area NDA3, and the fourth non-display area NDA4, to another point of the pad area PA.

[0126] Reference Figure 3 , in the display panel 110 according to an embodiment of the present disclosure, the encapsulation layer 200 may have a structure in which an inorganic layer and an organic layer are stacked. In this case, the edge of the encapsulation layer 200 may be the edge of the organic layer.

[0127] Reference Figure 3 , the substrate SUB of the display panel 110 according to an embodiment of the present disclosure may have a first groove 300 located outside the display area DA. That is, the first groove 300 formed in the substrate SUB may be located in the non-display area NDA.

[0128] Reference Figure 3 , the first groove 300 may be formed in the substrate SUB in the form of a trench along the second non-display area NDA2, the third non-display area NDA3, and the fourth non-display area NDA4.

[0129] Reference Figure 3 , in at least a partial area of the first non-display area NDA1, the first groove 300 may not be formed in the substrate SUB. At least a partial area in the first non-display area NDA1 where the first groove 300 is not formed in the substrate SUB may be an area between the display area DA and the pad area PA.

[0130] Reference Figure 3 , the first groove 300 formed in the substrate SUB may have a U shape.

[0131] Reference Figure 3 , the display panel 110 may include a first area 310, a second area 320, a third area 330, and a fourth area 340. In the display panel 110, the first area 310 may include the display area DA and the first non-display area NDA1, the second area 320 may include the display area DA and the second non-display area NDA2, the third area 330 may include the display area DA and the third non-display area NDA3, and the fourth area 340 may include the display area DA and the fourth non-display area NDA4.

[0132] Figure 4 is a cross-sectional view of the display panel 110 according to an embodiment of the present disclosure.

[0133] Referring Figure 4 , the substrate SUB may include a first substrate SUB1, an intermediate insulating layer IPD, and a second substrate SUB2. The intermediate insulating layer IPD may be located between the first substrate SUB1 and the second substrate SUB2. By configuring the substrate SUB with the first substrate SUB1, the intermediate insulating layer IPD, and the second substrate SUB2, moisture penetration can be prevented. For example, the first substrate SUB1 and the second substrate SUB2 may be polyimide (PI) substrates. In the substrate SUB, the first substrate SUB1 may be referred to as a primary PI substrate, and the second substrate SUB2 may be referred to as a secondary PI substrate.

[0134] Referring Figure 4 , on the substrate SUB, various patterns ACT, SD1, and GATE for forming transistors such as the driving transistor DT, various insulating layers MBUF, ABUF, GI, ILD1, ILD2, and PAS0, and various metal patterns TM, GM, ML1, and ML2 may be provided.

[0135] Referring Figure 4 , the multi-buffer layer MBUF may be provided on the second substrate SUB2, and the active buffer layer ABUF may be provided on the multi-buffer layer MBUF.

[0136] The first metal layer ML1 and the second metal layer ML2 may be provided on the multi-buffer layer MBUF. The first metal layer ML1 and the second metal layer ML2 may constitute a light-shielding pattern LS for shielding light.

[0137] The active buffer layer ABUF may be provided on the first metal layer ML1 and the second metal layer ML2. The active layer ACT of the driving transistor DT may be provided on the active buffer layer ABUF.

[0138] A gate insulating layer GI may be provided to cover the active layer ACT.

[0139] The gate electrode GATE of the driving transistor DT may be provided on the gate insulating layer GI. At a position different from the position where the driving transistor DT is formed, the gate material layer GM may be provided on the gate insulating layer GI together with the gate electrode GATE of the driving transistor DT.

[0140] A first interlayer dielectric layer ILD1 may be provided to cover the gate electrode GATE and the gate material layer GM. A metal pattern TM may be provided on the first interlayer dielectric layer ILD1. The metal pattern TM may be located at a position different from the position where the driving transistor DT is formed. A second interlayer dielectric layer ILD2 may be provided to cover the metal pattern TM on the first interlayer dielectric layer ILD1.

[0141] Two first source-drain electrode patterns SD1 may be provided on the second interlayer dielectric layer ILD2. One of the two first source-drain electrode patterns SD1 is a source node of the driving transistor DT, and the other may be a drain node of the driving transistor DT.

[0142] The two first source-drain electrode patterns SD1 may be electrically connected to one side and the other side of the active layer ACT through contact holes in the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, and the first gate insulating layer GI.

[0143] A portion of the active layer ACT overlapping with the first gate electrode GATE is a channel region. One of the two first source-drain electrode patterns SD1 may be connected to one side of the channel region in the active layer ACT, and the other of the two first source-drain electrode patterns SD1 may be connected to the other side of the channel region in the active layer ACT.

[0144] A passivation layer PAS0 is provided to cover the two first source-drain electrode patterns SD1. A planarization layer PLN may be provided on the passivation layer PAS0. The planarization layer PLN may include a first planarization layer PLN1 and a second planarization layer PLN2.

[0145] The first planarization layer PLN1 may be provided on the passivation layer PAS0.

[0146] A second source-drain electrode pattern SD2 may be provided on the first planarization layer PLN1. The second source-drain electrode pattern SD2 may be connected to one of the two first source-drain electrode patterns SD1 (corresponding to Figure 2 the second node N2 of the driving transistor DT in the sub-pixel SP) through a contact hole in the first planarization layer PLN1.

[0147] The second planarization layer PLN2 may be provided to cover the second source-drain electrode pattern SD2. A light-emitting element ED may be provided on the second planarization layer PLN2.

[0148] Looking at the stacked structure of the light-emitting element ED, an anode AND may be provided on the second planarization layer PLN2. The anode AND may be electrically connected to the second source-drain electrode pattern SD2 through a contact hole in the second planarization layer PLN2.

[0149] A partition bank BANK can be provided to cover a part of the anode AND. A part of the partition bank BANK corresponding to the light-emitting area EA of the sub-pixel SP can be open.

[0150] A part of the anode AND can be exposed through the opening (open part) of the partition bank BANK. The light-emitting layer EL can be located on the side of the partition bank BANK and in the opening (open part) of the partition bank BANK. All or part of the light-emitting layer EL can be located between adjacent parts of the partition bank BANK.

[0151] In the opening of the partition bank BANK, the light-emitting layer EL can be in contact with the anode AND. The cathode CAT can be provided on the light-emitting layer EL.

[0152] The light-emitting element ED can be formed by the anode AND, the light-emitting layer EL, and the cathode CAT. The light-emitting layer EL can include an organic layer.

[0153] The encapsulation layer ENCAP can be provided on the above-described light-emitting element ED.

[0154] The encapsulation layer ENCAP can have a single-layer structure or a multi-layer structure. For example, referring to Figure 4 , the encapsulation layer ENCAP can include a first encapsulation layer E-PAS1, a second encapsulation layer PCL, and a third encapsulation layer E-PAS2.

[0155] For example, the first encapsulation layer E-PAS1 and the third encapsulation layer E-PAS2 can be referred to as the first inorganic encapsulation layer and the second inorganic encapsulation layer, respectively, and the second encapsulation layer PCL can be referred to as the organic encapsulation layer. For example, the first encapsulation layer E-PAS1 and the third encapsulation layer E-PAS2 can be inorganic layers. For example, the second encapsulation layer PCL can be an organic layer. Among the first encapsulation layer E-PAS1, the second encapsulation layer PCL, and the third encapsulation layer E-PAS2, the second encapsulation layer PCL can be the thickest and serve as a planarization layer.

[0156] The first encapsulation layer E-PAS1 can be provided on the cathode CAT and can be provided closest to the light-emitting element ED. The first encapsulation layer E-PAS1 can be formed of an inorganic insulating material that can be deposited at a low temperature. For example, the first encapsulation layer E-PAS1 can include silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3). Since the first encapsulation layer E-PAS1 is deposited in a low-temperature atmosphere, during the deposition process, the first encapsulation layer E-PAS1 can prevent the light-emitting layer EL including an organic material vulnerable to a high-temperature atmosphere from being damaged.

[0157] The second encapsulation layer PCL may be formed to have a smaller area than the first encapsulation layer E-PAS1. In this case, the second encapsulation layer PCL may be formed to expose both ends of the first encapsulation layer E-PAS1. The second encapsulation layer PCL may be used to perform a buffering function of reducing stress between layers caused by warping of the display device 100, and may also be used to enhance planarization performance. For example, the second encapsulation layer PCL may include an acrylic resin, an epoxy resin, a polyimide, a polyethylene, or silicon oxycarbide (SiOC), and may be formed of an organic insulating material. For example, the second encapsulation layer PCL may be formed using an inkjet method.

[0158] The third encapsulation layer E-PAS2 may be formed over the substrate SUB on which the second encapsulation layer PCL is formed to cover the upper surfaces and side surfaces of each of the second encapsulation layer PCL and the first encapsulation layer E-PAS1. The third encapsulation layer E-PAS2 may minimize or prevent external moisture or oxygen from penetrating into the inorganic first encapsulation layer E-PAS1 and the organic second encapsulation layer PCL. For example, the third encapsulation layer E-PAS2 is formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), and aluminum oxide (Al2O3).

[0159] Reference Figure 4 , when the touch sensor TS is of the type in which the touch sensor TS is embedded in the display panel 110, the touch sensor TS may be disposed on the encapsulation layer ENCAP. The structure of the touch sensor TS will be described in detail below.

[0160] The touch buffer layer T-BUF may be disposed on the encapsulation layer ENCAP. The touch sensor TS may be disposed on the touch buffer layer T-BUF.

[0161] The touch sensor TS may include a touch sensor metal TSM and a touch bridge metal BRG located at different layers.

[0162] The touch interlayer insulating layer T-ILD may be disposed between the touch sensor metal TSM and the touch bridge metal BRG.

[0163] For example, the touch sensor metal TSM may include a first touch sensor metal TSM, a second touch sensor metal TSM, and a third touch sensor metal TSM that are disposed adjacent to each other. The third touch sensor metal TSM may be disposed between the first touch sensor metal TSM and the second touch sensor metal TSM, and when the first touch sensor metal TSM and the second touch sensor metal TSM need to be electrically connected to each other, the first touch sensor metal TSM and the second touch sensor metal TSM may be electrically connected to each other through touch bridging metals BRG disposed at different layers. The touch bridging metals BRG may be electrically isolated from the third touch sensor metal TSM through a touch interlayer insulating layer T-ILD.

[0164] When the touch sensor TS is formed on the display panel 110, moisture may be generated or introduced from the chemical solutions (developer, etchant, etc.) used in the process or from the outside. Since the touch sensor TS is disposed on the touch buffer layer T-BUF, chemical solutions or moisture can be prevented from penetrating into the light-emitting layer EL including an organic material during the manufacturing process of the touch sensor TS. Accordingly, the touch buffer layer T-BUF can prevent the light-emitting layer EL, which is vulnerable to chemical solutions or moisture, from being damaged.

[0165] In order to prevent the light-emitting layer EL including an organic material vulnerable to high temperatures from being damaged, the touch buffer layer T-BUF may be formed at a low temperature equal to or lower than a predetermined temperature (e.g., 100 °C) and may be formed of an organic insulating material having a low dielectric constant of 1 to 3. For example, the touch buffer layer T-BUF may be formed of an acrylic-based, epoxy-based, or siloxane-based material. When the display device 100 is warped, the encapsulation layer ENCAP may be damaged, and the touch sensor metal TSM disposed above the touch buffer layer T-BUF may be broken. Even when the display device 100 is warped, the touch buffer layer T-BUF made of an organic insulating material and having a planarization property can prevent the encapsulation layer ENCAP from being damaged and / or prevent the breakage of the metals TSM and BRG constituting the touch sensor TS.

[0166] The touch buffer layer T-BUF and the touch interlayer insulating layer T-ILD may be touch insulating layers.

[0167] A protective layer PAC may be provided to cover the touch sensor TS. The protective layer PAC may be an organic insulating layer.

[0168] Meanwhile, in the trimming edge region for errors in the display panel 110 during the trimming process, by removing various inorganic layers for forming transistors and the inorganic encapsulation layers E-PAS1 and E-PAS2 included in the encapsulation layer ENCAP, various inorganic layer cracks caused by defects occurring during trimming can be prevented from spreading into the display area DA. If the cracks spread into the display area DA, moisture may penetrate into the crack area and cause panel defects.

[0169] In the display panel 110 recently installed in a mobile terminal, the size of the bezel is gradually decreasing. If the trimming edge is applied in this case, due to the reduced adhesion between the inorganic encapsulation layers E-PAS1 and E-PAS2 of the encapsulation layer ENCAP and the underlying organic encapsulation layer (e.g., the planarization layer PLN), a layer lifting phenomenon may occur, and as a result, a moisture penetration defect may occur.

[0170] Although the inorganic encapsulation layers E-PAS1 and E-PAS2 of the encapsulation layer ENCAP can be located in the trimming edge region, there are limitations in processing capabilities, and there is still a risk of cracks occurring during trimming.

[0171] Considering these facts, the display device 100 according to an embodiment of the present disclosure may have a structure that can reduce moisture penetration defects while achieving a narrow bezel. This structure is referred to as a "narrow bezel structure and moisture penetration prevention structure".

[0172] Hereinafter, the "narrow bezel structure and moisture penetration prevention structure" of the display device 100 according to an embodiment of the present disclosure will be described.

[0173] Hereinafter, with reference to Figures 5 to 11 the narrow bezel structure and moisture penetration prevention structure in the second to fourth non-display regions NDA2, NDA3, and NDA4 will be described, and with reference to Figure 12 the narrow bezel structure and moisture penetration prevention structure in the first non-display region NDA1 will be described.

[0174] Figure 5 and 6 are cross-sectional views of some bezel regions (e.g., the second to fourth non-display regions NDA2, NDA3, and NDA4) in the display panel 110 according to an embodiment of the present disclosure having a narrow bezel structure and moisture penetration prevention structure.

[0175] With reference to Figure 5 in order to have a narrow bezel structure and moisture penetration prevention structure, the display panel 110 according to an embodiment of the present disclosure may include a substrate SUB, a first inorganic layer 510, a second inorganic layer 520, a third inorganic layer 530, and an organic layer 540.

[0176] The substrate SUB may include a display area DA provided with a plurality of sub-pixels SP and a non-display area NDA located outside the display area DA and including a pad area PA. The substrate SUB may have a first groove 300 in the non-display area NDA.

[0177] The first inorganic layer 510 may be provided on the substrate SUB, may extend from the display area DA to the non-display area NDA, and may have a second groove closer to the display area DA than the first groove 300 in the non-display area NDA.

[0178] The area where the first inorganic layer 510 is cut may correspond to the second groove of the first inorganic layer 510.

[0179] When forming the second groove, the display device 100 may minimize the impact propagating along the first inorganic layer 510. For example, by including the area where the first inorganic layer 510 is cut, the display device 100 may prevent cracks from spreading along the first inorganic layer 510.

[0180] The organic layer 540 may be provided on a part of the first inorganic layer 510 in the non-display area NDA and may fill the second groove of the first inorganic layer 510.

[0181] The second inorganic layer 520 may extend from the display area DA to the non-display area NDA, may be provided on the first inorganic layer 510 to cover the organic layer 540, and may extend into the first groove 300.

[0182] The inner surface (rear surface) of the second inorganic layer 520 may directly contact the organic layer 540. Thus, the layer lifting phenomenon between the second inorganic layer 520 and the organic layer 540 can be prevented.

[0183] The third inorganic layer 530 may extend from the display area DA to the non-display area NDA, may be provided on the second inorganic layer 520, and may extend into the first groove 300.

[0184] Reference Figure 5 , in order to have a narrow bezel structure and a moisture-proof penetration structure, the display panel 110 according to an embodiment of the present disclosure may further include a touch insulation layer 550 that extends from the display area DA to the non-display area NDA, is provided on the third inorganic layer 530, and overlaps with the organic layer 540.

[0185] The first inorganic layer 510 may include at least one inorganic layer for forming a transistor (e.g., a driving transistor DT). For example, reference Figure 4The first inorganic layer 510 may include at least one inorganic layer of a multi-buffer layer MBUF, an active buffer layer ABUF, a gate insulating layer GI, a first interlayer insulating layer ILD1, and a second interlayer insulating layer ILD2.

[0186] In the display area DA, the light emitting element ED may be disposed between the first inorganic layer 510 and the second inorganic layer 520, and the encapsulation layer ENCAP may be disposed on the light emitting element ED. The second inorganic layer 520 and the third inorganic layer 530 may be included in the encapsulation layer ENCAP.

[0187] For example, refer to Figure 4 , the second inorganic layer 520 may be a first encapsulation layer E-PAS1 included in the encapsulation layer ENCAP, and the third inorganic layer 530 may be a third encapsulation layer E-PAS2 included in the encapsulation layer ENCAP. The first encapsulation layer E-PAS1 may be referred to as a first inorganic encapsulation layer, and the third encapsulation layer E-PAS2 may be referred to as a second inorganic encapsulation layer.

[0188] As mentioned above Figure 4 As described above, the touch bridge metal BRG may be disposed on the encapsulation layer ENCAP, the touch sensor metal TSM may be disposed on the touch bridge metal BRG, and the touch interlayer insulating layer T-ILD may be disposed between the touch bridge metal BRG and the touch sensor metal TSM. The touch interlayer insulating layer T-ILD may be an inorganic layer or an organic layer.

[0189] refer to Figure 5 , the touch insulation layer 550 may include a touch interlayer insulation layer T-ILD disposed between the touch bridge metal BRG and the touch sensor metal TSM.

[0190] As mentioned above Figure 4 As described above, the touch buffer layer T-BUF may be disposed between the encapsulation layer ENCAP and the touch bridge metal BRG. The touch buffer layer T-BUF may be an inorganic layer or an organic layer. In this case, the touch insulation layer 550 may include the touch buffer layer T-BUF.

[0191] like Figure 5 As shown, the touch insulation layer 550 may not extend to the inside of the first groove 300 . Alternatively, the touch insulation layer 550 may extend to the inside of the first groove 300 .

[0192] refer to Figure 6 , when the second inorganic layer 520, the third inorganic layer 530 and the touch insulation layer 550 are configured to extend to the inside of the first groove 300 of the substrate SUB, the first groove 300 of the substrate SUB may have a depth or size corresponding to the total thickness of the second inorganic layer 520, the third inorganic layer 530 and the touch insulation layer 550.

[0193] For example, the first groove 300 of the substrate SUB may have a trapezoidal shape, and its width increases toward the top of the substrate SUB. Due to this shape, the areas where the second inorganic layer 520, the third inorganic layer 530, and the touch insulating layer 550 contact the substrate SUB can be significantly increased.

[0194] For example, as the areas where the second inorganic layer 520, the third inorganic layer 530, and the touch insulating layer 550 contact the substrate SUB increase, peeling or detachment of the second inorganic layer 520, the third inorganic layer 530, and the touch insulating layer 550 from the substrate SUB can be prevented or minimized.

[0195] Reference Figure 6 , the first inorganic layer 510 may include a first insulating layer 610 on the substrate SUB and a second insulating layer 620 on the first insulating layer 610. The second groove of the first inorganic layer 510 may correspond to a hole or a groove formed in the second insulating layer 620.

[0196] The area for cutting the second insulating layer 620 of the first inorganic layer 510 may correspond to the second groove of the first inorganic layer 510.

[0197] Reference Figure 6 , the first inorganic layer 510 may contact the second inorganic layer 520. For example, the first insulating layer 610 may contact the second inorganic layer 520. For example, the second insulating layer 620 may contact the second inorganic layer 520. More specifically, at least one of the side surface and the upper surface of the second insulating layer 620 may contact the rear surface of the second inorganic layer 520. When the first inorganic layer 510 and the second inorganic layer 520 contact each other, peeling or detachment of the second inorganic layer 520 from the substrate SUB can be prevented. For example, when the second inorganic layer 520 contacts a part of the first inorganic layer 510, the adhesion between the second inorganic layer 520 and the substrate SUB can be increased.

[0198] According to the above description, since the adhesion between the substrate SUB and the various insulating layers 510, 520, 530, 540, and 550 included in the display panel 110 increases, the overall reliability of the display panel 110 can be greatly improved.

[0199] Reference Figure 6 , the display panel 110 according to an embodiment of the present disclosure may further include a barrier metal 615 disposed on the first insulating layer 610.

[0200] Reference Figure 6, both ends of the barrier metal 615 may be located between the first insulating layer 610 and the second insulating layer 620, and a portion between both ends of the barrier metal 615 may overlap with the second groove of the first inorganic layer 510. That is, a part of the barrier metal 615 (the part between both ends of the barrier metal 615) may be exposed through the second groove of the first inorganic layer 510.

[0201] Reference Figure 6 , the barrier metal 615 may be disposed at the same layer as the shielding metal LS (reference Figure 4 ) disposed under a transistor (e.g., a driving transistor DT). That is, the barrier metal 615 may include the same material as the shielding metal LS.

[0202] Reference Figure 6 , the barrier metal 615 may prevent the substrate SUB from being etched when the first inorganic layer 510 is etched. Thus, the barrier metal 615 may prevent moisture from penetrating downward (downward moisture penetration).

[0203] Reference Figure 6 , the display panel 110 according to an embodiment of the present disclosure may further include at least one metal layer disposed between the first inorganic layer 510 and the second inorganic layer 520 and extending from the display area DA to the non-display area NDA.

[0204] Reference Figure 6 , the at least one metal layer may extend into the second groove of the first inorganic layer 510.

[0205] For example, the at least one metal layer may include a first source-drain electrode layer 630 in which a first source-drain electrode pattern SD1 (reference Figure 4 ) is formed and a second source-drain electrode layer 640 in which a second source-drain electrode pattern SD2 (reference Figure 4 ) is formed.

[0206] Reference Figure 6 , the touch insulating layer 550 may extend into the first groove 300.

[0207] Reference Figure 5 And Figure 6 , the display panel 110 according to an embodiment of the present disclosure does not have a dam structure for preventing the second encapsulation layer PCL, which is an organic encapsulation layer included in the encapsulation layer ENCAP, from overflowing in the non-display area NDA. Due to this fact, the size of the non-display area NDA can be reduced by the area where the dam structure is formed, making it easier to achieve a narrow border.

[0208] In this way, even if the display panel 110 does not have a dam structure, since the second inorganic layer 520 and the third inorganic layer 530 included in the encapsulation layer ENCAP are arranged to extend into the interior of the first groove 300 of the substrate SUB, the third inorganic layer 530 can be used as a dam to prevent the second encapsulation layer PCL, which is an organic encapsulation layer included in the encapsulation layer ENCAP, from overflowing.

[0209] Figures 7 to 9 It is an example of the structure of the organic layer 540 for forming a narrow border structure and a moisture-proof penetration structure in the display panel 110 according to an embodiment of the present disclosure.

[0210] As described above with reference to Figure 4 As described, the display panel 110 according to an embodiment of the present disclosure may include a planarization layer PLN disposed between the first inorganic layer 510 for forming a transistor and the second inorganic layer 520 included in the encapsulation layer ENCAP, a light-emitting element ED disposed on the planarization layer PLN, and a bank for defining a light-emitting region of the light-emitting element ED disposed on the planarization layer PLN.

[0211] Reference Figure 7 , the organic layer 540 may include a planarization layer PLN, and the planarization layer PLN may be disposed on a part of the first inorganic layer 510 in the non-display area NDA and may fill the second groove of the first inorganic layer 510. For example, the planarization layer PLN included in the organic layer 540 may be the second planarization layer PLN2 located immediately below the anode AND.

[0212] Reference Figure 8 , the organic layer 540 may further include a bank on the planarization layer PLN.

[0213] Reference Figure 9 , in addition to the planarization layer PLN and the bank, the organic layer 540 may further include spacers SPCR on the bank.

[0214] Figure 10 And Figure 11 It is an example of the structure of the first groove 300 for forming a narrow border structure and a moisture-proof penetration structure in the display panel 110 according to an embodiment of the present disclosure.

[0215] Reference Figure 10 And Figure 11 , in the display panel 110 according to an embodiment of the present disclosure, the substrate SUB may include a first substrate SUB1, an intermediate insulating layer IPD on the first substrate SUB1, and a second substrate SUB2 on the intermediate insulating layer IPD.

[0216] ReferenceFigure 10 and Figure 11 ,the first groove 300 of the substrate SUB may be formed in the second substrate SUB2.

[0217] Reference Figure 10 ,the first groove 300 of the substrate SUB may be formed to completely penetrate the second substrate SUB2.

[0218] In contrast, as Figure 11 shown, the first groove 300 of the substrate SUB may be formed in a form in which the first groove 300 does not completely penetrate the second substrate SUB2 and the second substrate SUB is recessed.

[0219] Figure 12 is a cross-sectional view of another border area (e.g., the first non-display area NDA1) having a narrow border structure and a moisture-proof penetration structure in the display panel 110 according to an embodiment of the present disclosure. In the following description, reference is also made to Figure 3 .

[0220] As Figures 5 to 11 shown, the first groove 300 may be formed only in some of the non-display areas NDA (e.g., the second non-display area NDA2 to the fourth non-display area NDA4).

[0221] In contrast, as Figure 12 shown, the first groove 300 may not be formed in the non-display area NDA (i.e., the first non-display area NDA1) located between the pad area PA and the display area DA among the non-display areas NDA.

[0222] As described above, the non-display area NDA may include a first non-display area NDA1 located outside the display area DA in a first direction, a second non-display area NDA2 located outside the display area DA in a second direction different from the first direction, a third non-display area NDA3 located outside the display area DA in a direction opposite to the first direction, and a fourth non-display area NDA4 located outside the display area DA in a direction opposite to the second direction.

[0223] As Figures 5 to 11 shown, the first groove 300 may be present in the second non-display area NDA2, the third non-display area NDA3, and the fourth non-display area NDA4. As Figure 12 shown, the first groove 300 may not be present in all or part of the first non-display area NDA1.

[0224] Reference Figure 12, the pad 800 may be disposed in the first non-display area NDA1. At least one insulating layer among the second inorganic layer 520, the third inorganic layer 530, and the touch insulating layer 550 may be disposed on at least a part of the pad 800.

[0225] A brief description of the embodiments of the present disclosure is as follows.

[0226] A display device according to an embodiment of the present disclosure may include: a substrate including a display area in which a plurality of sub-pixels are disposed and a non-display area located outside the display area and including a pad area, and having a first groove in the non-display area; a first inorganic layer disposed on the substrate, extending from the display area to the non-display area, and having a second groove in the non-display area, the second groove being closer to the display area than the first groove; an organic layer disposed on a part of the first inorganic layer in the non-display area and filling the second groove; a second inorganic layer extending from the display area to the non-display area, disposed on the first inorganic layer to cover the organic layer, and extending into the interior of the first groove; and a third inorganic layer extending from the display area to the non-display area, disposed on the second inorganic layer, and extending into the interior of the first groove.

[0227] A display device according to an embodiment of the present disclosure may further include a touch insulating layer extending from the display area to the non-display area, disposed on the third inorganic layer, and overlapping with the organic layer.

[0228] The first inorganic layer may include at least one inorganic layer for forming a transistor.

[0229] A display device according to an embodiment of the present disclosure may further include: a light-emitting element disposed between the first inorganic layer and the second inorganic layer in the display area; and a encapsulation layer on the light-emitting element. The second inorganic layer and the third inorganic layer may be included in the encapsulation layer.

[0230] A display device according to an embodiment of the present disclosure may further include a touch bridging metal disposed on the encapsulation layer; a touch sensor metal disposed on the touch bridging metal; and a touch interlayer insulating layer disposed between the touch bridging metal and the touch sensor metal. The touch insulating layer may include the touch interlayer insulating layer.

[0231] The display device according to an embodiment of the present disclosure may further include a touch buffer layer disposed between the encapsulation layer and the touch bridging metal. The touch insulating layer may further include a touch buffer layer.

[0232] The touch insulating layer may extend into the interior of the first groove.

[0233] In the display device according to an embodiment of the present disclosure, the first inorganic layer may include a first insulating layer on the substrate; and a second insulating layer on the first insulating layer. The second groove may correspond to a hole or a groove formed in the second insulating layer.

[0234] The display device according to an embodiment of the present disclosure may further include a barrier metal disposed on the first insulating layer.

[0235] Both ends of the barrier metal may be located between the first insulating layer and the second insulating layer, and a portion between both ends of the barrier metal may overlap with the second groove.

[0236] The display device according to an embodiment of the present disclosure may further include a transistor disposed in the display area; and a shielding metal disposed under the transistor.

[0237] The barrier metal may be disposed at the same layer as the shielding metal.

[0238] The display device according to an embodiment of the present disclosure may further include at least one metal layer disposed between the first inorganic layer and the second inorganic layer and extending from the display area to the non-display area.

[0239] The at least one metal layer may extend into the interior of the second groove of the first inorganic layer.

[0240] The display device according to an embodiment of the present disclosure may further include a planarization layer disposed between the first inorganic layer and the second inorganic layer; a light-emitting element disposed on the planarization layer; and a partition disposed on the planarization layer and defining a light-emitting area of the light-emitting element.

[0241] The organic layer may include the planarization layer.

[0242] The organic layer may further include the partition.

[0243] The organic layer may further include a spacer on the partition.

[0244] In a display device according to an embodiment of the present disclosure, the substrate may include: a first substrate; an intermediate insulating layer on the first substrate; and a second substrate on the intermediate insulating layer.

[0245] The first groove may be formed in the second substrate. Specifically, the first groove may be formed only in the second substrate and may not be formed in the intermediate insulating layer and the first substrate.

[0246] In a display device according to an embodiment of the present disclosure, the first groove may be formed only in a part of the non-display area, and the first groove may not be formed between the pad area and the display area in the non-display area.

[0247] For example, in a display device according to an embodiment of the present disclosure, the non-display area may include: a first non-display area located outside the display area in a first direction; a second non-display area located outside the display area in a second direction different from the first direction; a third non-display area located outside the display area in a direction opposite to the first direction; and a fourth non-display area located outside the display area in a direction opposite to the second direction.

[0248] For example, the first groove may be present in the second non-display area, the third non-display area, and the fourth non-display area, and the first groove may not be present in all or part of the first non-display area.

[0249] A display device according to an embodiment of the present disclosure may include: a substrate including a display area for displaying an image and a non-display area as an area outside the display area, and having a first groove in the non-display area; a first inorganic layer provided on the substrate, extending from the display area to the non-display area, and having a second groove in the non-display area, the second groove being closer to the display area than the first groove; a planarization layer on the first inorganic layer; an organic layer provided on a part of the first inorganic layer in the non-display area and filling the second groove; a light-emitting element on the planarization layer; a first inorganic encapsulation layer on the light-emitting element; an organic encapsulation layer on the first inorganic encapsulation layer; and a second inorganic encapsulation layer on the organic encapsulation layer.

[0250] The first inorganic encapsulation layer may extend from the display area to the non-display area, may be disposed on the first inorganic layer to cover the organic layer, and may extend into the interior of the first groove.

[0251] The second inorganic encapsulation layer may extend from the display area to the non-display area, may be disposed on the second inorganic layer, and may extend into the interior of the first groove.

[0252] The display device according to an embodiment of the present disclosure may further include a touch insulating layer that extends from the display area to the non-display area, is disposed on the second inorganic encapsulation layer, and overlaps with the organic layer.

[0253] The display device according to an embodiment of the present disclosure may further include a touch bridging metal disposed on the second inorganic encapsulation layer; a touch sensor metal disposed on the touch bridging metal; and a touch interlayer insulating layer disposed between the touch bridging metal and the touch sensor metal. The touch insulating layer may include the touch interlayer insulating layer.

[0254] The display device according to an embodiment of the present disclosure may further include a touch buffer layer disposed between the encapsulation layer and the touch bridging metal. The touch insulating layer may further include the touch buffer layer.

[0255] In the display device according to an embodiment of the present disclosure, the touch insulating layer may extend into the interior of the first groove of the substrate.

[0256] The above description has been presented to enable any person skilled in the art to make, use, and practice the technical features of the present disclosure, and the above description has been provided as an example in the context of a particular application and its requirements. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art, and the principles described herein may be applied to other embodiments and applications without departing from the scope of the present disclosure. The above description and drawings have provided examples of the technical features of the present disclosure for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical features of the present disclosure.

Claims

1. A display device, comprising: A substrate including a display area in which a plurality of sub-pixels are arranged and a non-display area outside the display area and including a pad area, and having a first groove in the non-display area; a first inorganic layer, the first inorganic layer being disposed on the substrate, extending from the display area to the non-display area, and having a second groove located in the non-display area, the second groove being closer to the display area than the first groove; an organic layer disposed on a portion of the first inorganic layer in the non-display area and filling the second groove; a second inorganic layer, the second inorganic layer extending from the display area to the non-display area, being disposed on the first inorganic layer to cover the organic layer, and extending to an interior of the first groove; as well as A third inorganic layer extending from the display area to the non-display area is disposed on the second inorganic layer and extends to an interior of the first groove.

2. The display device according to claim 1, further comprising: A touch insulating layer extends from the display area to the non-display area, is disposed on the third inorganic layer, and overlaps the organic layer.

3. The display device according to claim 1, wherein: The first inorganic layer includes at least one inorganic layer for forming a transistor.

4. The display device according to claim 2, further comprising: a light emitting element, the light emitting element being disposed between the first inorganic layer and the second inorganic layer in the display area; as well as an encapsulation layer, the encapsulation layer being on the light-emitting element, Wherein, the second inorganic layer and the third inorganic layer are included in the encapsulation layer.

5. The display device according to claim 4, further comprising: A touch bridge metal, wherein the touch bridge metal is disposed on the packaging layer; A touch sensor metal, wherein the touch sensor metal is disposed on the touch bridge metal; as well as a touch interlayer insulating layer, wherein the touch interlayer insulating layer is disposed between the touch bridge metal and the touch sensor metal, Wherein, the touch insulating layer includes the touch interlayer insulating layer.

6. The display device according to claim 5, further comprising: a touch buffer layer, wherein the touch buffer layer is disposed between the encapsulation layer and the touch bridge metal, Wherein, the touch insulation layer also includes the touch buffer layer.

7. The display device according to claim 2, wherein: The touch insulation layer extends to the inside of the first groove.

8. The display device according to claim 1, in, The first inorganic layer comprises: a first insulating layer, the first insulating layer being on the substrate; and a second insulating layer, the second insulating layer being on the first insulating layer, and The second groove corresponds to a hole or a groove formed in the second insulating layer.

9. The display device according to claim 8, further comprising: a barrier metal disposed on the first insulating layer, Wherein, two ends of the barrier metal are located between the first insulating layer and the second insulating layer, and a portion between the two ends of the barrier metal overlaps with the second groove.

10. The display device according to claim 9, further comprising: A transistor, wherein the transistor is arranged in the display area; as well as A shielding metal, the shielding metal being disposed below the transistor, The barrier metal is arranged at the same layer as the shielding metal.

11. The display device according to claim 1, further comprising: at least one metal layer, the at least one metal layer being disposed between the first inorganic layer and the second inorganic layer and extending from the display area to the non-display area, The at least one metal layer extends into the second groove of the first inorganic layer.

12. The display device according to claim 1, further comprising: a planarization layer, the planarization layer being disposed between the first inorganic layer and the second inorganic layer; A light emitting element, wherein the light emitting element is disposed on the planarization layer; as well as a bank, the bank being disposed on the planarization layer and defining a light emitting area of ​​the light emitting element, Wherein, the organic layer includes the planarization layer.

13. The display device according to claim 12, wherein: The organic layer further includes the bank.

14. The display device according to claim 13, further comprising: a spacer on the dam, Wherein, the organic layer further includes the spacer.

15. The display device according to claim 1, in, The substrate comprises: a first substrate; an intermediate insulating layer, the intermediate insulating layer being on the first substrate; and a second substrate on the intermediate insulating layer, and Wherein, the first groove is formed in the second substrate.

16. The display device according to claim 15, wherein: The first groove is formed only in the second substrate and is not formed in the first substrate.

17. The display device according to claim 1, wherein: The first groove is formed only in a portion of the non-display area, and The first groove is not formed between the pad area in the non-display area and the display area.

18. The display device according to claim 1, in, The non-display area includes: a first non-display area, the first non-display area being located outside the display area in a first direction; a second non-display area, the second non-display area being located outside the display area in a second direction different from the first direction; a third non-display area, the third non-display area being located outside the display area in a direction opposite to the first direction; and a fourth non-display area, the fourth non-display area being located outside the display area in a direction opposite to the second direction, wherein the first groove exists in the second non-display area, the third non-display area, and the fourth non-display area, and The first groove does not exist in the whole or part of the first non-display area.

19. A display device comprising: a substrate including a display area for displaying an image and a non-display area as an area outside the display area, and having a first groove in the non-display area; a first inorganic layer, the first inorganic layer being disposed on the substrate, extending from the display area to the non-display area, and having a second groove located in the non-display area, the second groove being closer to the display area than the first groove; a planarization layer, the planarization layer being on the first inorganic layer; an organic layer disposed on a portion of the first inorganic layer in the non-display area and filling the second groove; A light emitting element, wherein the light emitting element is on the planarization layer; a first inorganic encapsulation layer, the first inorganic encapsulation layer being on the light-emitting element; an organic encapsulation layer, the organic encapsulation layer being on the first inorganic encapsulation layer; as well as a second inorganic encapsulation layer, the second inorganic encapsulation layer being on the organic encapsulation layer, wherein the first inorganic encapsulation layer extends from the display area to the non-display area, is disposed on the first inorganic layer to cover the organic layer, and extends to the inside of the first groove, and The second inorganic encapsulation layer extends from the display area to the non-display area, is disposed on the second inorganic layer, and extends to the inside of the first groove.

20. The display device according to claim 19, further comprising: A touch insulating layer extends from the display area to the non-display area, is disposed on the second inorganic encapsulation layer, and overlaps the organic layer.

21. The display device according to claim 20, further comprising: A touch bridge metal, wherein the touch bridge metal is disposed on the second inorganic encapsulation layer; A touch sensor metal, wherein the touch sensor metal is disposed on the touch bridge metal; as well as a touch interlayer insulating layer, wherein the touch interlayer insulating layer is disposed between the touch bridge metal and the touch sensor metal, Wherein, the touch insulating layer includes the touch interlayer insulating layer.

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