Display device

Abstract

Disclosed is a display device that prevents appearance defects caused by a density difference between a normal area of a display area and a portion of the display area where a data link intersects the normal area from being perceived. To this end, an anode electrode of each pixel disposed on top of a planar hole in a region where a data link intersects a normal region extends into the planar hole to mask and fill the planar hole to reduce a density difference caused by the planar hole, thereby achieving a narrow bezel while improving yield.

Description

Technical Field

[0001] The present disclosure relates to a display device, and more particularly to a display device with a narrow border achieved by changing connections of data links provided in a display area. Background Art

[0002] An organic light emitting display device is a self-emitting display device. Different from a liquid crystal display device (LCD), the organic light emitting display device does not require a separate light source and can be manufactured in a light and thin form. In addition, the organic light emitting display device is not only advantageous in terms of power consumption caused by low voltage operation, but also has excellent color reproduction, response speed, viewing angle, and contrast ratio (CR), and thus is being studied as a next-generation display.

[0003] The organic light emitting display device uses a plurality of thin film transistors (TFTs) to control current flowing through an organic light emitting diode to display an image. In addition, a structure in which touch electrodes are formed on a display panel to enable a touch operation is applied to the organic light emitting display device.

[0004] The organic light emitting display device can be folded or bent into various shapes using a flexible substrate. In order to expand the display area of the display device and reduce the border area, pads connected to a printed circuit board can be provided on a surface opposite to the surface having the display area. For this purpose, a bending area where the flexible substrate is bent can be defined. Summary of the Invention

[0005] However, in the organic light emitting display device, the border area at the bottom corners of the display area becomes elongated by providing data links extending across the display area.

[0006] The data links for narrow borders in the display area transmit and receive vertical and horizontal signals via planar holes. Therefore, due to the planar holes, a density difference may occur between a normal area of the display area and a portion of the display area where the data link intersects the normal area.

[0007] As a result, an appearance defect in which such a density difference is perceived occurs.

[0008] To solve the above-mentioned problems, the inventors of the present disclosure invented a display device that prevents an appearance defect caused by planar holes in a portion of the display area where a data link intersects a normal area.

[0009] In addition, an object of the present disclosure is to provide a display device in which an anode electrode of each pixel on top of a planar hole provided in an area where a data link intersects a normal area extends into the planar hole to shield the planar hole, thereby reducing a density difference caused by the planar hole, achieving a narrow border, and improving the yield rate at the same time.

[0010] The objects according to the present disclosure are not limited to the above-mentioned objects. Other objects and advantages not mentioned according to the present disclosure can be understood based on the following description, and can be more clearly understood based on the embodiments according to the present disclosure. In addition, it will be easily understood that the objects and advantages according to the present disclosure can be achieved by using the means shown in the claims or combinations thereof.

[0011] An aspect of the present disclosure provides a display device, the display device including: a display panel including a display area provided with at least one pixel and a non-display area provided around the display area; a data driver provided in the non-display area; at least one data wiring respectively connecting at least one pixel to the data driver; and at least one first wiring provided between at least two data wirings and in the non-display area and extending into the display area, wherein at least one first wiring is bent in the display area to intersect with the data wiring; wherein the display area includes a first area provided with at least one pixel and a link area other than the first area, wherein the link area includes: a (1-1) area located at a lower portion of one of two opposite sides of the display area; and a (1-2) area located at a lower portion of the other of two opposite sides of the display area, wherein at least one first wiring is respectively connected to at least one data wiring or at least one power wiring through planar holes in each of the first area, the (1-1) area, and the (1-2) area.

[0012] Another aspect of the present disclosure provides a display device, the display device comprising: a display panel including a light-emitting element, a display area, a non-display area, and a bending area; a gate driver configured to supply a gate signal to the display panel; an upper substrate disposed on the display panel and in the display area; a bending protective layer disposed on an outer surface of a bending portion of the display panel and in the bending area; a data driver disposed below the bending portion of the display panel and in the non-display area and configured to supply a data voltage to the display panel; a controller configured to control the gate driver and the data driver; at least one data wiring respectively connecting at least one pixel to the data driver; at least one power wiring for respectively supplying power to at least one pixel; and at least one first wiring disposed between at least two data wirings and in a layer different from a layer of the at least one data wiring, wherein the at least one first wiring is bent in the display area to intersect the data wiring, wherein the display area includes a first area provided with at least one pixel and a link area other than the first area, wherein the link area includes: a first (1-1) area located at a lower portion of one of two opposite sides of the display area; and a first (1-2) area located at a lower portion of the other of two opposite sides of the display area, wherein the at least one first wiring is respectively connected to the at least one data wiring or the at least one power wiring through a planar hole in each of the first area, the first (1-1) area, and the first (1-2) area.

[0013] Another aspect of the present disclosure provides a display device, which includes a display panel. The display panel includes a display area provided with at least one pixel and a non-display area provided around the display area; a data driver disposed in the non-display area; at least one data wiring respectively connecting at least one pixel to the data driver; and a plurality of first wirings disposed between at least two data wirings and in the non-display area and extending into the display area, wherein the plurality of first wirings are bent in the display area to intersect with the data wirings; wherein the display area includes a first area provided with at least one pixel and a link area other than the first area, and the link area includes: a (1-1) area located at the lower part of one of two opposite sides of the display area; and a (1-2) area located at the lower part of the other of two opposite sides of the display area, and the plurality of first wirings include wirings connected to at least one data wiring or at least one power wiring through planar holes in the first area, wirings connected to dummy wirings extending in the column direction through planar holes in the (1-1) area, and wirings connected to at least one data wiring through planar holes in the (1-2) area.

[0014] Details of other embodiments are included in the detailed description and the drawings.

[0015] The technical solutions according to the embodiments of the present disclosure are not limited to the above-mentioned solutions, and other solutions not mentioned will be clearly understood by those skilled in the art according to the following description.

[0016] According to an embodiment of the present disclosure, the display device can achieve thinning of the border area at the lower corner of the display area by extending the data link across the display area of the display panel.

[0017] In addition, in the display device according to an embodiment of the present disclosure, the anode electrode can extend into the area where the data link intersects with the normal area of the display area to cover and fill the planar holes, thereby reducing the density difference caused by the planar holes. Therefore, in addition to improving the yield, the display device according to an embodiment of the present disclosure can also achieve a narrow border.

[0018] In addition, in the display device according to an embodiment of the present disclosure, it is possible to prevent the appearance defects caused by the density difference due to the planar holes in the area where the data link intersects with the normal area of the display area from being perceived, thereby improving the quality of the display device.

[0019] In addition, according to an embodiment of the present disclosure, as the quality of the display device is improved, its reliability can be ensured, thereby increasing the lifespan of the display panel and realizing a long-lifespan display device.

[0020] In addition to the above effects, while describing the specific details for implementing the present disclosure, the specific effects of the present disclosure are also described together.

[0021] The effects of the present disclosure are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 is a plan view of a display panel of a display device according to an embodiment of the present disclosure.

[0023] Figure 2 is along Figure 1 a cross-sectional view taken along line A-A' in

[0024] Figure 3 is a plan view of a display device magnifying Figure 1 region B of

[0025] Figure 4 is a cross-sectional view of a display device according to an embodiment of the present disclosure.

[0026] Figure 5 is a plan view of a display device magnifying Figure 3 region B of

[0027] Figure 6 is a cross-sectional view of a display panel according to an embodiment of the present disclosure cut along Figure 3 line C-C' in

[0028] Figure 7 is a view showing a display area including a link area in a display panel according to an embodiment of the present disclosure.

[0029] Figure 8 is a view showing an example of dividing a display area into a plurality of areas according to an embodiment of the present disclosure.

[0030] Figure 9 is a view showing an example of a wiring layout in a first area, a (1-1) area, a second area, and a third area of a display area according to an embodiment of the present disclosure.

[0031] Figure 10 is a view showing an example of a wiring layout in a (1-2) area of a display area according to an embodiment of the present disclosure.

[0032] Figure 11 is a view showing a line layout in a first area to a third area of a link area according to an embodiment of the present disclosure.

[0033] Figure 12 It is a cross-sectional view of a circuit layout in a first region of a link area according to an embodiment of the present disclosure.

[0034] Figure 13 It is a cross-sectional view of a circuit layout in a second region and a third region of a link area according to an embodiment of the present disclosure. Detailed Embodiments

[0035] Referring to the embodiments described in detail below in conjunction with the accompanying drawings, the advantages and features of the present disclosure and the methods for achieving these advantages and features will become apparent. However, the present disclosure is not limited to the embodiments disclosed below, but can be implemented in various different forms. Therefore, these embodiments are set forth only to make the present disclosure complete and to fully inform those of ordinary skill in the art to which the present disclosure pertains of the scope of the present disclosure, and the present disclosure is defined only by the scope of the claims.

[0036] For the sake of brevity and clarity of illustration, the elements in the figures are not necessarily drawn to scale. The same reference numerals in different figures represent the same or similar elements and thus perform similar functions. In addition, for the sake of simplicity of description, the description and details of well-known steps and elements are omitted. Furthermore, in the following detailed description of the present disclosure, many specific details are set forth to provide a thorough understanding of the present disclosure. However, it should be understood that the present disclosure can be practiced without these specific details. In other cases, well-known methods, processes, components, and circuits are not described in detail so as not to unnecessarily obscure aspects of the present disclosure. Examples of various embodiments are further illustrated and described below. It should be understood that the description herein is not intended to limit the claims to the specific embodiments described. Instead, it is intended to cover alternatives, modifications, and equivalents that may be included within the spirit and scope of the present disclosure as defined by the appended claims.

[0037] The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings used to describe the embodiments of the present disclosure are illustrative, and the present disclosure is not limited thereto. The same reference numerals herein refer to the same elements. In addition, for the sake of simplicity of description, the description and details of well-known steps and elements are omitted. Furthermore, in the following detailed description of the present disclosure, many specific details are set forth to provide a thorough understanding of the present disclosure. However, it should be understood that the present disclosure can be practiced without these specific details. In other cases, well-known methods, processes, components, and circuits are not described in detail so as not to unnecessarily obscure aspects of the present disclosure.

[0038] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “an” are also intended to include the plural forms. It will also be understood that the terms “comprises,” “comprising,” “includes” and “including,” when used in this specification, specify the presence of stated features, integers, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, operations, elements, components, and / or portions thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one,” when preceding a list of elements, can modify the entire list of elements and can also modify individual elements of the list. When interpreting numerical values, errors or tolerances can occur even if not explicitly described therein.

[0039] In addition, it will also be understood that when a first element or layer is referred to as being “on” a second element or layer, the first element can be directly disposed on the second element or can be indirectly disposed on the second element, where a third element or layer is disposed between the first element or layer and the second element or layer. It should be understood that when an element or layer is referred to as “connected to” or “coupled to” another element or layer, it can be directly on the other element or layer, directly connected to the other element or layer or directly coupled to the other element or layer, or there can be one or more intermediate elements or layers. In addition, it will also be understood that when an element or layer is referred to as being “between” two elements or layers, it can be the only element or layer between the two elements or layers, or there can also be one or more intermediate elements or layers.

[0040] Furthermore, as used herein, when a layer, film, region, plate, etc. is disposed “on” or “on top of” another layer, film, region, plate, etc., the former can directly contact the latter, or another layer, film, region, plate, etc. can be disposed between the former and the latter. As used herein, when a layer, film, region, plate, etc. is directly disposed “on” or “on top of” another layer, film, region, plate, etc., the former directly contacts the latter and no other layer, film, region, plate, etc. is disposed between the former and the latter. Furthermore, as used herein, when a layer, film, region, plate, etc. can be disposed “under” or “beneath” another layer, film, region, plate, etc., the former can directly contact the latter, or another layer, film, region, plate, etc. can be disposed between the former and the latter. As used herein, when a layer, film, region, plate, etc. is directly disposed “under” or “beneath” another layer, film, region, plate, etc., the former directly contacts the latter and no other layer, film, region, plate, etc. is disposed between the former and the latter.

[0041] In the description of temporal relationships, such as the temporal precedence relationship between two events like "after", "subsequently", "before", etc., unless "immediately after", "immediately subsequently", or "immediately before" is indicated, another event may occur between these two events.

[0042] When a certain implementation can be achieved in different ways, the functions or operations specified in a particular block may occur in an order different from the order specified in the flowchart. For example, two consecutive blocks can actually be executed substantially simultaneously, or these two blocks can be executed in the reverse order depending on the functions or operations involved.

[0043] It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, without departing from the spirit and scope of the present disclosure, the first element, component, region, layer, or part described below may be referred to as the second element, component, region, layer, or part.

[0044] The features of the various embodiments of the present disclosure can be partially or fully combined with each other and can be technically related or operable with each other. The embodiments can be implemented independently of each other and can be implemented together in an associated relationship.

[0045] When interpreting a numerical value, unless there is a separate and clear description of it, the value is interpreted as including the error range.

[0046] Unless otherwise defined, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept belongs. It should also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless explicitly defined herein as such.

[0047] The features of the various embodiments of the present disclosure can be partially or fully combined with each other and can be technically related or operable with each other. The embodiments can be implemented independently of each other and can be implemented together in an associated relationship.

[0048] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It should also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0049] As used herein, terms such as "embodiment", "example", "aspect", etc. should not be construed so as to make any described aspect or design superior or better than other aspects or designs.

[0050] In addition, the term "or" means "including or" rather than "exclusive or". That is, unless otherwise stated or clear from the context, the statement "x uses a or b" refers to any of the natural inclusive arrangements.

[0051] The terms used in the following description are chosen as general and common terms in the relevant technical field. However, depending on the development and / or changes in technology, convention, the preferences of those skilled in the art, etc., there may be other terms in addition to these terms. Therefore, the terms used in the following description should not be construed as a limitation on the technical concept, but should be understood as examples of terms used to describe embodiments.

[0052] In addition, in certain cases, the terms may be arbitrarily chosen by the applicant, and in such cases, their detailed meanings will be described in the corresponding description part. Therefore, the terms used in the following description should not be simply understood based on the name of the term, but should be understood based on the meaning of the term and the content of the entire specific embodiment.

[0053] When describing signal flow, for example, when a signal is transmitted from node A to node B, this may include the case where the signal is passed from node A to node B through another node, unless the phrase "immediately transmitted" or "directly transmitted" is used.

[0054] As used herein, the term "display device" may, in a narrow sense, include a display device having a liquid crystal module (LCM), an organic light emitting diode (OLED) module, or a quantum dot (QD) module, which display device includes a display panel and a driver for driving the display panel. In addition, the display device may, in a broad sense, include a laptop computer, a television, a computer monitor, an automotive device or an equipment display for a vehicle, a complete electronic device, a complete device or a complete set of equipment, which includes a complete product or end product having an LCM, an OLED module or a QD module.

[0055] Therefore, the display device according to the present disclosure may, in a narrow sense, include the display device itself having, for example, an LCM, an OLED module, a QD module, etc., and may, in a broad sense, include a set of devices as an application product or an end-user device, which includes a complete product or a final product having an LCM, an OLED module, or a QD module.

[0056] In addition, in some cases, an LCM, an OLED module, or a QD module composed of a display panel and a driver may be represented as a "display device" in a narrow sense. An electronic device as a complete product including an LCM, an OLED module, or a QD module may be represented as a "set of devices" in a broad sense. For example, the display device in the narrow sense may include: a display panel such as a liquid crystal panel, an organic light-emitting display panel, or a quantum dot display panel; and a source PCB as a controller for driving the display panel. The broad set of devices may include: a display panel such as a liquid crystal panel, an organic light-emitting display panel, or a quantum dot display panel; a source PCB as a controller for driving the display panel; and a set of PCBs as a set of controllers electrically connected to the source PCB and controlling the set of devices.

[0057] As used herein, the display panel may be any type of display panel, such as a liquid crystal display panel, an organic light-emitting diode (OLED) display panel, a quantum dot (QD) display panel, and an electroluminescent display panel, etc. The embodiments are not limited thereto. For example, the display panel may be implemented as the following display panel, which may be vibrated by a vibration device according to an embodiment of the present disclosure to generate sound. The display panel applied to the display device according to an embodiment of the present disclosure is not limited to the shape or size of the display panel.

[0058] Hereinafter, a display device according to an embodiment of the present disclosure will be described with reference to the drawings.

[0059] Figure 1 is a plan view of a display panel of a display device according to an embodiment of the present disclosure. Figure 2 is along Figure 1 in the cross-sectional view taken along line A-A'. Figure 3 is an enlarged Figure 1 of the region B of the plan view of the display device.

[0060] Referring to Figure 1 , a display device 10 according to an embodiment of the present disclosure may include a display panel 10' for implementing image display.

[0061] The display panel 10' may include a plurality of regions. For example, the display panel 10' may include a display region (active region) AA provided with at least one pixel PX and a non-display region (non-active region) NA provided around the display region AA. The display region AA is a region for displaying an image and is formed with a pixel array PXL.

[0062] One or more non-display regions NA where no visual image is displayed may include a driver circuit and dams and may be provided on one side of the display region AA. For example, the non-display region NA may be adjacent to one or more sides of the display region AA.

[0063] The non-display region NA surrounds the rectangular display region AA and may be located outside thereof. However, it should be understood that the shape of the display region AA and the position of the non-display region NA adjacent to the display region AA are not particularly limited to those in the display device 10 as Figure 1 shown. Each of the display region AA and the non-display region NA may have an arbitrary shape. Examples of these shapes may include a pentagon, a hexagon, a circle, an ellipse, etc. Embodiments of the present disclosure are not limited thereto.

[0064] The non-display region NA of the display panel 10' may include a region surrounding the display region AA, a pad wiring region PADA, an FPCB connection region FC, and a D-IC connection region DC.

[0065] The FPCB connection region FC may include a first pad FOP_PAD, and the D-IC connection region DC may include a second pad COP_PAD. The first pad FOP_PAD may be connected to the second pad COP_PAD through a plurality of pad wirings (pad data lines) PDL. In this regard, the pad wiring PDL may be a wiring for input and output to the second pad COP_PAD and may be referred to as a fan-out line.

[0066] In addition, a camera device hole CA provided with a camera device may be included within the display region AA. The display device 10 may include at least one camera device hole CA. For example, the display device 10 may include at least one camera device module overlapping with at least one camera device hole CA. However, embodiments of the present disclosure are not limited thereto. For example, the display device 10 may include an optical device including a camera device module.

[0067] When the display panel 10' has been bent, the pad wiring region PADA, the FPCB connection region FC, and the D-IC connection region DC of the display panel 10' may constitute the bottom of the display panel 10'.

[0068] Each pixel PX in the display area AA includes a plurality of sub-pixels SP, and the plurality of sub-pixels SP can display colors such as red (R), green (G), blue (B), and white (W). The plurality of sub-pixels SP can be disposed in the display area AA, and each of the sub-pixels SP can include one or more transistors such as ST1 and ST2. At least one transistor and the light-emitting element EL can be connected to each other.

[0069] Additionally, each of the pixel PX and the sub-pixel SP can be associated with a pixel circuit including one or more TFTs fabricated on the substrate of the display device 10. Each pixel circuit can be electrically connected to the gate line GL and the data wiring DL to communicate with one or more driver circuits, for example, the gate driver GIP and the data driver D-IC located in the non-display area NA of the display device 10.

[0070] The gate driver GIP supplies the gate signal SCAN to the display panel 10'.

[0071] One or more driver circuits can be implemented using the TFTs provided in the non-display area NA. For example, the gate driver GIP can be implemented using a plurality of TFTs on the substrate of the display device 10. Non-limiting examples of circuits that can be implemented using the TFTs on the substrate can include an inverter circuit, a multiplexer, and an electrostatic discharge (ESD) circuit. However, the embodiments of the present disclosure are not limited thereto.

[0072] Some driver circuits can be implemented as integrated circuit (IC) chips and can be mounted in the non-display area NA of the display device 10 using chip on glass (COG) or other similar schemes. Additionally, some driver circuits can be mounted on another substrate and can be coupled to the connection interfaces (pads / bumps, pins) provided in the non-display area NA using a flexible printed circuit board (FPCB), chip on film (COF), tape carrier package (TCP), or other suitable schemes.

[0073] In the embodiments of the present disclosure, at least two different types of TFTs can be provided in the TFT substrate of the display device. The types of TFTs employed in a part of the pixel circuit and a part of the driving circuit can vary according to the requirements of the display device.

[0074] For example, the pixel circuit may be implemented as a TFT (oxide TFT) having an oxide active layer. The driving circuit may be implemented as a TFT having a low-temperature polysilicon active layer (LTPS TFT) and a TFT having an oxide active layer. Different from the LTPS TFT, the oxide TFT is not affected by the variation in the threshold voltage Vth between pixels. A uniform threshold voltage Vth can also be obtained in the array of pixel circuits for display. The problem of the uniformity of the threshold voltage Vth of the TFTs implementing the driving circuit will have a relatively small direct impact on the luminance uniformity of the pixels.

[0075] Using the driving circuit implemented as an LTPS TFT on the substrate, signals and data can be provided to the pixels at a higher clock than in the case where all the TFTs in the TFT panel are implemented as oxide TFTs. Therefore, a display device capable of high-speed operation can be implemented without stains (such as non-uniformity). For example, the advantages of the oxide TFT and the LTPS TFT are combined with the design of the TFT panel, enabling the selective use of the oxide TFT and the LTPS TFT according to their advantages.

[0076] The flexible printed circuit board FPCB may be connected to the display panel 10' and may be disposed in the non-display area NA.

[0077] The data driver D-IC may be connected to the display panel 10' and may be arranged to be spaced apart from the flexible printed circuit board FPCB. The data driver D-IC may be disposed in the non-display area NA and may apply a high-potential driving voltage EVDD and a data voltage Vdata to the display panel 10'.

[0078] Referring to Figure 2 , the display device 10 according to an embodiment of the present disclosure may include a buffer layer 111 disposed on the substrate 100 and a first insulating layer 110 disposed on the buffer layer 111, and a first gate insulating layer 120 disposed on the first insulating layer 110 in the non-display area NA.

[0079] In this regard, the substrate 100 may include a first polyimide layer PL-1, an intermediate layer IL thereon, and a second polyimide layer PL-2 thereon. The buffer layer 111 may include a first buffer layer M-BUF and a second buffer layer A-BUF thereon.

[0080] In addition, the display device 10 may include a third buffer layer O-BUF on the first gate insulating layer 120, a second gate insulating layer 150 on the third buffer layer O-BUF, and a fourth insulating layer 160 disposed on the second gate insulating layer 150 in the non-display area NA.

[0081] In addition, in the non-display area NA, the display device 10 may include a pad wiring PDL on the fourth insulating layer 160, a second planarization layer 180 on the pad wiring PDL, insulating layers 800 and 820 on the second planarization layer 180, and a first touch electrode TE1, a sealing layer SPAC, and a second touch electrode TE2 provided on the pad wiring PDL and the insulating layers 800 and 820.

[0082] In this regard, the insulating layers 800 and 820 may include a touch buffer layer 800 and a touch insulating layer 820, and may be provided on the pad wiring PDL to completely cover the second planarization layer 180.

[0083] In addition, in the non-display area NA, a first adhesive layer ACF1 may be provided on the first touch electrode TE1 and the sealing layer SPAC, a first pad FOP_PAD may be provided on the first adhesive layer ACF1, and a flexible printed circuit board FPCB may be provided on the first pad FOP_PAD.

[0084] In addition, in the non-display area NA, a second adhesive layer ACF2 may be provided on the second touch electrode TE2, a second pad COP_PAD may be provided on the second adhesive layer ACF2, and a data driver D-IC may be provided on the second pad COP_PAD.

[0085] Although not shown in Figure 2 the insulating layers 800 and 820 may be provided on the light-emitting element EL in the display area AA. In the non-display area NA, a plurality of touch electrodes TE1 and TE2 may be provided on the insulating layers 800 and 820, and a plurality of adhesive layers ACF1 and the adhesive layer ACF2 may be respectively provided on the plurality of touch electrodes TE1 and the touch electrode TE2. Although not shown in the drawings, the plurality of adhesive layers ACF1 and the adhesive layer ACF2 may also include an adhesive resin and a plurality of conductive particles provided in the adhesive resin.

[0086] In the non-display area NA, the first pad FOP_PAD may be provided on the first adhesive layer ACF1 which is one of the adhesive layers provided on one side of the plurality of adhesive layers, and is provided below the flexible printed circuit board FPCB. In the non-display area NA, the second pad COP_PAD may be provided on the second adhesive layer ACF2 which is one of the adhesive layers provided on the other side of the plurality of adhesive layers, and is provided below the data driver D-IC.

[0087] A sealing layer SPAC located between a first adhesive layer ACF1 disposed on one side and an insulating layer 800 and an insulating layer 820 may be disposed on the insulating layer 800 and the insulating layer 820 to contact a first touch electrode TE1 disposed on one side among a plurality of touch electrodes.

[0088] In this regard, the sealing layer SPAC may include an insulating organic material. The insulating organic material may include at least one of BCB (benzocyclobutene), an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0089] A first pad FOP_PAD may be disposed under a flexible circuit board FPCB in a non-display area NA and electrically connected to the flexible circuit board FPCB.

[0090] A second pad COP_PAD may be disposed under a data driver D-IC in the non-display area NA and may be electrically connected to the data driver D-IC.

[0091] The plurality of touch electrodes TE1 and TE2 may include: a first touch electrode TE1 disposed on one side, disposed on the insulating layer 800 and the insulating layer 820 in the non-display area NA and under the first pad FOP_PAD; and a second touch electrode TE2 disposed on the other side, disposed on the insulating layer 800 and the insulating layer 820 in the non-display area NA and under the second pad COP_PAD.

[0092] The first adhesive layer ACF1 disposed on one side may be disposed on the first touch electrode TE1 disposed on one side and the sealing layer SPAC and under the first pad FOP_PAD. The second adhesive layer ACF2 disposed on the other side may be disposed on the insulating layer 800 and the insulating layer 820 and the second touch electrode TE2 disposed on the other side, and under the second pad COP_PAD to cover the second touch electrode TE2 disposed on the other side among the plurality of touch electrodes TE2.

[0093] Referring to Figure 3 , wirings extending from a display area AA to a non-display area NA may include data wirings for transmitting a data signal Data to each pixel, gate driving lines GIPL for transmitting a signal to a gate driver GIP, a high-potential voltage line VDD for transmitting a driving voltage, a low-potential voltage line VSS, and a touch signal line 840 for transmitting a touch signal.

[0094] The gate driving lines GIPL may be disposed to overlap with the touch signal line 840, the high-potential voltage line VDD, or the low-potential voltage line VSS.

[0095] The low potential voltage line VSS can be disposed between the touch signal line 840 and the high potential voltage line VDD. The low potential voltage line VSS or the high potential voltage line VDD can be disposed between the gate drive line GIPL and the touch signal line 840.

[0096] Referring to Figure 2 and Figure 3 , the low potential voltage line VSS can be formed in the same layer as the layer of the first wiring SD1 or the second wiring SD2. The high potential voltage line VDD can be formed in the same layer as the layer of the first wiring SD1 or the second wiring SD2.

[0097] These signal lines and voltage lines can be electrically connected to the data driver D-IC and the flexible printed circuit board FPCB.

[0098] At least one data wiring can connect at least one pixel PX and the data driver D-IC to each other respectively. At least one power line VSS can supply power to at least one pixel PX.

[0099] The data driver D-IC can be arranged to be spaced apart from the flexible printed circuit board FPCB by a certain distance.

[0100] The non-display area NA can include a bending area BA and a dam area DM, where the dam is arranged to define the position of the encapsulation layer to protect the light-emitting elements in the display area AA.

[0101] A first connection area CoA1 can be provided between the display area AA and the bending area BA. Contact holes for connecting the wiring extending from the display area AA into the non-display area NA to the bending wiring in the bending area BA are located in the first connection area CoA1.

[0102] In a second connection area CoA2 outside the bending area BA, the wiring in the pad wiring area PADA can be connected to the data driver D-IC and the flexible printed circuit board FPCB.

[0103] The bending area BA can be designated as the area between the first connection area CoA1 and the second connection area CoA2. However, the embodiments of the present disclosure are not limited thereto.

[0104] A plurality of partition walls 940 can be provided in the bending area BA. At least two of the plurality of partition walls 940 can be provided in an area adjacent to the first connection area CoA1, while at least one of the plurality of partition walls 940 can be provided in an area adjacent to the first connection area CoA1. However, the embodiments of the present disclosure are not limited thereto.

[0105] Figure 4 is a cross-sectional view of a display device according to an embodiment of the present disclosure.

[0106] Figure 4 A cross-sectional view schematically showing a bent region of the display panel 10' in the display device 10.

[0107] The first backplane 30 and the second backplane 33 that support the display panel 10' are attached to the bottom of the display panel 10'. The first backplane 30 may be disposed in the display area AA and the first connection area CoA1, while the second backplane 33 may be spaced apart from the first backplane 30 by a certain distance and may be disposed in the pad wiring area PADA, the data driver D-IC area, and the flexible circuit board FPCB area.

[0108] In the space between the first backplane 30 and the second backplane 33, the display panel 10' can be bent such that the lower surfaces of the first backplane 30 and the second backplane 33 face each other.

[0109] The fixing member 31 may be disposed below the first backplane 30. The fixing member 31 may include an adhesive and a heat sink, and may include a metal layer capable of reflecting external light therefrom. However, the embodiments of the present disclosure are not limited thereto.

[0110] The bonding member 32 may be disposed below the fixing member 31 to connect the fixing member 31 and the second backplane 33 to each other. The bonding member 32 may be implemented as a double-sided tape, a double-sided foam adhesive tape, or a double-sided foam adhesive pad.

[0111] A single support member may be cut away in the bending region BA such that the first backplane 30 is on top of the fixing member 31 and below the display panel 10', and the second backplane 33 is below the fixing member 31 and on the rear surface of the display panel 10'. In this regard, a single support member may be cut away in the bending region BA such that the display panel 10' is exposed in the bending region BA, and then, the bending protection layer 34 and the display panel 10' may be bent in the bending region BA such that the second backplane 33 can be attached to the fixing member 31 through the bonding member 32.

[0112] The first backplane 30 and the second backplane 33 may have the same thickness. Alternatively, the first backplane 30 and the second backplane 33 may have different thicknesses. However, the embodiments of the present disclosure are not limited thereto.

[0113] Each of the first backplane 30 and the second backplane 33 may have a strength and thickness equal to or greater than a certain value to supplement the rigidity of the display panel 10'. Since the first backplane 30 is formed to have a certain strength and thickness to supplement the rigidity of the display panel 10', the first backplane may not be formed in the bending region BA where the display panel 10' is bent to have a bent shape. The embodiments of the present disclosure are not limited thereto.

[0114] Based on the shape of the display panel 10' before bending, the second backplane 33 may be disposed below the display panel 10' so as to be spaced apart from the first backplane 30. The second backplane 33 may be disposed below the display panel 10' to supplement the rigidity of the display panel 10' and maintain the display panel 10' in a flat state. Since the second backplane 33 is formed to have a certain strength and thickness to supplement the rigidity of the display panel 10', the second backplane may not be formed in the bending region BA where the display panel 10' is bent to have a bent shape. Embodiments of the present disclosure are not limited thereto.

[0115] The fixing member 31 may support the plane of the display panel 10' when disposed between the first backplane 30 and the second backplane 33. The fixing member 31 may include, for example, metal to enhance the supporting force of the first backplane 30 and the second backplane 33. In addition, the fixing member 31 may be made of a plastic material including at least one of polycarbonate (PC), polyimide (PI), polyethylene naphthalate (PEN), and polyethylene terephthalate (PET). Embodiments of the present disclosure are not limited thereto. Alternatively, the fixing member 31 may include one or a combination of stainless steel (SUS), glass, ceramics, and metal.

[0116] The bending region BA of the display panel 10' may include a region where the partition wall 940 is disposed, and the bending protection layer 34 may be disposed to overlap the partition wall 940. The bending protection layer 34 may include a polymer material and may prevent moisture from penetrating into the bending region BA.

[0117] The bending protection layer 34 may be disposed on the outer surface of the display panel 10' and in the bending region BA. The bending protection layer 34 may improve the deformation of the display panel 10' in the bending region BA and may allow the display panel 10' to bend with a constant curvature. The bending protection layer 34 may be implemented as a resin layer to compensate for the weakening of the rigidity of the display panel due to the bending of the display panel 10' in the bending region BA. In addition, the bending protection layer 34 may be made of a polymer such as polyimide (PI) or polyethylene terephthalate (PET). When the bending protection layer 34 is implemented as a polymer film, the bending protection layer may have a modulus of about 1 GPa to about 10 GPa. Embodiments of the present disclosure are not limited thereto.

[0118] The bending protection layer 34 may include a resin, such as an ultraviolet (UV) curable acrylic resin. However, the present disclosure is not limited thereto. Specifically, the bending protection layer 34 may be made of a cured product of a resin obtained by coating and curing the resin. When the resin is an ultraviolet curable resin, ultraviolet rays may be used to cure the resin.

[0119] The curved protective layer 34 may be disposed on the outer surface of the curved portion of the display panel 10' to cover various signal lines between the pads and the encapsulation portion of the display panel 10'. Accordingly, the curved protective layer 34 may prevent moisture from penetrating into the signal lines while protecting the signal lines from external impacts.

[0120] In addition, the curved protective layer 34 may be disposed on the outer surface of the display panel 10' in the bending area BA, and thus may supplement the rigidity of the display panel 10' in the bending area BA where the support member has been removed. The curved protective layer 34 may include, for example, a micro-coating. The micro-coating (MCL) may be referred to as a micro-cover layer (MCL).

[0121] The data driver D-IC may be disposed under the curved portion of the display panel 10' in the non-display area NA. The data driver D-IC may supply a data voltage to the display panel 10'.

[0122] As Figure 3 shown, the display panel 10' may include a display area AA, a non-display area NA, a bending area BA, and a light-emitting element EL to be described later.

[0123] A cover window 80 may be disposed on the top of the display panel 10'.

[0124] The cover window 80 may include an optical film 81, an adhesive 82, and an upper substrate 83. The optical film 81 may include a polarizing film (POL). Embodiments of the present disclosure are not limited thereto. The adhesive 82 may include at least one layer and may be made of at least one of an OCA (Optically Clear Adhesive), an OCR (Optically Clear Resin), or a pressure-sensitive adhesive (PSA).

[0125] The upper substrate 83 may be disposed on the display panel 10' in the display area AA. The upper substrate 83 may extend such that its end portions are disposed outwardly beyond the curved end portions PE of the display panel 10'. Black ink 84 may be applied on the upper substrate 83 in the area of the display panel 10' corresponding to the non-display area NA to prevent light leakage.

[0126] Although not shown in the drawings, the display device 10 according to an embodiment of the present disclosure may include a gate driver GIP that supplies a gate signal to the display panel 10', and a controller T-Con that controls the gate driver GIP and the data driver D-IC.

[0127] As Figure 4As shown, in the display device 10 according to an embodiment of the present disclosure, an optical film 81 can be provided on the display panel 10', an upper substrate 83 can be provided on the optical film 81 through an adhesive 82, a first backplane 30 can be provided below the display panel 10', a fixing member 31 can be provided below the first backplane 30, a second backplane 33 can be provided below the fixing member 31 through an adhesive member 32, a bent portion of the display panel 10' can be provided below the second backplane 33, and a bending protection layer 34 can be provided below the bent portion of the display panel 10'.

[0128] Figure 5 is a cross-sectional view of a display panel according to an embodiment of the present disclosure taken along line B-B' in Figure 3 and Figure 6 is a cross-sectional view of a display panel according to an embodiment of the present disclosure cut along line C-C' in Figure 3

[0129] Figure 5 and Figure 6 show a flat state of the display panel 10' before its bending and schematically show data wirings for transmitting data signals to each pixel.

[0130] The substrate 100 of a display device according to an embodiment of the present disclosure can be composed of a first substrate, a second substrate, and an intermediate layer between the first substrate and the second substrate.

[0131] Each of the first substrate and the second substrate can be made of at least one of polyimide, polyethersulfone, polyethylene terephthalate, and polycarbonate. Embodiments of the present disclosure are not limited thereto. When the substrate is made of a plastic material, when a support substrate made of glass is provided below the substrate, a manufacturing process of the display device is performed. After the manufacturing process of the display device is completed, the support substrate can be released therefrom. In addition, after the support substrate is released, a backplane (or plate) for the support substrate can be provided below the substrate. When the substrate is made of a plastic material, moisture may penetrate the substrate and reach the thin film transistor or the light emitting element layer, thereby deteriorating the performance of the display device. A display device according to an embodiment of the present disclosure can include two substrates, namely, a first substrate and a second substrate made of a plastic material, to prevent the performance of the display device from deteriorating due to moisture penetration. In addition, an inorganic intermediate layer can be provided between the first substrate and the second substrate so that the performance reliability of the product can be improved by preventing moisture from penetrating the substrate. The intermediate layer can be made of an inorganic material. For example, the intermediate layer can be composed of a single layer or multiple layers made of silicon nitride (SiNx) or silicon oxide (SiOx). However, the present disclosure is not limited thereto.

[0132] ​A display device including a substrate 100 may include a plurality of regions. The regions may include a display region AA and a non-display region NA. However, the present disclosure is not limited thereto.

[0133] A buffer layer 111 composed of a single layer or multiple layers made of silicon nitride (SiNx) or silicon oxide (SiOx) may be provided in both the display region AA and the non-display region NA and on one surface of the substrate 100. The buffer layer 111 may improve the adhesion between the layer formed thereon and the substrate 100 and block various types of defect factors, such as alkaline components leaking from the substrate 100. In addition, the buffer layer 111 may delay the diffusion of moisture or oxygen that has penetrated the substrate 100.

[0134] Based on the type and material of the substrate, the structure and type of the thin-film transistor, etc., the buffer layer 111 may be omitted.

[0135] The transistors in the display region AA may include a switching transistor ST1 or a driving transistor DT for driving a sub-pixel SP.

[0136] A light-blocking layer 200 may be provided under the driving transistor DT.

[0137] The light-blocking layer 200 may be connected to the first drain electrode 230D of the driving transistor DT. The light-blocking layer 200 may prevent light from being guided to the first semiconductor layer 210 of the driving transistor DT and may be connected to the first drain electrode 230D to prevent the phenomenon of parasitic carrier accumulation in the first semiconductor layer 210, which may cause the drain current to increase rapidly or cause a change in the threshold voltage due to this phenomenon.

[0138] The light-blocking layer 200 may be composed of multiple layers including a first layer and a second layer. The first layer includes titanium (Ti), which is the same material as that of the first source electrode 230S and the first drain electrode 230D, and the second layer includes at least one of molybdenum (Mo), copper (Cu), aluminum (Al), silver (Ag), chromium (Cr), gold (Au), neodymium (Nd), and nickel (Ni). Embodiments of the present disclosure are not limited thereto.

[0139] A first insulating layer 110 may be provided on the light-blocking layer 200. The first insulating layer 110 may be made of an insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx), or may be made of an insulating inorganic material or an insulating organic material other than silicon nitride or silicon oxide. Embodiments of the present disclosure are not limited thereto.

[0140] The first semiconductor layer 210 of the driving transistor DT in the display region AA may be provided on the first insulating layer 110, and the first semiconductor layer 210 may overlap with the light-blocking layer 200.

[0141] The first semiconductor layer 210 may be made of low temperature polycrystalline silicon (LTPS).

[0142] The first gate insulating layer 120 may be disposed on the first semiconductor layer 210. The first gate insulating layer 120 may be made of an insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx), or may be made of an insulating inorganic material or an insulating organic material other than silicon nitride or silicon oxide. Embodiments of the present disclosure are not limited thereto.

[0143] The first gate electrode 220 may be disposed on the first gate insulating layer 120 to overlap the first semiconductor layer 210.

[0144] The first gate electrode 220 may be made of at least one of silver (Ag), molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), nickel (Ni), neodymium (Nd), tungsten (W), and gold (Au). Embodiments of the present disclosure are not limited thereto.

[0145] The first metal layer 300 overlapping the first switching transistor ST1 and the first capacitor electrode Cst1 of the capacitor Cst included in the sub-pixel SP may be disposed on the first gate insulating layer 120 in the display area AA. In the non-display area NA, the link wiring 650 may be disposed on the first gate insulating layer 120.

[0146] The first capacitor electrode Cst1, the first metal layer 300, and the link wiring 650 may be formed in the same process as the process of forming the first gate electrode 220. As Figure 3 shown, the link wiring 650 may include a gate driving line GIPL.

[0147] The first metal layer 300 may be driven by the lower gate electrode of the first switching transistor ST1, or may be used as a light blocking layer that can prevent light from reflecting toward the second semiconductor layer 310 of the first switching transistor ST1. Embodiments of the present disclosure are not limited thereto.

[0148] The second insulating layer 130 may be disposed on the first gate electrode 220, the first capacitor electrode Cst1, the first metal layer 300, and the first link wiring 650.

[0149] The second insulating layer 130 may be made of an insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx), or may be made of an insulating inorganic material or an insulating organic material other than silicon nitride or silicon oxide. Embodiments of the present disclosure are not limited thereto.

[0150] The second capacitor electrode Cst2 of the capacitor Cst can be disposed on the second insulating layer 130. The second capacitor electrode Cst2 can be disposed to overlap with the first capacitor electrode Cst1 and can be made of the same material as that of the first capacitor electrode Cst1.

[0151] The second link wiring 651 can be disposed in the non-display area and on the second insulating layer 130, and can be formed in the same process as the process of forming the second capacitor electrode Cst2.

[0152] The third insulating layer 140 can be disposed on the second capacitor electrode Cst2.

[0153] The third insulating layer 140 can be made of an insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx), or can be made of an insulating inorganic material or an insulating organic material other than silicon nitride or silicon oxide. Embodiments of the present disclosure are not limited thereto.

[0154] The second semiconductor layer 310 of the first switching transistor ST1 in the display area AA can be disposed on the third insulating layer 140.

[0155] The second semiconductor layer 310 can be made of a metal oxide semiconductor such as indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium gallium tin oxide (IGTO), and indium gallium oxide (IGO). However, the present disclosure is not limited thereto.

[0156] The metal oxide semiconductor can include a channel region, a source region, and a drain region in which electrons or holes migrate through.

[0157] For example, the conductive characteristics of the source region and the drain region can be improved by a doping process of implanting impurities. During an etching process of forming a gate electrode on the metal oxide semiconductor, oxygen in a region of the metal oxide semiconductor that does not overlap with the gate electrode can be released to improve its conductivity, so that the source region and the drain region can become conductive. The source electrode and the drain electrode can be connected to the source region and the drain region, respectively.

[0158] The second gate insulating layer 150 can be disposed on the second semiconductor layer 310, and the second gate electrode 320 can be disposed on the second gate insulating layer 150.

[0159] The second gate insulating layer 150 can be made of an insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx), or can be made of an insulating inorganic material or an insulating organic material other than silicon nitride or silicon oxide. Embodiments of the present disclosure are not limited thereto.

[0160] The second gate electrode 320 may be disposed on the second gate insulating layer 150 to overlap with the second semiconductor layer 310.

[0161] The second gate electrode 320 may be composed of a single layer or multiple layers made of one of silver (Ag), molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), nickel (Ni), neodymium (Nd), tungsten (W), and gold (Au), or an alloy thereof. Embodiments of the present disclosure are not limited thereto.

[0162] A third link wiring 652 may be disposed on the second gate insulating layer 150 in the non-display area NA.

[0163] The first link wiring 650, the second link wiring 651, and the third link wiring 652 may extend to the display area AA, and a signal or a power voltage may be applied to the display area AA. The first link wiring 650, the second link wiring 651, and the third link wiring 652 may be connected to each other via contact holes. However, embodiments of the present disclosure are not limited thereto.

[0164] The third link wiring 652 may extend from the non-display area NA and be disposed to at least partially overlap with the dam region DM in the non-display area NA.

[0165] A fourth insulating layer 160 may be disposed on the second gate electrode 320 and the third link wiring 652. The fourth insulating layer 160 may be made of an insulating inorganic material such as silicon nitride (SiNx) or silicon oxide (SiOx), or may be made of one or more organic insulating materials such as BCB (benzocyclobutene), acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. However, embodiments of the present disclosure are not limited thereto.

[0166] A first source electrode 230S and a first drain electrode 230D connected to the first semiconductor layer 210 and a second source electrode 330S and a second drain electrode 330D connected to the second semiconductor layer 310 may be disposed on the fourth insulating layer 160.

[0167] The first source electrode 230S and the first drain electrode 230D are connected to the first semiconductor layer 210 via contact holes extending through the first gate insulating layer 120, the second insulating layer 130, the third insulating layer 140, the second gate insulating layer 150, and the fourth insulating layer 160.

[0168] The second source electrode 330S and the second drain electrode 330D are connected to the second semiconductor layer 310 via contact holes extending through the second gate insulating layer 150 and the fourth insulating layer 160.

[0169] The fourth link wiring 654 may be disposed on the fourth insulating layer 160 in the non-display area NA. The fourth link wiring 654 may be formed in the same process as the process of forming the first source electrode 230S, the first drain electrode 230D, the second source electrode 330S, and the second drain electrode 330D.

[0170] Each of the first source electrode 230S, the first drain electrode 230D, the second source electrode 330S, the second drain electrode 330D, and the fourth link wiring 654 may be made of at least one of silver (Ag), molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), nickel (Ni), neodymium (Nd), tungsten (W), and gold (Au) or an alloy thereof. Embodiments of the present disclosure are not limited thereto.

[0171] The link wiring between the dam region DM of the non-display area NA and the display area AA may be electrically connected to each other via a contact hole. The fourth link wiring 654 may be electrically connected to the fifth link wiring 630 and the third link wiring 652. However, embodiments of the present disclosure are not limited thereto.

[0172] A plurality of contact holes may be formed in the first connection area CoA1 of the non-display area NA to connect the link wiring and the driving signal bending wiring 680 of the bending area BA to each other. In the first connection area CoA1, the first link wiring 650 and the fourth link wiring 654 may be connected to each other via a contact hole, or the second link wiring 651 may be connected to the fourth link wiring 654 via a contact hole, and the third link wiring 652 may be connected to the fourth link wiring 654 via a contact hole. However, embodiments of the present disclosure are not limited thereto.

[0173] The first planarization layer 170 may be disposed on the first source electrode 230S, the first drain electrode 230D, the second source electrode 330S, the second drain electrode 330D, and the fourth link wiring 654.

[0174] The first planarization layer 170 may be implemented as an organic insulating layer made of, for example, polyacrylate or polyimide, and may reduce steps due to the underlying wiring and contact holes.

[0175] Due to the bending curvature of the display panel 10' in the bending area BA, cracks may occur in the insulating film formed as an inorganic insulating film. Therefore, in the bending area BA, the inorganic insulating film may be easily penetrated by moisture. For this reason, the inorganic insulating film that is easily penetrated by moisture in the bending area BA may be completely removed in the etching process.

[0176] When each of the buffer layer 111, the first insulating layer 110, the first gate insulating layer 120, the second insulating layer 130, the third insulating layer 140, the second gate insulating layer 150, and the fourth insulating layer 160 is implemented as an inorganic insulating film, each of the buffer layer 111, the first insulating layer 110, the first gate insulating layer 120, the second insulating layer 130, the third insulating layer 140, the second gate insulating layer 150, and the fourth insulating layer 160 can be removed in the bending region BA during an etching process and may not be provided in the bending region BA.

[0177] A part of the substrate 100 can be etched to control the bending curvature of the bending region BA.

[0178] During the etching process, the ends of the insulating layers may not be aligned with each other in a vertical manner such that the insulating layers can be stacked in a stepped manner. However, embodiments of the present disclosure are not limited thereto.

[0179] The first planarization layer 170 can be in contact with the ends of the insulating layers and the substrate 100 in the bending region BA.

[0180] The connection electrode 240 can be provided on the first planarization layer 170 to connect the first drain electrode 230D and the anode electrode 600 to each other.

[0181] The connection electrode 240 can be electrically connected to the first drain electrode 230D via a contact hole formed in the first planarization layer 170.

[0182] On the first planarization layer 170, a fifth link wiring 630, a first connection region CoA1, and a driving signal bending wiring 680 of the bending region BA can be provided in the non-display region NA. The bending wiring 680 can be connected to the fourth link wiring 654 via a contact hole and can extend into the bending region BA to be electrically connected to the wiring of the pad wiring region PADA.

[0183] Each of the connection electrode 240, the fifth link wiring 630, and the bending wiring 680 can be made of at least one of silver (Ag), molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), nickel (Ni), neodymium (Nd), tungsten (W), and gold (Au) or an alloy thereof. Embodiments of the present disclosure are not limited thereto.

[0184] A second planarization layer 180 can be provided on the connection electrode 240, the fifth link wiring 630, and the driving signal bending wiring 680. The second planarization layer 180 can be implemented as an organic insulating layer made of, for example, polyacrylate or polyimide. Embodiments of the present disclosure are not limited thereto.

[0185] The second planarization layer 180 may be disposed on the first connection area CoA1 of the non-display area NA, and may be disposed on the driving signal bending wiring 680 in the bending area BA.

[0186] The light-emitting element EL may be disposed on the second planarization layer 180. The light-emitting element EL may include an anode electrode 600, a light-emitting layer 610, and a cathode electrode 620. Accordingly, the anode electrode 600 may be disposed on the second planarization layer 180.

[0187] The anode electrode 600 may be electrically connected to the connection electrode 240 through a through hole formed in the second planarization layer 180. The anode electrode 600 may be made of at least one of silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr), lead (Pd), indium tin oxide (ITO), indium zinc oxide (IZO), or an alloy thereof. Embodiments of the present disclosure are not limited thereto.

[0188] The bank 190 may be disposed on the anode electrode 600 and the second planarization layer 180.

[0189] The bank 190 may distinguish multiple sub-pixels from each other, and may minimize light blur and prevent color mixing from occurring at various viewing angles.

[0190] The bank 190 may not cover the portion of the anode electrode 600 corresponding to the light-emitting area to expose the anode electrode 600, and may overlap with the end portion of the anode electrode 600. The bank 190 may be made of an insulating inorganic material such as silicon nitride (SiNx) or silicon oxide (SiOx), or may be made of one or more organic insulating materials such as BCB (benzocyclobutene), acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. However, embodiments of the present disclosure are not limited thereto.

[0191] The spacer 191 may be further disposed on the bank 190. The spacer 191 may maintain a gap between the substrate 100 on which the light-emitting layer 610 is formed and the touch unit and the cover window disposed on top thereof. Accordingly, when an external physical impact is applied thereto, damage to the elements inside the display panel may be minimized due to the gap. The spacer 191 may be made of the same material as the material of the bank 190, and may be formed in the same process as the process of forming the bank 190. However, embodiments of the present disclosure are not limited thereto.

[0192] The light-emitting layer 610 may be disposed in the opening of the portion of the exposed anode electrode 600 of the bank 190. The light-emitting layer 610 may include one or more of a red light-emitting layer, a green light-emitting layer, a blue light-emitting layer, and a white light-emitting layer to emit light of a specific color. In addition, in addition to the organic light-emitting layer, the light-emitting layer 610 may further include a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer. However, embodiments of the present disclosure are not limited thereto. However, embodiments of the present disclosure are not limited thereto.

[0193] The hole injection layer, the hole transport layer, the electron transport layer, and the electron injection layer may be separately disposed in each of the sub-pixels and may have different thicknesses and materials. Alternatively, each of the hole injection layer, the hole transport layer, the electron transport layer, and the electron injection layer may be commonly disposed in the entire display area.

[0194] When the light-emitting layer 610 includes a white organic light-emitting layer, the light-emitting layer 610 may be disposed in the opening of the bank 190 and throughout the substrate.

[0195] A color filter may be disposed on the light-emitting layer 610 to convert the light emitted from the white organic light-emitting layer into light of a different color other than white.

[0196] A cathode electrode 620 may be disposed on the light-emitting layer 610. The cathode electrode 620 may supply electrons to the light-emitting layer 610 and may be made of a conductive material having a low work function.

[0197] When the display device 10 operates in a top-emission scheme, the cathode electrode 620 may be made of a transparent conductive material through which light is transmitted. For example, the cathode electrode 620 may be made of at least one of indium tin oxide (ITO) and indium zinc oxide (IZO). However, embodiments of the present disclosure are not limited thereto.

[0198] Alternatively, the cathode electrode 620 may be made of a semi-transparent conductive material through which light is transmitted. For example, the cathode electrode 620 may be made of at least one of the following alloys: LiF / Al, CsF / Al, Mg:Ag, Ca / Ag, Ca:Ag, LiF / Mg:Ag, LiF / Ca / Ag, and LiF / Ca:Ag. However, embodiments of the present disclosure are not limited thereto.

[0199] When the display device 10 operates in a bottom-emission scheme, the cathode electrode 620 may be implemented as a reflective electrode that reflects light and may be made of an opaque conductive material. For example, the cathode electrode 620 may be made of at least one of silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr), or an alloy thereof. However, embodiments of the present disclosure are not limited thereto.

[0200] In the non-display area NA, a driving circuit area and a dam area DM provided with a plurality of dams may be provided.

[0201] The dam area DM may be an area of the driving circuit area of the sealed display panel 10' and the pixel area PXL of the display area AA.

[0202] The dam area DM may include a plurality of dams, such as a first dam DM1 and a second dam DM2.

[0203] The first dam DM1 may use the same material as each of the first planarization layer 170 and the bank 190, and may be deposited in the same process as the process of forming each of the first planarization layer 170 and the bank 190. The second dam DM2 may use the same material as each of the first planarization layer 170, the bank 190, and the spacer 191, and may be deposited in the same process as the process of forming each of the first planarization layer 170, the bank 190, and the spacer 191. However, the embodiments of the present disclosure are not limited thereto.

[0204] The first dam DAM1 and the second dam DAM2 may have a first height and a second height, respectively, and may surround the display area AA.

[0205] The second dam DAM2 may be higher than the first dam DAM1. The second height may be greater than the first height. Although the second encapsulation layer 720 of the encapsulation layer 700 to be described later extends above the first dam DM1 in the dam area DM, the second encapsulation layer 720 may not extend beyond the second dam DM2 in the dam area DM and may be blocked by the second dam DM2.

[0206] The first encapsulation layer 710 and the third encapsulation layer 730 of the encapsulation layer 700 may extend above the second dam DM2 to an external area outside the dam area DM, and may be provided on the second planarization layer 180 in the first connection area CoA1.

[0207] The encapsulation layer 700 may be provided on a part of the cathode electrode 620 in the display area AA, a part of the cathode electrode 620 in the non-display area NA, and the second dam DM2.

[0208] The encapsulation layer 700 may protect the display device 10 from external moisture, oxygen, or foreign substances. For example, the encapsulation layer 700 may prevent oxygen and moisture from penetrating into the display device from the outside to prevent oxidation of the light-emitting material and the electrode material.

[0209] The encapsulation layer 700 may be made of a transparent material to transmit the light emitted from the light-emitting layer 610 therethrough.

[0210] The encapsulation layer 700 may be disposed on the light-emitting elements EL600, 610, or 620 of a pixel in the display area AA. The encapsulation layer 700 may include a first encapsulation layer 710, a second encapsulation layer 720, and a third encapsulation layer 730 that block the penetration of moisture or oxygen. However, embodiments of the present disclosure are not limited thereto. The first encapsulation layer 710, the second encapsulation layer 720, and the third encapsulation layer 730 may be sequentially stacked. However, embodiments of the present disclosure are not limited thereto.

[0211] Each of the first encapsulation layer 710 and the third encapsulation layer 730 may be made of at least one inorganic material selected from silicon nitride (SiNx), silicon oxide (SiOx), or aluminum oxide (AlyOz). However, embodiments of the present disclosure are not limited thereto.

[0212] The second encapsulation layer 720 may cover foreign substances or particles that may be generated during the manufacturing process. In addition, the second encapsulation layer 720 may flatten the surface steps of the first encapsulation layer 710.

[0213] The second encapsulation layer 720 may be made of an organic material such as silicon oxycarbide (SiOC), epoxy resin, polyimide, polyethylene, or an acrylate-based polymer. However, embodiments of the present disclosure are not limited thereto.

[0214] The touch buffer layer 800 may be disposed on the third encapsulation layer 730. The touch buffer layer 800 may be disposed throughout the entire display area AA and the non-display area NA, and may extend into a part of the bending area BA.

[0215] The touch buffer layer 800 may be made of at least one inorganic material selected from silicon nitride (SiNx), silicon oxide (SiOx), or aluminum oxide (AlyOz). However, embodiments of the present disclosure are not limited thereto.

[0216] The touch electrodes 810 and 830 may be disposed on the encapsulation layer 700 in the display area AA, and the touch electrodes 810 and 830 may include a first touch electrode 810 and a second touch electrode 830.

[0217] The touch buffer layer 800 may be disposed on the encapsulation layer 700, the first touch electrode 810 may be disposed on the touch buffer layer 800, the touch insulating layer 820 may be disposed on the touch buffer layer 800 and the first touch electrode 810, and the second touch electrode 830 may be disposed on the touch insulating layer 820.

[0218] The touch operation can be implemented by a plurality of sensing electrodes and a plurality of driving electrodes provided in the display area AA. Each sensing electrode may include a plurality of sub-sensing electrodes, and the plurality of sub-sensing electrodes extend in a first direction and are spaced apart from each other at regular intervals in a second direction. The plurality of sensing electrodes may not be disconnected, but may continuously extend in the first direction. The first direction and the second direction may intersect with each other. For example, the first direction and the second direction may be perpendicular to each other.

[0219] Each of the plurality of driving electrodes may include a plurality of sub-driving electrodes, and the sub-driving electrodes extend in the second direction and are spaced apart from each other at regular intervals in the first direction. The plurality of sub-driving electrodes may be electrically connected to each other in the second direction.

[0220] When the plurality of sub-sensing electrodes and the plurality of sub-driving electrodes are formed in the same layer, the plurality of sub-driving electrodes may be electrically connected to each other through a bridging pattern. The plurality of sub-sensing electrodes and the plurality of sub-driving electrodes may have a metal mesh structure.

[0221] Additionally, the plurality of sub-sensing electrodes may be electrically connected to each other through a bridging pattern, and the plurality of sub-driving electrodes may not be disconnected but may continuously extend and may be electrically connected to each other.

[0222] The first touch electrode 810 may serve as the plurality of sub-sensing electrodes, the plurality of sub-driving electrodes, or the bridging pattern.

[0223] The first touch electrode 810 may have a single-layer or multi-layer structure made of a metal material such as molybdenum (Mo), silver (Ag), titanium (Ti), copper (Cu), aluminum (Al), titanium / aluminum / titanium (Ti / Al / Ti), or molybdenum / aluminum / molybdenum (Mo / Al / Mo). However, the present disclosure is not limited thereto.

[0224] A touch insulating layer 820 may be provided on the first touch electrode 810. The touch insulating layer 820 may be provided over the entire display area AA and the non-display area NA, and may be provided to extend into a part of the bending area BA.

[0225] The touch insulating layer 820 may be made of at least one inorganic material selected from silicon nitride (SiNx), silicon oxide (SiOx), or aluminum oxide (AlyOz). However, the present disclosure is not limited thereto.

[0226] A second touch electrode 830 may be provided on the touch insulating layer 820. The second touch electrode 830 may serve as the plurality of sub-sensing electrodes, the plurality of sub-driving electrodes, or the bridging pattern for the touch operation.

[0227] In the same process as the process of forming the second touch electrode 830, a touch signal line 840 for transmitting a touch driving signal to the non-display area NA may be formed on the touch insulating layer 820. The touch signal line 840 may include the same material as the materials of the touch electrode 810 and the touch electrode 830.

[0228] Each of the second touch electrode 830 and the touch signal line 840 may have a single-layer or multi-layer structure made of a metal material such as molybdenum (Mo), silver (Ag), titanium (Ti), copper (Cu), aluminum (Al), titanium / aluminum / titanium (Ti / Al / Ti), or molybdenum / aluminum / molybdenum (Mo / Al / Mo). However, embodiments of the present disclosure are not limited thereto.

[0229] A third planarization layer 850 may be provided on the second touch electrode 830 and the touch signal line 840.

[0230] The third planarization layer 850 may cover the second touch electrode 830, the touch signal line 840, and the touch insulating layer 820, and planarization may be performed thereon. In addition, the third planarization layer 850 may be made of one or more organic insulating materials such as BCB (benzocyclobutene), acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. However, the present disclosure is not limited thereto.

[0231] A partition wall 940 may be provided in the bending area BA. The partition wall 940 may be formed in the same process as the process of forming the third planarization layer 850, and may be provided on the second planarization layer 180. The partition wall 940 may include a first partition wall 940_1, a second partition wall 940_2, and a third partition wall 940_3. The first partition wall 940_1 and the second partition wall 940_2 may be provided in an area adjacent to the display area, and the third partition wall 940_3 may be provided in an area adjacent to the pad wiring area PADA.

[0232] The first partition wall 940_1 may overlap with ends of each of the touch buffer layer 800 and the touch insulating layer 820 extending into a part of the bending area BA, and cover the ends of each of the touch buffer layer 800 and the touch insulating layer 820 extending into a part of the bending area BA.

[0233] The touch buffer layer 800 and the touch insulating layer 820 may extend beyond ends of each of the buffer layer 111, the first insulating layer 110, the first gate insulating layer 120, the second insulating layer 130, the third insulating layer 140, the second gate insulating layer 150, and the fourth insulating layer 160 provided under the first planarization layer 170, and then may extend into the bending area BA.

[0234] External moisture can penetrate through the contact holes formed in the first connection region CoA1 of the bending region BA. Such moisture penetration may cause corrosion of the wirings in the first connection region CoA1 and reduce the reliability of the display device 10.

[0235] Since the touch buffer layer 800 and the touch insulation layer 820 can be arranged to extend into the bending region BA, the external moisture penetration path can be further extended into the bending region BA, so that the moisture penetration into the light-emitting region and the electrode region can be reduced.

[0236] The protective layer 860 can be arranged on the third planarization layer 850. The protective layer 860 can protect the display panel 10' from foreign substances or particles and can planarize the surface steps of the display panel 10'. The protective layer 860 can be made of an organic material such as silicon oxycarbide (SiOC) or epoxy resin, polyimide, polyethylene or an acrylate-based polymer. However, the present disclosure is not limited thereto.

[0237] The protective layer 860 can extend beyond the third planarization layer 850 and can be arranged in a part of the bending region BA. The first partition wall 940_1 and the second partition wall 940_2 can prevent the protective layer 860 from extending into the region where the display panel 10' is substantially bent in the bending region BA.

[0238] The adhesive layer 71 for attaching the display panel 10' and the cover window 80 to each other can be arranged on the protective layer 860.

[0239] Figure 6 is a cross-sectional view of a display panel according to an embodiment of the present disclosure taken along line C-C' in Figure 3 and schematically shows a touch signal line 840 for transmitting a touch signal.

[0240] When describing Figure 6 the components in Figure 5 the description of the components that are the same as or corresponding to the components in

[0241] The touch signal line 840 can extend into the non-display region NA while being arranged on the touch insulation layer 820 to overlap with the dam region DM and is electrically connected to the touch bending wiring 690 in the first connection region CoA1.

[0242] The contact hole can extend through the second planarization layer, the touch buffer layer 800 and the touch insulation layer 820 in the first connection region CoA1, so that the touch signal line 840 and the touch bending wiring 690 can be connected to each other via the contact hole.

[0243] The touch bending wiring 690 can be formed in Figure 5in the same layer as the layer in which the driving signal bending wiring 680 is formed, and can be formed in the same process as the process of forming the driving signal bending wiring 680. Figure 5 in the same process as the process of forming the driving signal bending wiring 680.

[0244] The touch buffer layer 800 and the touch insulation layer 820 can extend beyond the end of the touch signal line 840 toward the bending area BA, and can be set to overlap with the first partition wall 940_1.

[0245] The end of the touch signal line 840 can overlap with the third planarization layer 850.

[0246] Figure 7 is a diagram showing a display area including a link area LiA in a display panel according to an embodiment of the present disclosure, and Figure 8 is an example of dividing the display area into multiple areas according to an embodiment of the present disclosure.

[0247] Referring to Figure 7 , the display panel 10' according to an embodiment of the present disclosure may include a link area LiA adjacent to the second pad COP_PAD in the display area AA.

[0248] In this regard, the link area LiA refers to an area where the data connection line intersects a part of the first wiring SL1 in the display area AA, and can be provided in the lower part of the display area AA.

[0249] In this regard, the second pad COP_PAD can be provided under the data driver D-IC in the non-display area NA, as Figure 2 shown, and can be electrically connected to the data driver D-IC. Therefore, in the display area AA, the link area LiA can be provided adjacent to the data driver D-IC.

[0250] In a conventional display panel, the fan-out data lines PDL can extend from the second pad COP_PAD to the data wiring in the display area in a fan shape, for example.

[0251] However, the fan-out data lines according to an embodiment of the present disclosure can be extended such that at least one first wiring SL1 extends in the column direction in the non-display area and is provided between the data wirings DL and extends into the display area AA, and is bent to extend in the row direction in the display area AA to overlap or intersect with a plurality of data wirings DL extending in the column direction.

[0252] Referring to Figure 8 , the display area AA according to an embodiment of the present disclosure may include a first area ① provided with at least one pixel PX and a link area LiA other than the first area.

[0253] The link area LiA may include a first (1-1) area ①' at the lower part of one of the two opposite sides in the row direction of the display area AA and a first (1-2) area ①" at the lower part of the other of the two opposite sides in the row direction of the display area AA. For example, the link area LiA may include the first (1-1) area ①' at the lower part of the left side of the display area AA and the first (1-2) area ①" at the lower part of the right side of the display area AA.

[0254] The link area LiA may further include a second area ② and a third area ③. For example, the link area LiA may include the second area ② and the third area ③ defined between the first (1-1) area ①' and the first (1-2) area ①".

[0255] The second area ② and the third area ③ may be positioned adjacent to each other. Each of the second area ② and the third area ③ may have a triangular shape. When the second area ② has a triangular shape, the third area ③ may have an inverted triangular shape.

[0256] In the link area LiA, the first (1-1) area ①' and the first (1-2) area ①" may be respectively disposed adjacent to two separate third areas ③. That is, one of the two separate third areas ③ is defined between the first (1-1) area ①' and the second area ②, and the other of the two separate third areas ③ is defined between the first (1-2) area ①" and the second area ②.

[0257] The data wiring DL may extend downward in the column direction from the first area ① of the display area AA to the link area LiA. The data wiring DL may extend downward in the column direction and then bend at a position adjacent to the link area LiA upward to extend in the row direction.

[0258] For example, the low-potential power wiring VSSL may be provided in each of the upper end and the lower end of the non-display area NA of the display panel 10'. At least one low-potential power wiring VSSL may supply low-potential power to the display panel 10'. For example, at least one low-potential power wiring VSSL may supply low-potential power to at least one pixel PX provided in the display panel 10' respectively.

[0259] Figure 9 is a diagram showing an example of the wiring arrangement in the first area ①, the first (1-1) area ①', the second area ②, and the third area ③ of the display area according to an embodiment of the present disclosure. Figure 10 is a diagram showing an example of the wiring arrangement in the first (1-2) area ①" of the display area according to an embodiment of the present disclosure.

[0260] At least one first wiring SL1 provided in the display area AA according to an embodiment of the present disclosure may include, for example, a low-potential power supply horizontal wiring H Link (VSSL) or a data power supply horizontal wiring H Link (DL).

[0261] Referring Figure 9 and Figure 10 , at least one first wiring SL1 may be connected to at least one data wiring DL or at least one power wiring VSSL via the planar holes PLN_H in the first region ①, the (1-1) region ①', and the (1-2) region ①".

[0262] In the first region ①, the low-potential power supply horizontal wiring H Link (VSSL) may intersect with the low-potential power supply vertical wiring V Link (VSSL) and the data wiring DL extending in the column direction. In this regard, the low-potential power supply horizontal wiring H Link (VSSL) may be electrically connected to the low-potential power supply vertical wiring V Link (VSSL) via the planar hole PLN_H.

[0263] In the second region ② and the third region ③, the low-potential power supply horizontal wiring H Link (VSSL) may intersect with the data power supply vertical wiring V Link (DL) and the data wiring DL extending in the column direction. In this regard, the low-potential power supply horizontal wiring H Link (VSSL) may be electrically connected to each of the data power supply vertical wiring VLink (DL) and the data wiring DL without passing through the planar hole PLN_H.

[0264] In the (1-1) region ①', one first wiring SL1 may intersect with the dummy wiring Dm and the data wiring DL extending in the column direction. In this regard, one first wiring SL1 may not be electrically connected to the data wiring DL. However, one first wiring SL1 may be electrically connected to each of the dummy wirings Dm via the planar hole PLN_H. Additionally, the anode electrode AE adjacent to the planar hole PLN_H may extend into the planar hole PLN_H and completely cover the planar hole PLN_H.

[0265] As Figure 5 described, one pixel PX among at least one or more pixels provided in the display area AA may include an anode electrode 600, a light-emitting layer 610, and a cathode electrode 620. One pixel may be referred to as a light-emitting element EL.

[0266] The anode electrode AE adjacent to the planar hole PLN_H may extend into the planar hole PLN_H to cover the planar hole PLN_H and may contact at least one data wiring DL or at least one power wiring VSSL.

[0267] Reference Figure 10 Referring to Figure 10 , in the (1 - 2) region ① of the link region LiA, as the first wiring SL1 of the data voltage supply horizontal wiring H_LiA(DL), it can extend in the row direction to intersect with the power wiring VDD, the dummy LiA wiring Dm, and the data wiring DL that extend in the column direction. In this regard, the first wiring SL1 can be electrically connected to one data wiring DL via the planar hole PLN_H(A). In addition, the second wiring SL2 can extend in the row direction to intersect with a plurality of data wirings DL, a plurality of power wirings VDD, and a plurality of dummy LiA wirings Dm that extend in the column direction. In this regard, the second wiring SL2 can be electrically connected to each dummy LiA wiring Dm only via the planar hole PLN_H(A).

[0268] In addition, as the first wiring SL1 of the data voltage supply horizontal wiring H_LiA(DL), it can extend in the row direction to intersect with the power wiring VDD, the dummy LiA wiring Dm, and a plurality of data wirings DL that extend in the column direction. In this regard, the first wiring SL1 can be electrically connected to the data wiring DL provided at the end via the planar hole PLN_H(B). In addition, the second wiring SL2 can extend in the row direction to intersect with a plurality of data wirings DL, a plurality of power wirings VDD, and a plurality of dummy LiA wirings Dm that extend in the column direction. In this regard, the second wiring SL2 can be electrically connected to each dummy LiA wiring Dm only via the planar hole PLN_H(B).

[0269] In addition, as the first wiring SL1 of the data voltage supply horizontal wiring H_LiA(DL), it can extend in the row direction to intersect with a plurality of power wirings VDD, a plurality of dummy LiA wirings Dm, and a plurality of data wirings DL that extend in the column direction. In this regard, the first wiring SL1 can be electrically connected to the data wiring DL provided at the end via the planar hole PLN_H(C). In addition, the second wiring SL2 can extend in the row direction to intersect with a plurality of data wirings DL, a plurality of power wirings VDD, and a plurality of dummy LiA wirings Dm that extend in the column direction. In this regard, the second wiring SL2 can be electrically connected to each dummy LiA wiring Dm only via the planar hole PLN_H(C).

[0270] In addition, as the first wiring SL1 of the data voltage supply level wiring H_LiA(DL), it can extend in the row direction to intersect with a plurality of power wirings VDD, a plurality of dummy LiA wirings Dm, and a plurality of data wirings DL that extend in the column direction. In this regard, the first wiring SL1 can be electrically connected to the data wiring DL provided at the end via the planar hole PLN_H(D). In addition, the second wiring SL2 can extend in the row direction to intersect with a plurality of data wirings DL, a plurality of power wirings VDD, and a plurality of dummy LiA wirings Dm that extend in the column direction. In this regard, the second wiring SL2 can be electrically connected to each dummy LiA wiring Dm only via the planar hole PLN_H(D).

[0271] Figure 11 is a diagram showing the line layout in the first region to the third region of the link area according to an embodiment of the present disclosure. Figure 12 is a diagram showing the line layout in the first region of the link area according to an embodiment of the present disclosure. Figure 13 is a diagram showing the line layout in the second region and the third region of the link area according to an embodiment of the present disclosure.

[0272] Referring to Figure 11 , in the first region ① according to an embodiment of the present disclosure, a plurality of data voltage supply link lines Link(DL) and data wirings DL can extend in the column direction, and the first wiring SL1 as the horizontal line H_LiA(DL) can extend in the row direction to intersect with the plurality of data voltage supply link lines Link(DL) and data wirings DL. A plurality of power lines VDD can extend in the column direction. In this regard, the plurality of power lines VDD, and the link lines Link(DL) and data wirings DL can be implemented as the second wiring SL2. Therefore, the first wiring SL1 that extends in the row direction to intersect with the plurality of power lines VDD, link lines Link(DL), and data wirings DL can be electrically connected to the second wiring SL2 of the data wiring DL via the planar hole PLN_H.

[0273] Referring to Figure 12 , in the first region ① having the above line layout, a buffer layer 111 can be provided on the substrate 100, a first insulating layer 110 can be provided on the buffer layer 111, and a first gate insulating layer 120 can be provided on the first insulating layer 110.

[0274] In addition, a second insulating layer 130 and a third insulating layer 140 may be provided on the first gate insulating layer 120. A second gate insulating layer 150 may be provided on the second insulating layer 130 and the third insulating layer 140. A fourth insulating layer 160 may be provided on the second gate insulating layer 150. The second insulating layer 130 may be an interlayer insulating layer ILD, the third insulating layer 140 may be a buffer layer O-BUF, and the fourth insulating layer 160 may be a second interlayer insulating layer O-ILD.

[0275] In addition, a first wiring SL1 may be provided on the fourth insulating layer 160, a first planarization layer 170 may be provided on the first wiring SL1, and a plurality of power supply second wirings SL2 (VDD), link lines Link, and data wirings DL may be provided on the first planarization layer 170.

[0276] A second planarization layer 180 may be provided on the plurality of power supply second wirings SL2 VDD, link lines Link, and data wirings DL.

[0277] In the first region ①, a planar hole PLN_H may be formed in each of the plurality of link lines Link and may be defined in the first planarization layer 170, and a connection line CoL may be formed in the planar hole PLN_H.

[0278] Therefore, in the first region ①, each of the plurality of link lines Link provided on the first planarization layer 170 may be electrically connected to the first wiring SL1 via the connection line CoL filling the planar hole PLN_H.

[0279] As described above, at least one first wiring SL1 may be respectively connected to at least one data wiring DL or at least one power wiring VSSL via the connection line CoL filling the planar hole PLN_H in the first region ①, the (1-1) region ①', and the (1-2) region ①".

[0280] However, referring again to Figure 11 , in the second region ② and the third region ③, the first wiring SL1 extending in the row direction to intersect the plurality of power lines VDD, link lines Link (DL), and data wirings DL extending in the column direction is not connected to the data wiring DL and the second wiring SL2 via the planar hole PLN_H.

[0281] Referring to Figure 13 , in the second region ② and the third region ③ according to an embodiment of the present disclosure, the first planarization layer 170 may be provided on the first wiring SL1, and no planar hole PLN_H is formed in the planarization layer 170.

[0282] Therefore, in the second region ② and the third region ③, any one of the plurality of power supply second wirings SL2 (VDD), link lines Link, and data wirings DL provided on the first planarization layer 170 may not be connected to the first wiring SL1.

[0283] A display device according to an embodiment of the present disclosure may achieve thinning of a border region at a lower corner of a display region by extending a data link across the display region of the display panel.

[0284] In addition, in a display device according to an embodiment of the present disclosure, an anode electrode may extend into a region where the data link intersects a normal region of the display region to cover and fill a planar hole, thereby reducing a density difference caused by the planar hole. Therefore, in addition to improving the yield, a display device according to an embodiment of the present disclosure may also achieve a narrow border.

[0285] In addition, in a display device according to an embodiment of the present disclosure, it is possible to prevent an appearance defect caused by a density difference due to a planar hole in a region where the data link intersects a normal region of the display region from being perceived, thereby improving the quality of the display device.

[0286] In addition, according to an embodiment of the present disclosure, as the quality of the display device is improved, its reliability can be ensured, thereby increasing the lifespan of the display panel and realizing a long-life display device.

[0287] The display device according to the present disclosure may be described as follows.

[0288] According to a first aspect of the present disclosure, there is provided a display device including: a display panel including a display region provided with at least one pixel and a non-display region provided around the display region; a data driver provided in the non-display region; at least one data wiring respectively connecting at least one pixel to the data driver; and at least one first wiring provided between at least two data wirings and in the non-display region and extending into the display region, wherein the at least one first wiring is bent in the display region to intersect the data wiring; wherein the display region includes a first region provided with at least one pixel and a link region other than the first region, wherein the link region includes: a (1-1) region located at a lower portion of one of two opposite sides of the display region; and a (1-2) region located at a lower portion of the other of the two opposite sides of the display region, wherein the at least one first wiring is respectively connected to the at least one data wiring or at least one power wiring via a planar hole in each of the first region, the (1-1) region, and the (1-2) region.

[0289] According to some embodiments of the first aspect, the link region further includes a second region and a third region disposed between the (1-1) region and the (1-2) region.

[0290] According to some embodiments of the first aspect, the second region and the third region are disposed adjacent to each other.

[0291] According to some embodiments of the first aspect, each of the second region and the third region has a triangular shape in the plan view of the device.

[0292] According to some embodiments of the first aspect, the second region has a triangular shape and the third region has an inverted triangular shape.

[0293] According to some embodiments of the first aspect, one of at least one pixel includes an anode electrode, a light-emitting layer, and a cathode electrode.

[0294] According to some embodiments of the first aspect, the anode electrode adjacent to the planar hole extends into the planar hole to cover the planar hole and contacts each of at least one data wiring or each of at least one power wiring.

[0295] According to some embodiments of the first aspect, a packaging layer is provided on the light-emitting element in the display region, wherein the packaging layer includes: a first packaging layer provided on the light-emitting element; a second packaging layer provided on the first packaging layer; and a third packaging layer provided on the second packaging layer.

[0296] According to some embodiments of the first aspect, a touch electrode is provided on the packaging layer in the display region, wherein the touch electrode includes a first touch electrode and a second touch electrode.

[0297] According to some embodiments of the first aspect, a touch buffer layer is provided on the packaging layer, wherein the first touch electrode is provided on the touch buffer layer, wherein a touch insulating layer is provided on the touch buffer layer and the first touch electrode, and wherein the second touch electrode is provided on the touch insulating layer.

[0298] According to a second aspect of the present disclosure, a display device is provided. The display device includes: a display panel including light-emitting elements, a display area, a non-display area, and a bending area; a gate driver configured to supply a gate signal to the display panel; an upper substrate disposed on the display panel and in the display area; a bending protective layer disposed on an outer surface of a bending portion of the display panel and in the bending area; a data driver disposed under the bending portion of the display panel and in the non-display area and configured to supply a data voltage to the display panel; a controller configured to control the gate driver and the data driver; at least one data wiring respectively connecting at least one pixel to the data driver; at least one power wiring for respectively supplying power to at least one pixel; and at least one first wiring disposed between at least two data wirings and in a layer different from a layer of the at least one data wiring, wherein the at least one first wiring is bent in the display area to intersect the data wiring, wherein the display area includes a first area provided with at least one pixel and a link area other than the first area, wherein the link area includes: a first (1-1) area located at a lower portion of one of two opposite sides of the display area; and a first (1-2) area located at a lower portion of the other of the two opposite sides of the display area, wherein the at least one first wiring is respectively connected to the at least one data wiring or the at least one power wiring via planar holes in each of the first area, the first (1-1) area, and the first (1-2) area.

[0299] According to some embodiments of the second aspect, an optical film is disposed on the display panel, wherein the upper substrate is disposed on the optical film through an adhesive, wherein a first back plate is disposed under the display panel, wherein a fixing member is disposed under the first back plate, wherein a second back plate is disposed under the fixing member through an adhesive member, wherein a bending portion of the display panel is disposed under the second back plate, and wherein a bending protective layer is disposed under the bending portion of the display panel.

[0300] According to some embodiments of the second aspect, the at least one first wiring is respectively connected to the at least one data wiring or the at least one power wiring via connection lines filling planar holes in each of the first area, the first (1-1) area, and the first (1-2) area.

[0301] Although the embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not necessarily limited to these embodiments and can be modified in various ways within the scope of the technical spirit of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are intended to describe rather than limit the technical idea of the present disclosure, and the scope of the technical idea of the present disclosure is not limited by these embodiments. Therefore, it should be understood that the above-described embodiments are not restrictive in all respects but illustrative.

Claims

1. A display device, comprising: A display panel, the display panel comprising a display area provided with at least one pixel and a non-display area provided around the display area; a data driver, the data driver being disposed in the non-display area; at least one data wiring, the at least one data wiring connecting the at least one pixel to the data driver, respectively; as well as at least one first wiring, the at least one first wiring being disposed between at least two data wirings and in the non-display region and extending into the display region, wherein the at least one first wiring is bent in the display region to intersect with the data wiring; The display area includes a first area where the at least one pixel is disposed and a link area other than the first area. Wherein, the link area includes: a (1-1)th region, the (1-1)th region being located at a lower portion of one of two opposite sides of the display region; and a (1-2)th region, the (1-2)th region being located at a lower portion of the other of the two opposite sides of the display region, The at least one first wiring is respectively connected to the at least one data wiring or the at least one power wiring via a planar hole in each of the first region, the (1-1)th region, and the (1-2)th region.

2. The display device according to claim 1, wherein: The link area further includes a second area and a third area provided between the (1-1)th area and the (1-2)th area.

3. The display device according to claim 2, wherein: The second region and the third region are disposed adjacent to each other.

4. The display device according to claim 2, wherein: Each of the second area and the third area has a triangular shape in a plan view of the display device.

5. The display device according to claim 4, wherein: The second region has a triangular shape, and the third region has an inverted triangular shape.

6. The display device according to claim 1, wherein: One of the at least one pixel includes a light emitting element including an anode electrode, a light emitting layer, and a cathode electrode.

7. The display device according to claim 6, wherein: The anode electrode adjacent to the planar hole extends into the planar hole to cover the planar hole and to contact each of the at least one data wiring or each of the at least one power wiring.

8. The display device according to claim 6, wherein: providing an encapsulation layer on the light emitting element in the display area, Wherein, the encapsulation layer comprises: A first encapsulation layer disposed on the light emitting element; a second encapsulation layer disposed on the first encapsulation layer; and A third encapsulation layer is disposed on the second encapsulation layer.

9. The display device according to claim 8, wherein: A touch electrode is provided on the encapsulation layer in the display area, Wherein, the touch electrodes include a first touch electrode and a second touch electrode.

10. The display device according to claim 9, wherein: A touch buffer layer is arranged on the encapsulation layer, Wherein, the first touch electrode is arranged on the touch buffer layer, Wherein, a touch insulating layer is provided on the touch buffer layer and the first touch electrode, Wherein, the second touch electrode is arranged on the touch insulation layer.

11. A display device, comprising: A display panel, the display panel comprising a light emitting element, a display area, a non-display area and a bending area; a gate driver configured to supply a gate signal to the display panel; an upper substrate, the upper substrate being disposed on the display panel and in the display area; a bending protection layer, the bending protection layer being disposed on an outer surface of the bent portion of the display panel and in the bent region; a data driver disposed under the bent portion of the display panel and in the non-display area and configured to supply a data voltage to the display panel; a controller configured to control the gate driver and the data driver; at least one data wiring, the at least one data wiring connecting at least one pixel in the display area to the data driver, respectively; at least one power wiring for supplying power to the at least one pixel, respectively; as well as at least one first wiring disposed between at least two data wirings and in a layer different from that of the at least one data wiring, wherein the at least one first wiring is bent in the display area to intersect the data wirings, The display area includes a first area where the at least one pixel is disposed and a link area other than the first area. Wherein, the link area includes: a (1-1)th region, the (1-1)th region being located at a lower portion of one of two opposite sides of the display region; and a (1-2)th region, the (1-2)th region being located at a lower portion of the other of the two opposite sides of the display region, The at least one first wiring is respectively connected to the at least one data wiring or the at least one power wiring via a planar hole in each of the first region, the (1-1)th region, and the (1-2)th region.

12. The display device according to claim 11, wherein: An optical film is provided on the display panel, wherein the upper substrate is disposed on the optical film via an adhesive, Wherein, a first backplane is arranged below the display panel, Wherein, a fixing member is arranged below the first back plate, Wherein, a second back plate is arranged below the fixing member through an adhesive member, Wherein, a curved portion of the display panel is arranged below the second back plate, Wherein, a bending protection layer is arranged under the bending portion of the display panel.

13. The display device according to claim 11, wherein: The at least one first wiring is respectively connected to the at least one data wiring or the at least one power wiring via a connection line filling the planar hole in each of the first region, the (1-1)th region, and the (1-2)th region.

14. A display device, comprising: A display panel, the display panel comprising a display area provided with at least one pixel and a non-display area provided around the display area; a data driver, the data driver being disposed in the non-display area; at least one data wiring, the at least one data wiring connecting the at least one pixel to the data driver, respectively; as well as a plurality of first wirings, the plurality of first wirings being disposed between at least two data wirings and in the non-display region and extending into the display region, wherein the plurality of first wirings are bent in the display region to intersect with the data wirings; The display area includes a first area where the at least one pixel is disposed and a link area other than the first area. Wherein, the link area includes: a (1-1)th region, the (1-1)th region being located at a lower portion of one of two opposite sides of the display region; and a (1-2)th region, the (1-2)th region being located at a lower portion of the other of the two opposite sides of the display region, Among them, the multiple first wirings include wiring connected to the at least one data wiring or the at least one power wiring via a planar hole in the first area, wiring connected to a dummy wiring extending along the column direction via a planar hole in the (1-1)th area, and wiring connected to the at least one data wiring via a planar hole in the (1-2)th area.

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