Wafer alignment method based on bonding pad
Through the YOLOv8 model, the wafer pad profile is segmented and straight lines are fitted, which solves the problem of low wafer alignment efficiency and accuracy, and achieves high-efficiency, low-cost and high-precision wafer alignment.
Patent Information
- Application Number
- CN202510394314.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-31
- Publication Date
- 2025-07-04
AI Technical Summary
In the prior art, wafer correcting efficiency and accuracy are poor, relying on the operator's skill level, slow speed and low efficiency.
The YOLOv8 model is used to segment the wafer pad profile, and wafer alignment is achieved by fitting a straight line in the center of the target pad profile. Combined with the image algorithm, the residual profile is removed, the target pad profile is selected and the angle is calculated to transmit to the probe station.
It improves the efficiency and accuracy of wafer alignment, reduces hardware and time costs, and realizes automated and high-precision wafer alignment.
Smart Images
Figure CN120252566A_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present disclosure relate to the technical field of data processing, and in particular, to a wafer alignment method based on pads. Background Art
[0002] Currently, after a wafer is placed on a semi-automatic probe station, there is an included angle θ between the wafer and its X-Y movement direction. To ensure that the probe can pierce the wafer pads during testing, it is necessary to eliminate the θ angle, and this process is called wafer alignment. The semi-automatic probe station generally uses a template matching algorithm to complete wafer alignment by positioning two feature markers. To avoid the feature markers exceeding the camera's field of view during wafer alignment, wafer alignment is usually divided into two steps: rough alignment and fine alignment. The rough alignment of the wafer is completed by referring to the template. Therefore, the template angle has an important impact on the rough alignment accuracy. However, before making the template, the wafer needs to be aligned by manually selecting points. Since manual point selection may introduce position errors, this process needs to be repeated multiple times to achieve wafer alignment, and its accuracy highly depends on the operator's skill level, with slow speed and low efficiency.
[0003] Obviously, there is an urgent need for a wafer alignment method based on pads with high alignment efficiency and accuracy. Summary of the Invention
[0004] In view of this, embodiments of the present disclosure provide a wafer alignment method based on pads, which at least partially solves the problem of poor alignment efficiency and accuracy in the prior art.
[0005] Embodiments of the present disclosure provide a wafer alignment method based on pads, including:
[0006] Step 1, obtaining a binary image of the wafer pad contour;
[0007] Step 2, removing the incomplete pad contours in the binary image of the wafer pad contour and retaining the complete contours;
[0008] Step 3, selecting a target pad contour in the binary image of the complete contour;
[0009] Step 4, achieving wafer alignment by fitting a straight line through the center of the target pad contour.
[0010] According to a specific implementation manner of the embodiments of the present disclosure, step 1 specifically includes:
[0011] Collecting a wafer image, using the trained YOLOv8 model to perform pad contour segmentation on the wafer image, and converting the segmented wafer pad contour image into a binary image.
[0012] According to a specific implementation manner of the embodiments of the present disclosure, step 2 specifically includes:
[0013] Step 2.1, use an image algorithm to determine the contours near the image edge and delete such types of contours;
[0014] Step 2.2, use the area ratio of the bounding rectangle of the contour to the contour to delete the contours with an area ratio less than the preset ratio, and obtain the complete contours.
[0015] According to a specific implementation manner of an embodiment of the present disclosure, step 3 specifically includes:
[0016] Step 3.1, classify the binary images of all complete contours by size through a contour screening algorithm;
[0017] Step 3.2, select the contour classification with the largest number of contours, and find the row and column with the most contours through a contour selection algorithm;
[0018] Step 3.3, compare the number of contours in the row and column with the most contours, and retain the complete contours in the row or column with the larger number of contours as the target pad contours.
[0019] According to a specific implementation manner of an embodiment of the present disclosure, step 4 specifically includes:
[0020] Step 4.1, fit a straight line through the center of the target pad contour, and obtain the wafer angle through the slope of the straight line;
[0021] Step 4.2, transmit the wafer angle to the probe station for wafer alignment.
[0022] The wafer alignment solution based on pads in the embodiment of the present disclosure includes: step 1, obtain the binary image of the wafer pad contour; step 2, remove the incomplete pad contours in the binary image of the wafer pad contour and retain the complete contours; step 3, select the target pad contour in the binary image of the complete contour; step 4, realize wafer alignment by fitting a straight line through the center of the target pad contour.
[0023] The beneficial effect of the embodiment of the present disclosure is that: through the solution of the present disclosure, a large number of wafer pad images are collected by a vision system for sample training of the deep learning algorithm YOLOv8. When wafer alignment is required, the YOLOv8 model is used to segment the wafer pads. Different from traditional image segmentation algorithms, this model does not need to consider the influence of the segmentation threshold on the segmentation effect. After successfully segmenting the pad contour using the YOLOv8 model, the center of the pad contour is used to fit a straight line, thereby calculating the angle of the wafer. Finally, this angle is transmitted to the motion mechanism of the probe station, and wafer alignment can be realized, improving the alignment efficiency and accuracy. Description of the Drawings
[0024] To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following will briefly introduce the drawings required for the embodiments. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.
[0025] Figure 1 It is a schematic flowchart of a wafer alignment method based on pads provided by an embodiment of the present disclosure;
[0026] Figure 2 It is a schematic structural diagram of a wafer alignment verification platform based on pads provided by an embodiment of the present disclosure;
[0027] Figure 3 It is a schematic flowchart of a wafer image segmentation provided by an embodiment of the present disclosure;
[0028] Figure 4 It is a schematic diagram of the same-size contours with the largest quantity provided by an embodiment of the present disclosure;
[0029] Figure 5 It is a schematic diagram of the row and column with the most contours provided by an embodiment of the present disclosure. Detailed implementation manners
[0030] The following will describe the embodiments of the present disclosure in detail with reference to the drawings.
[0031] The following illustrates the embodiments of the present disclosure through specific specific examples. Those skilled in the art can easily understand other advantages and effects of the present disclosure from the content disclosed in this specification. Obviously, the described embodiments are only some embodiments of the present disclosure, rather than all embodiments. The present disclosure can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present disclosure without creative efforts belong to the scope of protection of the present disclosure.
[0032] It should be noted that the following description relates to various aspects of embodiments within the scope of the appended claims. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is for illustrative purposes only. Based on this disclosure, those skilled in the art should understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of the aspects described herein can be used to implement a device and / or practice a method. Additionally, this device can be implemented and this method can be practiced using other structures and / or functionality in addition to one or more of the aspects described herein.
[0033] It should also be noted that the diagrams provided in the following embodiments only illustrate the basic concept of this disclosure schematically. The diagrams only show the components related to this disclosure and are not drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in its actual implementation can be arbitrarily changed, and the component layout type may also be more complex.
[0034] In addition, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that the aspects described can be practiced without these specific details.
[0035] An embodiment of this disclosure provides a wafer alignment method based on pads, and this method can be applied to the wafer alignment process in a production scenario.
[0036] See Figure 1 , which is a schematic flow diagram of a wafer alignment method based on pads provided by an embodiment of this disclosure. As Figure 1 shown, the method mainly includes the following steps:
[0037] Step 1, obtain a binary image of the wafer pad contour;
[0038] Further, step 1 specifically includes:
[0039] Collect a wafer image, use the trained YOLOv8 model to segment the pad contour of the wafer image, and convert the segmented wafer pad contour image into a binary image.
[0040] The verification platform corresponding to the wafer alignment method of the embodiment of this disclosure consists of an image acquisition system (1), a wafer (2), and a susceptor motion system (3), as Figure 2 shown. The image acquisition system (1) is used to collect images of the wafer (2), and the susceptor motion system (3) is used to adsorb and move the wafer (2).
[0041] In specific implementation, after collecting the wafer image using an image acquisition system, a binary image of the wafer pad contour can be obtained through an image algorithm. The specific process is as follows:
[0042] A. Train the YOLOv8 deep learning model through a large database of collected wafer pad images, and deploy the trained YOLOv8 model into the semi-automatic probe station operation software through the OpenCV image processing library;
[0043] B. Collect the wafer image, and use the trained YOLOv8 model to segment the pad contour of the wafer image. The segmented image becomes a binary contour image of the wafer.
[0044] Step 2: Remove the incomplete pad contours in the binary image of the wafer pad contour and retain the complete contours;
[0045] Based on the above embodiment, the specific steps of Step 2 include:
[0046] Step 2.1: Use an image algorithm to judge the contours close to the image edge and delete this type of contour;
[0047] Step 2.2: Use the ratio of the area of the bounding rectangle of the contour to the area of the contour to delete the contours with a ratio less than the preset ratio, and obtain the complete contours.
[0048] In specific implementation, remove the incomplete contours in the binary contour image of the wafer and only retain the complete contours. The specific process includes:
[0049] A. Read the pixel values of the first row, the last row, the first column, and the last column of the binary contour image through the at.() function of the OpenCV library. If the pixel value is not zero, save it as a seed point; use the region growing algorithm to obtain the pad contour where the seed point is located. This contour is the contour close to the image edge. Subtract this contour from the binary contour image to remove the contour close to the image edge;
[0050] B. Use the findContours function of the OpenCV library to find the contours, use the boundingRect function to obtain the area of the bounding rectangle of the contour, and use the contourArea function to obtain the pixel area of the contour. When the ratio of the pixel area to the area of the bounding rectangle is greater than 0.9, save this contour on a new blank binary image. Finally, only the complete contours are retained in the obtained binary contour image, as Figure 3 shown.
[0051] Step 3: Select the target pad contour in the binary image of the complete contour;
[0052] Furthermore, the specific steps of Step 3 include:
[0053] Step 3.1, classify the binary images of all complete contours by size through a contour screening algorithm;
[0054] Step 3.2, select the contour classification with the largest number of contours, and find the rows and columns with the most contours through a contour selection algorithm;
[0055] Step 3.3, compare the number of contours in the rows and columns with the most contours, and retain the complete contours in the row or column with the larger number of contours as the target pad contours.
[0056] During specific implementation, select contours in the same row or column from the complete contours for straight line fitting. The specific process is as follows:
[0057] A. For the binary image that only retains the complete contours, use the findContours function in the OpenCV library to find the contours, use the contourArea function to obtain the pixel area of the contours, sort the contours by pixel area size, and classify the contours through the contour area change gradient curve. The gradient curve is obtained by calculating the sorted contours. The calculation formula is y = xi - xi-1 (y is the area gradient, xi is the i-th contour after sorting, and xi-1 is the (i - 1)-th contour after sorting). The contours with the largest number selected are as Figure 4 shown;
[0058] B. Use the For loop function to scan the contour map with the largest number of contours selected ( Figure 3 ) row by row and column by column. During the scanning process, record the number of contour pixel points (the contours after segmentation are white and the background is black). The rows and columns with the most contour pixel points are the areas with the most wafer pad contours;
[0059] C. Compare the number of contours in the rows and columns with the most contours. The ones with the larger number of contours will be retained. For example, if there are 3 in the row direction and 5 in the column direction, only retain the contours on the column with the most. Figure 3 The column with the most contours is excluded because the number of contours is small, as Figure 5 shown.
[0060] Step 4, achieve wafer alignment by fitting a straight line through the center of the target pad contours.
[0061] Based on the above embodiments, step 4 specifically includes:
[0062] Step 4.1, fit a straight line through the center of the target pad contours, and obtain the wafer angle through the slope of the straight line;
[0063] Step 4.2, transmit the wafer angle to the probe station for wafer alignment.
[0064] In specific implementation, the process of wafer alignment by fitting a straight line through the center of the pad contour is as follows:
[0065] A. Use the findContours function of the OpenCV library to extract Figure 5 all the contours in, use the moments function to extract the center points of all the contours, and finally use the fitLine function to fit the contour centers into a straight line, and obtain the wafer angle α through the slope k of the straight line. The calculation formula is α = arctank;
[0066] B. Transmit the wafer angle α to the probe station PLC controller through the computer Modbus communication protocol, and then convert the wafer angle α into pulses through the PLC and transmit them to the rotary motor to make the wafer rotate by an angle α.
[0067] The wafer alignment method based on pads provided in this embodiment uses a vision system to collect a large number of wafer pad images for sample training of the deep learning algorithm YOLOv8. When wafer alignment is required, the YOLOv8 model is used to segment the wafer pads. Different from traditional image segmentation algorithms, this model does not need to consider the influence of segmentation thresholds on the segmentation effect. After successfully segmenting the pad contour using the YOLOv8 model, the center of the pad contour is used to fit a straight line, thereby calculating the angle of the wafer. Finally, this angle is transmitted to the motion mechanism of the probe station to achieve wafer alignment, improving the alignment efficiency and accuracy.
[0068] Calculate the wafer angle through the wafer pads to achieve wafer alignment. Among them, the wafer pads are realized by image segmentation using a deep learning segmentation algorithm. After combining traditional image processing algorithms to remove the incomplete contours in the segmented contours, then select the contours in the same row or the same column from the remaining complete contours for wafer angle calculation.
[0069] Specifically, image segmentation of the pads is realized through a deep learning algorithm. On this basis, the wafer angle is obtained through steps such as contour selection and straight line fitting, realizing high-precision wafer alignment. Secondly, a contour selection algorithm is proposed, realizing the functions of screening wafer pads of multiple size specifications and single-row contour selection, that is, only one row or one column of pads is retained for fitting, avoiding the influence of redundant pads on fitting to ensure the accuracy of the wafer angle.
[0070] Compared with the existing wafer alignment technologies, the advantages of the method of the present disclosure are as follows:
[0071] First, when aligning the wafer, there is no need to use a wafer pre-aligning device or a wafer rotating table. Just collect the wafer pad images on the probe station to achieve wafer alignment, with low hardware costs;
[0072] Second, when aligning the wafer, there is no need to continuously rotate the wafer to find the wafer edge. After automatically locating the wafer pad through the deep learning method, the angle of the wafer can be directly calculated, with low time cost;
[0073] Third, when aligning the wafer, there is no need to set the threshold for threshold segmentation. The pad contour segmentation can be directly achieved by training the segmentation model in advance through big data, with a high degree of intelligence.
[0074] It should be understood that each part of the present disclosure can be implemented by hardware, software, firmware, or a combination thereof.
[0075] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present disclosure should be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.
Claims
1. A wafer alignment method based on pads, characterized in that Including: Step 1: Obtain the binary image of the wafer pad contour. Step 2: Remove the incomplete pad contours in the binary image of the wafer pad contour and retain the complete contours. Step 3: Select the target pad contour in the binary image of the complete contour. Step 4: Align the wafer by fitting a straight line through the center of the target pad contour.
2. The method according to claim 1, characterized in that, The specific content of Step 1 includes: Collect the wafer image, use the trained YOLOv8 model to segment the pad contour of the wafer image, and convert the segmented wafer pad contour image into a binary image.
3. The method according to claim 2, wherein The specific content of Step 2 includes: Step 2.1: Use an image algorithm to judge the contours near the image edge and delete this type of contour. Step 2.2: Use the ratio of the area of the bounding rectangle of the contour to the area of the contour to delete the contours with a ratio less than the preset ratio, and obtain the complete contours.
4. The method according to claim 3, wherein The specific content of Step 3 includes: Step 3.1: Classify the binary images of all complete contours by size through a contour screening algorithm. Step 3.2: Select the contour classification with the largest number of contours, and find the row and column with the most contours through a contour selection algorithm. Step 3.3: Compare the number of contours in the row and column with the most contours, and retain the complete contours in the row or column with the larger number of contours as the target pad contour.
5. The method according to claim 4, wherein The specific content of Step 4 includes: Step 4.1: Fit a straight line through the center of the target pad contour, and obtain the wafer angle through the slope of the straight line. Step 4.2: Transmit the wafer angle to the probe station for wafer alignment.