Server memory resource allocation method, device, equipment, medium and program product

Abstract

The present application provides a method for allocating memory resources for a server, which can be applied to the fields of server and computer technology. The method comprises: in response to detecting that the server has entered the power-on self-test phase, obtaining link information of the PCI link interconnecting the peripheral components in the server, wherein the link information of the PCI link includes the port information of the PCI port and the device information of the PCI device; determining the memory resource reservation scheme of the PCI link based on the port information of the PCI port and the device information of the PCI device; in response to detecting that the server has entered the system startup phase, if it is determined that the server's operating system needs to reallocate memory resources, reallocating memory resources for the PCI link according to the memory resource reservation scheme of the PCI link. The present application also provides a memory resource allocation device, device, storage medium and program product.

Description

Technical Field

[0001] The present application relates to the field of server and computer technology, and in particular to a method, apparatus, device, medium and program product for allocating memory resources of a server. Background Art

[0002] Servers can connect to various Peripheral Component Interconnect (PCI) devices through PCI ports. PCI devices include data processing units (DPUs), graphics processing units (GPUs), and graphics cards. To ensure the proper functioning of PCI devices, memory resources must be reserved for them during server startup. However, this memory resource reservation method is often illogical. Summary of the Invention

[0003] In view of the above problems, the present application provides a method, apparatus, device, medium and program product for allocating memory resources of a server.

[0004] According to a first aspect of the present application, a method for allocating memory resources of a server is provided, comprising: in response to detecting that the server has entered a power-on self-test phase, obtaining link information of a peripheral component interconnect (PCI) link in the server, wherein the link information of the PCI link includes port information of the PCI port and device information of the PCI device; determining a memory resource reservation scheme for the PCI link based on the port information of the PCI port and the device information of the PCI device; in response to detecting that the server has entered a system startup phase, and in the event that it is determined that the operating system of the server needs to reallocate memory resources, reallocating memory resources for the PCI link according to the memory resource reservation scheme of the PCI link.

[0005] The second aspect of the present application provides a memory resource allocation device for a server, comprising: an acquisition module for acquiring link information of a PCI link in the server in response to detecting that the server has entered a power-on self-test phase, wherein the link information of the PCI link includes port information of the PCI port and device information of the PCI device; a determination module for determining a memory resource reservation scheme for the PCI link based on the port information of the PCI port and the device information of the PCI device; and a first allocation module for reallocating memory resources for the PCI link in response to detecting that the server has entered a system startup phase and, when it is determined that the operating system of the server needs to reallocate memory resources, reallocating memory resources for the PCI link according to the memory resource reservation scheme of the PCI link.

[0006] The third aspect of the present application provides an electronic device, comprising: one or more processors; a memory for storing one or more computer programs, wherein the one or more processors execute the one or more computer programs to implement the steps of the above method.

[0007] The fourth aspect of the present application further provides a computer-readable storage medium having a computer program or instructions stored thereon, which implements the steps of the above method when the computer program or instructions are executed by a processor.

[0008] The fifth aspect of the present application further provides a computer program product, comprising a computer program or instructions, which implement the steps of the above method when executed by a processor.

[0009] According to an embodiment of the present application, during the server's power-on self-test phase, the memory resource reservation plan for the PCI link can be determined based on the port information of the PCI port and the device information of the PCI device. Therefore, when the server enters the system startup phase, if memory resource reallocation is required, memory resource reallocation can be performed according to the memory resource reservation plan, making memory resource allocation more rational and avoiding server operation abnormalities caused by the PCI device or PCI port that requires memory resource allocation not being allocated memory resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above contents and other objects, features and advantages of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings.

[0011] Figure 1 A schematic diagram of the physical connection of a mainboard of a server according to an embodiment of the present application is shown.

[0012] Figure 2 A schematic diagram of the internal structure of a DPU device according to an embodiment of the present application is shown.

[0013] Figure 3 A schematic diagram of the link structure of a switching module according to an embodiment of the present application is shown.

[0014] Figure 4 A schematic diagram of the link structure of a multi-layer switching module according to an embodiment of the present application is shown.

[0015] Figure 5 A flow chart of a method for allocating memory resources of a server according to an embodiment of the present application is shown.

[0016] Figure 6 A flowchart of a method for allocating memory resources of a server according to an embodiment of the present application is shown when the PCI link is of the first type.

[0017] Figure 7 A flowchart of a method for allocating memory resources of a server according to an embodiment of the present application is shown when the PCI link is of the second type.

[0018] Figure 8 A flow chart of a method for allocating memory resources of a server during the system startup phase according to an embodiment of the present application is shown.

[0019] Figure 9 A structural block diagram of a memory resource allocation device for a server according to an embodiment of the present application is shown.

[0020] Figure 10 A block diagram of an electronic device suitable for implementing a memory resource allocation method for a server according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0021] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present application. In the detailed description below, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present application. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessarily confusing the concepts of the present application.

[0022] The terms used herein are only for describing specific embodiments and are not intended to limit the present application. The terms "include", "comprising" and the like used herein indicate that the features, steps, operations and The existence of a feature, step, operation or component does not exclude the existence or addition of one or more other features, steps, operations or components.

[0023] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0024] When using expressions such as "at least one of A, B, and C," it should generally be interpreted in accordance with the meaning of the expression generally understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include but is not limited to having A alone, B alone, C alone, A and B, A and C, B and C, and or a system with A, B, C, etc.).

[0025] A Smart Network Interface Card (SNIC) is a flexible and programmable network interface card (NIC) used in conjunction with servers. SmartNICs have computing capabilities. To reduce CPU power consumption, they can offload data processing functions unsuitable for the CPU, such as networking, security, and storage, to the SmartNIC. This allows servers to run critical applications and operating systems more efficiently, optimizing overall business data processing efficiency.

[0026] The development of smart NICs can be divided into three phases. The first phase is the basic function NIC. The second phase is the hardware offload NIC. The third phase is the smart NIC based on the DPU device. The DPU device is a dedicated processor that provides data center infrastructure virtualization services such as networking, storage, security, and management around data processing. The DPU device can fully offload security-related functions based on the data plane and control plane. The DPU device can be combined with a computing architecture composed of CPUs and hardware acceleration engines such as application-specific integrated circuits (ASICs), network processors (NPs), and field programmable gate arrays (FPGAs) in various architectures to form an entity that provides virtualization functions.

[0027] DPUs are widely used in various data center server architectures. Regardless of the server architecture, memory resource reservation is required for each DPU. This is because DPUs contain numerous devices, such as network ports, virtual network cards, and solid-state drives (SSDs), both physical and virtual. These devices require memory resources, and some have priority. For example, 32-bit memory resources require high priority. However, some DPUs also include switch modules. Switch modules can connect to other PCI device modules. When these modules are connected to other PCI devices, the PCI devices connected to the switch modules may also require memory resources. At the same time, in addition to the DPU device in the server including the switching module, the server's motherboard or PCI device will also include a similar switching module. The same switching module and the PCI device below it also require memory resources, but 32-bit memory resources are limited and the maximum is 4GB. If it exceeds 4GB, some devices will become unusable, such as the interface of the display function (DPU device display interface or onboard VGA interface) cannot be displayed, or the required device cannot be used normally in the system due to insufficient memory resource allocation or the device is lost.

[0028] To achieve this, memory resources are typically reserved during server startup. However, switching modules can consist of multiple layers, and some switching modules within each layer may require memory resource reservation while others do not. Whether memory resource reservation is required depends on the port usage and device. In this case, since a server may include many switching modules and the switching module layer cannot be fixed, it is impossible to predict which switching module will require memory resource reservation.

[0029] In view of this, the present application provides a method for allocating memory resources of a server, comprising: in response to detecting that the server has entered a power-on self-test phase, obtaining link information of a PCI link interconnecting peripheral components in the server, wherein the link information of the PCI link includes port information of the PCI port and device information of the PCI device; determining a memory resource reservation scheme for the PCI link based on the port information of the PCI port and the device information of the PCI device; in response to detecting that the server has entered a system startup phase, and in the case of determining that the operating system of the server needs to reallocate memory resources, reallocating memory resources for the PCI link according to the memory resource reservation scheme of the PCI link.

[0030] In order to better understand the memory resource allocation method of the server proposed in this application, the physical connection diagram of the server, DPU device, switching unit, etc. involved in this application is introduced below.

[0031] Figure 1 A schematic diagram of the physical connection of a mainboard of a server according to an embodiment of the present application is shown.

[0032] like Figure 1 As shown, server 100 may include a first CPU 111 and a second CPU 112 connected to first CPU 111. First CPU 111 includes four PCI ports: RC0, RC1, RC2, and RC3. The RC0 port can be connected to a first switch module 121, the RC1 port can be connected to a disk array card (RAID card), the RC2 port can be connected to a hard drive (e.g., an NVME hard drive), and the RC3 port can be connected to a second switch module 122.

[0033] The first switching module 121 can connect to the first PCI device 131, the second PCI device 132, and the third PCI device 133. The second switching module 122 can connect to the fourth PCI device 134 and the third switching module 135. The third switching module 135 can connect to the fifth PCI device 141.

[0034] The second CPU 112 may include two PCI ports RC4 and RC5 . The RC4 port may be connected to the DPU device 123 , and the RC5 port may be connected to the fourth switching module 124 .

[0035] The fourth switch module 124 can be connected to the fifth switch module 136, the sixth PCI device 137, the seventh PCI device 138, and the eighth PCI device 139. The fifth switch module 136 can be connected to the ninth PCI device 142, the tenth PCI device 143, and the sixth switch module 144. The sixth switch module 144 can be connected to the seventh switch module 151. The seventh switch module 151 can be connected to the eleventh PCI device 161, the twelfth PCI device 162, and the thirteenth PCI device 163.

[0036] The first CPU 111 can also be connected to the baseboard management controller (BMC) 125. The server 100 can detect the first CPU 111 through the Basic Input Output System (BIOS). The second CPU 112 can also include a USB interface and a data interface. The USB interface is used to connect to a removable storage device with a USB interface. The data interface can be used to connect to a hard disk with a data interface. The data transmission channels between the switch modules and between the switch modules and the CPUs can be 8 or 16 channels.

[0037] Figure 2 A schematic diagram of the internal structure of a DPU device according to an embodiment of the present application is shown.

[0038] like Figure 2 As shown, the DPU device 200 may include a third CPU 211. The third CPU 211 is connected to the eighth switching module 221 and the first PC hard disk 222. The third CPU 211 also includes a USB interface. The eighth switching module 221 is connected to the first PCI network card 231, the second PCI network card 232, and the second PC hard disk 233. Hotplug Enable indicates that the hot plug function of the port is enabled, and Hotplug Disable indicates that the hot plug function of the port is disabled. PCI 16 Lane indicates that the port has 16 transmission channels.

[0039] Figure 3 A schematic diagram of the link structure of a switching module according to an embodiment of the present application is shown.

[0040] like Figure 3 As shown, the ninth switching module 311 may include four ports DP0, DP1, DP2 and DP3. 16 represents the PCI port of the ninth switch module 311. PCI Device represents that the PCI port is connected to a PCI device. PCI No. Device indicates that the PCI port is not connected to a PCI device, PCI hotplug Enable indicates that the hot plug function of the PCI port is enabled, and PCI hotplug Disable indicates that the hot plug function of the PCI port is disabled. PCI Lane 16 or 8 indicates that the switch module can have 16 or 8 transmission channels. The PCI device connected to the PCI Device field can be either a PCI device that supports 32-bit memory resource expansion or a PCI device that does not support 32-bit memory resource expansion.

[0041] Figure 4 A schematic diagram of the link structure of a multi-layer switching module according to an embodiment of the present application is shown.

[0042] like Figure 4 As shown, the multi-layer switching module includes a tenth switching module, an eleventh switching module and a twelfth switching module connected in sequence. Figure 4 For explanations of each part, please refer to Figure 3 The explanation will not be repeated here.

[0043] Figure 5 A flow chart of a method for allocating memory resources of a server according to an embodiment of the present application is shown.

[0044] like Figure 5 As shown, the memory resource allocation method of the server in this embodiment includes operations S510 to S530.

[0045] In operation S510 , in response to detecting that the server enters a power-on self-test phase, link information of a PCI link in the server is acquired, wherein the link information of the PCI link includes port information of a PCI port and device information of a PCI device.

[0046] In operation S520, a memory resource reservation scheme of the PCI link is determined according to the port information of the PCI port and the device information of the PCI device.

[0047] In operation S530 , in response to detecting that the server enters the system startup phase, if it is determined that the operating system of the server needs to reallocate memory resources, memory resources are reallocated for the PCI link according to the memory resource reservation scheme of the PCI link.

[0048] The POST phase is the phase where the server performs hardware self-test and initialization after it is powered on. During the POST phase, the server's Basic Input Output System (BIOS) can be loaded. The BIOS is responsible for memory resource allocation, hardware initialization, self-test, system settings management, and booting the operating system, preparing for subsequent server system startup. The server's hardware structure can be referenced. Figure 1 The structure shown in .

[0049] The server can perform PCI enumeration through the BIOS to obtain PCI link information. This PCI link information includes PCI port information and PCI device information. PCI port information includes the port type and transmission rate. PCI device information includes the PCI device type, subtype, device identification code (DID), vendor identification code (VID), and PCI port number.

[0050] Through the port information of the PCI port and the device of the PCI device, it can be confirmed whether the PCI port or the PCI device needs to allocate memory resources and the bit width of the allocated memory resources, thereby determining the memory resource reservation scheme of the PCI link.

[0051] The server's system startup phase can be the process of loading the server's operating system. During this phase, the server kernel can detect the server's hardware devices and determine their memory usage. It can also read the configuration files of various services and processes on the server to determine the memory resources required. It can also monitor memory resource usage in real time, thereby determining whether memory resource reallocation is necessary from multiple perspectives.

[0052] According to an embodiment of the present application, during the server's power-on self-test phase, the memory resource reservation plan for the PCI link can be determined based on the port information of the PCI port and the device information of the PCI device. Therefore, when the server enters the system startup phase, if memory resource reallocation is required, memory resource reallocation can be performed according to the memory resource reservation plan, making memory resource allocation more rational and avoiding server operation abnormalities caused by the PCI device or PCI port that requires memory resource allocation not being allocated memory resources.

[0053] According to an embodiment of the present application, determining a memory resource reservation scheme for a PCI link based on port information of a PCI port and device information of a PCI device may include: when the PCI link is determined to be of the first type and the PCI link includes a PCI device based on the link information of the PCI link, determining a memory resource reservation scheme for the PCI device in the PCI link based on the device information of the PCI device; when the PCI link is determined to be of the first type and the PCI link does not include a PCI device based on the link information of the PCI link, determining a memory resource reservation scheme for the PCI port in the PCI link based on the port information of the PCI port in the PCI link.

[0054] The first type of PCI link may indicate that the PCI link does not include a second target device, and the second target device may be a switch module, for example Figures 1 to 4 The switching module shown in . The PCI link is of the first type, that is, the PCI link is a PCI port connected to a PCI device or includes only one PCI port.

[0055] When it is determined that the PCI link is of the first type and the PCI link includes a PCI device based on the link information of the PCI link, it is possible to determine whether the PCI device requires memory resources and the size of the required memory resources based on the device information of the PCI device, thereby determining the memory resource reservation plan for the PCI device in the PCI link.

[0056] When the PCI link is determined to be of the first type based on the link information of the PCI link and the PCI link does not include any PCI device, it can be determined whether memory resources need to be reserved for the PCI port based on the port information of the PCI port in the PCI link, thereby determining the memory resource reservation scheme for the PCI port in the PCI link.

[0057] According to an embodiment of the present application, determining the memory resource reservation scheme for the PCI device in the PCI link based on the device information of the PCI device may include: determining whether the PCI device in the PCI link is the first target device based on the device information of the PCI device; when it is determined that the PCI device is the first target device, determining that the memory resource reservation scheme for the PCI device in the PCI link is to reserve memory resources of the target bit width; when it is determined that the PCI device is not the first target device and the PCI device supports memory resource expansion, determining that the memory resource reservation scheme for the PCI device in the PCI link is to reserve memory resources of the extended bit width; when it is determined that the PCI device is not the first target device and does not support memory resource expansion, determining that the memory resource reservation scheme for the PCI device in the PCI link is to reserve memory resources of the target bit width.

[0058] The first target device may be a DPU device. The structure of the first target device may refer to Figure 2 In the structure. When it is determined that the PCI device is the first target device, the memory resource reservation scheme for the PCI device in the PCI link may be to reserve memory resources of the target bit width. The memory resources of the target bit width may be, for example, 32-bit memory resources. When it is determined that the PCI device is not the first target device and the PCI device supports memory resource expansion, the memory resource reservation scheme for the PCI device in the PCI link may be to reserve memory resources of the extended bit width. The memory resources of the extended bit width may be, for example, 64-bit memory resources. When it is determined that the PCI device is not the first target device and does not support memory resource expansion, the memory resource reservation scheme for the PCI device in the PCI link may be to reserve memory resources of the target bit width.

[0059] Since the target width memory resources are limited, if the PCI device can support memory resource expansion, allocating extended width memory resources to the PCI device can save the target width memory resources. Reserving memory resources for the first target device can ensure that the server's Internet access function is not affected.

[0060] According to an embodiment of the present application, determining a memory resource reservation scheme for a PCI port in a PCI link based on port information of the PCI port in the PCI link may include: determining whether the PCI port in the PCI link is a target port based on the port information of the PCI port in the PCI link; when it is determined that the PCI port is a target port, determining that the memory resource reservation scheme for the PCI port in the PCI link is to reserve memory resources of a target bit width; when it is determined that the PCI port is not a target port, determining that the memory resource reservation scheme for the PCI port in the PCI link is to not reserve memory resources.

[0061] The target port may be a port for which memory resources need to be reserved, such as a port for connecting to a graphics card, hard drive, or network card. If a PCI port is determined to be a target port, memory resources may be reserved for the PCI port. If a PCI port is determined not to be a target port, memory resources are not reserved for the PCI port. By identifying whether a PCI port is a target port, the memory resources reserved for the PCI port can be determined.

[0062] Figure 6 A flowchart of a method for allocating memory resources of a server according to an embodiment of the present application is shown when the PCI link is of the first type.

[0063] like Figure 6 As shown, the method includes operations S601 to S611.

[0064] In operation S601 , in response to detecting that the server enters a power-on self-test phase, link information of a PCI link in the server is acquired, wherein the link information of the PCI link includes port information of a PCI port and device information of a PCI device.

[0065] In operation S602, it is determined based on link information of the PCI link that the PCI link is of the first type.

[0066] In operation S603 , it is determined whether the PCI link includes a PCI device. If it is determined that the PCI link includes a PCI device, operation S604 is performed. If it is determined that the PCI link does not include a PCI device, operation S609 is performed.

[0067] In operation S604, it is determined whether the PCI device in the PCI link is the first target device based on the device information of the PCI device. If it is determined that the PCI device is the first target device, operation S605 is performed. If it is determined that the PCI device is not the first target device, operation S606 is performed.

[0068] In operation S605 , it is determined that a memory resource reservation scheme for a PCI device in a PCI link is to reserve memory resources of a target bit width.

[0069] In operation S606 , it is determined whether the PCI device supports memory resource expansion. If the PCI device supports memory resource expansion, operation S607 is performed. If the PCI device does not support memory resource expansion, operation S608 is performed.

[0070] In operation S607 , it is determined that the memory resource reservation scheme for the PCI device in the PCI link is to reserve memory resources with extended bit width.

[0071] In operation S608 , it is determined that a memory resource reservation scheme for the PCI device in the PCI link is to reserve memory resources of a target bit width.

[0072] In operation S609, based on the port information of the PCI port in the PCI link, determine whether the PCI port in the PCI link is a target port. If it is determined that the PCI port in the PCI link is a target port, perform operation S610; if it is determined that the PCI port is not a target port, perform operation S611.

[0073] In operation S610, it is determined that a memory resource reservation scheme for a PCI port in a PCI link is to reserve memory resources of a target bit width.

[0074] In operation S611 , it is determined that a memory resource reservation scheme for a PCI port in a PCI link is not to reserve memory resources.

[0075] According to the embodiments of the present application, by identifying the PCI link, the memory resource reservation scheme in various situations of the PCI link under the first type is fully considered, so that memory resources can be reasonably reserved for PCI devices and PCI ports in need during the server's power-on self-test phase.

[0076] According to an embodiment of the present application, determining the memory resource reservation scheme of the PCI link based on the port information of the PCI port and the device information of the PCI device may also include: when the PCI link is determined to be of the second type based on the link information of the PCI link, determining the first-level information of the PCI link, wherein the first-level information represents that the PCI link includes N second target devices connected in sequence, and N is an integer greater than 0.

[0077] According to an embodiment of the present application, when the second target device at the nth layer is connected to the PCI device at the n+1th layer, a memory resource reservation scheme for the PCI device at the n+1th layer in the PCI link is determined based on the device information of the PCI device at the n+1th layer, where n=1, ..., N. When the second target device at the nth layer is not connected to the PCI device at the n+1th layer, a memory resource reservation scheme for the PCI port at the n+1th layer in the PCI link is determined based on the port information of the second target device at the nth layer.

[0078] The second type can indicate that the PCI link includes a second target device, that is, the PCI link is multi-layered. The second target device can be regarded as a PCI device. The second target device can refer to Figure 3 The second target device can be extended to connect multiple PCI devices. The structure of the multi-layer second target device can refer to Figure 4 The structure in .

[0079] In the case where the PCI link is of the second type, it is necessary to confirm the port information of the multi-layer second target device and the connected PCI device information in sequence.

[0080] For example, taking N=2 as an example, the first-layer second target device and the second-layer second target device are connected in sequence. If the first-layer second target device is connected to a second-layer PCI device, the memory resource reservation scheme for the PCI device is determined based on the device information of the second-layer PCI device. If the first-layer second target device is not connected to a second-layer PCI device, the memory resource reservation scheme for the second-layer PCI port is determined based on the port information of the first-layer second target device. If the second-layer second target device is connected to a third-layer PCI device, the memory resource reservation scheme for the PCI device is determined based on the device information of the third-layer PCI device. If the second-layer second target device is not connected to a third-layer PCI device, the memory resource reservation scheme for the third-layer PCI port is determined based on the port information of the second-layer second target device.

[0081] According to an embodiment of the present application, based on the device information of the n+1th layer PCI device, determining the memory resource reservation scheme for the n+1th layer PCI device in the PCI link may include: when it is determined that the n+1th layer PCI device is the first target device, determining that the memory resource reservation scheme for the n+1th layer PCI device in the PCI link is to reserve memory resources of the target bit width; when it is determined that the n+1th layer PCI device is not the first target device and the n+1th layer PCI device supports memory resource expansion, determining that the memory resource reservation scheme for the n+1th layer PCI device in the PCI link is to reserve memory resources of extended bit width; when it is determined that the n+1th layer PCI device is not the first target device and the n+1th layer PCI device does not support memory resource expansion, determining that the memory resource reservation scheme for the n+1th layer PCI device in the PCI link is to reserve memory resources of the target bit width.

[0082] When it is determined that the n-layer second target device is connected to the n+1-layer PCI device, it can be determined whether the n+1-layer PCI device is the first target device. When it is determined that the n+1-layer PCI device is the first target device, that is, the n+1-layer PCI device needs to reserve memory resources of the target bit width, then the memory resource reservation scheme for the n+1-layer PCI device in the PCI link is determined to be to reserve memory resources of the target bit width. When it is determined that the n+1-layer PCI device is not the first target device, it can be detected whether the n+1-layer PCI device supports memory resource expansion. When the n+1-layer PCI device supports memory resource expansion, the memory resource reservation scheme for the n+1-layer PCI device in the PCI link is determined to be to reserve memory resources of the extended bit width; when it is determined that the n+1-layer PCI device does not support memory resource expansion, the memory resource reservation scheme for the n+1-layer PCI device in the PCI link is determined to be to reserve memory resources of the target bit width.

[0083] According to the embodiments of the present application, by sequentially confirming the PCI devices connected to the N second target devices, a corresponding memory resource reservation scheme can be determined for the PCI devices in the server that require reserved memory resources, providing a basis for memory resource allocation in the server. This can also reduce the need to reserve memory resources for unimportant PCI devices.

[0084] According to an embodiment of the present application, determining the memory resource reservation scheme for the n+1th layer PCI port in the PCI link based on the port information of the nth layer second target device may include: when it is determined that the n+1th layer PCI port of the nth layer second target device is the target port, determining that the memory resource reservation scheme for the downstream port of the nth layer second target device in the PCI link is to reserve memory resources of the target bit width; when it is determined that the n+1th layer PCI port of the nth layer second target device is not the target port, determining that the memory resource reservation scheme for the downstream port of the nth layer second target device in the PCI link is to not reserve memory resources.

[0085] When it is determined that the n-layer second target device is not connected to the n+1-layer PCI device, it can be determined whether the n+1-layer PCI port of the n-layer second target device is a target port. The n+1-layer PCI port can be a downstream port of the n-layer second target device. When it is determined that the n+1-layer PCI port is a target port, that is, the n+1-layer PCI port needs to reserve memory resources, it can be determined that the memory resource reservation scheme for the downstream port of the n-layer second target device in the PCI link is to reserve memory resources of the target bit width. When it is determined that the n+1-layer PCI port of the n-layer second target device is not a target port, that is, the n+1-layer PCI port does not need to reserve memory resources, it can be determined that the memory resource reservation scheme for the downstream port of the n-layer second target device in the PCI link is not to reserve memory resources.

[0086] Figure 7 A flowchart of a method for allocating memory resources of a server according to an embodiment of the present application is shown when the PCI link is of the second type.

[0087] like Figure 7 As shown, the method includes operations S701 to S712.

[0088] In operation S701 , in response to detecting that the server enters a power-on self-test phase, link information of a PCI link in the server is acquired, wherein the link information of the PCI link includes port information of a PCI port and device information of a PCI device.

[0089] In operation S702 , it is determined that the PCI link is of the second type according to link information of the PCI link, wherein the first-level information indicates that the PCI link includes N second target devices connected in sequence, where n=N.

[0090] In operation S703, determine whether the second target device of the nth layer in the PCI link is connected to the PCI device of the n+1th layer. If it is determined that the second target device of the nth layer in the PCI link is connected to the PCI device of the n+1th layer, perform operation S704. If it is determined that the second target device of the nth layer in the PCI link is not connected to the PCI device of the n+1th layer, perform operation S709.

[0091] In operation S704, it is determined whether the n+1th layer PCI device is the first target device. If it is determined that the n+1th layer PCI device is the first target device, operation S705 is performed. If it is determined that the n+1th layer PCI device is not the first target device, operation S706 is performed.

[0092] In operation S705 , it is determined that a memory resource reservation scheme for the n+1th layer PCI device in the PCI link is to reserve memory resources of a target bit width.

[0093] In operation S706, determine whether the n+1th layer PCI device supports memory resource expansion. If it is determined that the n+1th layer PCI device supports memory resource expansion, perform operation S707. If it is determined that the n+1th layer PCI device does not support memory resource expansion, perform operation S708.

[0094] In operation S707 , it is determined that the memory resource reservation scheme for the n+1th layer PCI device in the PCI link is to reserve memory resources with extended bit width.

[0095] In operation S708 , it is determined that the memory resource reservation scheme for the n+1th layer PCI device in the PCI link is to reserve memory resources of the target bit width.

[0096] In operation S709, determine whether the n+1th layer PCI port is a target port based on the port information of the nth layer second target device. If it is determined that the n+1th layer PCI port is the target port, perform operation S710; if it is determined that the n+1th layer PCI port is not the target port, perform operation S711.

[0097] In operation S710, it is determined that a memory resource reservation scheme for a downstream port of a second target device at the nth layer in a PCI link is to reserve memory resources of a target bit width.

[0098] In operation S711 , it is determined that a memory resource reservation scheme for a downstream port of a second target device at the nth layer in a PCI link is not to reserve memory resources.

[0099] In operation S712 , it is determined whether n is equal to 1. If n is equal to 1, the process ends; if n is not equal to 1, n=n−1 is set and operation S703 is executed.

[0100] According to the embodiments of the present application, by sequentially confirming the PCI ports of the N second target devices, a corresponding memory resource reservation scheme can be determined for the PCI ports in the server that require memory resource reservation, further providing a basis for memory resource allocation in the server. This can also reduce the need to reserve memory resources for unused PCI ports.

[0101] According to an embodiment of the present application, the memory resource allocation method of the server may further include: when memory resources are reserved for the PCI port in the PCI link, the downstream ports of N second target devices, and the upstream ports corresponding to the respective downstream ports of the N second target devices, setting the hot-plug function of the PCI port in the PCI link with reserved memory resources, the downstream ports of the N second target devices, and the upstream ports corresponding to the downstream ports of the N second target devices with reserved memory resources to be turned on.

[0102] The hot-swap function can be enabled for PCI ports with reserved memory resources through the BIOS. The PCI ports with reserved memory resources may include PCI ports in a first-type PCI link and upstream and downstream ports of a second target device in a second-type PCI link. If a downstream port of the second target device requires reserved memory resources, the upstream port of the second target device also requires reserved memory resources, and the hot-swap function needs to be enabled for both the upstream and downstream ports of the second target device.

[0103] According to an embodiment of the present application, the hot plug function is enabled for the port that needs to reserve memory resources, which can avoid the PCI port or PCI device that needs to reserve memory resources from not being allocated memory resources when the memory resources are reallocated during the system startup phase.

[0104] According to an embodiment of the present application, in response to detecting that a server has entered the system startup phase, when it is determined that the server's operating system needs to reallocate memory resources, reallocating memory resources for the PCI link according to the memory resource reservation scheme of the PCI link may include: when it is determined that the PCI link is of the first type and the hot plug function of the PCI port in the PCI link is turned on, allocating memory resources to the PCI link according to the memory resource reservation scheme of the PCI link; when it is determined that the PCI link is of the first type and the hot plug function of the PCI port in the PCI link is turned off, reallocating memory resources to the PCI link; when it is determined that the PCI link is of the second type and the hot plug functions of the upstream ports and downstream ports of N second target devices are all turned on, allocating memory resources to the PCI link according to the memory resource reservation scheme of the PCI link; when it is determined that the PCI link is of the second type and the hot plug functions of at least one of the upstream ports and downstream ports of the N second target devices are turned off, reallocating memory resources to the PCI link.

[0105] According to an embodiment of the present application, when it is determined that the operating system of the server does not need to reallocate memory resources, memory resources are allocated to the PCI device and PCI port according to the memory resource reservation scheme of the PCI link.

[0106] During the server's system startup phase, if it's determined that the server's operating system requires memory resource reallocation, you can add the PCI=realloc parameter (a parameter used to reallocate memory resources) to the Grub interface (the operating system's boot interface) to implement memory resource reallocation. If it's determined that the server's operating system does not require memory resource reallocation, you can remove the PCI=realloc parameter to allocate memory resources to PCI devices and PCI ports based on the PCI link's memory resource reservation scheme.

[0107] When it is determined that the operating system of the server needs to reallocate memory resources, the PCI links may be scanned in sequence to determine whether the hot plug function of the PCI ports in the PCI links is enabled.

[0108] When it is determined that the PCI link is of the first type, whether the hot plug function of the PCI port is turned on is detected. When the hot plug function of the PCI port in the PCI link is turned on, memory resources are allocated to the PCI link according to the memory resource reservation plan of the PCI link; when the hot plug function of the PCI port in the PCI link is turned off, memory resources are reallocated to the PCI link.

[0109] When the PCI link is of the second type, determine whether the hot plug functions of the upstream ports and downstream ports of the N second target devices in the PCI link are all turned on. When the hot plug functions of the upstream ports and downstream ports of the N second target devices in the PCI link are all turned on, allocate memory resources to the PCI link according to the memory resource reservation scheme of the PCI link; when the hot plug function of at least one of the upstream ports and downstream ports of the N second target devices in the PCI link is turned off, reallocate memory resources to the PCI link.

[0110] If the PCI link is of the second type, it can also be checked whether the hot-swap function of the upstream and downstream ports of each second target device is enabled. If the hot-swap function of any node in the entire PCI link is not enabled, memory resources are reallocated. If the hot-swap function of all nodes in the entire PCI link is enabled, memory resource allocation is performed using the memory resource solution used during the power-on self-test phase.

[0111] According to an embodiment of the present application, memory resources are reallocated according to a memory resource reservation scheme, so that PCI devices that need to allocate memory resources can allocate corresponding memory resources in a reasonable manner during the reallocation process.

[0112] According to an embodiment of the present application, reallocating memory resources for a PCI link may include: obtaining remaining memory resources when it is determined that the memory resources allocated to the PCI link according to the memory resource reservation scheme of the PCI link have been completed; and reallocating memory resources for the PCI link based on the remaining memory resources.

[0113] The PCI link that needs to reallocate memory resources can reallocate remaining memory resources after the memory resources of the PCI link that allocates memory according to the memory resource reservation scheme are allocated.

[0114] In the case where memory resources need to be reallocated, the remaining memory resources can be reallocated according to the scanning order of the PCI link. In the case of insufficient remaining memory resources, the memory resource allocation of the second target device and PCI device at the subsequent level can be abandoned. At the same time, by judging whether the existing PCI devices support memory resource expansion, the PCI devices that support memory resource expansion are allocated memory resources with extended bit width to save more memory resources with target bit width, which is convenient for more PCI devices that only support memory resources with target bit width to use, thereby meeting the demand for supporting more PCI devices under the operating system.

[0115] Taking the reallocation of memory resources of the second type as an example, after the PCI link scan level is completed, the operating system will reallocate resources for the scanned level. If there is no PCI device under the second target device of the first layer, no memory resources will be allocated to the second target device, or if the hot-swap function of the second target device of the first layer is not turned on, the reserved memory resources will be released; if there is a PCI device under the second target device of the first layer, memory resources will be allocated to the PCI device, and if the hot-swap function of the second target device of the first layer is turned on, the operating system will allocate memory resources to the PCI device; if there is a PCI device under the second target device of the first layer and there is also a lower-level second target device, memory resources need to be allocated to the PCI device and it is necessary to determine whether there is a PCI device in the lower-level second target device. If there is no PCI device in the lower-level second target device and the hot-swap function of the lower-level second target device is turned off, no memory resources need to be allocated to the lower-level second target device. If there is a PCI device in the lower-level second target device, memory resources are allocated to the lower-level second target device, or if the hot-swap function of the lower-level second target device is turned on, memory resources are allocated according to the memory resource reservation plan. Memory resource allocation is performed N+1 times in this way until the remaining memory resources are allocated. When the memory resource allocation of all PCI devices of the server is completed, there is no problem if the memory resources of the target bit width meet the needs of all current PCI devices. If the memory resources of the target bit width are insufficient, after the PCI device connected to the second target device of the current level allocates memory resources of the target bit width and there are no memory resources to allocate, memory resources will not be allocated to the remaining PCI devices of the second target device of the current level or the second target device and PCI device of the next level.

[0116] Figure 8 A flow chart of a method for allocating memory resources of a server during the system startup phase according to an embodiment of the present application is shown.

[0117] like Figure 8 As shown, the method includes operations S801 to S809.

[0118] In operation S801, determine whether the server's operating system requires memory resource reallocation. If it is determined that the server's operating system requires memory resource reallocation, execute operation S802. If it is determined that the server's operating system does not require memory resource reallocation, execute operation S809.

[0119] In operation S802 , it is determined whether the PCI link is of the first type. If it is determined that the PCI link is of the first type, operation S803 is performed. If it is determined that the PCI link is not of the first type, operation S805 is performed.

[0120] In operation S803 , it is determined whether the hot plug function of the PCI port in the PCI link is enabled. If the hot plug function of the PCI port is enabled, operation S804 is performed. If the hot plug function of the PCI port is disabled, operation S807 is performed.

[0121] In operation S804, memory resources are allocated to the PCI link according to the memory resource reservation scheme of the PCI link.

[0122] In operation S805, determine whether the hot plug functions of the upstream ports and downstream ports of the N second target devices in the PCI link are all turned on. If it is determined that the hot plug functions of the upstream ports and downstream ports of the N second target devices in the PCI link are all turned on, perform operation S806. If the hot plug function of at least one of the upstream ports and downstream ports of the N second target devices is turned off, perform operation S807.

[0123] In operation S806, memory resources are allocated to the PCI link according to the memory resource reservation scheme of the PCI link.

[0124] In operation S807 , when it is determined that the memory resources allocated to the PCI links in which the hot plug functions are all enabled according to the memory resource reservation scheme of the PCI links are completed, the remaining memory resources are acquired.

[0125] In operation S808, memory resources are reallocated to the PCI link according to the remaining memory resources.

[0126] In operation S809 , memory resources are allocated to the PCI device and the PCI port according to the memory resource reservation scheme of the PCI link.

[0127] Since the hot-swap function of the PCI link where the first target device and target port to which memory resources need to be allocated is located is turned on during the power-on self-test phase, when memory resources are reallocated, it is possible to avoid the first target device and target port being unusable due to memory resource reallocation, thereby ensuring that the first target device and target port can be used normally at any time, without having to worry about the problem of the first target device and target port being unusable due to memory resource problems.

[0128] Based on the above server memory resource allocation method, this application also provides a server memory resource allocation device. Figure 9 The device is described in detail.

[0129] Figure 9 A structural block diagram of a memory resource allocation device for a server according to an embodiment of the present application is shown.

[0130] like Figure 9 As shown, the memory resource allocation device 900 of the server in this embodiment includes an acquisition module 910 , a determination module 920 and a first allocation module 930 .

[0131] The acquisition module 910 is used to acquire link information of the PCI link interconnecting the peripheral components in the server in response to detecting that the server enters the power-on self-test phase, wherein the link information of the PCI link includes port information of the PCI port and device information of the PCI device.

[0132] The determination module 920 is configured to determine a memory resource reservation scheme for the PCI link according to the port information of the PCI port and the device information of the PCI device.

[0133] The first allocation module 930 is configured to, in response to detecting that the server enters the system startup phase and determining that the server's operating system requires memory resource reallocation, reallocate memory resources for the PCI link according to the memory resource reservation scheme of the PCI link.

[0134] The determination module 920 includes: a first determination submodule, which is used to determine the memory resource reservation scheme for the PCI device in the PCI link based on the device information of the PCI device when the PCI link is determined to be of the first type and the PCI link includes a PCI device according to the link information of the PCI link; and a second determination submodule, which is used to determine the memory resource reservation scheme for the PCI port in the PCI link based on the port information of the PCI port in the PCI link when the PCI link is determined to be of the first type and the PCI link does not include a PCI device according to the link information of the PCI link.

[0135] The first determination submodule includes: a first determination unit, used to determine whether the PCI device in the PCI link is the first target device based on the device information of the PCI device; a second determination unit, used to determine that the memory resource reservation scheme for the PCI device in the PCI link is to reserve memory resources of the target bit width when it is determined that the PCI device is the first target device; a third determination unit, used to determine that the memory resource reservation scheme for the PCI device in the PCI link is to reserve memory resources of the extended bit width when it is determined that the PCI device is not the first target device and the PCI device supports memory resource expansion; a fourth determination unit, used to determine that the memory resource reservation scheme for the PCI device in the PCI link is to reserve memory resources of the target bit width when it is determined that the PCI device is not the first target device and does not support memory resource expansion.

[0136] The second determination submodule includes: a fifth determination unit, used to determine whether the PCI port in the PCI link is a target port based on the port information of the PCI port in the PCI link; a sixth determination unit, used to determine that the memory resource reservation scheme for the PCI port in the PCI link is to reserve memory resources of the target bit width when it is determined that the PCI port is the target port; and a seventh determination unit, used to determine that the memory resource reservation scheme for the PCI port in the PCI link is to not reserve memory resources when it is determined that the PCI port is not the target port.

[0137] The determination module 920 also includes: a third determination submodule, which is used to determine the first-level information of the PCI link when the PCI link is determined to be of the second type based on the link information of the PCI link, wherein the first-level information represents that the PCI link includes N second target devices connected in sequence, and N is an integer greater than 0; a fourth determination submodule, which is used to determine the memory resource reservation scheme for the n+1-layer PCI device in the PCI link based on the device information of the n+1-layer PCI device when the n-layer second target device is connected to the n+1-layer PCI device, where n=1,…,N; and a fifth determination submodule, which is used to determine the memory resource reservation scheme for the n+1-layer PCI port in the PCI link based on the port information of the n-layer second target device when the n-layer second target device is not connected to the n+1-layer PCI device.

[0138] The fourth determination submodule includes: an eighth determination unit, which is used to determine that the memory resource reservation scheme for the n+1th layer PCI device in the PCI link is to reserve memory resources of the target bit width when it is determined that the n+1th layer PCI device is the first target device; a ninth determination unit, which is used to determine that the memory resource reservation scheme for the n+1th layer PCI device in the PCI link is to reserve memory resources of extended bit width when it is determined that the n+1th layer PCI device is not the first target device and the n+1th layer PCI device supports memory resource expansion; a tenth determination unit, which is used to determine that the memory resource reservation scheme for the n+1th layer PCI device in the PCI link is to reserve memory resources of the target bit width when it is determined that the n+1th layer PCI device is not the first target device and the n+1th layer PCI device does not support memory resource expansion.

[0139] The fifth determination submodule includes: an eleventh determination unit, which is used to determine that the memory resource reservation scheme for the downstream port of the second target device in the nth layer in the PCI link is to reserve memory resources of the target bit width when it is determined that the n+1th layer PCI port of the second target device in the nth layer is the target port; and a twelfth determination unit, which is used to determine that the memory resource reservation scheme for the downstream port of the second target device in the nth layer in the PCI link is to not reserve memory resources when it is determined that the n+1th layer PCI port of the second target device in the nth layer is not the target port.

[0140] The memory resource allocation device 900 of the server may further include: an enabling module for setting the hot-plug function of the PCI port in the PCI link with reserved memory resources, the downstream ports of the N second target devices, and the upstream ports corresponding to the downstream ports of the N second target devices with reserved memory resources to be enabled, when memory resources are reserved for the PCI port in the PCI link, the downstream ports of the N second target devices, and the upstream ports corresponding to the downstream ports of the N second target devices.

[0141] The first allocation module 930 includes: a first allocation sub-module, which is used to allocate memory resources to the PCI link according to the memory resource reservation scheme of the PCI link when it is determined that the PCI link is of the first type and the hot plug function of the PCI port in the PCI link is turned on; a second allocation sub-module, which is used to reallocate memory resources to the PCI link when it is determined that the PCI link is of the first type and the hot plug function of the PCI port in the PCI link is turned off; a third allocation sub-module, which is used to allocate memory resources to the PCI link according to the memory resource reservation scheme of the PCI link when it is determined that the PCI link is of the second type and the hot plug functions of the upstream ports and downstream ports of the N second target devices are all turned on; and a fourth allocation sub-module, which is used to reallocate memory resources to the PCI link when it is determined that the PCI link is of the second type and the hot plug function of at least one of the upstream ports and downstream ports of the N second target devices is turned off.

[0142] The second allocation submodule includes: a first allocation unit, which is used to obtain remaining memory resources when it is determined that the memory resources allocated to the PCI link according to the memory resource reservation scheme of the PCI link are completed; and a second allocation unit, which is used to reallocate memory resources to the PCI link according to the remaining memory resources.

[0143] The server memory resource allocation device 900 further includes: a second allocation module for allocating memory resources to PCI devices and PCI ports according to the memory resource reservation scheme of the PCI link when it is determined that the server operating system does not need to reallocate memory resources.

[0144] According to embodiments of the present application, any multiple modules among the acquisition module 910, determination module 920, and first allocation module 930 may be combined into a single module, or any one of these modules may be split into multiple modules. Alternatively, at least part of the functionality of one or more of these modules may be combined with at least part of the functionality of other modules and implemented in a single module. According to embodiments of the present application, at least one of the acquisition module 910, determination module 920, and first allocation module 930 may be at least partially implemented as a hardware circuit, such as a field programmable gate array (FPGA), a programmable logic array (PLA), a system on a chip, a system on a substrate, a system on a package, an application-specific integrated circuit (ASIC), or may be implemented in hardware or firmware through any other reasonable means of circuit integration or packaging, or may be implemented in any one of the three implementation methods of software, hardware, and firmware, or any appropriate combination of these. Alternatively, at least one of the acquisition module 910, determination module 920, and first allocation module 930 may be at least partially implemented as a computer program module that, when executed, performs the corresponding functionality.

[0145] Figure 10 A block diagram of an electronic device suitable for implementing a memory resource allocation method for a server according to an embodiment of the present application is shown.

[0146] like Figure 10 As shown, the electronic device 1000 according to an embodiment of the present application includes a processor 1001, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1002 or a program loaded from a storage unit 1008 into a random access memory (RAM) 1003. The processor 1001 may include, for example, a general-purpose microprocessor (e.g., a CPU), an instruction set processor and / or a related chipset and / or a special-purpose microprocessor (e.g., an application-specific integrated circuit (ASIC)), etc. The processor 1001 may also include onboard memory for caching purposes. The processor 1001 may include a single processing unit or multiple processing units for performing different actions of the method flow according to the embodiment of the present application.

[0147] Various programs and data required for the operation of the electronic device 1000 are stored in the RAM 1003. The processor 1001, the ROM 1002, and the RAM 1003 are connected to each other via a bus 1004. The processor 1001 performs various operations of the method flow according to the embodiment of the present application by executing the programs in the ROM 1002 and / or the RAM 1003. It should be noted that the programs may also be stored in one or more memories other than the ROM 1002 and the RAM 1003. The processor 1001 may also perform various operations of the method flow according to the embodiment of the present application by executing the programs stored in the one or more memories.

[0148] According to an embodiment of the present application, electronic device 1000 may further include an input / output (I / O) interface 1005, which is also connected to bus 1004. Electronic device 1000 may also include one or more of the following components connected to I / O interface 1005: an input section 1006 including a keyboard, mouse, etc.; an output section 1007 including devices such as a cathode ray tube (CRT), liquid crystal display (LCD), and speakers; a storage section 1008 including a hard disk; and a communication section 1009 including a network interface card such as a LAN card or modem. Communication section 1009 performs communication processing via a network such as the Internet. A drive 1010 is also connected to I / O interface 1005 as needed. Removable media 1011, such as a magnetic disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed in drive 1010 as needed, so that computer programs read from the removable media can be installed into storage section 1008 as needed.

[0149] This application also provides a computer-readable storage medium, which may be included in the device / apparatus / system described in the above embodiments, or may exist independently and not be incorporated into the device / apparatus / system. The computer-readable storage medium carries one or more programs, and when the one or more programs are executed, the method according to the embodiments of this application is implemented.

[0150] According to an embodiment of the present application, a computer-readable storage medium may be a non-volatile computer-readable storage medium, and may include, for example, but not limited to: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In the present application, a computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. For example, according to an embodiment of the present application, a computer-readable storage medium may include the ROM 1002 and / or RAM 1003 described above and / or one or more memories other than ROM 1002 and RAM 1003.

[0151] The embodiments of the present application also include a computer program product, which includes a computer program containing program code for executing the method shown in the flowchart. When the computer program product is run in a computer system, the program code is used to enable the computer system to implement the method provided in the embodiments of the present application.

[0152] The computer program executes the above functions defined in the system / device of the embodiment of the present application when the computer program is executed by the processor 1001. According to the embodiment of the present application, the system, device, module, unit, etc. described above can be implemented by a computer program module.

[0153] In one embodiment, the computer program may be stored on a tangible storage medium such as an optical storage device or a magnetic storage device. In another embodiment, the computer program may be transmitted and distributed in the form of a signal on a network medium, downloaded and installed via the communication portion 1009, and / or installed from the removable medium 1011. The program code contained in the computer program may be transmitted using any appropriate network medium, including but not limited to wireless, wired, or any suitable combination thereof.

[0154] In such an embodiment, the computer program can be downloaded and installed from a network via the communication section 1009, and / or installed from the removable medium 1011. When the computer program is executed by the processor 1001, the above-mentioned functions defined in the system of the embodiment of the present application are performed. According to the embodiment of the present application, the systems, devices, means, modules, units, etc. described above can be implemented by computer program modules.

[0155] Those skilled in the art will appreciate that the features described in the various embodiments of this application may be combined and / or coupled in various ways, even if such combinations or couplings are not explicitly described in this application. In particular, the features described in the various embodiments of this application may be combined and / or coupled in various ways without departing from the spirit and teachings of this application. All such combinations and / or couplings fall within the scope of this application.

[0156] The embodiments of the present application have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present application. Although each embodiment has been described separately above, this does not mean that the measures in each embodiment cannot be advantageously used in combination. Without departing from the scope of the present application, those skilled in the art may make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the present application.

Claims

1. A method for allocating memory resources of a server, characterized in that: The method comprises: In response to detecting that the server enters a power-on self-test phase, obtaining link information of a PCI link interconnecting peripheral components in the server, wherein the link information of the PCI link includes port information of a PCI port and device information of a PCI device; Determining a memory resource reservation scheme for the PCI link according to the port information of the PCI port and the device information of the PCI device; In response to detecting that the server enters a system startup phase, if it is determined that the operating system of the server needs to reallocate memory resources, reallocate memory resources for the PCI link according to the memory resource reservation scheme of the PCI link; Wherein, determining the memory resource reservation scheme of the PCI link according to the port information of the PCI port and the device information of the PCI device includes: When it is determined based on the link information of the PCI link and the device information of the PCI device that the PCI link is of the first type, the PCI link includes the PCI device, and the PCI device is a first target device, determining that a memory resource reservation scheme for the PCI device in the PCI link is to reserve memory resources of a target bit width; When it is determined that the PCI device is not the first target device and the PCI device supports memory resource expansion, determining that a memory resource reservation scheme for the PCI device in the PCI link is to reserve memory resources with extended bit width; When it is determined that the PCI device is not the first target device and does not support memory resource expansion, determining that a memory resource reservation scheme for the PCI device in the PCI link is to reserve memory resources of the target bit width; The determining of the memory resource reservation scheme of the PCI link according to the port information of the PCI port and the device information of the PCI device further includes: In a case where it is determined that the PCI link is of the second type according to the link information of the PCI link, determining first-level information of the PCI link, wherein the first-level information represents that the PCI link includes N second target devices connected sequentially, where N is an integer greater than 0; In a case where the second target device at the nth layer is connected to the PCI device at the n+1th layer, determining a memory resource reservation scheme for the PCI device at the n+1th layer in the PCI link according to the device information of the PCI device at the n+1th layer, where n=1, ..., N; When the nth layer second target device is not connected to the n+1th layer PCI device, a memory resource reservation scheme for the n+1th layer PCI port in the PCI link is determined according to the port information of the nth layer second target device.

2. The method according to claim 1, characterized in that The determining of the memory resource reservation scheme of the PCI link according to the port information of the PCI port and the device information of the PCI device includes: When it is determined according to the link information of the PCI link that the PCI link is of the first type and the PCI device is included in the PCI link, determining a memory resource reservation scheme for the PCI device in the PCI link according to the device information of the PCI device; When it is determined according to the link information of the PCI link that the PCI link is of the first type and the PCI device is not included in the PCI link, a memory resource reservation scheme for the PCI port in the PCI link is determined according to the port information of the PCI port in the PCI link.

3. The method according to claim 2, characterized in that The determining, based on the port information of the PCI port in the PCI link, a memory resource reservation scheme for the PCI port in the PCI link includes: determining, according to port information of a PCI port in the PCI link, whether the PCI port in the PCI link is a target port; In a case where it is determined that the PCI port is the target port, determining that a memory resource reservation scheme for the PCI port in the PCI link is to reserve memory resources of the target bit width; In the case where it is determined that the PCI port is not the target port, a memory resource reservation scheme for the PCI port in the PCI link is determined to be not reserving memory resources.

4. The method according to claim 3, characterized in that The determining, based on the device information of the n+1th layer PCI device, a memory resource reservation scheme for the n+1th layer PCI device in the PCI link includes: In a case where the n+1th layer PCI device is determined to be the first target device, determining that a memory resource reservation scheme for the n+1th layer PCI device in the PCI link is to reserve memory resources of the target bit width; When it is determined that the n+1th layer PCI device is not the first target device and the n+1th layer PCI device supports memory resource expansion, determining that a memory resource reservation scheme for the n+1th layer PCI device in the PCI link is to reserve memory resources of the extended bit width; When it is determined that the n+1th layer PCI device is not the first target device and the n+1th layer PCI device does not support memory resource expansion, the memory resource reservation scheme for the n+1th layer PCI device in the PCI link is determined to reserve memory resources of the target bit width.

5. The method according to claim 3, characterized in that Determining, according to the port information of the second target device at the nth layer, a memory resource reservation scheme for the PCI port at the n+1th layer in the PCI link, comprising: When it is determined that the PCI port of the nth layer second target device is the target port, determining that the memory resource reservation scheme for the downlink port of the nth layer second target device in the PCI link is to reserve memory resources of the target bit width; When it is determined that the n+1th layer PCI port of the nth layer second target device is not the target port, the memory resource reservation scheme for the downlink port of the nth layer second target device in the PCI link is determined to be not reserving memory resources.

6. The method according to claim 5, characterized in that Also includes: In a case where memory resources are reserved for the PCI port in the PCI link, the N downstream ports of the second target devices, and the upstream ports corresponding to the respective downstream ports of the N second target devices, the hot plug function of the PCI port in the PCI link with reserved memory resources, the N downstream ports of the second target devices, and the upstream ports corresponding to the downstream ports of the N second target devices with reserved memory resources is set to be turned on.

7. The method according to any one of claims 3 to 6, characterized in that In response to detecting that the server enters a system startup phase, in the case where it is determined that the operating system of the server needs to reallocate memory resources, reallocating memory resources for the PCI link according to the memory resource reservation scheme of the PCI link includes: When it is determined that the PCI link is of the first type and the hot plug function of the PCI port in the PCI link is enabled, allocating memory resources to the PCI link according to the memory resource reservation scheme of the PCI link; reallocating memory resources for the PCI link when it is determined that the PCI link is of the first type and the hot plug function of the PCI port in the PCI link is disabled; When it is determined that the PCI link is of the second type and hot plug functions of the uplink ports and the downlink ports of the N second target devices are all enabled, allocating memory resources to the PCI link according to the memory resource reservation scheme of the PCI link; When it is determined that the PCI link is of the second type and the hot plug function of at least one of the N upstream ports and downstream ports of the second target devices is disabled, memory resources are reallocated to the PCI link.

8. The method according to claim 7, characterized in that The reallocating memory resources for the PCI link includes: When it is determined that the memory resources allocated to the PCI link according to the memory resource reservation scheme of the PCI link are completed, obtaining remaining memory resources; Memory resources are reallocated to the PCI link according to the remaining memory resources.

9. The method according to claim 7, characterized in that Also includes: When it is determined that the operating system of the server does not need to reallocate memory resources, memory resources are allocated to the PCI device and the PCI port according to the memory resource reservation scheme of the PCI link.

10. A memory resource allocation device for a server, characterized in that: The device comprises: an acquisition module, configured to acquire link information of a PCI link interconnecting peripheral components in the server in response to detecting that the server enters a power-on self-test phase, wherein the link information of the PCI link includes port information of a PCI port and device information of a PCI device; a determination module, configured to determine a memory resource reservation scheme for the PCI link based on the port information of the PCI port and the device information of the PCI device; a first allocation module, configured to, in response to detecting that the server enters a system startup phase and, if determining that the operating system of the server needs to reallocate memory resources, reallocate memory resources for the PCI link according to the memory resource reservation scheme of the PCI link; The first determining submodule includes: a first determining unit for determining, when it is determined according to link information of the PCI link that the PCI link is of the first type and the PCI device is included in the PCI link, whether the PCI device in the PCI link is a first target device based on the device information of the PCI device; a second determining unit for determining, when it is determined that the PCI device is the first target device, that a memory resource reservation scheme for the PCI device in the PCI link is to reserve memory resources of a target bit width; a third determining unit for determining, when it is determined that the PCI device is not the first target device and the PCI device supports memory resource expansion, that a memory resource reservation scheme for the PCI device in the PCI link is to reserve memory resources of an extended bit width; a fourth determining unit for determining, when it is determined that the PCI device is not the first target device and does not support memory resource expansion, that a memory resource reservation scheme for the PCI device in the PCI link is to reserve memory resources of the target bit width; The determination module includes: a third determination submodule, used to determine the first-level information of the PCI link when the PCI link is determined to be of the second type according to the link information of the PCI link, wherein the first-level information represents that the PCI link includes N second target devices connected in sequence, and N is an integer greater than 0; a fourth determination submodule, used to determine the memory resource reservation scheme for the n+1-th layer PCI device in the PCI link according to the device information of the n+1-th layer PCI device when the n-th layer second target device is connected to the n+1-th layer PCI device, n=1,…,N; and a fifth determination submodule, used to determine the memory resource reservation scheme for the n+1-th layer PCI port in the PCI link according to the port information of the n-th layer second target device when the n-th layer second target device is not connected to the n+1-th layer PCI device.

11. An electronic device comprising: one or more processors; a memory for storing one or more computer programs, It is characterized in that the one or more processors execute the one or more computer programs to implement the steps of the method according to any one of claims 1 to 9.

12. A computer-readable storage medium having a computer program or instruction stored thereon, characterized in that: When the computer program or instruction is executed by a processor, the steps of the method according to any one of claims 1 to 9 are implemented.

13. A computer program product comprising a computer program or instructions, characterized in that When the computer program or instruction is executed by a processor, the steps of the method according to any one of claims 1 to 9 are implemented.

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