System self-protection safety management method in severe environment

Abstract

The invention relates to a system self-protection safety management method in a severe environment, and belongs to the field of computer software and hardware. Two GPIO hardware pins of a processor CPU are physically connected with a GPIO pin of an FPGA, a counter is configured in the FPGA and used for working timing, and meanwhile, the FPGA keeps continuously monitoring status bits of the two GPIO pins; when the computing device is in a low-temperature scene and is powered on and started, a counter in the FPGA starts to work and time, status bits of the two GPIO pins are monitored synchronously, and when it is monitored that the status of the GPIO pins does not conform to preset setting, power-on starting of the device again is completed. According to the method, the function mode and the initial status bit are configured for the hardware pin in the firmware, the automatic script is configured under the operating system to reconfigure the status bit of the hardware pin, meanwhile, the FPGA continuously monitors the state of the hardware pin and manages self-starting of the equipment, and the use reliability and stability of the equipment are greatly improved.

Description

Technical Field

[0001] The present invention belongs to the field of computer software and hardware, and particularly relates to a system self-protection security management method in a harsh environment. Background Art

[0002] In a harsh environment, especially in a low-temperature scenario, the main test is the working performance of the main processor of the device. When the ambient temperature is lower than the lower limit of the working temperature of the main processor of the device for a long time, the low temperature causes the conductivity of electronic components to decrease, and the device may experience phenomena such as slow startup, freezing, and crashing, making it unable to start normally, which seriously affects the use and maintenance of the device.

[0003] Currently, one of the important components of the accusation system is a computing device, which can provide end-data computing support services for the system. Its processor is based on the Feiteng D2000 platform, and the two GMAC interfaces respectively implement the physical layer protocol conversion from RGMII to Gigabit Serdes via PHY chips, which is an important channel for data interaction between devices in the accusation system. Therefore, the performance such as reliability and stability of the computing device needs to be focused on in a harsh environment.

[0004] The low-temperature lower limit of the commercial-grade chip of the processor D2000 is 0°C. When the ambient temperature approaches -40°C for a long time (-40°C ± 3°C), the computing device may experience the phenomenon of unable to start up when powered on, which has a certain impact on the reliability of the accusation system. Since the computing device does not work properly, the data of the accusation system cannot be processed collaboratively, and the effective interaction of data cannot be completed. Summary of the Invention

[0005] (1) Technical Problems to be Solved

[0006] The technical problem to be solved by the present invention is how to provide a system self-protection security management method in a harsh environment to solve the problem that the computing device cannot start normally in a harsh environment (especially in a low-temperature scenario).

[0007] (2) Technical Solutions

[0008] To solve the above technical problems, the present invention proposes a system self-protection security management method in a harsh environment. The device ecological environment in which this method works includes: a processor CPU, an FPGA, firmware, an operating system, and a power supply module;

[0009] Two GPIO hardware pins of the processor CPU are physically connected to the GPIO pins of the FPGA. A counter is configured in the FPGA for working timing. At the same time, the FPGA continuously monitors the status bits of these two GPIO pins. In addition, the FPGA will complete the enabling configuration of all power supply modules of the device and manage the status of the power supply of the device;

[0010] In the firmware, the initial state bits of two GPIO pins of the processor CPU are set to 11; the device startup process includes two stages. When the first stage is completed, that is, when the firmware configuration boot item enters the operating system, the firmware configures the state bits of the two GPIO pins of the processor CPU from the initial value of 11 to 10; when the second stage is completed, that is, when entering the login interface, the automated script configured in the operating system configures the state bits of the two GPIO pins of the processor CPU from 10 to 00;

[0011] When the computing device is in a low-temperature scenario, after power-on startup, the counter in the FPGA starts to work and count time, and synchronously monitors the state bits of two GPIO pins;

[0012] When the counted time reaches the completion time of the first stage, when the state bit is monitored as 10, the FPGA does not perform any operation on the device; when the state bit is monitored as 11, the FPGA will re-automatically configure all power modules of the device to be re-enabled, and complete the re-power-on startup of the device;

[0013] When the counted time reaches the completion time of the second stage, when the state bit is monitored as 00, the FPGA does not perform any operation on the device; when the state bit is monitored as 10, the FPGA will re-configure the enabling of all power modules of the device, and complete the re-power-on startup of the device.

[0014] (III) Beneficial effects

[0015] The present invention proposes a system self-protection safety management method in a harsh environment. This method relies on the device hardware link and comprehensively uses firmware, system, and FPGA to jointly solve the problem that the device cannot start up when it is in a low-temperature scenario for a long time.

[0016] In the present invention, the function mode and initial state bits of the hardware pins are configured in the firmware, an automated script is configured under the operating system to re-configure the state bits of the hardware pins, and at the same time, the FPGA continuously monitors the state of the hardware pins and manages the self-startup of the device, greatly improving the reliability and stability of device use. Description of the drawings

[0017] Figure 1 It is a device ecological environment block diagram of the system self-protection safety management method of the present invention in a harsh environment. Specific implementation manners

[0018] To make the purpose, content, and advantages of the present invention clearer, the following further describes the specific implementation manners of the present invention in detail with reference to the drawings and embodiments.

[0019] The present invention proposes a system self - protection security management method in harsh environments, specifically a system self - protection security management method applied to the Feiteng D2000 processor platform, to solve the problem that computing devices cannot start normally in harsh environments (especially in low - temperature scenarios), and can effectively improve the reliability of device use.

[0020] The purpose of this invention patent is to propose a system self - protection security management method applied to the Feiteng D2000 processor platform to improve the reliability of computing devices in low - temperature scenarios. This method relies on the device hardware link, and the device firmware, operating system, and FPGA cooperate to jointly solve the problem that computing devices cannot start when in a low - temperature scenario for a long time, and can effectively improve the collaborative computing ability among devices in the command and control system.

[0021] The present invention provides a system self - protection security management method in harsh environments. The device ecological environment in which this method works includes: processor CPU, FPGA, firmware, operating system, and power module;

[0022] Two GPIO hardware pins of the processor CPU are physically connected to the GPIO pins of the FPGA. A counter is configured in the FPGA for working timing. At the same time, the FPGA continuously monitors the status bits of these two GPIO pins. In addition, the FPGA will complete the enable (EN) configuration of all power modules of the device and manage the power status of the device;

[0023] In the firmware, the initial status bits of the two GPIO pins of the processor CPU are set to 11; The device startup process includes two stages. In the first stage, when the firmware configuration boot item enters the operating system, the firmware configures the status bits of the two GPIO pins of the processor CPU from the initial value 11 to 10; In the second stage, when entering the login interface, the operating system configures an automation script to configure the status bits of the two GPIO pins of the processor CPU from 10 to 00;

[0024] When the computing device is in a low - temperature scenario and powered on and started, the counter in the FPGA starts to work and time, and synchronously monitors the status bits of the two GPIO pins;

[0025] When the timing reaches the completion time of the first stage, when the status bit is monitored as 10, the FPGA does not perform any operation on the device; When the status bit is monitored as 11, the FPGA will re - automatically configure the enable of all power modules of the device and complete the re - power - on startup of the device;

[0026] When the timing reaches the completion time of the second stage, when the status bit is monitored as 00, the FPGA does not perform any operation on the device; When the status bit is monitored as 10, the FPGA will re - configure the enable of all power modules of the device and complete the re - power - on startup of the device.

[0027] Embodiment 1:

[0028] As Figure 1 shown, the present invention provides a system self - protection safety management method under harsh environments. The device ecological environment involved mainly includes five parts: the processor CPU, FPGA, firmware, operating system, and power supply module. Among them, the CPU is a D2000 processor; the FPGA functions for logical operation and controlling the power supply timing in the device; the firmware adopts the UEFI standard to facilitate initializing the hardware and loading the operating system when the device starts up; the operating system is the Galaxy Kylin V10 version.

[0029] The present invention relies on 2 GPIO hardware pins of the D2000 processor to achieve physical connection with the GPIO pins of the FPGA. A counter is configured in the FPGA. Since the device powers on and starts up, the counter starts working and timing, and at the same time continuously monitors the status bits of these two GPIO pins. In addition, the FPGA will complete the enable (EN) configuration of all power supply modules of the device and manage the power supply status of the device.

[0030] In the firmware, function settings are first carried out. The "safety management mode" option bar is set, and the default state of the safety management mode is configured to be turned on; at the same time, the initial values of the 2 GPIO pins of the D2000 are configured under the "safety management mode", and both are set to the pull - up mode of the internal resistor of the D2000, that is, the initial status bits of the GPIO pins are 11.

[0031] According to the test of the startup time of the computing device under normal working scenarios, it can be known that the device startup is completed in two stages: one is that the time for the device to complete the firmware configuration is about 30s, and the other is that the time for the firmware to boot into the operating system and enter the system login interface is about 10s.

[0032] When the first stage is completed, that is, when the firmware configuration boot item enters the operating system, the firmware will complete the re - configuration of the values of the 2 GPIO pins of the D2000 processor, and the status bits are configured from the initial value 11 to 10; when the second stage is completed, that is, when entering the login interface, the operating system configures an automated script and will complete the re - configuration of the values of the 2 GPIO pins again, and the status bits are configured from 10 to 00.

[0033] When the computing device is in a low-temperature scenario, after power-on startup, the counter in the FPGA starts working and timing, and simultaneously monitors the status bits of 2 GPIO pins. When the timing reaches 30s and the monitored status bits are 10, it proves that the device has completed the configuration of the firmware boot item, and at this time the FPGA does not perform any operations on the device; if the monitored status bits are 11, it proves that the device has not completed the firmware-side configuration. At this time, the FPGA will re-enable all power modules of the device automatically and complete the power-on startup of the device again. When the timing reaches 40s (30s for firmware configuration and 10s for booting into the operating system), and the monitored status bits are 00, it proves that the device has entered the operating system login interface and the device startup is completed. At this time, the FPGA does not perform any operations on the device; if the monitored status bits are 10, it proves that the device is stuck in the process of entering the operating system login interface and the device startup is not completed. At this time, the FPGA will also reconfigure the enabling of all power modules of the device and complete the power-on startup of the device again.

[0034] Setting two monitoring points in the FPGA can manage the computing device more effectively and avoid the phenomenon that the device is stuck in the firmware stage in a low-temperature environment (-43°C) but still needs to wait 40s before it can restart the system automatically. This method can enable the device to achieve the effect of system self-startup by increasing the internal environmental temperature of the device when it cannot enter the operating system login interface for the first time in a low-temperature environment.

[0035] In addition, when the device needs to reinstall the system, it can first enter the graphical management interface of the firmware and turn off the "security management mode" to prevent the system self-protection security management mode from being triggered during the system reinstallation process.

[0036] The system self-protection security management method proposed by the present invention, after actual testing, in a low-temperature environment (-43°C), the startup reliability of the computing device is increased from 90% to 100%, avoiding the phenomenon that the device randomly freezes and cannot start up and enter the operating system login interface, and greatly improving the collaborative processing ability among devices of the command and control system.

[0037] The present invention proposes a system self-protection security management method in a harsh environment. This method relies on the device hardware link and comprehensively uses firmware, system and FPGA to jointly solve the problem that the device cannot start up for a long time in a low-temperature scenario.

[0038] The present invention configures the function mode and initial status bits of the hardware pins in the firmware, configures an automated script under the operating system to reconfigure the status bits of the hardware pins, and at the same time the FPGA continuously monitors the status of the hardware pins and manages the device self-startup, greatly improving the reliability and stability of device use.

[0039] The above are only the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the technical principle of the present invention, several improvements and modifications can be made, and these improvements and modifications should also be regarded as the protection scope of the present invention.

Claims

1. A system self - protection safety management method in a harsh environment, characterized in that, The device ecological environment in which the method works includes: a processor CPU, an FPGA, firmware, an operating system, and a power module; Two GPIO hardware pins of the processor CPU are physically connected to the GPIO pins of the FPGA. A counter is configured in the FPGA for working timing. At the same time, the FPGA continuously monitors the status bits of these two GPIO pins. In addition, the FPGA will complete the enabling configuration of all power modules of the device and manage the status of the device's power supply; In the firmware, the initial status bits of the two GPIO pins of the processor CPU are set to 11; The device startup process includes two stages. When the first stage is completed, that is, when the firmware configuration boot item enters the operating system, the firmware configures the status bits of the two GPIO pins of the processor CPU from the initial value 11 to 10; When the second stage is completed, that is, when entering the login interface, the operating system configures an automation script to configure the status bits of the two GPIO pins of the processor CPU from 10 to 00; When the computing device is in a low-temperature scenario, after power-on startup, the counter in the FPGA starts to work and time, and simultaneously monitors the status bits of the two GPIO pins; When the timing reaches the completion time of the first stage, when the status bit is monitored as 10, the FPGA does not perform any operation on the device; When the status bit is monitored as 11, the FPGA will re-automatically configure the enabling of all power modules of the device and complete the re-power-on startup of the device; When the timing reaches the completion time of the second stage, when the status bit is monitored as 00, the FPGA does not perform any operation on the device; When the status bit is monitored as 10, the FPGA will reconfigure the enabling of all power modules of the device and complete the re-power-on startup of the device.

2. The system self-protection safety management method in a harsh environment according to claim 1, characterized in that The processor CPU is a D2000 processor.

3. The system self-protection safety management method under harsh environment according to claim 1, characterized in that The firmware adopts the UEFI standard, which is convenient for the device to initialize the hardware and load the operating system during startup.

4. The system self-protection safety management method under harsh environment according to claim 1, characterized in that, The operating system is the Galaxy Kylin V10 version.

5. The system self-protection safety management method under harsh environments according to claim 1, characterized in that, Function settings are made in the firmware. The "Security Management Mode" option bar is set, and the default state of the security management mode is configured to be on; At the same time, the initial values of the two GPIO pins of the D2000 are configured in the "Security Management Mode", and both are set to the pull-up mode of the internal resistor of the D2000, that is, the initial status bits of the GPIO pins are 11.

6. The system self-protection safety management method in a harsh environment according to claim 5, characterized in that When the device needs to reinstall the system, first enter the graphical management interface of the firmware and turn off the "Security Management Mode" to prevent the system self-protection security management mode from being triggered during the system reinstallation process.

7. The system self - protection safety management method under harsh environments according to any one of claims 1 - 6, characterized in that, The completion time of the first stage, that is, the time when the device completes the firmware configuration, is 30s.

8. The system self-protection safety management method in a harsh environment according to claim 7, characterized in that The completion time of the second stage is the sum of the completion time of the first stage and the time from the firmware boot to the operating system and entering the system login interface. The time from the firmware boot to the operating system and entering the system login interface is 10s.

9. The system self - protection safety management method in a harsh environment according to claim 8, characterized in that, When the timing reaches 30s, if the status bit is monitored as 10, it proves that the device has completed the configuration of the firmware boot item. At this time, the FPGA does not perform any operation on the device; If the status bit is monitored as 11, it proves that the device has not completed the firmware-side configuration. At this time, the FPGA will re-automatically configure the enabling of all power modules of the device and complete the re-power-on startup of the device.

10. The system self-protection safety management method in a harsh environment according to claim 9, characterized in that When the timing reaches 40s and the status bit is monitored as 00, it proves that the device has entered the operating system login interface and the device startup is completed. At this time, the FPGA does not perform any operations on the device; if the status bit is monitored as 10, it proves that the device is stuck in the process of entering the operating system login interface and the device startup is not completed. At this time, the FPGA will also reconfigure the enabling of all power modules of the device to complete the power-on startup of the device again.

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