Gate drive circuit and display panel

Abstract

The embodiment of the invention provides a gate drive circuit and a display panel. A sixth transistor in a conducting state is additionally arranged between a first node and a second node, and when the second node is in a negative potential with a large absolute value for a long time, the absolute value of the potential of the first node is smaller than the absolute value of the potential of the second node due to the voltage dividing effect of the sixth transistor. Therefore, the stress borne by the first transistor connected with the first node can be reduced, the risk that the electrical characteristic value of the first transistor drifts under the action of the stress is reduced, and the stability of the gate drive circuit is improved.

Description

Technical Field

[0001] This application relates to the field of display technologies, and particularly to a gate driving circuit and a display panel. Background Art

[0002] GOA (Gate Driver on Array) technology, that is, the row driving technology for an array substrate, directly fabricates a gate driving circuit on the array substrate, thereby saving the space for separately arranging a scanning driving circuit through an integrated chip, and facilitating the realization of a narrow bezel design for a display. Therefore, GOA technology is increasingly widely applied in the field of display panels.

[0003] Currently, during the continuous output of scanning signals, electrical characteristic values such as the threshold voltage of transistors in the gate driving circuit change, which is not conducive to the stable operation of the gate driving circuit. Summary of the Invention

[0004] Embodiments of this application provide a gate driving circuit and a display panel, which reduce the stress on transistors in the gate driving circuit under negative voltage and improve the stability of the gate driving circuit to at least partially solve the above technical problems.

[0005] To achieve the above object, according to the first aspect of the embodiments of the present application, a gate driving circuit is provided. The gate driving circuit includes a plurality of gate driving units. At least one of the gate driving units includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a capacitor. A first electrode of the first transistor is connected to a first node, and a second electrode of the first transistor is configured to receive a start signal or a stage transmission signal. A gate of the second transistor is connected to the first node or a second node, a first electrode of the second transistor is configured to receive a first-level voltage, and a second electrode of the second transistor is connected to a third node. A gate of the third transistor is connected to the first node or the second node. A first electrode of the third transistor is connected to the third node. A second electrode of the third transistor is configured to receive a second-level voltage. The second-level voltage is different from the first-level voltage. A channel region type of the third transistor is different from a channel region type of the second transistor. A gate of the fourth transistor is connected to the second node, and a first electrode of the fourth transistor is connected to a scan signal output terminal. One plate of the capacitor is connected to the scan signal output terminal, and the other plate of the capacitor is connected to the second node. A gate of the fifth transistor is connected to the third node, and a first electrode of the fifth transistor is connected to the scan signal output terminal. A first electrode of the sixth transistor is connected to the first node, a second electrode of the sixth transistor is connected to the second node, and a gate of the sixth transistor is configured to receive a third-level voltage and is in a conducting state.

[0006] According to the second aspect of the embodiments of the present application, the display panel includes the above-mentioned gate driving circuit and a plurality of pixel driving circuits. One of the pixel driving circuits includes a plurality of transistors, and a gate of at least one of the transistors of the pixel driving circuit is connected to the scan signal output terminal.

[0007] In the gate driving circuit and the display panel according to some embodiments of the present application, a sixth transistor in a conducting state is added between the first node and the second node. When the second node is in a negative potential with a relatively large absolute value for a long time, the voltage-dividing effect of the sixth transistor makes the absolute value of the potential of the first node less than the absolute value of the potential of the second node. In this way, the stress on the first transistor connected to the first node can be reduced, the risk of drift of the electrical characteristic value of the first transistor under the action of stress can be reduced, and the stability of the gate driving circuit can be improved. Description of the Drawings

[0008] Figure 1 It is a schematic plan view of the display panel provided by the embodiments of the present application;

[0009] Figure 2Circuit diagram of a pixel driving circuit provided by an embodiment of the present application;

[0010] Figure 3 Provided by an embodiment of the present application Figure 2 Signal timing diagram of the pixel driving circuit shown;

[0011] Figure 4 Circuit diagram of a gate driving circuit provided by an embodiment of the present application;

[0012] Figure 5 Circuit diagram of another gate driving circuit provided by an embodiment of the present application;

[0013] Figure 6 Circuit diagram of yet another gate driving circuit provided by an embodiment of the present application;

[0014] Figure 7 Circuit diagram of yet another gate driving circuit provided by an embodiment of the present application;

[0015] Figure 8 Circuit diagram of yet another gate driving circuit provided by an embodiment of the present application;

[0016] Figure 9 Circuit diagram of yet another gate driving circuit provided by an embodiment of the present application;

[0017] Figure 10 Signal timing diagram of a gate driving unit provided by an embodiment of the present application;

[0018] Figure 11 Another signal timing diagram of the gate driving unit provided by an embodiment of the present application.

[0019] Explanation of reference numerals:

[0020] 100, display panel; 100A, display area; 100B, non-display area;

[0021] 10, pixel driving circuit;

[0022] Td, driving transistor; Tw, data writing transistor; Cst, storage capacitor; Cbst, bootstrap capacitor; Tc, compensation transistor; Ti, initialization transistor; Tem1, first light-emitting control transistor; Tem2, second light-emitting control transistor; Trst1, first reset transistor; Trst2, second reset transistor;

[0023] VDD, first power signal terminal; VSS, second power signal terminal;

[0024] 11, light-emitting device;

[0025] Pscan, the first scan signal; Nscan1, the second scan signal; Nscan2, the third scan signal; Pscan2, the fourth scan signal; Vi1, the first initialization signal; Vi2, the second initialization signal; Vi3, the third initialization signal; Data, the data signal; EM, the light emission control signal;

[0026] ta, the first initialization period; tb, the second initialization stage; tc, the data writing period; td, the third initialization period; te, the light emission period;

[0027] 20, the gate driving circuit; 201, the gate driving unit;

[0028] T1, the first transistor; T2, the second transistor; T3, the third transistor; T4, the fourth transistor; T5, the fifth transistor; T6, the sixth transistor; T7, the seventh transistor; T8, the eighth transistor; T9, the ninth transistor;

[0029] M, the first node; Q, the second node; P, the third node; C1, the capacitor;

[0030] STV, the start signal; STn, the stage transfer signal; CK1, the first clock signal; CK2, the second clock signal; CK3, the third clock signal; NOUT, the scan signal output terminal. Detailed implementation manners

[0031] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts belong to the scope of protection of the present application.

[0032] Figure 1 It is a schematic plan view of the display panel provided by the embodiment of the present application. Figure 2 It is a circuit diagram of a pixel driving circuit provided by the embodiment of the present application.

[0033] As Figure 1 and Figure 2 shown, the display panel 100 has a display area 100A. The display panel 100 includes a plurality of pixel driving circuits 10 and a plurality of light emitting devices 11 located in the display area 100A. The plurality of pixel driving circuits 10 are respectively connected to the plurality of light emitting devices 11 to drive the plurality of light emitting devices 11 to emit light.

[0034] In some embodiments, the light-emitting device 11 may include at least one of a liquid crystal display device, an organic light-emitting diode device, a micro light-emitting diode device, and a submillimeter light-emitting diode device. Exemplarily, the light-emitting device 11 may be an organic light-emitting diode device.

[0035] As Figure 2 shown, the pixel driving circuit 10 includes a driving transistor Td, a data writing transistor Tw, a storage capacitor Cst, a compensation transistor Tc, an initialization transistor Ti, a first light-emitting control transistor Tem1, and a second light-emitting control transistor Tem2.

[0036] The first electrode of the driving transistor Td is connected to the first power supply signal terminal VDD, and the second electrode of the driving transistor Td is connected to the second power supply signal terminal VSS. The first electrode and the second electrode of the light-emitting device 11 are connected in series between the second electrode of the driving transistor Td and the second power supply signal terminal VSS. When the driving transistor Td is turned on, a driving current flows out from the second electrode of the driving transistor Td to the light-emitting device 11, causing the light-emitting device 11 to emit light.

[0037] The first power supply signal terminal VDD is configured to input a first power supply signal. The second power supply signal terminal VSS is configured to input a second power supply signal. The second power supply signal is different from the first power supply signal. In some embodiments, the first power supply signal may be a high-level power supply voltage, and the second power supply signal may be a low-level power supply voltage.

[0038] The first electrode of the light-emitting device 11 may be an anode, and the second electrode of the light-emitting device 11 may be a cathode.

[0039] The first electrode of the data writing transistor Tw is connected to a data line (not shown in the figure) to receive a data signal Data transmitted by the data line. The second electrode of the data writing transistor Tw is connected to the first electrode of the driving transistor Td. The gate of the data writing transistor Tw is connected to a first scanning signal line (not shown in the figure) to receive a first scanning signal Pscan transmitted by the first scanning signal line. When the data writing transistor Tw is turned on under the action of the first scanning signal Pscan, the data signal Data is written into the first electrode of the driving transistor Td through the turned-on data writing transistor Tw.

[0040] The storage capacitor Cst includes a first electrode plate and a second electrode plate. The first electrode plate is connected to the first power supply signal terminal VDD. The second electrode plate is connected to the gate of the driving transistor Td.

[0041] The first electrode and the second electrode of the first light-emitting control transistor Tem1 are connected in series between the first electrode of the driving transistor Td and the first power supply signal terminal VDD. The gate of the first light-emitting control transistor Tem1 is connected to a light-emitting control signal line (not shown in the figure) to receive a light-emitting control signal EM transmitted by the light-emitting control signal line.

[0042] The first electrode and the second electrode of the second light-emitting control transistor Tem2 are connected in series between the second electrode of the driving transistor Td and the light-emitting device 11. The gate of the second light-emitting control transistor Tem2 is connected to the light-emitting control signal line to receive a light-emitting control signal EM transmitted by the light-emitting control signal line.

[0043] When the first light-emitting control transistor Tem1 and the second light-emitting control transistor Tem2 are turned on under the action of the light-emitting control signal EM and the driving transistor Td is turned on, the driving transistor Td drives the light-emitting device 11 to emit light.

[0044] The first electrode of the compensation transistor Tc is connected to the second electrode of the driving transistor Td. The second electrode of the compensation transistor Tc is connected to the gate of the driving transistor Td. The gate of the compensation transistor Tc is connected to a second scan signal line (not shown in the figure) to receive a second scan signal Nscan1 transmitted by the second scan signal line. When the compensation transistor Tc is turned on under the action of the second scan signal Nscan1, a short circuit occurs between the second electrode and the gate of the driving transistor Td, so as to facilitate the compensation of the threshold voltage of the driving transistor Td.

[0045] The first electrode of the initialization transistor Ti is connected to the gate of the driving transistor Td and the second electrode of the compensation transistor Tc. The second electrode of the initialization transistor Ti is connected to a first initialization signal line to receive a first initialization signal Vi1 transmitted by the first initialization signal line. The gate of the initialization transistor Ti is connected to a third scan signal line (not shown in the figure) to receive a third scan signal Nscan2 transmitted by the third scan signal line. When the initialization transistor Ti is turned on under the action of the third scan signal Nscan2, the first initialization signal Vi1 is output to the gate of the driving transistor Td to initialize the potential of the gate of the driving transistor Td.

[0046] In some embodiments, the first initialization signal Vi1 may be a negative voltage.

[0047] In some embodiments, the pixel driving circuit 10 further includes a bootstrap capacitor Cbst. The bootstrap capacitor Cbst includes a third electrode plate and a fourth electrode plate. The third electrode plate is connected to a first scan signal line (not shown in the figure) to receive a first scan signal Pscan transmitted by the first scan signal line. The fourth electrode plate is connected to the gate of the driving transistor Td. The bootstrap capacitor Cbst functions to pull up the first scan signal Pscan, ensuring that the data writing transistor Tw can be stably turned on.

[0048] In some embodiments, as Figure 2 shown, the pixel driving circuit 10 further includes a first reset transistor Trst1. The first electrode of the first reset transistor Trst1 is connected to the first electrode of the light emitting device 11. The second electrode of the first reset transistor Trst1 is connected to a second initialization signal line to receive a second initialization signal Vi2 transmitted by the second initialization signal line. The gate of the first reset transistor Trst1 is connected to a fourth scan signal line (not shown in the figure) to receive a fourth scan signal Pscan2 transmitted by the fourth scan signal line. When the first reset transistor Trst1 is turned on, the second initialization signal Vi2 is transmitted to the first electrode of the light emitting device 11 through the turned-on first reset transistor Trst1, realizing the initialization of the potential of the first electrode of the light emitting device 11.

[0049] In some embodiments, as Figure 2 shown, the pixel driving circuit 10 further includes a second reset transistor Trst2. The first electrode of the second reset transistor Trst2 is connected to the first electrode of the driving transistor Td. The second electrode of the second reset transistor Trst2 is connected to a third initialization signal line to receive a third initialization signal Vi3 transmitted by the third initialization signal line. The gate of the second reset transistor Trst2 is connected to a fourth scan signal line (not shown in the figure) to receive a fourth scan signal Pscan2 transmitted by the fourth scan signal line. When the second reset transistor Trst2 is turned on, when the third initialization signal Vi3 is transmitted to the first electrode of the driving transistor Td through the turned-on second reset transistor Trst2, the initialization of the potential of the first electrode of the driving transistor Td is realized.

[0050] In some embodiments, the third initialization signal may be a positive voltage.

[0051] It should be noted that in the present application, the first electrode and the second electrode of transistors such as the driving transistor Td are the source electrode and the drain electrode respectively. For other transistors except the driving transistor Td, the first electrode and the second electrode are also the source electrode and the drain electrode respectively.

[0052] In some embodiments, as Figure 2As shown, the driving transistor Td, data writing transistor Tw, first light-emitting control transistor Tem1, second light-emitting control transistor Tem2, first reset transistor Trst1, and second reset transistor Trst2 can all be P-type transistors, and the compensation transistor Tc and initialization transistor Ti can both be n-type transistors. Therefore, the driving transistor Td, data writing transistor Tw, first light-emitting control transistor Tem1, second light-emitting control transistor Tem2, first reset transistor Trst1, and second reset transistor Trst2 are all turned on under the action of a low-level voltage and turned off under the action of a high-level voltage. Moreover, the compensation transistor Tc and initialization transistor Ti are turned on under the action of a high-level voltage and turned off under the action of a low-level voltage.

[0053] In some embodiments, the driving transistor Td, data writing transistor Tw, first light-emitting control transistor Tem1, second light-emitting control transistor Tem2, first reset transistor Trst1, and second reset transistor Trst2 can all include a low-temperature polysilicon active layer, that is, these transistors are all low-temperature polysilicon transistors. Low-temperature polysilicon transistors not only have the advantages of high electron mobility and low power consumption but also facilitate the display panel 100 to achieve high-resolution display. Moreover, the compensation transistor Tc and initialization transistor Ti can both include a metal oxide active layer, that is, these transistors are metal oxide transistors. Metal oxide transistors have low leakage current, reducing the leakage current when the compensation transistor Tc and initialization transistor Ti are in the off state.

[0054] Figure 3 Provided by the embodiments of the present application Figure 2 The signal timing diagram of the pixel driving circuit shown.

[0055] The working process of the pixel driving circuit 10 of the embodiments of the present application includes a first initialization period ta, a second initialization stage tb, a data writing period tc, a third initialization period td, and a light-emitting period te.

[0056] In the first initialization period ta, the first scan signal Pscan, the second scan signal Nscan1, and the light-emitting control signal EM all have a high level, and the third scan signal Nscan2 and the fourth scan signal Pscan2 have a low level. Therefore, the first reset transistor Trst1, the second reset transistor Trst2, and the compensation transistor Tc are all turned on, and the initialization transistor Ti, the data writing transistor Tw, the first light-emitting control transistor Tem1, and the second light-emitting control transistor Tem2 are all turned off. Moreover, since the first initialization period ta is after the light-emitting period of the previous frame, the driving transistor Td is also turned on.

[0057] During the first initialization period ta, the first reset transistor Trst1 and the second reset transistor Trst2 are turned on to initialize the potential of the first electrode of the light-emitting device 11 and the potential of the first electrode of the driving transistor Td before the data signal Data is received at the first electrode of the driving transistor Td. Moreover, since the second reset transistor Trst2, the driving transistor Td, and the compensation transistor Tc are all turned on, a path is formed to reset all three electrodes of the driving transistor Td, namely the first electrode, the second electrode, and the gate, to initialize the three electrodes of the driving transistor Td before the data signal Data is received at the first electrode of the driving transistor Td, thereby improving the hysteresis effect of the driving transistor.

[0058] During the second initialization stage tb, the first scan signal Pscan, the third scan signal Nscan2, the fourth scan signal Pscan2, and the light-emitting control signal EM all have high levels, while the second scan signal Nscan1 has a low level. Therefore, the initialization transistor Ti is turned on, and the first reset transistor Trst1, the second reset transistor Trst2, the driving transistor Td, the compensation transistor Tc, the data writing transistor Tw, the first light-emitting control transistor Tem1, and the second light-emitting control transistor Tem2 are all turned off.

[0059] During the second initialization stage tb, the initialization transistor Ti is turned on to initialize the driving transistor Td, ensuring that the driving transistor Td is turned on during the data writing period tc to write the data signal Data more quickly.

[0060] During the data writing period tc, the first scan signal Pscan and the third scan signal Nscan2 have low levels, while the second scan signal Nscan1, the fourth scan signal Pscan2, and the light-emitting control signal EM have high levels. Therefore, the data writing transistor Tw, the driving transistor Td, and the compensation transistor Tc are all turned on. The data signal Data is compensated after passing through the turned-on driving transistor Td and compensation transistor Tc, and the compensated data signal Data is transmitted to the gate of the driving transistor Td. Moreover, the first reset transistor Trst1, the second reset transistor Trst2, the initialization transistor Ti, the first light-emitting control transistor Tem1, and the second light-emitting control transistor Tem2 are all turned off.

[0061] During the third initialization period td, the second scan signal Nscan1, the third scan signal Nscan2, and the fourth scan signal Pscan2 all have low levels, and the emission control signal EM and the first scan signal Pscan have high levels. Therefore, the first reset transistor Trst1 and the second reset transistor Trst2 are turned on, and the data write transistor Tw, the initialization transistor Ti, the compensation transistor Tc, the first emission control transistor Tem1, and the second emission control transistor Tem2 are all turned off.

[0062] During the third initialization period td, the first reset transistor Trst1 and the second reset transistor Trst2 are turned on to initialize the potentials of the first electrode of the driving transistor Td and the first electrode of the light-emitting device 11 before the light-emitting device 11 emits light, thereby improving the influence of the potential difference between the first electrode of the driving transistor Td and the first electrode of the light-emitting device 11 on light emission.

[0063] During the light-emitting period te, the emission control signal EM, the second scan signal Nscan1, and the third scan signal Nscan2 all have low levels, and the first scan signal Pscan and the fourth scan signal Pscan2 all have high levels. Therefore, the first emission control transistor Tem1, the second emission control transistor Tem2, and the driving transistor Td are all turned on, and the driving current generated by the driving transistor Td flows through the light-emitting device 11, causing the light-emitting device 11 to emit light. Also, the data write transistor Tw, the compensation transistor Tc, the initialization transistor Ti, the first reset transistor Trst1, and the second reset transistor Trst2 are all turned off.

[0064] It can be seen from this that the pixel driving circuit 10 can drive the light-emitting device 11 to emit light to ensure that the display panel 100 displays an image.

[0065] Please continue to refer to Figure 3 It can be known that during one working cycle of the pixel driving circuit 10, the emission control signal EM, the second scan signal Nscan1, the third scan signal Nscan2, and the fourth scan signal Pscan2 are in a low level state for a long time and in a high level state for a short time. Also, the first scan signal Pscan is in a high level state for a long time and in a low level state for a short time. For the fourth scan signal Pscan2, it is also in a high level state for a long time. Therefore, different gate driving circuits need to be provided to output a variety of different control signals, so as to meet the requirements of the pixel driving circuit 10 to ensure the normal operation of the pixel driving circuit 10.

[0066] Refer to Figure 1, the display panel 100 further includes a gate driving circuit 20. In some embodiments, the gate driving circuit 20 may be located in the non-display area 100B of the display panel 100, and the non-display area 100B is located at the periphery of the display area 100A. In other embodiments, the gate driving circuit 20 may also be located in the display area 100A of the display panel 100.

[0067] In some embodiments, the gate driving circuit 20 may be configured to output one or more of a light emission control signal EM, a first scan signal Pscan, a second scan signal Nscan1, a third scan signal Nscan2, and a fourth scan signal Pscan2.

[0068] The gate driving circuit 20 includes a plurality of gate driving units 201. At least one gate driving unit 201 is connected to the gates of at least one transistor of a pixel driving circuit 10 to provide one or more control signals to one or more transistors of a pixel driving circuit 10.

[0069] In some embodiments, the gate driving circuit 20 may include a first gate driving unit (not shown in the figure), and the first gate driving unit is configured to output a light emission control signal EM. The output terminal of the first gate driving unit may be connected to the gates of the first light emission control transistor and the second light emission control transistor of the pixel driving circuit 10 through a light emission control signal line.

[0070] In some embodiments, the gate driving circuit 20 may further include a second gate driving unit (not shown in the figure), and the second gate driving unit is configured to output a second scan signal Nscan1. The output terminal of the second gate driving unit may be connected to the gate of the compensation transistor Tc of the pixel driving circuit 10 through a second scan signal line.

[0071] In some embodiments, the gate driving circuit 20 may further include a third gate driving unit (not shown in the figure), and the third gate driving unit is configured to output a third scan signal Nscan2. The output terminal of the third gate driving unit may be connected to the gate of the initialization transistor Ti of the pixel driving circuit 10 through a third scan signal line.

[0072] In some embodiments, the gate driving circuit 20 may further include a fourth gate driving unit (not shown in the figure), and the fourth gate driving unit is configured to output a fourth scan signal Pscan2. The output terminal of the third gate driving unit may be connected to the gates of the first reset transistor Trst1 and the second reset transistor Trst2 of the pixel driving circuit 10 through a fourth scan signal line.

[0073] In some embodiments, the gate driving circuit 20 may include a fifth gate driving unit (not shown in the figure), and the fifth gate driving unit is configured to output a first scan signal Pscan. The output terminal of the first gate driving unit may be connected to the gate of the data writing transistor of the pixel driving circuit 10 through a first scan signal line.

[0074] Figure 4 The circuit diagram of a gate driving circuit provided by an embodiment of the present application. Figure 5 The circuit diagram of another gate driving circuit provided by an embodiment of the present application.

[0075] As Figure 4 and Figure 5 shown, at least one gate driving unit 201 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6.

[0076] The first transistor T1 is configured to control the potential of the first node M. The first electrode of the first transistor T1 is connected to the first node M, and the second electrode of the first transistor T1 is configured to receive a start signal STV or a stage transmission signal STn.

[0077] In some embodiments, the stage transmission signal STn may be a scan signal output by a previous-stage gate driving unit 201, that is, a scan signal output by a gate driving unit 201 before the current-stage gate driving unit 201; the stage transmission signal STn may also be a scan signal output by a subsequent-stage gate driving unit 201, that is, a scan signal output by a gate driving unit after the current-stage gate driving unit 201.

[0078] It should be noted that, for the first few levels of the gate driving units 201 among multiple gate driving units 201, the second electrode of the first transistor T1 may be configured to receive the start signal STV. For the other gate driving units 201 except for the first few levels of the gate driving units 201 among multiple gate driving units 201, the second electrode of the first transistor T1 may be configured to receive the stage transmission signal STn.

[0079] The second transistor T2 and the third transistor T3 cooperate with each other to form an inverter. The second transistor T2 and the third transistor T3 adjust the potential of the third node P according to the potential of at least one of the first node M and the second node Q. The logic state of the third node P is opposite to the logic states of the first node M and the second node Q. Specifically, when the potentials of the first node M and the second node Q are high levels, the potential of the third node P is a low level.

[0080] The type of the channel region of the third transistor T3 is different from that of the channel region of the second transistor T2. In this way, the second transistor T2 and the third transistor T3 are turned on by level voltages of different logic states. Specifically, the channel region of one of the third transistor T3 and the second transistor T2 is an N-type channel region, and the channel region of the other of the third transistor T3 and the second transistor T2 is a P-type channel region. Therefore, when one of the second transistor T2 and the third transistor T3 is turned off, the other of the second transistor T2 and the third transistor T3 is turned on. Moreover, the second transistor T2 and the third transistor T3 form an inverter, ensuring that the second node Q and the third node P are in opposite logic states, while significantly reducing the number of transistors in the gate driving unit 201, which is beneficial to reducing the size occupied when the gate driving circuit 20 is located in the non-display area 100B of the display panel 100, and enabling the display panel 100 to achieve a narrow border.

[0081] The gate of the second transistor T2 is connected to the first node M or the second node Q. The first electrode of the second transistor T2 is configured to receive the first level voltage. The second electrode of the second transistor T2 is connected to the third node P. When the second transistor T2 is turned on according to the potential of the first node M or the second node Q, the first level voltage is transmitted to the third node P.

[0082] The gate of the third transistor T3 is connected to the first node M or the second node Q. The first electrode of the third transistor T3 is connected to the third node P. The second electrode of the third transistor T3 is configured to receive the second level voltage. The second level voltage is different from the first level voltage. When the third transistor T3 is turned on according to the potential of the first node M or the second node Q, the second level voltage is transmitted to the third node P.

[0083] In some embodiments, the first level voltage is the high level voltage VGH, and the second level voltage is the low level voltage VGL. Therefore, when the second transistor T2 is turned on, the potential of the third node P is in the high level state. When the third transistor T3 is turned on, the potential of the third node P is in the low level state.

[0084] In some embodiments, the gate of the third transistor T3 includes a top gate and a bottom gate. The top gate and the bottom gate are located between the channel regions of the third transistor T3, and the top gate is connected to the bottom gate. In this way, the third transistor T3 has two gates, so as to improve the problem of electrical drift under stress.

[0085] In other embodiments, the third transistor T3 may also include one gate, for example, including a top gate or a bottom gate.

[0086] In some embodiments, the second transistor T2 is a P-type transistor, that is, the channel region of the second transistor T2 is a P-type channel region, reducing the driving power consumption of the second transistor T2 and reducing the area occupied by the second transistor T2. The third transistor T3 is an N-type transistor, that is, the channel region of the third transistor T3 is an N-type channel region.

[0087] In some embodiments, the third transistor T3 includes a metal oxide active layer, reducing the leakage current when the third transistor T3 is in the off state. The second transistor T2 includes a low-temperature polycrystalline silicon active layer, ensuring that the second transistor T2 has a faster switching speed and a higher driving current, and improving the high-temperature stability of the second transistor T2.

[0088] The fourth transistor T4 and the fifth transistor T5 cooperate with each other to output a scan signal from the scan signal output terminal NOUT of the gate driving unit 201 according to the potentials of the second node Q and the third node P. When the potentials of the second node Q and the third node P are in opposite logical states, when one of the fourth transistor T4 and the fifth transistor T5 is turned on, the other of the fourth transistor T4 and the fifth transistor T5 is turned off.

[0089] The gate of the fourth transistor T4 is connected to the second node Q, and the first electrode of the fourth transistor T4 is connected to the scan signal output terminal NOUT. When the fourth transistor T4 is turned on under the action of the potential of the second node Q, the received signal of the second electrode of the fourth transistor T4 is output as a scan signal from the scan signal output terminal NOUT.

[0090] The gate of the fifth transistor T5 is connected to the third node P, and the first electrode of the fifth transistor T5 is connected to the scan signal output terminal NOUT. When the fifth transistor T5 is turned on under the action of the potential of the third node P, the received signal of the second electrode of the fifth transistor T5 is output as a scan signal from the scan signal output terminal NOUT.

[0091] At least one gate driving unit 201 further includes a capacitor C1. One plate of the capacitor C1 is connected to the scan signal output terminal NOUT, and the other plate of the capacitor is connected to the second node Q. When the scan signal output terminal NOUT outputs a scan signal, the coupling effect of the capacitor C1 raises the potential of the second node Q, making the absolute value of the potential of the second node Q larger, and the fourth transistor T4 outputs the scan signal more stably.

[0092] The first electrode of the sixth transistor T6 is connected to the first node M, the second electrode of the sixth transistor T6 is connected to the second node Q, and the gate of the sixth transistor T6 is configured to receive a third-level voltage and is in a conducting state.

[0093] When the second node Q is at a relatively large negative potential for a long time, the sixth transistor T6 in the conducting state plays a voltage dividing role, making the absolute value of the potential of the first node M smaller than the absolute value of the potential of the second node Q, and reducing the stress on the first transistor T1 connected to the first node M. In this way, the risk of drift of electrical characteristic values such as the threshold voltage of the first transistor T1 under stress is reduced, and the stability of the gate driving circuit 20 is improved.

[0094] Moreover, the absolute value of the potential of the first node M is smaller than the absolute value of the potential of the second node Q, which is also beneficial to reducing the stress on at least one of the second transistor T2 and the third transistor T3 when connected to the first node M and the first electrode of the sixth transistor T6, and also reduces the risk of drift of electrical characteristic values such as the threshold voltage of at least one of the second transistor T2 and the third transistor T3 under stress, further improving the stability of the gate driving circuit 20.

[0095] In some embodiments, the sixth transistor T6 includes a low-temperature polysilicon active layer. The low-temperature polysilicon active layer has a high resistance, ensuring that the conducting sixth transistor T6 has a high resistance. After voltage division by the sixth transistor T6, the absolute value of the potential of the first node M is even smaller, which is beneficial to improving the stress on the transistors connected to the first node M, improving the problem of drift of the electrical properties of the transistors, and improving the stability of the gate driving circuit 20.

[0096] In some embodiments, the sixth transistor T6 can be a P-type transistor, which is beneficial to reducing the power consumption required by the sixth transistor T6 and reducing the layout area occupied by the sixth transistor T6, which is beneficial to the display panel 100 to achieve a narrow border.

[0097] In some embodiments, when the sixth transistor T6 can be a P-type transistor, the third-level voltage can be a low-level voltage VGL, that is, the third-level voltage can be the same as the second-level voltage.

[0098] In some embodiments, the channel regions of the first transistor T1, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are of the same type as the channel region of the second transistor T2. In this way, the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are all the same as the second transistor T2.

[0099] In some embodiments, the channel regions of the first transistor T1, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are all P-type channels, that is, these transistors are all P-type transistors, so as to reduce the area occupied by these transistors and reduce the area occupied by the gate driving unit 21 in the non-display area, which is beneficial to the display panel to achieve a narrow border.

[0100] In some embodiments, the first transistor T1, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may all include a low-temperature polysilicon active layer, that is, these transistors are all low-temperature polysilicon transistors, so as to improve the high-temperature resistance and switching speed of these transistors.

[0101] In some embodiments, such as Figure 4 and Figure 5 As shown, the gates of the second transistor T2 and the third transistor T3 are both connected to the first node M and the first electrode of the sixth transistor T6. In this way, when the potential of the second node Q is a negative potential with a relatively large absolute value, the voltage division effect of the sixth transistor T6 makes the potential of the first node M connected to the first electrode of the sixth transistor T6 a negative potential with a relatively small absolute value, reducing the stress on the first transistor T1, the second transistor T2, and the third transistor T3 connected to the first node M, and further improving the problem of drift of the electrical characteristic values of the three.

[0102] Figure 6 This is a circuit diagram of another gate driving circuit provided by an embodiment of the present application.

[0103] In some embodiments, such as Figure 6 As shown, the gates of the second transistor T2 and the third transistor T3 are both connected to the second node Q and the second electrode of the sixth transistor T6. In this way, when the potential of the second node Q is a negative potential with a relatively large absolute value, the voltage division effect of the sixth transistor T6 makes the potential of the first node M a negative potential with a relatively small absolute value, reducing the stress on the first transistor T1 connected to the first node M, so as to improve the problem of drift of the electrical properties of the first transistor T1.

[0104] Figure 7 This is a circuit diagram of another gate driving circuit provided by an embodiment of the present application. Figure 8 This is a circuit diagram of another gate driving circuit provided by an embodiment of the present application. Figure 9 This is a circuit diagram of another gate driving circuit provided by an embodiment of the present application.

[0105] In still other embodiments, such as Figures 7 to 9As shown, the gate of one of the second transistor T2 and the third transistor T3 is connected to the first node M and the first electrode of the sixth transistor T6, and the gate of the other of the second transistor T2 and the third transistor T3 is connected to the second node Q and the second electrode of the sixth transistor T6. In this way, when the second node Q is at a negative potential with a larger absolute value and the voltage division effect of the sixth transistor T6 makes the potential of the first node M at a negative potential with a smaller absolute value, not only the stress on the first transistor T1 connected to the first node M is reduced, but also the stress on one of the second transistor T2 and the third transistor T3 when connected to the first node M is reduced, thereby improving the problem of drift of the electrical characteristic values of one of the second transistor T2 and the third transistor T3 and the first transistor T1.

[0106] In some other embodiments, as Figure 7 and Figure 8 shown, the gate of the second transistor T2 can be connected to the first node M and the first electrode of the sixth transistor T6, and the gate of the third transistor T3 can be connected to the second node Q and the second electrode of the sixth transistor T6. In this way, the stress on the gate of the second transistor T2 when connected to the first node M is reduced, thereby improving the problem of drift of the electrical characteristic values of the second transistor T2.

[0107] In some embodiments, as Figure 9 shown, the gate of the third transistor T3 can be connected to the first node M and the first electrode of the sixth transistor T6, and the gate of the second transistor T2 can be connected to the second node Q and the second electrode of the sixth transistor T6. The stress on the gate of the third transistor T3 when connected to the first node M is reduced, thereby improving the problem of drift of the electrical characteristic values of the third transistor T3.

[0108] In some embodiments, as Figure 5 and Figure 9 shown, at least one gate driving unit 201 may further include a seventh transistor T7. The gate of the seventh transistor T7 is connected to the third node P, and the first electrode and the second electrode of the seventh transistor T7 are connected between the scan signal output terminal NOUT and the first electrode of the fifth transistor T5. When the voltage difference between the scan signal output by the scan signal output terminal NOUT and the received voltage of the second electrode of the fifth transistor T5 is large, the seventh transistor T7 reduces the risk that the large voltage difference causes the received voltage output by the second electrode of the fifth transistor T5 to be output to the scan signal output terminal NOUT, thereby reducing the risk of incorrect output of the scan signal output terminal NOUT.

[0109] In some embodiments, the seventh transistor T7 may be the same as the fifth transistor T5. In this way, the seventh transistor T7 and the fifth transistor T5 can be turned on or off simultaneously under the control of the potential of the third node P.

[0110] In some embodiments, the seventh transistor T7 may be a P-type transistor to reduce the driving power consumption of the seventh transistor T7. In some embodiments, the seventh transistor T7 may include a low-temperature polysilicon active layer to increase the switching speed of the seventh transistor T7 and reduce the area occupied by the seventh transistor T7.

[0111] In some embodiments, such as Figure 5 and Figure 9 shown, at least one gate driving unit 201 may further include an eighth transistor T8. The gate of the eighth transistor T8 is connected to the scan signal output terminal NOUT. The first electrode of the eighth transistor T8 is connected to the first electrode of the fifth transistor T5. The second electrode of the eighth transistor T8 is configured to receive a fourth-level voltage. In this way, the eighth transistor T8 is turned on under the control of the scan signal output from the scan signal output terminal NOUT to write the fourth-level voltage to the first electrode of the fifth transistor T5, reducing the voltage difference between the voltage of the first electrode of the fifth transistor T5 and the scan signal output from the scan signal output terminal NOUT, and reducing the risk of short circuit of the seventh transistor T7 due to a large voltage difference in the off state.

[0112] In some embodiments, the eighth transistor T8 may be a P-type transistor to reduce the driving power consumption of the eighth transistor T8. In some embodiments, the eighth transistor T8 may include a low-temperature polysilicon active layer to increase the switching speed of the eighth transistor T8 and reduce the area occupied by the eighth transistor T8.

[0113] In some embodiments, the fourth-level voltage may be a low-level voltage VGL, that is, the fourth-level voltage may be the same as the second-level voltage.

[0114] In some embodiments, such as Figure 4 shown, at least one gate driving unit 201 may further include a ninth transistor T9. The gate of the ninth transistor T9 is connected to the third node P, the first electrode of the ninth transistor T9 is configured to receive a fifth-level voltage, and the second electrode of the ninth transistor is connected to the first electrode or the second electrode of the sixth transistor T6. The ninth transistor T9 is configured to output the fifth-level voltage to the first node M or the second node Q in response to the potential of the third node P to stabilize the potential of the first node or the second node, so that the fourth transistor T4 is turned off, reducing the risk of mis-conduction of the fourth transistor T4 due to the coupling effect of the clock signal or the like when the fourth transistor T4 is turned off.

[0115] In some embodiments, the ninth transistor T9 may be a P-type transistor to reduce the driving power consumption of the ninth transistor T9. In some embodiments, the ninth transistor T9 may include a low-temperature polysilicon active layer to increase the switching speed of the ninth transistor T9 and reduce the area occupied by the ninth transistor T9.

[0116] In some embodiments, as Figure 4 shown, the second electrode of the ninth transistor T9 may be connected to the first electrode of the sixth transistor T6 to reduce the stress on the second electrode of the ninth transistor T9.

[0117] In some other embodiments, the second electrode of the ninth transistor T9 may also be connected to the second electrode of the sixth transistor T6.

[0118] In some embodiments, the fifth-level voltage may be the high-level voltage VGH, that is, the fifth-level voltage may be the same as the first-level voltage. In this way, when the ninth transistor T9 outputs the fifth-level voltage to the fourth transistor T4, the potential of the first node M or the second node Q can be pulled up, so that the fourth transistor T4 is in the off state.

[0119] For Figures 4 to 9 the gate driving unit 201 shown, the number of transistors is less than or equal to 9, significantly reducing the number of transistors in the gate driving circuit 20 and the area occupied by the transistors in the gate driving unit 201, which is beneficial for the display panel 100 to achieve a narrow border.

[0120] As Figure 4 and Figure 7 shown, the gate of the first transistor T1 is configured to receive the first clock signal CK1. The second electrode of the fourth transistor T4 is configured to receive the second clock signal CK2. The second electrode of the fifth transistor T5 is configured to receive the high-level voltage. The first clock signal CK1 is different from the second clock signal CK2.

[0121] Figure 10 This is a signal timing diagram of the gate driving unit provided by the embodiment of the present application.

[0122] In some embodiments, as Figure 10 shown, the working period of at least one gate driving unit includes a first period t1, a second period t2, and a third period t3.

[0123] In the first period t1, the fourth transistor T4 is configured to output the second clock signal CK2 with a low level to the scan signal output terminal NOUT in response to the potential of the second node Q, and the fifth transistor T5 is configured to be in the off state in response to the potential of the third node P.

[0124] During a second time period t2, the fourth transistor T4 is configured to output a second clock signal CK2 having a high level to a scan signal output terminal NOUT in response to a potential of a second node Q, and the fifth transistor T5 is configured to be in an off state in response to a potential of a third node P.

[0125] During a third time period t3, the fourth transistor T4 is configured to be in an off state in response to a potential of the second node Q, and the fifth transistor T5 is configured to output a high-level voltage to the scan signal output terminal NOUT in response to a potential of the third node P.

[0126] Thus, during a first time period t1, the fourth transistor T4 outputs a second clock signal CK2 having a low level as a scan signal having a low level. And, during the second time period t2 and the third time period t3, the second clock signal CK2 having a high level output by the fourth transistor T4 and the high-level voltage output by the fifth transistor T5 serve as a scan signal having a high level. The duration of the scan signal having a high level can be greater than the duration of the scan signal having a low level.

[0127] In some embodiments, as Figure 10 shown, during the first time period t1 and the second time period t2, the potentials of the first node M and the second node Q are at a low level. The second transistor T2 is configured to output a first-level voltage to the third node P in response to the potential of the first node M or the second node Q, and the third transistor T3 is configured to be turned off in response to the potential of the first node M or the second node Q. Thus, during the first time period t1 and the second time period t2, the first-level voltage output by the second transistor T2 pulls up the potential of the third node P to a high level, so that the fifth transistor T5 is turned off during this time period.

[0128] In some embodiments, during the third time period t3, the potentials of the first node M and the second node Q are at a high level. The second transistor T2 is configured to be turned off in response to the potential of the first node M or the second node Q, and the third transistor T3 is configured to output a second-level voltage to the third node P in response to the potential of the first node M or the second node Q. Thus, during the third time period t3, the second-level voltage output by the third transistor T3 pulls down the potential of the third node P to a low level, so that the fifth transistor T5 is turned on during this time period.

[0129] The first clock signal CK1 and the second clock signal CK2 have different phases. In some embodiments, as Figure 10 shown, the first clock signal CK1 can be a signal obtained by shifting the phase of the second clock signal CK2 by two horizontal periods. In some embodiments, the durations of the first clock signal CK1 and the second clock signal CK2 having a high level can correspond to four horizontal periods of the display panel.

[0130] In some embodiments, as Figure 10 shown, the period during which the start signal STV or the stage transmission signal STn has a low level overlaps with the period during which the first clock signal CK1 has a low level and does not overlap with the period during which the second clock signal CK2 has a low level.

[0131] In some embodiments, in the first period t1, the start signal STV or the stage transmission signal STn has a high level, the first clock signal CK1 has a high level, and the second clock signal CK2 has a low level.

[0132] In some embodiments, in the second period t2, the start signal STV or the stage transmission signal STn has a high level, the first clock signal CK1 has a low level or a high level, and the second clock signal CK2 has a high level.

[0133] In some embodiments, in the third period t3, the start signal STV or the stage transmission signal STn is at a high level, and the first clock signal CK1 and the second clock signal CK2 have a high level or a low level.

[0134] In an exemplary embodiment, as Figure 4 and Figure 10 shown, the operation process of the gate driving unit may include a first period t1, a period t0 before the first period t1, a second period t2 after the first period t1, and a third period t3.

[0135] In the period t0, the first clock signal CK1 has a low level, the second clock signal CK2 has a high level, and the start signal STV has a low level. Thus, the first transistor T1 is turned on and transmits the start signal STV with a low level to the first node M, and the start signal STV is transmitted to the second node Q via the turned-on sixth transistor T6, so that the second node Q has a low level. Since the first node M has a low level, the second transistor T2 is turned on to output a first-level voltage to the third node P, so that the potential of the third node P has a high level. The potential of the third node P has a high level, so that the fifth transistor T5 and the ninth transistor T9 are turned off. Since the second node Q has a low level, the fourth transistor T4 is turned on to output the second clock signal CK2 with a high level as a scan signal to the scan signal output terminal NOUT.

[0136] In the first time period t1, the first clock signal CK1 has a high level, the second clock signal CK2 has a low level, and the start signal STV has a high level. Moreover, after the time period t0, the potentials of the first node M and the second node Q are maintained at a low level, and the potential of the third node P is maintained at a high level. The first transistor T1, the third transistor T3, the fifth transistor T5, and the ninth transistor T9 are turned off, and the fourth transistor T4 is turned on to output the second clock signal CK2 with a low level as a scan signal to the scan signal output terminal NOUT.

[0137] In the second time period t2, the first clock signal CK1 has a high level, the second clock signal CK2 has a high level, and the start signal STV has a high level. Moreover, the potentials of the first node M and the second node Q still remain at a low level, and the potential of the third node P is maintained at a high level. The first transistor T1, the third transistor T3, the fifth transistor T5, and the ninth transistor T9 are turned off, and the fourth transistor T4 is turned on to output the second clock signal CK2 with a high level as a scan signal to the scan signal output terminal NOUT.

[0138] In the third time period t3, the first clock signal CK1 has a low level, the second clock signal CK2 has a high level, and the start signal STV has a high level. The first transistor T1 is turned on to transmit the start signal STV with a high level to the first node M, and the start signal STV is transmitted to the second node Q via the turned-on sixth transistor T6, so that the second node Q has a high level. Since the first node M and the second node Q have a high level, the second transistor T2 and the fourth transistor T4 are turned off, and the third transistor T3 is turned on to output a second-level voltage to the third node P, so that the potential of the third node P is low. Since the third node P has a low level, the ninth transistor T9 is turned off to output a fifth-level voltage to the first node M, so that the potentials of the first node M and the second node Q are maintained at a high level, reducing the risk of the fourth transistor T4 being erroneously turned on due to the coupling of the second clock signal CK2 to the second node Q; moreover, since the third node P has a low level, the fifth transistor T5 is turned on to output the second clock signal CK2 with a high level as a scan signal to the scan signal output terminal NOUT.

[0139] Combining the above content, it can be seen that Figure 10 Applying the Figure 4 and Figure 7 shown timing sequence to the Figure 4 and Figure 7The scan signal output by the shown gate driving unit 201 is matched with the first scan signal Pscan, and can Figure 4 and Figure 7 the shown gate driving unit 201 is used as the fifth gate driving unit.

[0140] In some embodiments, such as Figure 5 、 Figure 6 、 Figures 8 to 9 shown, the gate of the first transistor T1 is configured to receive the third clock signal CK3, the second electrode of the fourth transistor T4 is configured to receive the low-level voltage VGL, and the second electrode of the fifth transistor T5 is configured to receive the high-level voltage VGH.

[0141] Figure 11 Another signal timing diagram of the gate driving unit provided by the embodiment of the present application.

[0142] In some embodiments, such as Figure 11 shown, the working process of at least one gate driving unit includes a fourth period t4 and a fifth period t5.

[0143] In the fourth period t4, the fourth transistor T4 is configured to output a low-level voltage to the scan signal output terminal NOUT in response to the potential of the second node Q, and the fifth transistor T5 is configured to turn off in response to the potential of the third node P. In the fifth period t5, the fourth transistor T4 is configured to turn off in response to the potential of the second node Q, and the fifth transistor T5 is configured to output a high-level voltage to the scan signal output terminal NOUT in response to the potential of the third node P. Thus, in the fourth period t4, the fourth transistor T4 outputs a low-level voltage as the low-level scan signal. In the fifth period t5, the fifth transistor T5 outputs a high-level voltage as the high-level scan signal.

[0144] In some embodiments, such as Figure 11 shown, in the fourth period t4, the potentials of the first node M and the second node Q are at a low level. The second transistor T2 is configured to output a first-level voltage to the third node P in response to the potential of the first node M or the second node Q, and the third transistor T3 is configured to turn off in response to the potential of the first node M or the second node Q. Thus, in the fourth period t4, the first-level voltage output by the second transistor T2 pulls up the potential of the third node P to a high level, causing the fifth transistor T5 to turn off.

[0145] In some embodiments, during the fifth time period t5, the potentials of the first node M and the second node Q are at a high level. The second transistor T2 is configured to turn off in response to the potential of the first node M or the second node Q, and the third transistor T3 is configured to output a second-level voltage to the third node P in response to the potential of the first node M or the second node Q. Thus, during the fifth time period t5, the potential of the third node P is pulled down to a low level by the second-level voltage output by the third transistor T3, causing the fifth transistor T5 to conduct.

[0146] In an exemplary embodiment, as Figure 5 and Figure 11 shown, the operation process of the gate driving unit may include a fourth time period t4 and a fifth time period t5 after the fourth time period t4.

[0147] During the fourth time period t4, the start signal STV starts to have a low level, and the third clock signal CK3 starts to have a low level. The first transistor T1 conducts under the action of the third clock signal CK3 having a low level to output the start signal STV having a low level to the first node M. The start signal STV having a low level is output to the second node Q via the conducting sixth transistor T6. Since the potentials of the first node M and the second node Q are both at a low level, the third transistor T3 turns off, and the second transistor T2 conducts to output a first-level voltage to the third node P to pull up the potential of the third node P to a high level. Since the potential of the second node Q is at a low level, the fourth transistor T4 conducts to output a low-level voltage to the scan signal output terminal NOUT. Since the scan signal output terminal NOUT outputs a low-level scan signal, the eighth transistor T8 conducts to output a fourth-level voltage to the first electrode of the fifth transistor T5 to pull down the potential of the first electrode of the fifth transistor T5, reducing the voltage difference between the voltage of the first electrode of the fifth transistor T5 and the voltage of the scan signal output terminal NOUT, and reducing the risk of leakage of the fifth transistor T5. Also, since the potential of the third node P is at a high level, the fifth transistor T5 and the seventh transistor T7 turn off.

[0148] Then, the level of the start signal STV remains at a low level, the level of the third clock signal CK3 alternates between a low level and a high level, the potentials of the first node M and the second node Q are maintained at a low level, the potential of the third node P is maintained at a high level, and the fourth transistor T4 continuously outputs a low-level voltage to the scan signal output terminal NOUT.

[0149] Finally, the level of the start signal STV changes from a low level to a high level, the level of the third clock signal CK3 is at a high level, the potentials of the first node M and the second node Q are maintained at a low level, the potential of the third node P is maintained at a high level, and the fourth transistor T4 continuously outputs a low-level voltage to the scan signal output terminal NOUT.

[0150] Therefore, in the fourth time period t4, the fourth transistor T4 continuously outputs a low-level voltage as a low-level scan signal to the scan signal output terminal NOUT.

[0151] In the fifth time period t5, the start signal STV has a high level, and the third clock signal CK3 starts to have a low level. The first transistor T1 is turned on under the action of the third clock signal CK3 with a low level to output the start signal STV with a high level to the first node M. The start signal STV with a high level is output to the second node Q via the turned-on sixth transistor T6. Since both the first node M and the second node Q are at a high level, the third transistor T3 is turned on to output a second-level voltage to the third node P to pull down the potential of the third node P to a low level; and, the fourth transistor T4 is turned off, and the fifth transistor T5 is turned on to output a high-level voltage to the scan signal output terminal NOUT.

[0152] Then, the start signal STV still has a high level, the level of the third clock signal CK3 changes from a low level to a high level, and then alternates between a high level and a low level. The potentials of the first node M and the second node Q are maintained at a high level, the potential of the third node P is maintained at a low level, and the fifth transistor T5 continuously outputs a high-level voltage to the scan signal output terminal NOUT.

[0153] Therefore, in the fifth time period t5, the fifth transistor T5 continuously outputs a high-level voltage as a high-level scan signal to the scan signal output terminal NOUT.

[0154] Combining the above, Figure 11 When the shown timing is applied to Figure 5 , Figure 6 , Figures 8 to 9 the gate driving unit 201 shown, the duration of the scan signal with a high level output by the gate driving unit 201 can be less than the duration of the scan signal with a low level output by it. And, combining the foregoing, it can be known that the light emission control signal EM, the second scan signal Nscan1, and the third scan signal Nscan2 are in a low level state for a long time and are in a high level state for a short time. Therefore, Figure 5 , Figure 6 , Figures 8 to 9 the scan signal output by the gate driving unit 201 shown is matched with these control signals, and the gate driving unit 201 shown in Figure 5 , Figure 6 , Figures 8 to 9 can be used as at least one of the first gate driving unit to the third gate driving unit.

[0155] In addition, on the basis of adjusting the duration of the start signal STV or the stage transmission signal STn with a high level, for example, when the duration of the start signal STV or the stage transmission signal STn with a high level becomes longer, it is also possible to Figure 5 , Figure 6 , Figures 8 to 9 The gate driving unit 201 shown as the fifth gate driving unit.

[0156] The description of the above embodiments is only used to help understand the technical solution and its core idea of the present application; those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A gate driving circuit, characterized in that, including a plurality of gate driving units, at least one of the gate driving units comprising: a first transistor, a first electrode of the first transistor being connected to a first node, and a second electrode of the first transistor being configured to receive a start signal or a stage transfer signal; a second transistor, a gate of the second transistor being connected to the first node or a second node, a first electrode of the second transistor being configured to receive a first-level voltage, and a second electrode of the second transistor being connected to a third node; a third transistor, a gate of the third transistor being connected to the first node or the second node, a first electrode of the third transistor being connected to the third node, and a second electrode of the third transistor being configured to receive a second-level voltage; the second-level voltage being different from the first-level voltage, and a type of a channel region of the third transistor being different from a type of a channel region of the second transistor; a fourth transistor, a gate of the fourth transistor being connected to the second node, and a first electrode of the fourth transistor being connected to a scan signal output terminal; a capacitor, one plate of the capacitor being connected to the scan signal output terminal, and another plate of the capacitor being connected to the second node; a fifth transistor, a gate of the fifth transistor being connected to the third node, and a first electrode of the fifth transistor being connected to the scan signal output terminal; and a sixth transistor, a first electrode of the sixth transistor being connected to the first node, a second electrode of the sixth transistor being connected to the second node, and a gate of the sixth transistor being configured to receive a third-level voltage to be in an on state.

2. The gate driving circuit according to claim 1, wherein The gate of the second transistor and the gate of the third transistor are connected to the first electrode of the sixth transistor and the first node.

3. The gate driving circuit according to claim 1, wherein The gate of one of the second transistor and the third transistor is connected to the first electrode of the sixth transistor and the first node, and the gate of the other of the second transistor and the third transistor is connected to the second electrode of the sixth transistor and the second node.

4. The gate driving circuit according to claim 1, wherein The gate of the second transistor and the gate of the third transistor are connected to the second electrode of the sixth transistor and the second node.

5. The gate driving circuit according to any one of claims 1 to 4, characterized in that The gate of the first transistor is configured to receive a first clock signal, the second electrode of the fourth transistor is configured to receive a second clock signal, the second electrode of the fifth transistor is configured to receive a high-level voltage, and the first clock signal is different from the second clock signal.

6. The gate driving circuit according to claim 5, wherein An operating period of at least one of the gate driving units includes a first period, a second period, and a third period; In the first period, the fourth transistor is configured to output the second clock signal having a low level to the scan signal output terminal in response to a potential of the second node, and the fifth transistor is configured to be in an off state in response to a potential of the third node; In the second period, the fourth transistor is configured to output the second clock signal with a high level to the scan signal output terminal in response to the potential of the second node, and the fifth transistor is configured to be in an off state in response to the potential of the third node; In the third period, the fourth transistor is configured to be in an off state in response to the potential of the second node, and the fifth transistor is configured to output the high-level voltage to the scan signal output terminal in response to the potential of the third node.

7. The gate driving circuit according to claim 6, wherein In the first period and the second period, the second transistor is configured to output the first-level voltage to the third node in response to the potential of the first node or the second node, and the third transistor is configured to be turned off in response to the potential of the first node or the second node; In the third period, the second transistor is configured to be turned off in response to the potential of the first node or the second node, and the third transistor is configured to output the second-level voltage to the third node in response to the potential of the first node or the second node.

8. The gate driving circuit according to claim 6, wherein In the first period, the start signal or the stage transfer signal has a high level, the first clock signal has a high level, and the second clock signal has a low level; In the second period, the start signal or the stage transfer signal has a high level, the first clock signal has a low level or a high level, and the second clock signal has a high level; In the third period, the start signal or the stage transfer signal is at a high level, and the first clock signal and the second clock signal have a high level or a low level.

9. The gate driving circuit according to any one of claims 1 to 4, characterized in that, The gate of the first transistor is configured to receive the third clock signal, the second electrode of the fourth transistor is configured to receive a low-level voltage, and the second electrode of the fifth transistor is configured to receive a high-level voltage.

10. The gate driving circuit according to claim 9, wherein The operation process of at least one of the gate driving units includes a fourth period and a fifth period; In the fourth period, the fourth transistor is configured to output the low-level voltage to the scan signal output terminal in response to the potential of the second node, and the fifth transistor is configured to be in an off state in response to the potential of the third node; In the fifth period, the fourth transistor is configured to be in an off state in response to the potential of the second node, and the fifth transistor is configured to output the high-level voltage to the scan signal output terminal in response to the potential of the third node.

11. The gate driving circuit according to claim 10, wherein In the fourth period, the second transistor is configured to output the first-level voltage to the third node in response to the potential of the first node or the second node, and the third transistor is configured to be turned off in response to the potential of the first node or the second node; In the fifth period, the second transistor is configured to be turned off in response to the potential of the first node or the second node, and the third transistor is configured to output the second-level voltage to the third node in response to the potential of the first node or the second node.

12. The gate driving circuit according to claim 10, wherein, In the fourth period, the start signal or the stage transfer signal has a high level or a low level; In the fifth time period, the start signal or the stage transmission signal has a high level.

13. The gate driving circuit according to any one of claims 1 to 4, characterized in that Further included are: A seventh transistor, the gate of the seventh transistor is connected to the third node, and the first electrode and the second electrode of the seventh transistor are connected between the scan signal output terminal and the first electrode of the fifth transistor.

14. The gate driving circuit according to claim 13, wherein Further included are: An eighth transistor, the gate of the eighth transistor is connected to the scan signal output terminal, the first electrode of the eighth transistor is connected to the first electrode of the fifth transistor, and the second electrode of the eighth transistor is configured to receive a fourth-level voltage.

15. The gate driving circuit according to any one of claims 1 to 4, characterized in that, Further included are: A ninth transistor, the gate of the ninth transistor is connected to the third node, the first electrode of the ninth transistor is configured to receive a fifth-level voltage, and the second electrode of the ninth transistor is connected to the first electrode or the second electrode of the sixth transistor.

16. The gate driving circuit according to claim 15, wherein The second electrode of the ninth transistor is connected to the first electrode of the sixth transistor.

17. The gate driving circuit according to any one of claims 1 to 4, characterized in that, The gate of the third transistor includes a top gate and a bottom gate, and the channel region of the third transistor is located between the top gate and the bottom gate.

18. The gate driving circuit according to any one of claims 1 to 4, characterized in that, The first transistor, the second transistor, the fourth transistor, the fifth transistor, and the sixth transistor include low-temperature polysilicon active layers, and the third transistor includes a metal oxide active layer.

19. The gate driving circuit according to any one of claims 1 to 4, characterized in that, The first transistor, the second transistor, the fourth transistor, the fifth transistor, and the sixth transistor are P-type transistors, and the third transistor is an N-type transistor.

20. A display panel, characterized in that, The display panel includes the gate driving circuit according to any one of claims 1 to 19 and a plurality of pixel driving circuits. One pixel driving circuit includes a plurality of transistors, and the gate of at least one of the transistors of the pixel driving circuit is connected to the scan signal output terminal.

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