Display device
Through the gate driver sub-circuit with 7T1C structure, the first node potential is forced to be lowered by the seventh transistor, which solves the abnormal problem caused by signal delay in the traditional gate driver circuit, reduces power consumption and improves fault tolerance, and ensures normal signal transmission and circuit stability.
Patent Information
- Application Number
- CN202510465744.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-14
- Publication Date
- 2025-07-04
AI Technical Summary
When the traditional gate driving circuit drives a display area with a large load, the output gate driving signal has a delay, resulting in abnormal signals, affecting the normal operation of the subsequent gate driving sub-circuit.
The gate driver sub-circuit adopts a 7T1C structure, through the seventh transistor, the potential of the first node is forced to lower the signal when the start signal is delayed, ensuring normal signal transmission, and the fault tolerance ability of reducing power consumption and improving threshold voltage drift is designed through the combination of capacitors and transistors.
It effectively solves the stage-transfer failure problem caused by the delay of the start signal, reduces circuit power consumption, and improves the fault tolerance of transistor threshold voltage drift, ensuring the normal output of the gate driving signal and the stability of the circuit.
Smart Images
Figure CN120260465A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of display technologies, and particularly relates to a display device. Background Art
[0002] When the gate driving sub-circuit of a traditional gate driver circuit (Gate-driver On Array, GOA) drives pixels in a display area (Active Area, AA) with a large load, the output gate driving signal will have a relatively large delay. If this gate driving signal is used as the input of the start signal of a subsequent (for example, the next-level) gate driving sub-circuit, and the delay of the gate driving signal output by this gate driving signal exceeds a predetermined time, the delayed signal (abnormal signal) will be transmitted to the subsequent gate driving sub-circuit, ultimately causing the gate driving signal output at the output end of the gate driving signal to be abnormal.
[0003] Therefore, it is necessary to propose a new technical solution to solve the above technical problems. Summary of the Invention
[0004] The objective of the embodiments of the present application is to provide a display device, aiming to solve the problem that the gate driving signal output by the gate driver circuit is abnormal.
[0005] Embodiments of the present application provide a display device. The display device includes a gate driving circuit, and the gate driving circuit includes a plurality of cascaded gate driving sub - circuits. The gate driving sub - circuit includes: a first transistor, the gate of the first transistor is electrically connected to the clock signal input terminal of the gate driving sub - circuit, the source is electrically connected to the start signal input terminal of the gate driving sub - circuit, and the drain is electrically connected to the first node of the gate driving sub - circuit; a second transistor, the gate of the second transistor is electrically connected to the first node, the source is electrically connected to the high - potential signal input terminal of the gate driving sub - circuit, and the drain is electrically connected to the second node of the gate driving sub - circuit; a third transistor, the gate of the third transistor is electrically connected to the first node, the source is electrically connected to the low - potential signal input terminal of the gate driving sub - circuit, and the drain is electrically connected to the second node; a fifth transistor, the gate of the fifth transistor is electrically connected to the third node of the gate driving sub - circuit, the source is electrically connected to the low - potential signal input terminal, and the drain is electrically connected to the gate driving signal output terminal of the gate driving sub - circuit; a sixth transistor, the gate of the sixth transistor is electrically connected to the second node, the source is electrically connected to the high - potential signal input terminal, and the drain is electrically connected to the gate driving signal output terminal; and a seventh transistor, the gate of the seventh transistor is electrically connected to the second node, the source is electrically connected to the low - potential signal input terminal, and the drain is electrically connected to the first node. The seventh transistor is configured to pull down the potential of the first node when the start signal at the start signal input terminal switches from high potential to low potential and the first transistor is turned on.
[0006] In the above - mentioned display device, the gate driving sub - circuit further includes: a fourth transistor, the gate of the fourth transistor is electrically connected to the low - potential signal input terminal, the source is electrically connected to the first node, and the drain is electrically connected to the third node; and a capacitor, one plate of the capacitor is electrically connected to the third node, and the other plate of the capacitor is electrically connected to the gate driving signal output terminal.
[0007] In the above - mentioned display device, the third transistor and the seventh transistor are both N - type transistors, and the first transistor, the second transistor, the fourth transistor, the fifth transistor, and the sixth transistor are all P - type transistors.
[0008] In the above - mentioned display device, when the first node is at a low potential, the second transistor is turned on, the third transistor is turned off, and the second node is at a high potential; when the first node is at a high potential, the second transistor is turned off, the third transistor is turned on, and the second node is at a low potential.
[0009] In the above display device, the third transistor includes two gates, one of which is electrically connected to the first node, and the other is electrically connected to the source of the third transistor; the seventh transistor includes two gates, one of which is electrically connected to the second node, and the other is electrically connected to the source of the seventh transistor.
[0010] In the above display device, the gate driving sub-circuit further includes: an eighth transistor, the gate of which is electrically connected to the second node, the source is electrically connected to the drain of the sixth transistor, and the drain is electrically connected to the gate driving signal output terminal; and a ninth transistor, the gate of which is electrically connected to the gate driving signal output terminal, the source is electrically connected to the low potential signal input terminal, and the drain is electrically connected to the source of the eighth transistor.
[0011] In the above display device, both the eighth transistor and the ninth transistor are P-type transistors.
[0012] In the above display device, during the process of the start signal switching from a high potential to a low potential, when the clock signal at the clock signal input terminal is at a high potential, the potential of the second node P is at a low potential, the first transistor is turned off, and the seventh transistor is turned off; when the clock signal at the clock signal input terminal is at a low potential, the potential of the second node P is at a high potential, the first transistor is turned on, and the seventh transistor is turned on.
[0013] An embodiment of the present application further provides a display device. The display device includes a gate driving circuit. The gate driving circuit includes a plurality of cascaded gate driving sub - circuits. The gate driving sub - circuit includes: a first transistor, the gate of the first transistor is electrically connected to the clock signal input terminal of the gate driving sub - circuit, the source is electrically connected to the start signal input terminal of the gate driving sub - circuit, and the drain is electrically connected to the first node of the gate driving sub - circuit; a second transistor, the gate of the second transistor is electrically connected to the third node of the gate driving sub - circuit, the source is electrically connected to the high - potential signal input terminal of the gate driving sub - circuit, and the drain is electrically connected to the second node of the gate driving sub - circuit; a third transistor, the gate of the third transistor is electrically connected to the first node, the source is electrically connected to the low - potential signal input terminal of the gate driving sub - circuit, and the drain is electrically connected to the second node; a fourth transistor, the gate of the fourth transistor is electrically connected to the low - potential signal input terminal, the source is electrically connected to the first node, and the drain is electrically connected to the third node; a fifth transistor, the gate of the fifth transistor is electrically connected to the third node, the source is electrically connected to the low - potential signal input terminal, and the drain is electrically connected to the gate driving signal output terminal of the gate driving sub - circuit; and a sixth transistor, the gate of the sixth transistor is electrically connected to the second node, the source is electrically connected to the high - potential signal input terminal, and the drain is electrically connected to the gate driving signal output terminal.
[0014] In the above - mentioned display device, the gate driving sub - circuit further includes: a seventh transistor, the gate of the seventh transistor is electrically connected to the second node, the source is electrically connected to the low - potential signal input terminal, and the drain is electrically connected to the first node. The seventh transistor is configured to pull down the potential of the first node when the start signal at the start signal input terminal switches from high potential to low potential and there is a delay; and a capacitor, one plate of the capacitor is electrically connected to the third node, and the other plate of the capacitor is electrically connected to the gate driving signal output terminal.
[0015] In the above - mentioned display device, the seventh transistor includes two gates. One gate of the seventh transistor is electrically connected to the second node, and the other gate is electrically connected to the source of the seventh transistor.
[0016] In the above - mentioned display device, during the process of the start signal switching from high potential to low potential, when the clock signal at the clock signal input terminal is at high potential, the potential of the second node P is at low potential, the first transistor is turned off, and the seventh transistor is turned off. When the clock signal at the clock signal input terminal is at low potential, the potential of the second node P is at high potential, the first transistor is turned on, and the seventh transistor is turned on.
[0017] In the above display device, the first transistor, the second transistor, the fourth transistor, the fifth transistor, and the sixth transistor are all P-type transistors, and the third transistor and the seventh transistor are both N-type transistors.
[0018] In the above display device, when the third node is at a low potential and the first node is also at a low potential, the second node is at a high potential; when the third node is at a high potential or the first node is at a high potential, the second node is at a low potential.
[0019] In the above display device, the third transistor includes two gates. One gate of the third transistor is electrically connected to the first node, and the other gate is electrically connected to the source of the third transistor.
[0020] In the above display device, the gate driving sub-circuit further includes: an eighth transistor, whose gate is electrically connected to the second node, source is electrically connected to the drain of the sixth transistor, and drain is electrically connected to the gate driving signal output terminal; and a ninth transistor, whose gate is electrically connected to the gate driving signal output terminal, source is electrically connected to the low-potential signal input terminal, and drain is electrically connected to the source of the eighth transistor.
[0021] In the above display device, the eighth transistor and the ninth transistor are both P-type transistors.
[0022] In the display device of the present application, since the gate of the seventh transistor is electrically connected to the second node, the source is electrically connected to the low-potential signal input terminal, and the drain is electrically connected to the first node, and the seventh transistor is configured to pull down the potential of the first node when the signal at the start signal input terminal switches from a high potential to a low potential and the first transistor is turned on, it can effectively solve the problem of stage transmission failure caused by the delay of the start signal in the traditional gate driving sub-circuit. Specifically, during the process of the start signal switching from a high potential to a low potential, if there is a delay, the traditional circuit cannot pull down the first node in time, resulting in abnormal subsequent signal transmission. However, in the present application, the seventh transistor forcibly pulls down the first node to a low potential, ensuring that even when there is a delay in the start signal, the first node can be correctly pulled down, thus guaranteeing the normal output of the gate driving signal.
[0023] In addition, when the clock signal is set high, the potential of the first node may be higher than the expected low-potential signal level. This abnormal potential can cause the N-type third transistor to conduct partially, generating a direct current from the high potential to the low potential. This will not only interfere with the normal potential of the second node, resulting in abnormal waveforms, but also significantly increase the static power consumption of the circuit. In this application, the potential of the first node is forced to be pulled down to the standard low potential by the seventh transistor, effectively solving this problem and greatly reducing the circuit power consumption. Experimental data shows that the gate driving sub-circuit in the display device of this application can reduce the leakage current of the third transistor from about 300 nA to about 10 pA, significantly reducing the leakage current.
[0024] In addition, the display device of this application improves the fault tolerance ability against the threshold voltage drift of the transistor. Through experimental verification, when the threshold voltage of the low-temperature polysilicon transistor in the 7T1C structure gate driving sub-circuit of this application drifts negatively by 1.5 V, the gate driving signal output at the output terminal of the gate driving signal is still normal. This is because the seventh transistor can write the low-potential signal into the first node, forcing the delay signal transmitted by the start signal to be pulled to the low potential, eliminating the delay signal and ensuring that the delay signal stage will not be transmitted. Description of the Drawings
[0025] Figure 1 is a waveform diagram of the gate driving signals output by the first 5-stage gate driving sub-circuit of a traditional display device.
[0026] Figure 2 is a schematic diagram of the display device provided by the embodiment of this application.
[0027] Figure 3 is a schematic diagram of the gate driving circuit in the display device provided by the embodiment of this application.
[0028] Figure 4 is a circuit diagram of the first embodiment of the i-th stage gate driving sub-circuit in the display device provided by this application.
[0029] Figure 5 is a waveform diagram of the gate driving signals output by the first 5-stage gate driving sub-circuit of the display device after applying the technical solution of the first embodiment of this application.
[0030] Figure 6 is a waveform diagram of the signals in the i-th stage gate driving sub-circuit of the display device after applying the technical solution of the first embodiment of this application.
[0031] Figure 7 is a waveform diagram of the gate driving signals output by the first 5-stage gate driving sub-circuit of the display device after applying the technical solution of the first embodiment of this application.
[0032] Figure 8It is a circuit diagram of the second embodiment of the i-th stage gate driving sub-circuit in the display device provided by the present application.
[0033] Figure 9 It is a circuit diagram of the third embodiment of the i-th stage gate driving sub-circuit in the display device provided by the present application.
[0034] Figure 10 It is a waveform diagram of signals in the i-th stage gate driving sub-circuit of the display device after applying the technical solution of the third embodiment of the present application.
[0035] Figure 11 It is a circuit diagram of the fourth embodiment of the i-th stage gate driving sub-circuit in the display device provided by the present application. Detailed implementation manners
[0036] The following will describe the detailed implementation manners of the present application with reference to the accompanying drawings.
[0037] Terms such as "first", "second" and similar words do not denote any order, quantity or importance, but are only used to distinguish different technical features. The term "plurality" and similar words mean two or more, unless otherwise clearly defined.
[0038] The embodiments of the present application can be combined with each other.
[0039] The display device provided by the embodiments of the present application can be, for example, an OLED display device, a Mini-LED display device, a Micro-LED display device. The embodiments of the present application will be described by taking the OLED display device as an example.
[0040] As Figure 2 and Figure 3 shown, the display device provided by the embodiments of the present application includes a display panel. The display panel includes a gate driving circuit and a plurality of pixels PX. The gate driving circuit includes multiple cascaded gate driving sub-circuits, and one stage of the gate driving sub-circuit is electrically connected to one row of pixels PX.
[0041] The display panel includes a display area and a non-display area. The display area is provided with a plurality of pixels PX arranged in an array, and the non-display area is located around the display area. The display panel further includes a plurality of scan lines SCAN, a plurality of data lines DATA, a plurality of emission control signal lines EM, an emission controller, and a gate driver circuit. The plurality of scan lines SCAN and the plurality of emission control signal lines EM extend in a first direction and are arranged in a second direction, the plurality of data lines DATA extend in the second direction and are arranged in the first direction, and the first direction is perpendicular to the second direction. The gate driver circuit is provided in the non-display area and is electrically connected to the plurality of scan lines SCAN. The source driver circuit is electrically connected to the plurality of data lines DATA through a flexible circuit board. The timing controller is electrically connected to the gate driver circuit and the source driver circuit.
[0042] The display panel includes an organic light-emitting diode array substrate and a packaging layer. The organic light-emitting diode array substrate includes a substrate, a buffer layer provided on the substrate, an active layer provided on the buffer layer, a gate insulating layer provided on the active layer, a first metal layer provided on the gate insulating layer, an interlayer insulating layer provided on the first metal layer, a second metal layer provided on the interlayer insulating layer, a planarization layer provided on the second metal layer, a first electrode layer provided on the planarization layer, a pixel defining layer provided on the first electrode layer, an organic light-emitting layer provided in the opening area defined by the pixel defining layer, and a second electrode layer provided on the organic light-emitting layer. The first metal layer includes the scan line SCAN and the gate electrode. The second metal layer includes the data line DATA, the source electrode, and the drain electrode. The packaging layer is hermetically connected to the organic light-emitting diode array substrate.
[0043] Each pixel PX includes a pixel driving circuit and a light-emitting device. The pixel driving circuit includes at least two transistors and a storage capacitor. One of the transistors serves as a switching transistor, whose gate is electrically connected to the corresponding scan line SCAN and whose source is electrically connected to the corresponding data line DATA; the other transistor serves as a driving transistor, whose gate is electrically connected to the drain of the switching transistor, whose source is electrically connected to the first power supply voltage line, and whose drain is electrically connected to the anode of the light-emitting device. One end of the storage capacitor is electrically connected to the gate of the driving transistor, and the other end is electrically connected to the source or drain of the driving transistor. The cathode of the light-emitting device is electrically connected to the second power supply voltage line.
[0044] Each stage of the gate driving sub - circuit in the gate driving circuit is electrically connected to a scan line SCAN. Under the control of the timing controller, the gate driving sub - circuit sequentially outputs scan signals to scan each row of pixels PX in the display area row by row. The source driving circuit generates and outputs data signals according to the image data under the control of the timing controller. The timing controller is used to receive and process externally input image data and timing signals, generate control signals, and transmit the image data to the source driving circuit. The power management chip is used to provide operating voltages for various parts of the display device, including providing a second power voltage for the cathode of the light - emitting device, providing a first power voltage for the first power voltage line, providing a gate driving voltage for the gate driving circuit, etc.
[0045] In a traditional gate driving sub - circuit, when the signal output from the gate driving signal output terminal has a large delay, due to the signal transmission of the shift register delay stage of the transistor and the clock signal input terminal CK, the potential of a specific node in the gate driving sub - circuit cannot be switched normally, and finally the gate driving signal output from the gate driving signal output terminal Nout_i is abnormal.
[0046] In an embodiment of the present application, the i - th stage gate driving sub - circuit in the multi - stage cascaded gate driving sub - circuit adopts a 7T1C structure, as Figure 4 shown. The i - th stage gate driving sub - circuit includes a first transistor T1_i, a second transistor T2_i, a third transistor T3_i, a fourth transistor T4_i, a fifth transistor T5_i, a sixth transistor T6_i, a seventh transistor T7_i, and a capacitor C1_i.
[0047] The gate of the first transistor T1_i is electrically connected to the clock signal input terminal CK of the gate driver circuit, the source is electrically connected to the start signal input terminal STV of the gate driver circuit, and the drain is electrically connected to the first node M_i of the gate driver circuit. The first node M_i is the node of the line between the first transistor T1_i and the fourth transistor T4_i, the node of the line between the first transistor T1_i and the third transistor T3_i, and the node of the line between the first transistor T1_i and the second transistor T2_i. The gate of the second transistor T2_i is electrically connected to the first node M_i, the source is electrically connected to the high potential signal input terminal VGH of the gate driver circuit, and the drain is electrically connected to the second node P_i of the gate driver circuit. The second node P_i is the node of the line between the second transistor T2_i and the sixth transistor T6_i, and the node of the line between the second transistor T2_i and the third transistor T3_i. The gate of the third transistor T3_i is electrically connected to the first node M_i, the source is electrically connected to the low potential signal input terminal VGL of the gate driver circuit, and the drain is electrically connected to the second node P_i. The gate of the fourth transistor T4_i is electrically connected to the low potential signal input terminal VGL, the source is electrically connected to the first node M_i, and the drain is electrically connected to the third node Q_i of the gate driver circuit. The third node Q_i is the node of the line between the fourth transistor T4_i and the fifth transistor T5_i, and the node of the line between the fourth transistor T4_i and the capacitor C1_i. The gate of the fifth transistor T5_i is electrically connected to the third node Q_i, the source is electrically connected to the low potential signal input terminal VGL, and the drain is electrically connected to the gate drive signal output terminal Nout_i of the gate driver circuit. The gate of the sixth transistor T6_i is electrically connected to the second node P_i, the source is electrically connected to the high potential signal input terminal VGH, and the drain is electrically connected to the gate drive signal output terminal Nout_i. One plate of the capacitor C1_i is electrically connected to the third node Q_i, and the other plate is electrically connected to the gate drive signal output terminal Nout_i. The gate of the seventh transistor T7_i is electrically connected to the second node P_i, the source is electrically connected to the low potential signal input terminal VGL, and the drain is electrically connected to the first node M_i.
[0048] The seventh transistor T7_i is configured to pull down the potential of the first node M_i when the signal at the start signal input terminal STV switches from a high potential to a low potential and the first transistor T1_i is turned on.
[0049] The first transistor T1_i, the second transistor T2_i, the fourth transistor T4_i, the fifth transistor T5_i, and the sixth transistor T6_i are all P-type transistors, and the first transistor T1_i, the second transistor T2_i, the fourth transistor T4_i, the fifth transistor T5_i, and the sixth transistor T6_i are all low-temperature polysilicon transistors.
[0050] In an embodiment of the present application, the seventh transistor T7_i is configured to pull down the potential of the first node M_i when the signal at the start signal input terminal STV switches from a high potential to a low potential and the clock signal transmitted at the clock signal input terminal CK is at a low potential. This setting ensures that even if there is a delay in the action of the start signal switching from a high potential to a low potential, the first node M_i can be correctly pulled down, solving the problem of abnormal gate drive signals caused by stage transmission failure in the gate drive sub-circuit.
[0051] During the process of the start signal switching from a high potential to a low potential, after a preset time (for example, 2H, where H is the unit time), the clock signal will turn on the first transistor T1_i so that the first transistor T1_i transmits the start signal. However, when the first transistor T1_i is turned on, the start signal has not completely switched from a high potential to a low potential (there is a delay in the high and low potential switching of the start signal), so there will be a phenomenon of stage transmission delay, ultimately leading to stage transmission failure. Therefore, it is necessary to complete the switching of the start signal from a high potential to a low potential when the clock signal turns on the first transistor T1_i, so that the delay of the gate drive signal output at the gate drive signal output terminal Nout_i is less than the preset time. The gate drive sub-circuit with a 7T1C structure in the present application pulls down the potential of the first node M_i to a potential (for example, -7.9V, close to the potential of the low-level signal output terminal VGL of -8.0V, and the absolute value of the difference between the potential of the seventh transistor T7_i after the potential is pulled down by the seventh transistor T7_i and the potential of the low-level signal output terminal VGL is less than or equal to 5% of the potential of the low-level signal output terminal VGL), ensuring normal stage transmission output, as Figure 6 shown.
[0052] During the process of the start signal switching from a high potential to a low potential (within the preset time), when the clock signal at the clock signal input terminal CK is at a high potential, the potential of the second node P_i is at a low potential, the first transistor T1_i is turned off, and the seventh transistor T7_i is turned off. When the clock signal at the clock signal input terminal CK is at a low potential, the potential of the second node P_i is at a high potential, the first transistor T1_i is turned on, transmitting the start signal to the first node M_i, and the seventh transistor T7_i is turned on, transmitting a low-potential signal to the first node M_i.
[0053] Through experiments, it is verified in the embodiment of the present application that when the threshold voltage of the low-temperature polysilicon transistor in the gate drive sub-circuit with a 7T1C structure drifts negatively by 1.5V, the gate drive signal output at the gate drive signal output terminal Nout_i is still normal. This is because the seventh transistor T7_i can write a low-potential signal into the first node M_i, forcibly pulling the delayed signal transmitted by the start signal to a low potential, eliminating the delayed signal, and ensuring that the delayed signal will not be stage-transmitted.
[0054] As Figure 1 shown, under the condition that the threshold voltages Vth of the first transistor T1_i and the fifth transistor T5_i have different negative drifts (for example, 0V, -0.5V, -1V, -1.5V, -2V), the first 5-stage gate driving sub-circuit in the conventional display device is tested. It can be seen that there are significant abnormalities in the gate driving signals output by the first 5-stage gate driving sub-circuit.
[0055] As Figure 5 shown, under the same condition (the threshold voltages Vth of the first transistor T1_i and the fifth transistor T5_i have different negative drifts (for example, 0V, -0.5V, -1V, -1.5V, -2V)), the waveform of the gate driving signal output by the first 5-stage gate driving sub-circuit of the display device after applying the technical solution of the first embodiment of the present application is Figure 1 significantly improved compared with the conventional technical solution shown. In particular, even when the threshold voltages Vth of the first transistor T1_i and the fifth transistor T5_i have a negative drift of 1.5V, the gate driving signal output by the gate driving signal output terminal Nout_i in the display device provided by the present application is still normal.
[0056] The third transistor T3_i and the seventh transistor T7_i are both N-type transistors, and the third transistor T3_i and the seventh transistor T7_i are both indium gallium zinc oxide transistors.
[0057] The second transistor T2_i and the third transistor T3_i form an inverter. When the first node M_i is at a low potential, the second transistor T2_i is turned on while the third transistor T3_i is turned off, and the second node P_i is at a high potential; when the first node M_i is at a high potential, the second transistor T2_i is turned off while the third transistor T3_i is turned on, and the second node P_i is at a low potential.
[0058] In the gate driving sub - circuit of the above - mentioned 7T1C structure, the second node \(P_i\) controls the turning on and off of the seventh transistor \(T7_i\). The source of the seventh transistor \(T7_i\) is electrically connected to the low - potential signal input terminal \(VGL\), and the drain is electrically connected to the first node \(M_i\). Since the second node \(P_i\) is in a high - potential signal state for a long time, the seventh transistor \(T7_i\) is subjected to PBTS (Positive Bias Temperature Stress), resulting in a positive shift of the threshold voltage of the seventh transistor \(T7_i\), and the reset effect on the first node \(M_i\) becomes weaker. Considering stability factors, in this application, the seventh transistor \(T7_i\) and the third transistor \(T3_i\) are designed with a structure where the bottom gate is electrically connected to the source, that is, both transistors include two gates, one gate is electrically connected to the control node, and the other gate is electrically connected to the source. This can improve the stability of the gate driving sub - circuit.
[0059] Specifically, the third transistor \(T3_i\) includes two gates, one of which is electrically connected to the first node \(M_i\), and the other gate is electrically connected to the source of the third transistor \(T3_i\); the seventh transistor \(T7_i\) includes two gates, one of which is electrically connected to the second node \(P_i\), and the other gate is electrically connected to the source of the seventh transistor \(T7_i\).
[0060] In addition, since the fourth transistor \(T4_i\) shields the ultra - low potential of the third node \(Q_i\) (the charge of the third node \(Q_i\) does not flow to the first node \(M_i\) through the fourth transistor \(T4_i\)), the low potential of the first node \(M_i\) comes from the process of the start signal switching from high potential to low potential. This will cause the phenomenon that the gate - source voltage of the third transistor \(T3_i\) is greater than zero, and then lead to continuous leakage current of the third transistor \(T3_i\). The magnitude of the leakage current \(I(T3_i)\) is about 300 nA, as Figure 7 shown. In the gate driving sub - circuit of the 7T1C structure of this application, by pulling down the potential of the first node \(M_i\) through the seventh transistor \(T7_i\), the leakage current \(I(T3_i)\) of the third transistor \(T3_i\) can be reduced to about 10 pA, as Figure 6 shown, greatly reducing the leakage current and achieving the purpose of power consumption saving.
[0061] The gate driving sub - circuit of the 7T1C structure of this application also solves another important problem: as Figure 7As shown, when the clock signal is set high, the potential of the first node M_i (e.g., -6V) may be higher than the potential of the expected low-potential signal (e.g., -10.8V). This abnormal potential will not only affect the circuit performance but also cause the first transistor T1_i to bear an uneven gate-source voltage for a long time, accelerating the negative drift of its threshold voltage. When the potential of the first node M_i is higher than the potential of the low-potential signal VGL, it will cause the N-type third transistor T3_i to conduct partially, generating a shoot-through current from the drain (high potential) to the source (low potential) in the third transistor T3_i. This situation has two serious consequences: First, the shoot-through current will interfere with the normal potential of the second node P_i, resulting in abnormal waveforms and preventing the high-potential signal from being output normally; Second, the continuous shoot-through current between the high and low potentials will significantly increase the static power consumption of the circuit. The gate drive sub-circuit of the 7T1C structure in this application effectively solves these problems by forcing the potential of the first node M_i to the standard low potential through the seventh transistor T7_i.
[0062] It should be noted that for the P-type transistor (such as the first transistor T1_i) in this application, if its gate is electrically connected to the low-potential signal input terminal VGL and its source is also electrically connected to the low-potential signal input terminal VGL, then due to the conduction characteristics of the P-type transistor, the voltage of its drain will be equal to the voltage of the low-potential signal input terminal VGL plus the absolute value of the threshold voltage of this transistor. For example, when the low-potential signal is -10.8V and the threshold voltage of the P-type transistor is -2V, the drain voltage is approximately -8.8V, which is higher than the low-potential signal. This situation will cause the potential of the first node M_i to be abnormal, thereby causing partial conduction of the third transistor T3_i and power consumption problems. This application solves this problem by forcing the first node M_i to the standard low potential through the seventh transistor T7_i.
[0063] In another embodiment of this application, a display device is provided. The i-th stage gate drive sub-circuit of the display device further includes an eighth transistor T8_i and a ninth transistor T9_i, forming a 9T1C structure, as Figure 8 shown.
[0064] The gate of the eighth transistor T8_i is electrically connected to the second node P_i, the source is electrically connected to the drain of the sixth transistor T6_i, and the drain is electrically connected to the gate drive signal output terminal Nout_i. The drain of the sixth transistor T6_i is no longer electrically connected to the gate drive signal output terminal Nout_i. The gate of the ninth transistor T9_i is electrically connected to the gate drive signal output terminal Nout_i, the source is electrically connected to the low-potential signal input terminal VGL, and the drain is electrically connected to the source of the eighth transistor T8_i.
[0065] The eighth transistor T8_i and the ninth transistor T9_i are both P-type transistors. The eighth transistor T8_i and the ninth transistor T9_i are low-temperature polysilicon transistors.
[0066] By adding the eighth transistor T8_i and the ninth transistor T9_i, the output control of the gate driving signal can be optimized, and the response characteristics of the gate driving signal can be improved. Specifically, when the second node P_i is at a low potential, both the sixth transistor T6_i and the eighth transistor T8_i are turned on, forming a series conduction path from the high-potential signal input terminal VGH to the gate driving signal output terminal Nout_i, and a high-potential signal is output. This series structure increases the control accuracy of the output link and can control the signal timing characteristics more precisely than a single-transistor structure. When the potential of the gate driving signal output terminal Nout_i is relatively low (close to the low potential), the P-type ninth transistor T9_i is turned on because the gate-source voltage difference exceeds the threshold voltage, and the low-potential signal VGL is output to the source of the eighth transistor T8_i, so that the potential of the source of the eighth transistor T8_i can be dynamically adjusted, thereby affecting the voltage characteristics of the high-potential signal transmitted from the sixth transistor T6_i through the eighth transistor T8_i to the gate driving signal output terminal Nout_i, which helps to optimize the signal transmission characteristics during the output state transition.
[0067] As the potential of the gate driving signal output terminal Nout_i gradually rises to a high potential, the gate-source voltage difference of the ninth transistor T9_i decreases, the conduction ability decreases and finally turns off, cutting off the connection path between the source of the eighth transistor T8_i and the low-potential signal input terminal VGL, so that the gate driving sub-circuit can automatically adjust the internal electrical characteristics according to the change of the potential of the output gate driving signal, avoiding potential interference between high and low potentials and unexpected current reflux, and thus being able to more precisely control the rising and falling timings of the output signal, realize the dynamic adjustment of the output impedance, reduce the timing deviation and voltage drop during the charging process of the load capacitance of the large-area display panel, ensure the integrity of the high-potential signal amplitude and the stability of signal conversion, and are suitable for the precise driving requirements of large-size or high-resolution display panels.
[0068] In another embodiment of the present application, a display device is provided. The display device includes a gate driving sub-circuit with another 7T1C structure, as Figure 9 shown. The i-th stage gate driving sub-circuit includes: a first transistor T1_i, a second transistor T2_i, a third transistor T3_i, a fourth transistor T4_i, a fifth transistor T5_i, a sixth transistor T6_i, a seventh transistor T7_i, and a capacitor C1_i.
[0069] The gate of the first transistor T1_i is electrically connected to the clock signal input terminal CK of the gate driver circuit, the source is electrically connected to the start signal input terminal STV of the gate driver circuit, and the drain is electrically connected to the first node M_i of the gate driver circuit. The gate of the second transistor T2_i is electrically connected to the third node Q_i of the gate driver circuit, the source is electrically connected to the high potential signal input terminal VGH of the gate driver circuit, and the drain is electrically connected to the second node P_i of the gate driver circuit. The gate of the third transistor T3_i is electrically connected to the first node M_i, the source is electrically connected to the low potential signal input terminal VGL of the gate driver circuit, and the drain is electrically connected to the second node P_i. The gate of the fourth transistor T4_i is electrically connected to the low potential signal input terminal VGL, the source is electrically connected to the first node M_i, and the drain is electrically connected to the third node Q_i. The gate of the fifth transistor T5_i is electrically connected to the third node Q_i, the source is electrically connected to the low potential signal input terminal VGL, and the drain is electrically connected to the gate drive signal output terminal Nout_i of the gate driver circuit. The gate of the sixth transistor T6_i is electrically connected to the second node P_i, the source is electrically connected to the high potential signal input terminal VGH, and the drain is electrically connected to the gate drive signal output terminal Nout_i. One plate of the capacitor C1_i is electrically connected to the third node Q_i, and the other plate of the capacitor C1_i is electrically connected to the gate drive signal output terminal Nout_i. The gate of the seventh transistor T7_i is electrically connected to the second node P_i, the source is electrically connected to the low potential signal input terminal VGL, and the drain is electrically connected to the first node M_i. The seventh transistor T7_i is configured to pull down the potential of the first node M_i when the signal at the start signal input terminal STV switches from a high potential to a low potential and there is a delay, as Figure 10 shown.
[0070] The third transistor T3_i includes two gates, one of which is electrically connected to the first node M_i and the other is electrically connected to the source of the third transistor T3_i; the seventh transistor T7_i includes two gates, one of which is electrically connected to the second node P_i and the other is electrically connected to the source of the seventh transistor T7_i.
[0071] Both the third transistor T3_i and the seventh transistor T7_i are N-type transistors, and the first transistor T1_i, the second transistor T2_i, the fourth transistor T4_i, the fifth transistor T5_i, and the sixth transistor T6_i are all P-type transistors.
[0072] The third transistor T3_i and the seventh transistor T7_i are indium gallium zinc oxide transistors, and the first transistor T1_i, the second transistor T2_i, the fourth transistor T4_i, the fifth transistor T5_i, and the sixth transistor T6_i are low temperature polycrystalline silicon transistors.
[0073] During the process of the start signal switching from a high potential to a low potential (within a preset time), when the clock signal at the clock signal input terminal CK is at a high potential, the potential of the second node P_i is at a low potential, the first transistor T1_i is turned off, and the seventh transistor T7_i is turned off. When the clock signal at the clock signal input terminal CK is at a low potential, the potential of the second node P_i is at a high potential, the first transistor T1_i is turned on, the start signal is transmitted to the first node M_i, and the seventh transistor T7_i is turned on, transmitting a low potential signal to the first node M_i.
[0074] When the third node Q_i is at a low potential and the first node M_i is also at a low potential, the second node P_i is at a high potential; when the third node Q_i is at a high potential or the first node M_i is at a high potential, the second node P_i is at a low potential.
[0075] Compared with the gate driving sub - circuit of the 7T1C structure in the previous embodiment, the main difference in the gate driving sub - circuit of the 7T1C structure in this embodiment lies in the gate connection of the second transistor T2_i. In this embodiment, the gate of the second transistor T2_i is electrically connected to the third node Q_i instead of the first node M_i. By providing the control signals of the second transistor T2_i and the third transistor T3_i respectively from the third node Q_i and the first node M_i, the separation of the control signals of the second transistor T2_i and the third transistor T3_i is achieved, improving the stability and reliability of the gate driving sub - circuit in this embodiment. Specifically, this technical solution for separating control signals has the following advantages: First, it avoids the potential fluctuation of the first node M_i affecting both the second transistor T2_i and the third transistor T3_i simultaneously, reducing the dependence of the gate driving sub - circuit in this embodiment on the potential stability of the first node M_i. Second, since the third node Q_i is isolated by the fourth transistor T4_i, the third node Q_i has more stable potential characteristics. By electrically connecting the gate of the second transistor T2_i to the third node Q_i, the sensitivity of the gate driving sub - circuit in this embodiment to abnormal potentials of the first node M_i is reduced. Third, when the potential of the first node M_i is unstable, separating the control signals of the second transistor T2_i and the third transistor T3_i can prevent the abnormal potential of the first node M_i from affecting both the second transistor T2_i and the third transistor T3_i simultaneously, improving the fault - tolerance ability of the gate driving sub - circuit in this embodiment and enabling the gate driving sub - circuit to operate normally under more severe working conditions.
[0076] In another embodiment of the present application, a display device is provided. The display device includes a gate driving sub - circuit of another 9T1C structure, the gate of the second transistor T2_i is electrically connected to the third node Q_i, and the i - th stage gate driving sub - circuit further includes an eighth transistor T8_i and a ninth transistor T9_i, asFigure 11 as shown
[0077] The gate of the eighth transistor T8_i is electrically connected to the second node P_i, the source is electrically connected to the drain of the sixth transistor T6_i, and the drain is electrically connected to the gate drive signal output terminal Nout_i.
[0078] The gate of the ninth transistor T9_i is electrically connected to the gate drive signal output terminal Nout_i, the source is electrically connected to the low potential signal input terminal VGL, and the drain is electrically connected to the source of the eighth transistor T8_i.
[0079] Both the eighth transistor T8_i and the ninth transistor T9 are P-type transistors. The eighth transistor T8_i and the ninth transistor T9_i are low-temperature polysilicon transistors.
[0080] The gate drive sub-circuit in the embodiment of the present application is applicable to driving the pixel circuit of the 8T2C structure of an LTPO (Low Temperature Polycrystalline Oxide) display panel product. The gate drive signal output by the gate drive sub-circuit can be used as one of the gate drive signals of the pixel circuit of the 8T2C structure.
[0081] Through the above technical solution, the embodiment of the present application achieves the purpose of reducing the power consumption of the gate drive sub-circuit and improving the threshold voltage fault tolerance (fault tolerance limit (Vth Margin)). Specifically, through the function of the seventh transistor T7_i, on the one hand, it can prevent the abnormal potential phenomenon that occurs after the start signal passes through the first transistor T1_i, and avoid the low potential of the first node M_i being higher than the potential of the low potential signal during the high interval of the clock signal, thereby preventing the third transistor T3_i from having a large impact current from the high potential signal input terminal VGH to the low potential signal input terminal VGL; on the other hand, by forcibly pulling the potential of the first node M_i to the low potential, the normal operation of the stage transfer operation is ensured, and the fault tolerance (fault tolerance limit) of the gate drive sub-circuit to the threshold voltage drift of the low-temperature polysilicon transistor is improved.
[0082] The above has introduced the embodiments of the present application in detail. The content of this specification should not be construed as a limitation on the protection scope of the present application.
Claims
1. A display device, characterized in that, The display device includes a gate driving circuit, the gate driving circuit includes a plurality of cascaded gate driving sub - circuits, and the gate driving sub - circuit includes: A first transistor, the gate of the first transistor is electrically connected to the clock signal input terminal of the gate driving sub - circuit, the source is electrically connected to the start signal input terminal of the gate driving sub - circuit, and the drain is electrically connected to the first node of the gate driving sub - circuit; A second transistor, the gate of the second transistor is electrically connected to the first node, the source is electrically connected to the high - potential signal input terminal of the gate driving sub - circuit, and the drain is electrically connected to the second node of the gate driving sub - circuit; A third transistor, the gate of the third transistor is electrically connected to the first node, the source is electrically connected to the low - potential signal input terminal of the gate driving sub - circuit, and the drain is electrically connected to the second node; A fifth transistor, the gate of the fifth transistor is electrically connected to the third node of the gate driving sub - circuit, the source is electrically connected to the low - potential signal input terminal, and the drain is electrically connected to the gate driving signal output terminal of the gate driving sub - circuit; A sixth transistor, the gate of the sixth transistor is electrically connected to the second node, the source is electrically connected to the high - potential signal input terminal, and the drain is electrically connected to the gate driving signal output terminal; and A seventh transistor, the gate of the seventh transistor is electrically connected to the second node, the source is electrically connected to the low - potential signal input terminal, and the drain is electrically connected to the first node. The seventh transistor is configured to pull down the potential of the first node when the start signal at the start signal input terminal switches from high potential to low potential and the first transistor is turned on.
2. The display device according to claim 1, characterized in that, The gate driving sub - circuit further includes: A fourth transistor, the gate of the fourth transistor is electrically connected to the low - potential signal input terminal, the source is electrically connected to the first node, and the drain is electrically connected to the third node; and A capacitor, one plate of the capacitor is electrically connected to the third node, and the other plate of the capacitor is electrically connected to the gate driving signal output terminal.
3. The display device according to claim 2, wherein The third transistor and the seventh transistor are both N - type transistors, and the first transistor, the second transistor, the fourth transistor, the fifth transistor and the sixth transistor are all P - type transistors.
4. The display device according to claim 3, characterized in that, When the first node is at a low potential, the second transistor is turned on, the third transistor is turned off, and the second node is at a high potential; When the first node is at a high potential, the second transistor is turned off, the third transistor is turned on, and the second node is at a low potential.
5. The display device according to claim 1, wherein The third transistor includes two gates, one of which is electrically connected to the first node and the other is electrically connected to the source of the third transistor; The seventh transistor includes two gates, one of which is electrically connected to the second node and the other is electrically connected to the source of the seventh transistor.
6. The display device according to claim 1, wherein The gate driving sub - circuit further includes: An eighth transistor, the gate of the eighth transistor is electrically connected to the second node, the source is electrically connected to the drain of the sixth transistor, and the drain is electrically connected to the gate driving signal output terminal; and A ninth transistor, the gate of the ninth transistor is electrically connected to the gate driving signal output terminal, the source is electrically connected to the low potential signal input terminal, and the drain is electrically connected to the source of the eighth transistor.
7. The display device according to claim 6, characterized in that, Both the eighth transistor and the ninth transistor are P-type transistors.
8. The display device according to claim 1, wherein During the process of the start signal switching from a high potential to a low potential, when the clock signal at the clock signal input terminal is at a high potential, the potential of the second node is at a low potential, the first transistor is turned off, and the seventh transistor is turned off; when the clock signal at the clock signal input terminal is at a low potential, the potential of the second node is at a high potential, the first transistor is turned on, and the seventh transistor is turned on.
9. A display device, characterized in that, The display device includes a gate driving circuit, and the gate driving circuit includes a plurality of cascaded gate driving sub-circuits. The gate driving sub-circuit includes: A first transistor, the gate of the first transistor is electrically connected to the clock signal input terminal of the gate driving sub-circuit, the source is electrically connected to the start signal input terminal of the gate driving sub-circuit, and the drain is electrically connected to the first node of the gate driving sub-circuit; A second transistor, the gate of the second transistor is electrically connected to the third node of the gate driving sub-circuit, the source is electrically connected to the high potential signal input terminal of the gate driving sub-circuit, and the drain is electrically connected to the second node of the gate driving sub-circuit; A third transistor, the gate of the third transistor is electrically connected to the first node, the source is electrically connected to the low potential signal input terminal of the gate driving sub-circuit, and the drain is electrically connected to the second node; A fourth transistor, the gate of the fourth transistor is electrically connected to the low potential signal input terminal, the source is electrically connected to the first node, and the drain is electrically connected to the third node; A fifth transistor, the gate of the fifth transistor is electrically connected to the third node, the source is electrically connected to the low potential signal input terminal, and the drain is electrically connected to the gate driving signal output terminal of the gate driving sub-circuit; and A sixth transistor, the gate of the sixth transistor is electrically connected to the second node, the source is electrically connected to the high potential signal input terminal, and the drain is electrically connected to the gate driving signal output terminal.
10. The display device according to claim 9, wherein, The gate driving sub-circuit further includes: A seventh transistor, the gate of the seventh transistor is electrically connected to the second node, the source is electrically connected to the low potential signal input terminal, and the drain is electrically connected to the first node. The seventh transistor is configured to pull down the potential of the first node when the start signal at the start signal input terminal switches from a high potential to a low potential and there is a delay; and A capacitor, one plate of the capacitor is electrically connected to the third node, and the other plate of the capacitor is electrically connected to the gate driving signal output terminal.
11. The display device according to claim 10, characterized in that, The seventh transistor includes two gates. One gate of the seventh transistor is electrically connected to the second node, and the other gate is electrically connected to the source of the seventh transistor.
12. The display device according to claim 10, wherein During the process of the start signal switching from a high potential to a low potential, when the clock signal at the clock signal input terminal is at a high potential, the potential of the second node P is at a low potential, the first transistor is turned off, and the seventh transistor is turned off. When the clock signal at the clock signal input terminal is at a low potential, the potential of the second node P is at a high potential, the first transistor is turned on, and the seventh transistor is turned on.
13. The display device according to claim 10, characterized in that, The first transistor, the second transistor, the fourth transistor, the fifth transistor, and the sixth transistor are all P-type transistors, and the third transistor and the seventh transistor are both N-type transistors.
14. The display device according to claim 13, characterized in that, When the third node is at a low potential and the first node is also at a low potential, the second node is at a high potential; When the third node is at a high potential or the first node is at a high potential, the second node is at a low potential.
15. The display device according to claim 9, wherein The third transistor includes two gates. One gate of the third transistor is electrically connected to the first node, and the other gate is electrically connected to the source of the third transistor.
16. The display device according to claim 9, wherein The gate driving sub-circuit further includes: An eighth transistor, whose gate is electrically connected to the second node, source is electrically connected to the drain of the sixth transistor, and drain is electrically connected to the gate driving signal output terminal; and A ninth transistor, whose gate is electrically connected to the gate driving signal output terminal, source is electrically connected to the low potential signal input terminal, and drain is electrically connected to the source of the eighth transistor.
17. The display device according to claim 16, wherein The eighth transistor and the ninth transistor are both P-type transistors.