Display device

Abstract

The invention relates to the technical field of display, and discloses a display device which comprises a display panel and a driving chip. The driving chip comprises a detection compensation module, the detection compensation module comprises an addition operational amplifier circuit and a low-dropout voltage stabilizer, the first power supply signal line is electrically connected with the first input end of the addition operational amplifier circuit, and the output end of the low-dropout voltage stabilizer is electrically connected with the second input end of the addition operational amplifier circuit; the output end of the addition operational amplifier circuit is electrically connected with a first reference voltage signal line; the display device comprises a first driving mode, and in the first driving mode, the detection compensation module is configured to control the voltage difference between the first power supply voltage provided by the first power supply signal line and the first reference voltage provided by the first reference voltage signal line to be the same at different driving moments. The problem of brightness jump can be effectively solved, flickering of a display picture is avoided, and the display effect and the user experience are improved.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and particularly to a display device. Background Art

[0002] Organic light-emitting diode (OLED) is an emerging display technology. Compared with traditional liquid crystal displays, the display screen made of OLED has higher contrast, faster response speed and wider viewing angle, and has currently been widely applied in the field of high-performance displays. To provide users with a good experience, a display brightness value (DBV) for adjusting the brightness of the OLED display screen can be preset in an electronic device. For example, when the light is strong, the user can increase the display brightness value of the OLED display screen so that the user can clearly see the content displayed on the OLED display screen; when the light is weak, the user can decrease the display brightness value of the OLED display screen to avoid the user's eyes from being stung due to the too large brightness difference between the ambient light and the display screen.

[0003] Since the display brightness of the OLED display screen is determined by the voltage difference between the two ends of the light-emitting diode of the OLED display screen, adjusting the display brightness value of the OLED display screen is actually adjusting the voltage difference between the two ends of the light-emitting diode of the OLED display screen. And the voltage difference between the two ends of the OLED is associated with the difference between the initial anode voltage of the initial anode signal line of the OLED and the cathode voltage (ElectroLuminescence Source Supply Voltage, ELVSS) of the OLED.

[0004] Currently, due to reasons such as transmission loss in the prior art, the cathode voltage ELVSS of the OLED changes when adjusting the brightness of the display screen, resulting in a change in the voltage difference between the two ends of the OLED. Especially in low gray-scale display, once the initial anode voltage of the initial anode signal line and the cathode voltage ELVSS of the OLED do not change synchronously, then there may be a large brightness jump problem, and further, during the process of adjusting the brightness of the display screen, the user may see an obvious display screen flicker phenomenon.

[0005] Therefore, it is a technical problem urgently to be solved by those skilled in the art to provide a display device that can effectively solve the brightness jump problem, avoid display screen flicker, and is beneficial to improving the display effect and the user experience. Summary of the Invention

[0006] To solve the above technical problems, the present disclosure provides a display device to solve the problem that the display screen in the prior art is prone to sudden brightness changes during the brightness adjustment process, making it easy for users to perceive screen flicker during viewing, thereby affecting the display effect.

[0007] The present disclosure provides a display device, including a display panel and a driving chip;

[0008] The display panel includes a plurality of sub-pixels, a first reference voltage signal line, and a first power supply signal line;

[0009] The sub-pixel includes a pixel circuit and a light-emitting element connected electrically; the pixel circuit includes at least a driving module and an anode reset module. The first end of the anode reset module is electrically connected to the first reference voltage signal line, the second end of the anode reset module is electrically connected to the anode of the light-emitting element, the driving module is electrically connected to the anode of the light-emitting element, and the cathode of the light-emitting element is electrically connected to the first power supply signal line;

[0010] The driving chip includes a detection and compensation module, and the detection and compensation module includes an adder operational amplifier circuit and a low-dropout regulator. The first power supply signal line is electrically connected to the first input end of the adder operational amplifier circuit, the output end of the low-dropout regulator is electrically connected to the second input end of the adder operational amplifier circuit, and the output end of the adder operational amplifier circuit is electrically connected to the first reference voltage signal line;

[0011] The display device includes a first driving mode. In the first driving mode, the detection and compensation module is configured to control the voltage difference between the first power supply voltage provided by the first power supply signal line and the first reference voltage provided by the first reference voltage signal line to be the same at different driving times.

[0012] The technical solution provided by the embodiments of the present disclosure has the following advantages compared with the prior art:

[0013] The driving chip of the display device provided in the present disclosure includes a detection and compensation module, which can be integrally arranged in the driving chip through a pre-designed integrated circuit structure. The detection and compensation module includes an adder operational amplifier circuit and a low dropout regulator. The low dropout regulator is used to provide a fixed voltage difference between a preset stable first power supply voltage and a first reference voltage. The display device includes a first driving mode. In the first driving mode, the function of the detection and compensation module is configured to control the voltage difference between the first power supply voltage provided by the first power supply signal line and the first reference voltage provided by the first reference voltage signal line to be the same at different driving times. The specific implementation method is that the first power supply signal line in the display panel is electrically connected to the first input terminal of the adder operational amplifier circuit of the driving chip, and the output terminal of the low dropout regulator is electrically connected to the second input terminal of the adder operational amplifier circuit. The change of the first power supply voltage on the first power supply signal line is detected in real time through the first input terminal of the adder operational amplifier circuit, and the fixed voltage difference between the first power supply voltage and the first reference voltage provided by the output terminal of the low dropout regulator is connected to the second input terminal of the adder operational amplifier circuit. Even if the first power supply voltage on the first power supply signal line changes, the first reference voltage can ensure that the first reference voltage input to the first reference voltage signal line and the first power supply voltage are always at a fixed voltage difference through the fixed voltage difference provided by the second input terminal of the adder operational amplifier circuit, which can avoid the brightness mutation of the display device due to the change of the first power supply voltage during the display brightness adjustment process, and can also avoid the brightness mutation of the display device due to the change of the first reference voltage during the display brightness adjustment process. Furthermore, it can improve the problem of display screen flicker, which is beneficial to improving the display effect and user experience satisfaction. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings herein are incorporated into and constitute a part of this specification, showing embodiments consistent with the present disclosure and, together with the specification, are used to explain the principles of the present disclosure.

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0016] Figure 1 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure;

[0017] Figure 2 is Figure 1 a simplified electrical connection schematic diagram of the display panel and the driving chip of the display device in;

[0018] Figure 3 is Figure 1 a schematic diagram of an electrical connection structure of a sub-pixel in;

[0019] Figure 4 Is Figure 1 Another schematic diagram of the electrical connection structure of sub-pixels;

[0020] Figure 5 Is a schematic diagram of the pressure difference corresponding to the nodes of different display brightness values in the ideal state of the solution for improving brightness mutation adopted in the prior art;

[0021] Figure 6 Is a schematic diagram of the first power supply voltage and the first reference voltage corresponding to the nodes of different display brightness values in the actual state of the solution for improving brightness mutation adopted in the prior art;

[0022] Figure 7 Is Figure 1 Another simplified electrical connection schematic diagram of the display panel and the driving chip in the display device in

[0023] Figure 8 Is Figure 1 Another simplified electrical connection schematic diagram of the display panel and the driving chip in the display device in

[0024] Figure 9 Is Figure 1 Another simplified electrical connection schematic diagram of the display panel and the driving chip in the display device in

[0025] Figure 10 Is a schematic diagram of the pressure difference corresponding to different driving moments of the display device provided by the embodiment of the present disclosure in the first driving mode;

[0026] Figure 11 Is a schematic diagram of the pressure difference corresponding to different driving moments of the display device provided by the embodiment of the present disclosure in the second driving mode;

[0027] Figure 12 Is a schematic diagram of the different pressure differences between the first power supply voltage and the first reference voltage of the display device provided by the embodiment of the present disclosure in different driving modes;

[0028] Figure 13 Is a schematic diagram of one of the different pressure differences between the first power supply voltage and the first reference voltage of the display device provided by the embodiment of the present disclosure in the first driving mode;

[0029] Figure 14 Is another schematic diagram of the different pressure differences between the first power supply voltage and the first reference voltage of the display device provided by the embodiment of the present disclosure in the first driving mode. Detailed implementation manners

[0030] To better understand the above objects, features, and advantages of the present disclosure, the solutions of the present disclosure will be further described below. It should be noted that, without conflict, the embodiments of the present disclosure and the features in the embodiments may be combined with each other.

[0031] In the following description, many specific details are set forth to facilitate a thorough understanding of the present disclosure, but the present disclosure may be practiced in other ways different from those described herein; obviously, the embodiments in the specification are only a part of the embodiments of the present disclosure, rather than all the embodiments.

[0032] Please refer to Figures 1 - 3 , Figure 1 which is a schematic structural diagram of a display device provided by an embodiment of the present disclosure, Figure 2 is Figure 1 a simplified electrical connection schematic diagram of the display panel and the driving chip of the display device in Figure 3 is Figure 1 a schematic diagram of an electrical connection structure of a sub-pixel in . The display device 000 provided in this embodiment includes a display panel 10 and a driving chip 20;

[0033] The display panel 10 includes a plurality of sub-pixels 101, a first reference voltage signal line REF1, and a first power supply signal line PVEE;

[0034] The sub-pixel 101 includes a pixel circuit 101A and a light-emitting element 101B connected electrically; the pixel circuit 101A includes at least a driving module 101A1 and an anode reset module 101A2. The first end of the anode reset module 101A2 is electrically connected to the first reference voltage signal line REF1, the second end of the anode reset module 101A2 is electrically connected to the anode 101B1 of the light-emitting element 101B, the driving module 101A1 is electrically connected to the anode 101B1 of the light-emitting element 101B, and the cathode 101B2 of the light-emitting element 101B is electrically connected to the first power supply signal line PVEE;

[0035] The driving chip 20 includes a detection compensation module 201. The detection compensation module 201 includes an adder operational amplifier circuit 201A and a low dropout regulator 201B. The first power supply signal line PVEE is electrically connected to the first input terminal 201A-IN1 of the adder operational amplifier circuit 201A, the output terminal 201B-OUT of the low dropout regulator 201B is electrically connected to the second input terminal 201A-IN2 of the adder operational amplifier circuit 201A, and the output terminal 201A-OUT of the adder operational amplifier circuit 201A is electrically connected to the first reference voltage signal line REF1;

[0036] The display device 000 includes a first driving mode. In the first driving mode, the detection compensation module 201 is configured to control the voltage difference between the first power supply voltage ELVSS provided by the first power supply signal line PVEE and the first reference voltage Vref1 provided by the first reference voltage signal line REF1 to be the same at different driving times.

[0037] Specifically, the display device 000 provided in this embodiment may be an organic light-emitting diode display device, including a display panel 10 and a driving chip 20. The display panel 10 may be an organic light-emitting diode display panel. The driving chip 20 may be an integrated driving chip that is bonded and electrically connected to the display panel 10 using the COF technology (i.e., Chip On Flex, Chip On Film, a chip-on-flexible-film technology that is a chip-on-flexible-board packaging technology), or the driving chip 20 may also be an integrated driving chip directly bonded to the display panel 10, and is used to provide power signals, driving signals, etc. to the display panel 10. It can be understood that the electrical connection structure between the driving chip 20 and the display panel 10 is not limited in this embodiment. Figure 1 Only the electrical connection between the driving chip 20 and the display panel 10 through the flexible circuit board 30 is schematically shown. In specific implementation, the electrical connection structure between the driving chip 20 and the display panel 10 includes but is not limited to this, and may also be other electrical connection methods, which are not elaborated in this embodiment. It can be understood that the final structure presented by the display device 000 in this embodiment may be a structure in which the driving chip 20 is located on the backlight side of the display panel 10 through the bending of the flexible circuit board, thereby minimizing the overall size of the display device 000 as much as possible and avoiding the driving chip 20 from occupying the space of the device.

[0038] The display panel 10 of this embodiment includes a plurality of sub-pixels 101, a first reference voltage signal line REF1, and a first power supply signal line PVEE. The plurality of sub-pixels 101 may include at least three types of sub-pixels 101 with different colors. It can be understood that in this embodiment Figure 1 the arrangement of the plurality of sub-pixels 101 in an array arrangement is taken as an example for illustration. In specific implementation, the arrangement of the plurality of sub-pixels 101 includes but is not limited to this. For example Figure 3As shown, sub-pixel 101 includes a pixel circuit 101A and a light-emitting element 101B that are electrically connected. The pixel circuit 101A is used to provide a driving current for the light-emitting element 101B electrically connected thereto to achieve the light-emitting display function of the light-emitting element 101B. The light-emitting element 101B can be an organic light-emitting diode. The pixel circuit 101A at least includes a driving module 101A1 and an anode reset module 101A2. The first end of the anode reset module 101A2 is electrically connected to the first reference voltage signal line REF1, and the second end of the anode reset module 101A2 is electrically connected to the anode 101B1 of the light-emitting element 101B. The anode reset module 101A2 is used to reset the anode 101B1 of the light-emitting element 101B with the first reference voltage Vref1 provided by the first reference voltage signal line REF1 in the conducting state, so that the anode 101B1 of the light-emitting element 101B is initialized, thereby improving the residue of the previous frame data signal, improving the ghosting phenomenon, and enhancing the display effect. The driving module 101A1 is electrically connected to the anode 101B1 of the light-emitting element 101B. The cathode 101B2 of the light-emitting element 101B is electrically connected to the first power supply signal line PVEE. The first power supply signal line PVEE is used to provide a first power supply voltage ELVSS for the cathode 101B2 of the light-emitting element 101B. Optionally, the driving module 101A1 can also be electrically connected to the second power supply signal line PVDD. The second power supply signal line PVDD is used to provide a second power supply voltage ELVDD for the driving module 101A1.

[0039] As Figure 4 shown, Figure 4 is Figure 1 Another schematic diagram of the electrical connection structure of the sub-pixel in the neutron. In this embodiment, the electrical connection structure of the pixel circuit 101A and the light-emitting element 101B included in the sub-pixel 101 is Figure 4Taking the example shown, the display panel 10 can be a display panel adopting LTPO technology. The pixel circuit 101A of the sub-pixel 101 in the display panel 10 includes 8 transistors (transistors T1, T2, T3, T4, T5, T6, T7, T8) and 1 capacitor (capacitor Cst). Among them, the driving module 101A1 includes transistor T3, and transistors T4 and T5 electrically connected to the gate of transistor T3 are both N-type metal oxide transistors, such as IGZO (indium gallium zinc oxide) transistors, and the remaining transistors are P-type LTPS (low temperature polycrystalline silicon) transistors. That is, transistors T4 and T5 are turned on when the gate potential is high, while the remaining transistors are turned on when the gate potential is low. The anode reset module 101A2 includes transistor T7. The first pole of transistor T7 is electrically connected to the first reference voltage signal line REF1, and the second pole of transistor T7 is electrically connected to the anode 101B1 of the light-emitting element 101B. The potential of the N4 node in the pixel circuit 101A is the potential of the anode 101B1 of the light-emitting element 101B, and the voltage difference between the N4 node and the cathode 101B2 of the light-emitting element 101B determines the magnitude of the current flowing through the light-emitting element 101B. Figure 4 The transistor T8 in the provided pixel circuit 101A is used to adjust the bias state of the transistor T3. It should be noted that the connection structure and working principle of the above pixel circuit are not elaborated herein. For specific understanding, reference can be made to the explanation of LTPO technology in related technologies.

[0040] In the prior art, if Figure 4 When the pixel circuit shown is used to drive the light-emitting element to emit light, the second power supply signal line PVDD provides the second power supply voltage ELVDD for the driving module 101A1, and the first power supply signal line PVEE provides the first power supply voltage ELVSS for the cathode 101B2 of the light-emitting element 101B. The driving current I0 formed by the driving module 101A1 is the sum of the current I1 flowing through the light-emitting element 101B and the current I2 flowing through the anode reset module 101A2. In the low gray-scale display of the display device, when the voltage of the cathode 101B2 of the light-emitting element 101B, that is, the first power supply voltage ELVSS, changes, the voltage difference between the anode 101B1 and the cathode 101B2 of the light-emitting element 101B changes, so the current I1 flowing through the light-emitting element 101B mutates, and the driving current I0 formed by the driving module 101A1 remains unchanged. Therefore, the current I2 flowing through the anode reset module 101A2 also mutates accordingly, resulting in a sudden change in the brightness of the light-emitting element 101B, and further causing a flicker problem.

[0041] The applicant has found that when and only when the first power supply voltage ELVSS and the first reference voltage Vref1 change synchronously, the current I1 flowing through the light-emitting element 101B and the current I2 flowing through the anode reset module 101A2 change less, and the probability of brightness mutation is small. As Figure 5 shown, Figure 5 Figure is a schematic diagram of the voltage difference corresponding to different display brightness value nodes in the ideal state of the prior art's solution for improving brightness mutation. The common improvement method in the prior art is to set different display brightness value DBV nodes. When the display device is adjusted from the first display brightness value node DBV1 to the second display brightness value node DBV2, ideally, the voltage difference between the first power supply voltage ELVSS and the first reference voltage Vref1 is the same, that is, to maintain Figure 5 △V1 in equal to △V2 in. The display brightness value nodes are determined by interpolation. For example, the value range of the display brightness value can be set as [0, 100], and the brightness of the display panel is adjusted by changing the display brightness value. When it is necessary to make the voltage difference between the first power supply voltage ELVSS and the first reference voltage Vref1 the same, if the first power supply voltage ELVSS is also determined by the interpolation voltage method, the interpolation voltage accuracy and the algorithm of the interpolated display brightness value must be highly consistent to make it possible to keep the voltage difference between the first power supply voltage ELVSS and the first reference voltage Vref1 fixed for different display brightness value DBV nodes and achieve Figure 5 the ideal state shown.

[0042] However, in actual use, misalignment of the interpolated DBV nodes may occur in different interpolations of the first power supply voltage ELVSS. As Figure 6 shown, Figure 6 Figure is a schematic diagram of the first power supply voltage and the first reference voltage corresponding to different display brightness value nodes in the actual state of the prior art's solution for improving brightness mutation. It can be seen from Figure 6 that only at the three DBV nodes J1, J2, and J3 circled by the dotted line, the voltage difference between the corresponding first power supply voltage and the first reference voltage is the same, while at the other DBV nodes, the voltage difference between the first power supply voltage and the first reference voltage is inconsistent due to misalignment of the interpolation nodes, that is, the first power supply voltage and the first reference voltage do not change synchronously, and thus the situation of brightness mutation will occur.

[0043] To solve the above problems, in this embodiment, the driving chip 20 is provided with a detection compensation module 201, which can be integrally arranged in the driving chip 20 through a pre-designed integrated circuit structure. The detection compensation module 201 includes an adder operational amplifier circuit 201A and a low-dropout regulator 201B. The low-dropout regulator 201B (Low-dropout regulator, LDO) is used to provide a preset stable fixed voltage difference △V between the first power supply voltage ELVSS and the first reference voltage Vref1. In different actual usage scenarios, △V can be different; the size of the fixed voltage difference △V between the first power supply voltage ELVSS and the first reference voltage Vref1 can be adjusted through register instructions. For example, the low-dropout regulator 201B can include a voltage regulator for the first reference voltage Vref1, and by inputting a digital value, the output corresponding fixed voltage difference △V can be adjusted. In this embodiment, the working principle of the low-dropout regulator 201B will not be elaborated. During specific implementation, it only needs to satisfy that the low-dropout regulator 201B can adjust the output fixed voltage difference △V between the stable first power supply voltage ELVSS and the first reference voltage Vref1 in different scenarios according to the instructions of the actual register. Therefore, in this embodiment, the display device 000 is provided with a first driving mode. In the first driving mode, the function of the detection compensation module 201 is configured to make the voltage difference between the first power supply voltage ELVSS provided by the first power supply signal line PVEE and the first reference voltage Vref1 provided by the first reference voltage signal line REF1 the same at different driving moments.Specific implementation method: The first power supply signal line PVEE in the display panel 10 is electrically connected to the first input terminal 201A-IN1 of the summing operational amplifier circuit 201A of the driving chip 20, and the output terminal 201B-OUT of the low dropout regulator 201B is electrically connected to the second input terminal 201A-IN2 of the summing operational amplifier circuit 201A. The change of the first power supply voltage ELVSS on the first power supply signal line PVEE is detected in real time through the first input terminal 201A-IN1 of the summing operational amplifier circuit 201A, and the fixed voltage difference △V between the first power supply voltage ELVSS provided by the output terminal 201B-OUT of the low dropout regulator 201B and the first reference voltage Vref1 is connected to the second input terminal 201A-IN2 of the summing operational amplifier circuit 201A. When the output terminal 201A-OUT of the summing operational amplifier circuit 201A is electrically connected to the first reference voltage signal line REF1, the first reference voltage Vref1 obtained on the first reference voltage signal line REF1 in the display panel 10 remains equal to the sum of the first power supply voltage ELVSS and △V. Even if the first power supply voltage ELVSS on the first power supply signal line PVEE changes, the first reference voltage Vref1 can also ensure that the first reference voltage Vref1 input to the first reference voltage signal line REF1 and the first power supply voltage ELVSS are always a fixed voltage difference △V through the fixed voltage difference △V provided by the second input terminal 201A-IN2 of the summing operational amplifier circuit 201A. Thus, it is possible to avoid the brightness sudden change of the display device 000 during the display brightness adjustment process due to the change of the first power supply voltage ELVSS, and it is also possible to avoid the brightness sudden change of the display device 000 during the display brightness adjustment process due to the change of the first reference voltage Vref1. Furthermore, it is possible to improve the problem of display screen flicker, which is beneficial to improving the display effect and user experience satisfaction.

[0044] In this embodiment, when the display device 000 is set to the first driving mode, the function of the detection compensation module 201 is configured such that at different driving times, the voltage difference between the first power supply voltage ELVSS provided by the first power supply signal line PVEE and the first reference voltage Vref1 provided by the first reference voltage signal line REF1 is the same. Since the value of the first power supply voltage ELVSS is relatively large and the current flowing through it is relatively large during high-brightness display of the display device 000, the IR drop (power supply voltage drop) of the first power supply voltage ELVSS is relatively large. In the prior art, if the first power supply voltage increases and the first reference voltage does not change synchronously, the voltage difference between the first power supply voltage and the first reference voltage will become smaller, and the smaller the voltage difference between the two, the worse the uniformity. Therefore, in this embodiment, the voltage difference between the first power supply voltage ELVSS provided by the first power supply signal line PVEE and the first reference voltage Vref1 provided by the first reference voltage signal line REF1 does not change with the change of the first power supply voltage ELVSS, but remains a fixed voltage difference. Therefore, the in-plane uniformity problem caused by the IR drop of the first power supply voltage ELVSS during high-brightness display can be effectively reduced, and the display quality can be better improved.

[0045] It can be understood that in this embodiment, the first power supply signal line PVEE in the display panel 10 is electrically connected to the first input terminal 201A-IN1 of the adder operational amplifier circuit 201A of the driving chip 20. The connection can be a direct electrical connection or an indirect electrical connection through other intermediate structures. Similarly, the output terminal 201A-OUT of the adder operational amplifier circuit 201A is electrically connected to the first reference voltage signal line REF1 in the display panel 10. The connection can be a direct electrical connection or an indirect electrical connection through other intermediate structures. This embodiment does not make any limitations in this regard.

[0046] It should be noted that Figure 2 the structure included in the display device 000 in this embodiment only exemplifies the electrical connection relationship between them, and does not represent the actual set structure. During specific implementation, the actual set position, shape and other structures of the product can be considered. And during specific implementation, the structure of the display device 000 includes but is not limited to this, and also includes other structures, such as the analog-to-digital voltage converter between the adder operational amplifier circuit 201A and the low-dropout voltage regulator 201B, the analog-to-digital voltage converter between the adder operational amplifier circuit 201A and the display panel 10, etc. The structure of the display panel 10 can be understood by referring to the structure of the OLED display panel in related technologies.

[0047] In some alternative embodiments, please refer to Figure 1 、 Figure 3 and Figure 7 , Figure 7 is Figure 1Another simplified schematic diagram of the electrical connection between the display panel and the driving chip of the display device. In this embodiment, the driving chip 20 includes a display driving chip 202 and a power management integrated circuit 203; the display driving chip 201 is electrically connected to the display panel 10 by bonding, and the power management integrated circuit 203 at least includes a first power voltage output terminal 203-ELVSS-OUT, and the first power voltage output terminal 203-ELVSS-OUT is electrically connected to the first power signal line PVEE.

[0048] This embodiment explains that the driving chip 20 includes a display driving chip 202 and a power management integrated circuit 203. The display driving chip 202 can be understood as a DDIC (Display Driver Integrated Circuit), which is mainly used to control the display panel 10, drive the display panel 10 through electrical signals, transmit display driving data, cooperate with the display panel 10 to achieve thin, flexible and foldable, and provide a wide color gamut and high-fidelity display signals. The power management integrated circuit 203 can be understood as a PMIC (Power Management IC), which is mainly used to supply power to the display device 000, that is, the power supply for the display panel 10 to perform display work, the power supply for the display driving chip 202 to control the display driving signal, and the power supply requirements of other modules included in the display device 000 are all provided by the power management integrated circuit 203. As Figure 7 shown, the first power voltage ELVSS provided by the first power signal line PVEE for the pixel circuit 101A can be provided to the display driving chip 202 through the first power voltage output terminal 203-ELVSS-OUT of the power management integrated circuit 203, and then transmitted to the first power signal line PVEE in the display panel 10 through the output pin of the display driving chip 202, so as to realize that the power management integrated circuit 203 provides the first power voltage ELVSS for the display panel 10.

[0049] Optionally, as Figure 1 、 Figure 3 and Figure 7As shown, the first power supply voltage output terminal 203 - ELVSS - OUT is electrically connected to the first input terminal 201A - IN of the summing operational amplifier circuit 201A. The first power supply voltage output terminal 203 - ELVSS - OUT is also electrically connected to the first input pin PIN1 - IN1 of the display driver chip 202. The first input pin PIN - IN1 of the display driver chip 202 is electrically connected to the first output pin PIN - OUT1 of the display driver chip 202. The first output pin PIN - OUT1 of the display driver chip 202 is electrically connected to the first power supply signal line PVEE. Optionally, the first output pin PIN - OUT1 of the display driver chip 202 is electrically connected to multiple first power supply signal lines PVEE within the display panel 10 through the peripheral traces of the border of the display panel 10.

[0050] This embodiment explains that the first input terminal 201A - IN of the summing operational amplifier circuit 201A is connected to the first power supply voltage output terminal 203 - ELVSS - OUT of the power management integrated circuit 203. That is, the summing operational amplifier circuit 201A actually detects the first power supply voltage ELVSS on the first power supply voltage output terminal 203 - ELVSS - OUT of the power management integrated circuit 203. Also, it means that the summing operational amplifier circuit 201A actually detects the first power supply voltage ELVSS on the first power supply voltage output terminal 203 - ELVSS - OUT of the power management integrated circuit 203 that has not been transmitted to the first power supply signal line PVEE within the display panel 10. Thus, the wiring between the first input terminal 201A - IN of the summing operational amplifier circuit 201A and the first power supply signal line PVEE within the display panel 10 can be saved. The first input terminal 201A - IN of the summing operational amplifier circuit 201A can be directly connected to the first power supply voltage output terminal 203 - ELVSS - OUT of the power management integrated circuit 203 to detect the first power supply voltage ELVSS in real - time. After providing a fixed voltage difference △V between the first power supply voltage ELVSS provided by the output terminal 201B - OUT of the low - dropout regulator 201B and the first reference voltage Vref1, the value of the first reference voltage Vref1 output from the output terminal 201A - OUT of the summing operational amplifier circuit 201A can be ensured to change synchronously with the first power supply voltage ELVSS provided by the first power supply voltage output terminal 203 - ELVSS - OUT of the power management integrated circuit 203 as much as possible. This is beneficial to improving flicker and enhancing the display effect. At the same time, it is also beneficial to saving the layout space of the entire device, simplifying the wiring structure, and reducing the wiring difficulty.

[0051] Optionally, as Figure 1 、 Figure 3 and Figure 8 shown, Figure 8 is Figure 1Another simplified electrical connection schematic diagram of the display panel and the driving chip of the display device. In this embodiment, the first power supply voltage output terminal 203-ELVSS-OUT is electrically connected to the first input pin PIN-IN1 of the display driving chip 202. The first input pin PIN-IN1 of the display driving chip 202 is electrically connected to the first output pin PIN-OUT1 of the display driving chip 202. The first output pin PIN-OUT1 of the display driving chip 202 is electrically connected to the first power supply signal line PVEE. Optionally, the first output pin PIN-OUT1 of the display driving chip 202 is electrically connected to multiple first power supply signal lines PVEE in the display panel 10 through the peripheral wiring of the border of the display panel 10. The first output pin PIN-OUT1 of the display driving chip 202 is also electrically connected to the first input terminal 201A-IN of the adder operational amplifier circuit 201A.

[0052] This embodiment explains that the first power supply voltage output terminal 203-ELVSS-OUT of the power management integrated circuit 203 is electrically connected to the first power supply signal line PVEE through the first input pin PIN-IN1 and the first output pin PIN-OUT1 of the display driving chip 202, so as to provide the first power supply voltage ELVSS for the first power supply signal line PVEE in the plane of the display panel 10. The first input terminal 201A-IN of the adder operational amplifier circuit 201A is electrically connected to the first output pin PIN-OUT1 of the display driving chip 202, that is, the first input terminal 201A-IN of the adder operational amplifier circuit 201A is wired to the plane of the display panel 10 and electrically connected to the first output pin PIN-OUT1 of the display driving chip 202. The first power supply voltage ELVSS detected in real time by the adder operational amplifier circuit 201A is the first power supply voltage ELVSS on the first power supply signal line PVEE that has been transmitted into the plane of the display panel 10 in the plane of the display panel 10. Therefore, the first power supply voltage ELVSS in the plane of the display panel 10 detected in real time by the adder operational amplifier circuit 201A can be more accurate. After providing a fixed voltage difference △V between the first power supply voltage ELVSS provided by the output terminal 201B-OUT of the low-dropout regulator 201B and the first reference voltage Vref1, the value of the first reference voltage Vref1 output from the output terminal 201A-OUT of the adder operational amplifier circuit 201A is as accurate as possible, and it is ensured as much as possible to change synchronously with the first power supply voltage ELVSS provided by the first power supply voltage output terminal 203-ELVSS-OUT of the power management integrated circuit 203, which is beneficial to improving flicker and the display effect. At the same time, the first input terminal 201A-IN of the adder operational amplifier circuit 201A does not need to extract the changing first power supply voltage ELVSS from the first output pin PIN-OUT1 of the display driving chip 202, which is also beneficial to saving the power consumption of the display driving chip 202.

[0053] In some alternative embodiments, please refer to Figure 1 , Figure 3 and Figure 9 . Figure 9 is Figure 1 Another simplified electrical connection schematic diagram of the display panel and the driving chip in the display device in this embodiment. In this embodiment, the output terminal 201A-OUT of the adder operational amplifier circuit 201A is electrically connected to the second input pin PIN-IN2 of the display driving chip 202. The second input pin PIN-IN2 of the display driving chip 202 is electrically connected to the second output pin PIN-OUT2 of the display driving chip 202. The second output pin PIN-OUT2 of the display driving chip 202 is electrically connected to the first reference voltage signal line REF1. Optionally, the second output pin PIN-OUT2 of the display driving chip 202 is electrically connected to multiple first reference voltage signal lines REF1 in the display panel 10 through the peripheral traces of the border of the display panel 10.

[0054] This embodiment explains that when the output terminal 201A-OUT of the adder operational amplifier circuit 201A provides the first reference voltage Vref1 that changes synchronously with the first power supply voltage ELVSS for multiple first reference voltage signal lines REF1 in the display panel 10, the output terminal 201A-OUT of the adder operational amplifier circuit 201A and the multiple first reference voltage signal lines REF1 in the display panel 10 can be indirectly electrically connected. For example, the output terminal 201A-OUT of the adder operational amplifier circuit 201A is electrically connected to the first reference voltage signal line REF1 through the display driving chip 202. The output terminal 201A-OUT of the adder operational amplifier circuit 201A is first electrically connected to the second input pin PIN-IN2 of the display driving chip 202. The second input pin PIN-IN2 of the display driving chip 202 is electrically connected to the second output pin PIN-OUT2 inside the display driving chip 202. The second output pin PIN-OUT2 of the display driving chip 202 is electrically connected to multiple first reference voltage signal lines REF1 in the display panel 10 through the peripheral traces of the border of the display panel 10, thereby realizing providing the first reference voltage Vref1 that is transmitted and changes synchronously with the first power supply voltage ELVSS to multiple first reference voltage signal lines REF1 in the display panel 10, improving the flicker of the display screen and enhancing the display effect.

[0055] In some alternative embodiments, please continue to refer to Figures 1 - 4 , Figures 7 - 9, in this embodiment, in the first driving mode of the display device 000, the low-dropout regulator 201B is configured such that the output terminal 201B-OUT of the low-dropout regulator 201B provides a first voltage difference ΔV1. The first voltage difference ΔV1 represents: at different driving moments in the first driving mode, the absolute value of the voltage difference between the first power supply voltage ELVSS provided by the first power supply signal line PVEE and the first reference voltage Vref1 provided by the first reference voltage signal line REF1, that is, ΔV1 = ∣ELVSS - Vref1∣. It can be understood that at different driving moments of the display device 000 in the first driving mode, it can be understood as different display brightness value DBV nodes of the display device 000 in the first driving mode, that is, in the first driving mode of the display device 000, by adjusting the display brightness value DBV, the display brightness of the display panel 10 of the display device 000 is adjusted. During this process, the low-dropout regulator 201B and the summing operational amplifier circuit 201A of this embodiment work together. As described in the above embodiment, at different display brightness value DBV nodes of the display device 000 in the first driving mode, the low-dropout regulator 201B is configured such that the absolute value of the voltage difference between the first power supply voltage ELVSS provided by the first power supply signal line PVEE and the first reference voltage Vref1 provided by the first reference voltage signal line REF1 is the same. Thus, through the summing operational amplifier circuit 201A, the value of the first reference voltage Vref1 output from the output terminal 201A-OUT of the summing operational amplifier circuit 201A can be ensured to change synchronously with the first power supply voltage ELVSS provided by the first power supply voltage output terminal 203-ELVSS-OUT of the power management integrated circuit 203 as much as possible.

[0056] Optionally, in the first driving mode of the display device 000, the detection and compensation module 201 is configured such that different driving moments include a first driving moment and a second driving moment. The target display brightness value of the display panel 10 at the first driving moment is a first display brightness value, and the target display brightness value of the display panel at the second driving moment is a second display brightness value; in the first driving mode, the detection and compensation module 201 is configured such that at the first display brightness value and the second display brightness value, the voltage difference between the first power supply voltage ELVSS provided by the first power supply signal line PVEE and the first reference voltage Vref1 provided by the first reference voltage signal line REF1 is the same.

[0057] As Figure 10 shown, Figure 10It is a schematic diagram of the pressure difference corresponding to different driving moments of the display device provided by the embodiments of the present disclosure. The different driving moments of the display device 000 in the first driving mode include the m-th driving moment, the (m + 1)-th driving moment, and the (m + 2)-th driving moment (m is a positive integer). The display brightness value at the m-th driving moment is DBV(m), the display brightness value at the (m + 1)-th driving moment is DBV(m + 1), and the display brightness value at the (m + 2)-th driving moment is DBV(m + 2). At the m-th driving moment, the low-dropout regulator 201B and the adder operational amplifier circuit 201A work together, so that the absolute value of the pressure difference between the first power supply voltage ELVSS provided by the first power supply signal line PVEE and the first reference voltage Vref1 provided by the first reference voltage signal line REF1, that is, the first pressure difference at the m-th driving moment, is ΔV1(m); at the (m + 1)-th driving moment, the low-dropout regulator 201B and the adder operational amplifier circuit 201A work together, so that the absolute value of the pressure difference between the first power supply voltage ELVSS provided by the first power supply signal line PVEE and the first reference voltage Vref1 provided by the first reference voltage signal line REF1, that is, the first pressure difference at the (m + 1)-th driving moment, is ΔV1(m + 1); at the (m + 2)-th driving moment, the low-dropout regulator 201B and the adder operational amplifier circuit 201A work together, so that the absolute value of the pressure difference between the first power supply voltage ELVSS provided by the first power supply signal line PVEE and the first reference voltage Vref1 provided by the first reference voltage signal line REF1, that is, the first pressure difference at the (m + 2)-th driving moment, is ΔV1(m + 2). Then ΔV1(m) = ΔV1(m + 1) = ΔV1(m + 2), realizing that even at different driving moments and different display brightness nodes in the first driving mode, the value of the first reference voltage Vref1 output from the output terminal 201A-OUT of the adder operational amplifier circuit 201A can ensure synchronous change with the first power supply voltage ELVSS provided by the first power supply voltage output terminal 203-ELVSS-OUT of the power management integrated circuit 203.

[0058] In some alternative embodiments, please continue to refer to Figures 1 - 4 、 Figures 7 - 9, in this embodiment, the display device 000 further includes a second driving mode. In the second driving mode, the low-dropout regulator 201B is configured such that the output terminal 201B-OUT of the low-dropout regulator 201B provides a second voltage difference ΔV2. The second voltage difference ΔV2 represents the absolute value of the voltage difference between the first power supply voltage ELVSS provided by the first power supply signal line PVEE and the first reference voltage Vref1 provided by the first reference voltage signal line REF1 at different driving moments in the second driving mode. That is, ΔV2 = ∣ELVSS - Vref1∣. It can be understood that different driving moments of the display device 000 in the second driving mode can be understood as different display brightness value DBV nodes of the display device 000 in the second driving mode. That is, in the second driving mode of the display device 000, the display brightness of the display panel 10 of the display device 000 is adjusted by adjusting the display brightness value DBV. During this process, the low-dropout regulator 201B and the adder operational amplifier circuit 201A of this embodiment work together. As described in the above embodiment, at different display brightness value DBV nodes of the display device 000 in the second driving mode, the low-dropout regulator 201B is configured such that the absolute value of the voltage difference between the first power supply voltage ELVSS provided by the first power supply signal line PVEE and the first reference voltage Vref1 provided by the first reference voltage signal line REF1 is the same. Thus, through the adder operational amplifier circuit 201A, the value of the first reference voltage Vref1 output from the output terminal 201A-OUT of the adder operational amplifier circuit 201A can be ensured to change synchronously with the first power supply voltage ELVSS provided by the first power supply voltage output terminal 203-ELVSS-OUT of the power management integrated circuit 203 as much as possible.

[0059] Optionally, in the second driving mode of the display device 000, the detection compensation module 201 is configured such that different driving moments include a third driving moment and a fourth driving moment. The target display brightness value of the display panel 10 at the third driving moment is the third display brightness value, and the target display brightness value of the display panel at the fourth driving moment is the fourth display brightness value. In the second driving mode, the detection compensation module 201 is configured such that at the third display brightness value and the fourth display brightness value, the voltage difference between the first power supply voltage ELVSS provided by the first power supply signal line PVEE and the first reference voltage Vref1 provided by the first reference voltage signal line REF1 is the same.

[0060] As Figure 11 shown, Figure 11It is a schematic diagram of the pressure difference corresponding to different driving moments of the display device provided by the embodiments of the present disclosure in the second driving mode. Different driving moments of the display device 000 in the second driving mode include the nth driving moment, the (n + 1)th driving moment, and the (n + 2)th driving moment (n is a positive integer). The display brightness value at the nth driving moment is DBV(n), the display brightness value at the (n + 1)th driving moment is DBV(n + 1), and the display brightness value at the (n + 2)th driving moment is DBV(n + 2). At the nth driving moment, the low-dropout regulator 201B and the adder operational amplifier circuit 201A work together, so that the absolute value of the pressure difference between the first power supply voltage ELVSS provided by the first power supply signal line PVEE and the first reference voltage Vref1 provided by the first reference voltage signal line REF1, that is, the first pressure difference at the nth driving moment, is ΔV2(n); at the (n + 1)th driving moment, the low-dropout regulator 201B and the adder operational amplifier circuit 201A work together, so that the absolute value of the pressure difference between the first power supply voltage ELVSS provided by the first power supply signal line PVEE and the first reference voltage Vref1 provided by the first reference voltage signal line REF1, that is, the first pressure difference at the (n + 1)th driving moment, is ΔV2(n + 1); at the (n + 2)th driving moment, the low-dropout regulator 201B and the adder operational amplifier circuit 201A work together, so that the absolute value of the pressure difference between the first power supply voltage ELVSS provided by the first power supply signal line PVEE and the first reference voltage Vref1 provided by the first reference voltage signal line REF1, that is, the first pressure difference at the (n + 2)th driving moment, is ΔV2(n + 2). Then, ΔV2(n) = ΔV2(n + 1) = ΔV2(n + 2), realizing that even at different driving moments and different display brightness nodes in the second driving mode, the value of the first reference voltage Vref1 output from the output terminal 201A - OUT of the adder operational amplifier circuit 201A can ensure synchronous change with the first power supply voltage ELVSS provided by the first power supply voltage output terminal 203 - ELVSS - OUT of the power management integrated circuit 203.

[0061] Optionally, in this embodiment, the first voltage difference ΔV1 provided at the output terminal 201B-OUT of the low-dropout regulator 201B when the display device 000 is in the first driving mode, and the second voltage difference ΔV2 provided at the output terminal 201B-OUT of the low-dropout regulator 201B when the display device 000 is in the second driving mode can be the same, ΔV1(m) = ΔV1(m+1) = ΔV1(m+2) = ΔV2(n) = ΔV2(n+1) = ΔV2(n+2), that is, when the display device 000 is driving the display, regardless of whether the display device 000 is in the first driving mode or the second driving mode, the same fixed voltage difference between the first power supply voltage ELVSS and the first reference voltage Vref1 can be shared. When the display device 000 is driving, no matter how the first power supply voltage ELVSS provided by the first power supply signal line PVEE changes and adjusts, through the combined action of the low-dropout regulator 201B and the adder operational amplifier circuit 201A, the first reference voltage Vref1 provided by the first reference voltage signal line REF1 can be made to change synchronously with it.

[0062] Optionally, in this embodiment, the first voltage difference ΔV1 provided at the output terminal 201B-OUT of the low dropout regulator 201B in the first driving mode of the display device 000 and the second voltage difference ΔV2 provided at the output terminal 201B-OUT of the low dropout regulator 201B in the second driving mode of the display device 000 may be different. The ΔV1 in the first driving mode is the same, ΔV1(m) = ΔV1(m+1) = ΔV1(m+2), and the ΔV2 in the second driving mode is the same, ΔV2(n) = ΔV2(n+1) = ΔV2(n+2), but ΔV1 is not equal to ΔV2. That is, when the display device 000 is driving the display and the first power supply voltage ELVSS provided by the first power supply signal line PVEE changes and is adjusted at different driving times in the first driving mode, through the combined action of the low dropout regulator 201B and the summing operational amplifier circuit 201A, the first reference voltage Vref1 provided by the first reference voltage signal line REF1 changes synchronously therewith; when the first power supply voltage ELVSS provided by the first power supply signal line PVEE changes and is adjusted at different driving times in the second driving mode, through the combined action of the low dropout regulator 201B and the summing operational amplifier circuit 201A, the first reference voltage Vref1 provided by the first reference voltage signal line REF1 changes synchronously therewith. However, in the first driving mode and the second driving mode, the voltage difference between the first power supply voltage ELVSS provided by the first power supply signal line PVEE and the first reference voltage Vref1 provided by the first reference voltage signal line REF1 may be different. The ΔV1 in the first driving mode and the ΔV2 in the second driving mode can be set separately, so that the driving mode of the display device 000 can be flexibly selected, and different fixed voltage differences between the first power supply voltage ELVSS and the first reference voltage Vref1 in different driving modes can be realized, making the application scenarios of the display device 000 wider and more flexible.

[0063] In some alternative embodiments, please refer to Figures 1 - 4 、 Figures 7 - 9 and Figure 12 , Figure 12 FIG. is a schematic diagram of different voltage differences between the first power supply voltage and the first reference voltage of the display device provided by the embodiments of the present disclosure in different driving modes. In this embodiment, the refresh rate FrameRate1 of the display device 000 in the first driving mode is different from the refresh rate FrameRate2 of the display device 000 in the second driving mode;

[0064] The first voltage difference ΔV1 and the second voltage difference ΔV2 are different.

[0065] Optionally, the refresh rate FrameRate1 of the display device 000 in the first driving mode is less than the refresh rate FrameRate2 of the display device 000 in the second driving mode, and the first voltage difference ΔV1 is less than the second voltage difference ΔV2.

[0066] This embodiment explains that the display device 000 may include multiple driving modes, such as at least including a first driving mode and a second driving mode, or may further include a third driving mode and a fourth driving mode. The refresh frequencies of the display device 000 under different driving modes are different, so that the display device 000 can be applied to different usage environments. In this embodiment, when the display device 000 is under driving modes with different refresh frequencies, the voltage difference between the first power supply voltage ELVSS provided by the first power supply signal line PVEE and the first reference voltage Vref1 provided by the first reference voltage signal line REF1 is different. However, under the same driving mode, the voltage difference between the first power supply voltage ELVSS provided by the first power supply signal line PVEE and the first reference voltage Vref1 provided by the first reference voltage signal line REF1 remains the same. For example, if the refresh frequency FrameRate1 of the display device 000 in the first driving mode is less than the refresh frequency FrameRate2 of the display device 000 in the second driving mode, then the first voltage difference ΔV1 is less than the second voltage difference ΔV2. If the refresh frequency FrameRate2 of the display device 000 in the second driving mode is less than the refresh frequency FrameRate3 of the display device 000 in the third driving mode, then the second voltage difference ΔV2 is less than the third voltage difference ΔV3. If the refresh frequency FrameRate3 of the display device 000 in the third driving mode is less than the refresh frequency FrameRate4 of the display device 000 in the fourth driving mode, then the third voltage difference ΔV3 is less than the fourth voltage difference ΔV4. Since the leakage current situation of the display device 000 is different under driving modes with different refresh frequencies, the required voltage difference between the first power supply voltage ELVSS provided by the first power supply signal line PVEE and the first reference voltage Vref1 provided by the first reference voltage signal line REF1 is different. Generally, the lower the refresh frequency, the smaller the voltage difference between the first power supply voltage ELVSS provided by the first power supply signal line PVEE and the first reference voltage Vref1 provided by the first reference voltage signal line REF1. Thus, while the display device 000 can adapt to different display environments and usage requirements, it can also ensure the display effect of the display device 000 under different driving modes and avoid the problem of screen flicker.

[0067] It can be understood that the different fixed voltage differences between the first power supply voltage ELVSS and the first reference voltage Vref1 provided under different driving modes in this embodiment can be preset by the low-dropout regulator 201B. When the display device 000 selects different driving modes, such as different refresh frequencies, the output terminal 201B - OUT of the low-dropout regulator 201B outputs the preset fixed voltage difference value corresponding to the current driving mode between the first power supply voltage ELVSS and the first reference voltage Vref1.

[0068] In some alternative embodiments, please refer to Figures 1 - 4 , Figures 7 - 10 and Figure 13 . Figure 13 is a schematic diagram showing different voltage differences between the first power supply voltage and the first reference voltage of the display device provided in the embodiments of the present disclosure in the first driving mode. In this embodiment, the first driving mode of the display device 000 includes multiple display frames, and the multiple display frames include a refresh frame RF (Refresh Frame) and first hold frames HF1 (Hold Frame1), second hold frames HF2 (Hold Frame2), and third hold frames HF3 (Hold Frame3) sequentially executed after the refresh frame;

[0069] The different driving moments include the second hold frame HF2 and the third hold frame HF3.

[0070] Optionally, in the first driving mode, the detection and compensation module 201 is further configured to:

[0071] In the refresh frame RF, control the voltage difference ΔV1 between the first power supply voltage ELVSS provided by the first power supply signal line PVEE and the first reference voltage Vref1 provided by the first reference voltage signal line REF1 to be a first value ΔV1-0;

[0072] In the first hold frame HF1, control the voltage difference ΔV1 between the first power supply voltage ELVSS provided by the first power supply signal line PVEE and the first reference voltage Vref1 provided by the first reference voltage signal line REF1 to be a second value ΔV1-1;

[0073] The first value ΔV1-0 is different from the second value ΔV1-1.

[0074] Optionally, in the second hold frame HF2, the detection and compensation module 201 controls the voltage difference ΔV1 between the first power supply voltage ELVSS provided by the first power supply signal line PVEE and the first reference voltage Vref1 provided by the first reference voltage signal line REF1 to be a third value ΔV1-2;

[0075] The first value ΔV1-0 is different from the third value ΔV1-2, and the second value ΔV1-1 is different from the third value ΔV1-2.

[0076] This embodiment explains the different driving times of the display device 000 in the first driving mode, which can be understood as other holding frames of the display device 000 in the first driving mode except for the first holding frame HF1. Specifically, the first driving mode of the display device 000 includes a plurality of display frames, and the plurality of display frames include a refresh frame RF and other holding frames such as the first holding frame HF1, the second holding frame HF2, and the third holding frame HF3 that are sequentially executed after the refresh frame. Through the combined action of the low-dropout regulator 201B and the adder operational amplifier circuit 201A, different driving times with the same voltage difference between the first power supply voltage ELVSS provided by the first power supply signal line PVEE and the first reference voltage Vref1 provided by the first reference voltage signal line REF1 refer to the second holding frame HF2 and the third holding frame HF3 that are executed after the refresh frame RF and after the first holding frame HF1. In order to achieve low-frequency driving, that is, a low refresh rate, the display device 000 generally selects to use skip Frame, that is, frame skipping control, such as Figure 13Among the multiple display frames shown, the previous frame is a refresh frame (refresh frequency: 120 Hz), and the following three frames are hold frames (indicating no refresh of image information). In this way, the refresh frequency of the display device 000 controlled is 30 Hz (1 frame refresh + 3 frames hold). In the first driving mode of the display device 000, through the combined action of the low-dropout regulator 201B and the summing operational amplifier circuit 201A, different driving moments when the voltage difference between the first power supply voltage ELVSS provided by the first power supply signal line PVEE and the first reference voltage Vref1 provided by the first reference voltage signal line REF1 is the same refer to the second hold frame HF2 and the third hold frame HF3. That is, in the first driving mode of the display device 000, during the refresh frame RF, through the combined action of the low-dropout regulator 201B and the summing operational amplifier circuit 201A, the voltage difference between the first power supply voltage ELVSS provided by the first power supply signal line PVEE and the first reference voltage Vref1 provided by the first reference voltage signal line REF1 is the first value ΔV1-0; during the first hold frame HF1, through the combined action of the low-dropout regulator 201B and the summing operational amplifier circuit 201A, the voltage difference between the first power supply voltage ELVSS provided by the first power supply signal line PVEE and the first reference voltage Vref1 provided by the first reference voltage signal line REF1 is the second value ΔV1-1; during the second hold frame HF2, through the combined action of the low-dropout regulator 201B and the summing operational amplifier circuit 201A, the voltage difference between the first power supply voltage ELVSS provided by the first power supply signal line PVEE and the first reference voltage Vref1 provided by the first reference voltage signal line REF1 is the third value ΔV1-2; during the third hold frame HF3, through the combined action of the low-dropout regulator 201B and the summing operational amplifier circuit 201A, the voltage difference between the first power supply voltage ELVSS provided by the first power supply signal line PVEE and the first reference voltage Vref1 provided by the first reference voltage signal line REF1 is also ΔV1-2. The refresh frequency of the refresh frame RF is greater than the refresh frequency of the first hold frame HF1, greater than the refresh frequency of the second hold frame HF2, and greater than the refresh frequency of the third hold frame HF3. Therefore, ΔV1-0 can be greater than ΔV1-1, ΔV1-0 can be greater than ΔV1-2, and ΔV1-2 can be greater than ΔV1-1. Thus, in the first driving mode of the display device 000, during different driving moments of the second hold frame HF2 and the third hold frame HF3, through the combined action of the low-dropout regulator 201B and the summing operational amplifier circuit 201A, the voltage difference between the first power supply voltage ELVSS provided by the first power supply signal line PVEE and the first reference voltage Vref1 provided by the first reference voltage signal line REF1 is the same, and the voltage differences between the first power supply voltage ELVSS and the first reference voltage Vref1 of the remaining refresh frame RF and the first hold frame HF1 are different from it, which is beneficial to improving the screen flickering problem and can also achieve flexible control of the display device.

[0077] It can be understood that in this embodiment, Figure 13 taking the multiple display frames of the display device 000 in the first driving mode including a refresh frame and first holding frames, second holding frames, and third holding frames sequentially executed after the refresh frame as an example, the low-frequency driving effect of the display device is achieved. In specific implementation, the number of holding frames includes but is not limited to this, and can be specifically set according to actual requirements.

[0078] In some other alternative embodiments, please refer to Figures 1 - 4 、 Figures 7 - 10 and Figure 14 , Figure 14 which is another schematic diagram of the different voltage differences between the first power supply voltage and the first reference voltage of the display device provided by the embodiments of the present disclosure in the first driving mode. In order to achieve low-frequency driving, that is, a low refresh rate, the display device 000 can also choose to use skip EM, that is, skip the EM pulse (light emission control signal pulse) control. As Figure 14 shown in the multiple skip EM regions, the previous region is the active region (Active region), and the added Skip EM regions behind belong to the porch region (belonging to the blank region). By increasing the number of EM pulses in the porch region, the total number of display rows will increase, thereby achieving a frequency reduction. In the first driving mode of the display device 000, through the combined action of the low-dropout regulator 201B and the adder operational amplifier circuit 201A, different driving moments with the same voltage difference between the first power supply voltage ELVSS provided by the first power supply signal line PVEE and the first reference voltage Vref1 provided by the first reference voltage signal line REF1 refer to other porch regions except the first porch region in the porch region, as Figure 14As shown, in the first driving mode of the display device 000, skip EM control is used to achieve low-frequency driving. In the Active area in the first driving mode, through the combined action of the low-dropout regulator 201B and the adder operational amplifier circuit 201A, the voltage difference between the first power supply voltage ELVSS provided by the first power supply signal line PVEE and the first reference voltage Vref1 provided by the first reference voltage signal line REF1 is the first value ΔV1-3; in the first porch area, through the combined action of the low-dropout regulator 201B and the adder operational amplifier circuit 201A, the voltage difference between the first power supply voltage ELVSS provided by the first power supply signal line PVEE and the first reference voltage Vref1 provided by the first reference voltage signal line REF1 is the second value ΔV1-4; in the second porch area, through the combined action of the low-dropout regulator 201B and the adder operational amplifier circuit 201A, the voltage difference between the first power supply voltage ELVSS provided by the first power supply signal line PVEE and the first reference voltage Vref1 provided by the first reference voltage signal line REF1 is the third value ΔV1-5; in the third porch area, through the combined action of the low-dropout regulator 201B and the adder operational amplifier circuit 201A, the voltage difference between the first power supply voltage ELVSS provided by the first power supply signal line PVEE and the first reference voltage Vref1 provided by the first reference voltage signal line REF1 is also ΔV1-5. ΔV1-3 can be greater than ΔV1-4, ΔV1-3 can be greater than ΔV1-5, and ΔV1-5 can be greater than ΔV1-3. Thus, in the first driving mode of the display device 000, at different driving times in the second porch area and the third porch area, through the combined action of the low-dropout regulator 201B and the adder operational amplifier circuit 201A, the voltage difference between the first power supply voltage ELVSS provided by the first power supply signal line PVEE and the first reference voltage Vref1 provided by the first reference voltage signal line REF1 is the same, and the voltage differences between the first power supply voltage ELVSS and the first reference voltage Vref1 in the remaining Active area and the first porch area are different from it. This is beneficial to improving the screen flicker problem and can also achieve flexible control of the display device.

[0079] It should be noted that, in this document, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variation thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements but also includes other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising said element.

[0080] The above are only specific embodiments of the present disclosure, enabling those skilled in the art to understand or implement the present disclosure. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments described herein, but rather to the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display device, characterized in that, It includes a display panel and a driving chip; The display panel includes a plurality of sub-pixels, a first reference voltage signal line, and a first power supply signal line; The sub-pixel includes a pixel circuit and a light-emitting element connected electrically; the pixel circuit includes at least a driving module and an anode reset module, a first end of the anode reset module is electrically connected to the first reference voltage signal line, a second end of the anode reset module is electrically connected to an anode of the light-emitting element, the driving module is electrically connected to the anode of the light-emitting element, and a cathode of the light-emitting element is electrically connected to the first power supply signal line; The driving chip includes a detection and compensation module, the detection and compensation module includes an addition operational amplifier circuit and a low-dropout regulator, the first power supply signal line is electrically connected to a first input terminal of the addition operational amplifier circuit, an output terminal of the low-dropout regulator is electrically connected to a second input terminal of the addition operational amplifier circuit, and an output terminal of the addition operational amplifier circuit is electrically connected to the first reference voltage signal line; The display device includes a first driving mode, in the first driving mode, the detection and compensation module is configured to control a pressure difference between a first power supply voltage provided by the first power supply signal line and a first reference voltage provided by the first reference voltage signal line to be the same at different driving moments.

2. The display device according to claim 1, characterized in that, The driving chip includes a display driving chip and a power management integrated circuit; the display driving chip is bound and electrically connected to the display panel, the power management integrated circuit includes at least a first power supply voltage output terminal, and the first power supply voltage output terminal is electrically connected to the first power supply signal line.

3. The display device according to claim 2, characterized in that The first power supply voltage output terminal is electrically connected to the first input terminal of the addition operational amplifier circuit, the first power supply voltage output terminal is further electrically connected to a first input pin of the display driving chip, the first input pin of the display driving chip is electrically connected to a first output pin of the display driving chip, and the first output pin of the display driving chip is electrically connected to the first power supply signal line.

4. The display device according to claim 2, characterized in that, The first power supply voltage output terminal is electrically connected to the first input pin of the display driving chip, the first input pin of the display driving chip is electrically connected to the first output pin of the display driving chip, the first output pin of the display driving chip is electrically connected to the first power supply signal line, and the first output pin of the display driving chip is further electrically connected to the first input terminal of the addition operational amplifier circuit.

5. The display device according to claim 2, characterized in that, The output terminal of the addition operational amplifier circuit is electrically connected to a second input pin of the display driving chip, the second input pin of the display driving chip is electrically connected to a second output pin of the display driving chip, and the second output pin of the display driving chip is electrically connected to the first reference voltage signal line.

6. The display device according to claim 1, characterized in that, In the first driving mode, the low-dropout regulator is configured to provide a first pressure difference at an output terminal of the low-dropout regulator, and the first pressure difference represents an absolute value of a pressure difference between a first power supply voltage provided by the first power supply signal line and a first reference voltage provided by the first reference voltage signal line at different driving moments in the first driving mode.

7. The display device according to claim 6, characterized in that, The display device further includes a second driving mode. In the second driving mode, the low-dropout regulator is configured such that the output terminal of the low-dropout regulator provides a second voltage difference, and the second voltage difference represents the absolute value of the voltage difference between the first power supply voltage provided by the first power supply signal line and the first reference voltage provided by the first reference voltage signal line at different driving times in the second driving mode.

8. The display device according to claim 7, characterized in that, The first voltage difference is the same as the second voltage difference; or, the first voltage difference is different from the second voltage difference.

9. The display device according to claim 7, wherein The refresh frequency of the display device in the first driving mode is different from the refresh frequency of the display device in the second driving mode; The first voltage difference is different from the second voltage difference.

10. The display device according to claim 7, characterized in that, The refresh frequency of the display device in the first driving mode is less than the refresh frequency of the display device in the second driving mode, and the first voltage difference is less than the second voltage difference.

11. The display device according to claim 1, wherein In the first driving mode, the detection compensation module is configured such that different driving times include a first driving time and a second driving time. The target display brightness value of the display panel at the first driving time is a first display brightness value, and the target display brightness value of the display panel at the second driving time is a second display brightness value; In the first driving mode, the detection compensation module is configured such that at the first display brightness value and the second display brightness value, the voltage difference between the first power supply voltage provided by the first power supply signal line and the first reference voltage provided by the first reference voltage signal line is the same.

12. The display device according to claim 1, characterized in that, The first driving mode includes a plurality of display frames, and the plurality of display frames include a refresh frame and a first holding frame, a second holding frame, and a third holding frame sequentially executed after the refresh frame; Different driving times include the second holding frame and the third holding frame.

13. The display device according to claim 12, wherein In the first driving mode, the detection compensation module is further configured to: In the refresh frame, control the voltage difference between the first power supply voltage provided by the first power supply signal line and the first reference voltage provided by the first reference voltage signal line to be a first value; In the first holding frame, control the voltage difference between the first power supply voltage provided by the first power supply signal line and the first reference voltage provided by the first reference voltage signal line to be a second value; The first value is different from the second value.

14. The display device according to claim 13, characterized in that, In the second holding frame, the detection compensation module controls the voltage difference between the first power supply voltage provided by the first power supply signal line and the first reference voltage provided by the first reference voltage signal line to be a third value; The first value is different from the third value, and the second value is different from the third value.

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