Power semiconductor packaging structure

Abstract

The invention discloses a power semiconductor packaging structure which comprises a substrate, a power semiconductor chip, a PCB and a packaging sealing layer. The substrate upper conductive metal layer comprises a left side metal layer and a right side metal layer which are physically separated by a separation groove and are electrically insulated; a sinking left mounting platform is arranged on the side, close to the separation groove, of the left metal layer, a sinking right mounting platform is arranged in the middle of the right metal layer, the right mounting platform is used for arranging a chip, and the PCB is erected on the left mounting platform and the right mounting platform; the drain electrode of the chip is interconnected with the right mounting platform; the left side metal layer is connected to a chip source electrode through the PCB, the PCB is provided with an extension part used for being connected with an external driving circuit of the power semiconductor packaging structure on the edge of one side of the right side metal layer, and the extension part enables a grid electrode and the source electrode of the chip to be connected with a driving circuit of an external circuit. A substrate connecting part electrically connected with the left mounting platform is arranged on the back surface of the PCB; and a chip connecting part interconnected with the source electrode of the chip is arranged on the back surface of the PCB.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a power semiconductor packaging structure. Background Art

[0002] Power semiconductor packaging is an industrial product that allows power semiconductor chips to be electrically connected to external circuit boards, thermally connected to external heat sinks, and protect power semiconductor chips. The packaging of power semiconductors has the following functions: providing electrical contact with the semiconductor chip, usually completed by bonding wires, ensuring connection with the electrical interface outside the package; providing sufficient connection to the heat sink and cooling system paths so that they can dissipate hundreds or thousands of watts of heat loss; the package must also protect the semiconductor from environmental influences, especially from the intrusion of moisture.

[0003] Existing power semiconductor packaging structures are very diverse. For example, CN 219435850U discloses a MOSFET chip power semiconductor packaging structure, which includes a plastic-encapsulated shell and a silicon chip arranged in the plastic-encapsulated shell. The plastic-encapsulated shell is also provided with a plurality of copper strips bonded to the top of the silicon chip, source pins and gate pins respectively bonded to one end of different copper strips, a drain pin bonded to the bottom of the silicon chip, and a heat-conducting base plate connected to the bottom of the drain pin. A metal shell is coated and bonded on the plastic-encapsulated shell, and heat is conducted to the PCB base plate through the drain pin and the heat-conducting base plate, providing more heat dissipation contact area, and taking heat away from the silicon chip. At the same time, by providing a metal shell on the plastic-encapsulated shell, the metal shell is wrapped around the extended end of the drain pin, so that heat can also be conducted to the metal shell. The heat is dissipated through the metal shell, and the heat dissipation effect is better. When the current demand increases, the heat dissipation demand can still be met, and the PCB thermal saturation phenomenon is avoided.

[0004] The preparation process of the power semiconductor device packaging structure disclosed in the document CN110676176B is that by setting a flexible conductive layer and an insulating plate covered with a conductive layer on both sides, the E electrode does not directly act on the chip component, the current of the chip component reaches the E electrode through the flexible conductive layer, and the heat of the chip component is vertically conducted to the heat dissipation medium through the flexible conductive layer (for example, heat is transferred to the electrodes around), and the first conductive protrusion receives the flexible conductive layer, which disperses the compressive stress acting on the chip component. The flexible conductive layer realizes a smaller compressive stress on the welding surface of the chip component, avoids a larger pressure directly acting on the surface of the chip component, reduces the three-dimensional stress damage under high pressure stress conditions during temperature cycling of the chip component, improves the connection reliability, realizes the decoupling of pressure from conductivity and thermal conductivity, and finally improves the reliability of the power semiconductor device packaging structure.

[0005] The packaging structure of the power semiconductor device disclosed in Document CN114551378A belongs to the technical field of the installation structure of semiconductor power devices, and at least solves the technical problem in the prior art that the structure arranged in a leadless manner results in low heat dissipation efficiency of the power device. It includes a packaging container and a radiator partially embedded at the top of the packaging container. A heat dissipation component is arranged in the packaging container. The heat dissipation component can clamp or wrap the power device, can conduct electricity with the power device, and is in contact with the radiator. Among them: the heat generated when the power device works is transferred to the radiator in a heat conduction manner through the heat dissipation component to cool or dissipate heat from the power device. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a power semiconductor packaging structure with stable performance and good heat dissipation.

[0007] To solve the above technical problem, the technical solution adopted by the present invention is: a power semiconductor packaging structure, including a substrate, a power semiconductor chip, and an interconnection printed circuit board PCB connecting the corresponding parts of the power semiconductor chip and the substrate; a packaging sealing layer wrapping the power semiconductor chip and the interconnection printed circuit board PCB is arranged on the substrate;

[0008] The substrate includes an intermediate insulating layer, an upper conductive metal layer of the substrate, and a lower conductive metal layer of the substrate. The lower conductive metal layer of the substrate is used to connect to the radiator; the upper conductive metal layer of the substrate includes a left metal layer and a right metal layer physically separated and electrically insulated by a separation groove; a sunken left mounting platform is arranged on one side of the left metal layer close to the separation groove, and a sunken right mounting platform is arranged in the middle part of the right metal layer. The right mounting platform is used to set the power semiconductor chip, and the interconnection printed circuit board PCB is erected on the left mounting platform and the right mounting platform;

[0009] The drain of the power semiconductor chip is located at the bottom, and the source and gate of the power semiconductor chip are located at the top; the drain of the power semiconductor chip is interconnected with the right mounting platform; the left metal layer is connected to the source of the power semiconductor chip through the interconnection printed circuit board PCB. An extension part for connecting to the external drive circuit of the power semiconductor packaging structure is arranged on the edge of the interconnection printed circuit board PCB close to the right metal layer side. The extension part connects the source and gate of the power semiconductor chip to the drive circuit of the external circuit;

[0010] The interconnection printed circuit board PCB includes an insulating substrate. A substrate connection part is arranged on the reverse side of the interconnection printed circuit board PCB. The substrate connection part is electrically connected to the left mounting platform on the substrate. The higher surface of the copper layer of the left metal layer serves as the interface of the entire power semiconductor packaging structure to the outside; a power semiconductor chip connection part interconnected with the source of the power semiconductor chip is arranged on the reverse side of the interconnection printed circuit board PCB;

[0011] Between the corresponding part of the substrate on the front side and the connection part of the substrate on the back side of the interconnected printed circuit board (PCB), there are several first conductive vias for electrical interconnection; on the back side of the interconnected PCB, there is a gate connection part connected to the gate, and between the chip corresponding part on the front side of the interconnected PCB and the power semiconductor chip connection part on the back side, there are several second conductive vias for electrical interconnection;

[0012] The protruding part of the interconnected PCB and the top surfaces of the left and right metal layers at the two far ends on the substrate expose the encapsulation sealing layer for interconnection with the external main circuit.

[0013] As a preferred solution, the interconnected PCB is provided with several vertically penetrating glue injection holes for allowing the sealing material of the encapsulation sealing layer to penetrate into the free space below the interconnected PCB during encapsulation.

[0014] As a preferred solution, the extension part is provided with a backside conductive part conducting with the gate connection part and a front side conductive part conducting with the source connection part.

[0015] The beneficial effects of the present invention are:

[0016] This encapsulation structure realizes the cancellation of parasitic inductance in the encapsulation and reduces it to a very low level; reduces the parasitic parameters in the power semiconductor package and improves the high-frequency performance of the circuit; and the negative coupling design between the chip and the DC bus further reduces the parasitic inductance; adopts injection molding or silicone encapsulation to realize the sealing protection of the chip and prevent the intrusion of moisture and other environmental factors;

[0017] Due to the flexible PCB design with several vertically penetrating through holes for allowing the sealing material of the encapsulation sealing layer to penetrate into the free space below the interconnected PCB during encapsulation, it is convenient for the encapsulation material to penetrate better, making the encapsulated structure more firm, further ensuring the reliability of use, and improving the sealing performance and electrical isolation effect.

[0018] This structure can directly form the chip mounting groove and the electrical connection area through the step etching process, reducing the complexity of multi-step processing in traditional encapsulation; and adopts connection processes such as silver sintering or welding to provide a reliable and efficient assembly method.

[0019] This flexible PCB structure of the present invention provides a stress relief function, effectively reducing the influence of thermal expansion or mechanical vibration on the chip connection; and can use high thermal conductivity isolation substrates such as DBC or AMB, effectively reducing the thermal resistance during device operation; the step etching design ensures the close contact between the chip and the substrate, thereby optimizing the heat conduction path. Description of the Drawings

[0020] Figure 1 It is a schematic diagram of the internal structure of the power semiconductor package structure.

[0021] Figure 2 It is a schematic structural diagram of a power semiconductor chip.

[0022] Figure 3 It is a schematic structural diagram of an interconnected printed circuit board (PCB).

[0023] Figure 4 It is a schematic structural diagram of a power semiconductor package structure connected to a main circuit circuit board.

[0024] Figure 5 It is a schematic overall diagram after the power semiconductor package structure is encapsulated.

[0025] In the figure: power semiconductor package structure 100, substrate 200, power semiconductor chip 300, interconnected printed circuit board (PCB) 400, encapsulation sealing layer 600;

[0026] Upper conductive metal layer 201 of the substrate, intermediate insulating layer 202, lower conductive metal layer 203 of the substrate, right mounting platform 204, separation groove 205, right metal layer 206, left metal layer 207, left mounting platform 208;

[0027] Source electrode 301, gate electrode 302, drain electrode 303; extension part 401, insulating substrate 402;

[0028] Corresponding part 410 of the substrate, corresponding part 411 of the chip, front conductive part 412, potting hole 413;

[0029] Substrate connection part 420, first conductive via 421, power semiconductor chip connection part 422, gate connection part 423, back conductive part 424. Specific embodiments

[0030] The following will describe in detail the specific implementation schemes of the present invention in conjunction with the accompanying drawings.

[0031] As Figures 1-5 shown, the power semiconductor package structure 100 includes a substrate 200, a power semiconductor chip 300, and an interconnected printed circuit board (PCB) 400 that connects the corresponding parts of the power semiconductor chip 300 and the substrate 200; an encapsulation sealing layer 600 that wraps the power semiconductor chip 300 and the interconnected printed circuit board (PCB) 400 is provided on the substrate;

[0032] As Figure 1As shown, the substrate 200 includes an intermediate insulating layer 202, an upper conductive metal layer 201 of the substrate, and a lower conductive metal layer 203 of the substrate. The lower conductive metal layer 203 of the substrate is used to connect to a radiator. A power semiconductor chip 300 is disposed on the upper conductive metal layer 201 of the substrate, and the upper conductive metal layer 201 of the substrate serves as a part of electrical connection to connect the power semiconductor chip 300 to other circuit boards or conductors;

[0033] The upper conductive metal layer 201 of the substrate includes a left metal layer 207 and a right metal layer 206 that are physically separated and electrically insulated by a separation groove 205; a sunken left mounting platform 208 is provided on one side of the left metal layer 207 close to the separation groove 205, and a sunken right mounting platform 204 is provided in the middle part of the right metal layer 206. The right mounting platform 204 is used to dispose the power semiconductor chip 300. The interconnection printed circuit board PCB 400 is erected on the left mounting platform 208 and the right mounting platform 204; the drain 303 of the power semiconductor chip is interconnected with the right mounting platform 204;

[0034] As Figure 2 shown, the drain 303 of the power semiconductor chip 300 is located at the bottom, and the source 301 and gate 302 of the power semiconductor chip 300 are located at the top;

[0035] The left metal layer 207 is connected to the source 301 of the power semiconductor chip 300 through the interconnection printed circuit board PCB 400. The interconnection printed circuit board PCB 400 is provided with an extension part 401 for connecting to an external drive circuit of the power semiconductor package structure on the edge close to the right metal 206. The extension part 401 connects the gate 302 and source 301 of the power semiconductor chip to the drive circuit of the external circuit.

[0036] As Figure 3 shown, the interconnection printed circuit board PCB 400 includes an insulating substrate 402. A substrate connection part 420 is provided on the reverse side of the interconnection printed circuit board PCB. The substrate connection part 420 is electrically connected to the left mounting platform 208 on the substrate 200. The higher surface of the copper layer of the left metal layer 207 serves as an interface of the entire power semiconductor package structure 100 to the outside; a power semiconductor chip connection part 422 interconnected with the source 301 of the power semiconductor chip is provided on the reverse side of the interconnection printed circuit board PCB 400;

[0037] Between the substrate corresponding part 410 on the front side and the substrate connection part 420 on the back side of the interconnected printed circuit board PCB400, there are several first conductive vias 421 for electrical interconnection; on the back side of the interconnected printed circuit board PCB400, there is a gate connection part 423 connected to the gate 302, on the extension part 401, there is a back-side conductive part 424 conducting with the gate connection part 423 and a front-side conductive part 412 conducting with the source connection part 422; between the chip corresponding part 411 on the front side and the power semiconductor chip connection part 422 on the back side of the interconnected printed circuit board PCB400, there are several second conductive vias for electrical interconnection.

[0038] On the interconnected printed circuit board PCB400, there are several glue injection holes 413 that penetrate up and down and are used to allow the sealing material of the encapsulation sealing layer 600 to penetrate into the free space below the interconnected printed circuit board PCB400 during encapsulation.

[0039] The protrusion 401 of the interconnected printed circuit board PCB400 for connecting to an external drive circuit and the top surfaces of the left and right metal layers 207 and 206 at the two far ends on the substrate are exposed from the encapsulation sealing layer 600 for interconnection with an external main circuit. It can be directly connected to the main circuit board 500, as Figure 4 shown.

[0040] This structure is applicable to both vertical-structured power semiconductors (such as SiC MOSFETs) and can also be extended to other types of power devices, such as laterally-structured devices.

[0041] The above embodiments are only illustrative of the principles and effects of the present invention and some applied embodiments, rather than limiting the present invention; it should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all fall within the protection scope of the present invention.

Claims

1. A power semiconductor package structure (100) includes a substrate (200), a power semiconductor chip (300), and an interconnected printed circuit board PCB (400) connecting corresponding parts on the power semiconductor chip (300) and the substrate (200); characterized in that: The substrate is provided with a packaging and sealing layer (600) that wraps the power semiconductor chip (300) and the interconnection printed circuit board PCB (400). The substrate (200) includes an intermediate insulating layer (202), an upper conductive metal layer (201) of the substrate, and a lower conductive metal layer (203) of the substrate. The lower conductive metal layer (203) of the substrate is used to connect to the radiator. The upper conductive metal layer (201) of the substrate includes a left metal layer (207) and a right metal layer (206) that are physically separated and electrically insulated by a separation groove (205). On one side of the left metal layer (207) close to the separation groove (205), there is a sunken left mounting platform (208). In the middle part of the right metal layer (206), there is a sunken right mounting platform (204). The right mounting platform (204) is used to set the power semiconductor chip (300). The interconnection printed circuit board PCB (400) is erected on the left mounting platform (208) and the right mounting platform (204). The drain (303) of the power semiconductor chip (300) is located at the bottom, and the source (301) and gate (302) of the power semiconductor chip (300) are located at the top. The drain (303) of the power semiconductor chip is interconnected with the right mounting platform (204). The left metal layer (207) is connected to the source (301) of the power semiconductor chip (300) through the interconnection printed circuit board PCB (400). On the edge of the interconnection printed circuit board PCB (400) close to the right metal layer (206), there is an extension part (401) for connecting to the external drive circuit of the power semiconductor packaging structure. The extension part (401) connects the source (301) and gate (302) of the power semiconductor chip (300) to the drive circuit of the external circuit. The interconnection printed circuit board PCB (400) includes an insulating substrate (402). On the reverse side of the interconnection printed circuit board PCB, there is a substrate connection part (420). The substrate connection part (420) is electrically connected to the left mounting platform (208) on the substrate (200). The higher surface of the copper layer of the left metal layer (207) serves as the interface of the entire power semiconductor packaging structure (100) to the outside. On the reverse side of the interconnection printed circuit board PCB (400), there is a power semiconductor chip connection part (422) interconnected with the source (301) of the power semiconductor chip. Between the substrate corresponding part (410) on the front side of the interconnection printed circuit board PCB (400) and the substrate connection part (420) on the reverse side, there is electrical interconnection through a number of first conductive vias. On the reverse side of the interconnection printed circuit board PCB (400), there is a gate connection part (423) connected to the gate (302). The chip corresponding part (411) on the front side of the interconnection printed circuit board PCB (400) and the power semiconductor chip connection part (422) on the reverse side are electrically interconnected through a number of second conductive vias. The protruding part (401) of the interconnection printed circuit board PCB (400) and the top surfaces of the two distal left metal layer (207) and right metal layer (206) on the substrate are exposed from the packaging and sealing layer (600) for interconnection with the external main circuit.

2. The power semiconductor package structure according to claim 1, wherein: The interconnected printed circuit board PCB (400) is provided with a plurality of glue injection holes (411) that penetrate up and down and are used to allow the sealing material of the encapsulation sealing layer (600) to penetrate into the free space below the interconnected printed circuit board PCB (400) during encapsulation.

3. A power semiconductor package structure according to claim 1, characterized in that: The extension part (401) is provided with a reverse conductive part (424) that conducts with the gate connection part (423) and a front conductive part (412) that conducts with the source connection part (422).

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