Signal processing method and device and FPGA

Abstract

The invention provides a signal processing method and device and an FPGA, and relates to the technical field of signal processing. The method comprises the following steps: performing signal multiplexing on an input signal to obtain at least two paths of parallel signals; resampling is carried out on each path of parallel signal in the at least two paths of parallel signals at different delay times to obtain at least two paths of resampled signals, and the different delay times are used for covering periodic uniform distribution points in a symbol period corresponding to the input signal; and determining a first target data sequence according to the at least two paths of resampling signals, wherein the delay time of the resampling signals corresponding to the first target data sequence points to a correct sampling moment. According to the method, a multi-path signal parallel and multi-delay resampling mode is adopted to attempt to cover all possibly available sampling points so as to realize bit synchronization, so that the calculation complexity of a bit synchronization step is reduced, the signal processing efficiency is improved, and the requirement on hardware resources is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of signal processing, and in particular, to a signal processing method, apparatus, and FPGA. Background Art

[0002] In digital communication, a receiver is responsible for recovering original data from a radio frequency signal. The signal processing steps of the receiver include down-conversion, decimation filtering, frequency synchronization, matched filtering, demodulation, phase ambiguity resolution, bit synchronization, frame synchronization, etc. Among them, the bit synchronization (Timing Synchronization) step refers to recovering a bit clock signal synchronized with the sending end at the receiving end to ensure correct sampling and decision-making of the data stream, that is, the role is to determine the optimal sampling moment. Currently, the bit synchronization method generally adopts the Gadner loop method.

[0003] However, in the prior art, the Gadner loop method for bit synchronization has problems of relatively complex calculation process and large demand for hardware resources. Summary of the Invention

[0004] The present invention provides a signal processing method, apparatus, and FPGA to solve the defects of relatively high calculation complexity of the bit synchronization method in the prior art and large demand for hardware resources. By adopting a multi-channel signal parallel and multi-delay resampling method to try to cover all possible available sampling points to achieve bit synchronization, the calculation complexity of the bit synchronization step is reduced, thereby improving the signal processing efficiency and reducing the demand for hardware resources.

[0005] The present invention provides a signal processing method, including the following steps: Performing signal multiplexing on an input signal to obtain at least two parallel signals, where the input signal is obtained by oversampling and matched filtering an in-phase quadrature signal; Performing resampling with different delay times on each of the at least two parallel signals to obtain at least two resampled signals, where the different delay times are used to cover periodically uniformly distributed points in the symbol period corresponding to the input signal; Determining a first target data sequence according to the at least two resampled signals, where the delay time of the resampled signal corresponding to the first target data sequence points to the correct sampling moment.

[0006] According to the signal processing method provided by the present invention, the performing resampling with different delay times on each of the at least two parallel signals to obtain at least two resampled signals includes: Determining at least two delay units, where the at least two delay units are used to generate at least two phase delays uniformly distributed within a symbol period; Each of the at least two parallel signals is respectively passed through a corresponding one of the at least two delay units to obtain the at least two resampled signals.

[0007] According to a signal processing method provided by the present invention, the at least two parallel signals include four parallel signals, the at least two delay units include four delay units, and the four delay units include a unit without delay, a unit delaying a quarter symbol period, a unit delaying a half symbol period, and a unit delaying three quarters of a symbol period.

[0008] According to a signal processing method provided by the present invention, determining the first target data sequence according to the at least two resampled signals includes: Demodulating each of the at least two resampled signals to obtain at least two first data sequences; Performing correlation detection on each of the at least two first data sequences with a preset synchronization header to obtain at least two first detection results; Determining the first data sequence corresponding to the first target detection result among the at least two first detection results as the first target data sequence, where the first target detection result is a first detection result among the at least two first detection results indicating that the correlation with the preset synchronization header meets a preset correlation requirement.

[0009] According to a signal processing method provided by the present invention, determining the first target data sequence according to the at least two resampled signals includes: Performing signal multiplexing on each of the at least two resampled signals to obtain at least four multiplexed signals corresponding to each resampled signal; Performing phase rotation at different angles on each of the at least four multiplexed signals corresponding to each resampled signal to obtain at least four rotated signals corresponding to each resampled signal; Determining a second target data sequence corresponding to each resampled signal according to the at least four rotated signals corresponding to each resampled signal, where the rotation angle of the rotated signal corresponding to the second target data sequence points to the correct restoration phase; Determining the first target data sequence according to the second target data sequence corresponding to each resampled signal.

[0010] According to a signal processing method provided by the present invention, performing phase rotation at different angles on each of the at least four multiplexed signals corresponding to each resampled signal to obtain at least four rotated signals corresponding to each resampled signal includes: Determine the inverse matrices of at least four rotation matrices corresponding to each resampled signal, where the inverse matrices of the at least four rotation matrices are used to perform inverse rotations of at least four angles uniformly distributed in the symbol phase space; Multiply each of the at least four multiplexed signals corresponding to each resampled signal by the corresponding inverse rotation matrix among the inverse matrices of the at least four rotation matrices corresponding to each resampled signal, to obtain at least four rotated signals corresponding to each resampled signal.

[0011] According to a signal processing method provided by the present invention, the at least four multiplexed signals corresponding to each resampled signal include four multiplexed signals, the inverse matrices of the at least four rotation matrices corresponding to each resampled signal include inverse matrices of four rotation matrices, and the inverse matrices of the four rotation matrices include the inverse matrix of the identity matrix, the inverse matrix of the 90° rotation matrix, the inverse matrix of the 180° rotation matrix, and the inverse matrix of the 270° rotation matrix.

[0012] According to a signal processing method provided by the present invention, the determining the second target data sequence corresponding to each resampled signal based on the at least four rotated signals corresponding to each resampled signal includes: Demodulate each of the at least four rotated signals corresponding to each resampled signal to obtain at least four second data sequences corresponding to each resampled signal; Perform correlation detection on each of the at least four second data sequences corresponding to each resampled signal with a preset synchronization header to obtain at least four second detection results corresponding to each resampled signal; Determine the second data sequence corresponding to the second target detection result among the at least four second detection results corresponding to each resampled signal as the second target data sequence corresponding to each resampled signal, where the second target detection result is a second detection result among the at least four second detection results that indicates that the correlation with the preset synchronization header meets a preset correlation requirement.

[0013] According to a signal processing method provided by the present invention, the determining the first target data sequence based on the second target data sequence corresponding to each resampled signal includes: Perform correlation detection on the second target data sequence corresponding to each resampled signal with a preset synchronization header to obtain at least two third detection results corresponding to the at least two resampled signals; Determine that the second target data sequence corresponding to the third target detection result among the at least two third detection results corresponding to the at least two resampled signals is the first target data sequence, where the third target detection result is one of the at least two third detection results indicating that the correlation with the preset synchronization header meets the preset correlation requirement.

[0014] The present invention also provides a signal processing device, including the following modules: A signal multiplexing module, configured to perform signal multiplexing on an input signal to obtain at least two parallel signals, where the input signal is obtained by oversampling and matched filtering an in-phase quadrature signal; A signal delay module, configured to perform resampling on each of the at least two parallel signals with different delay times to obtain at least two resampled signals, where the different delay times are used to cover the periodically evenly distributed points in the symbol period corresponding to the input signal; A sequence selection module, configured to determine a first target data sequence according to the at least two resampled signals, where the delay time of the resampled signal corresponding to the first target data sequence points to the correct sampling moment.

[0015] The present invention also provides an FPGA, including a memory, a processor, and instructions stored on the memory and running on the processor, where when the processor executes the instructions, it implements the signal processing method as described in any one of the above.

[0016] The signal processing method, device, and FPGA provided by the present invention attempt to cover all possible available sampling points by adopting a multi-channel signal parallel and multi-delay resampling method to achieve bit synchronization, reducing the computational complexity of the bit synchronization step, thereby improving the signal processing efficiency and reducing the demand for hardware resources. Description of the Drawings

[0017] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0018] Figure 1 It is a schematic diagram of the transmitter processing flow provided by the present invention.

[0019] Figure 2 It is a schematic diagram of the receiver processing flow provided by the present invention.

[0020] Figure 3 It is a schematic diagram of the signal processing method provided by the present invention.

[0021] Figure 4 It is one of the schematic flowcharts of the method for obtaining the first target data sequence provided by the present invention.

[0022] Figure 5 It is the second of the schematic flowcharts of the method for obtaining the first target data sequence provided by the present invention.

[0023] Figure 6 It is the first part of the schematic diagram of the multi-channel parallel bit synchronization and phase ambiguity resolution processing flow provided by the present invention.

[0024] Figure 7 It is the second part of the schematic diagram of the multi-channel parallel bit synchronization and phase ambiguity resolution processing flow provided by the present invention.

[0025] Figure 8 It is the schematic structural diagram of the signal processing device provided by the present invention.

[0026] Figure 9 It is the schematic physical structure diagram of the FPGA provided by the present invention. Detailed implementation manners

[0027] To make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions in the present invention will be clearly and completely described below with reference to the accompanying drawings in the present invention. Apparently, the described embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present invention without making creative efforts shall fall within the protection scope of the present invention.

[0028] First, the actual application scenario of the signal processing method provided by the present invention will be introduced. Exemplarily, in an orthogonal phase shift keying QPSK modulation communication implemented based on a Field Programmable Gate Array (FPGA), the QPSK modulation communication includes a transmitter and a receiver.

[0029] Figure 1 It is the schematic diagram of the transmitter processing flow provided by the present invention. As Figure 1 shown, the transmitter processing flow includes: data source - scrambling - encoding - interleaving - framing - phase modulation - shaping filtering - interpolation filtering - up-conversion - DAC (Digital-to-Analog Converter). Among them, the objective of the transmitter is to convert the original data into a QPSK modulation signal suitable for wireless transmission.

[0030] Figure 2 It is the schematic diagram of the receiver processing flow provided by the present invention. As Figure 2As shown in the figure, the receiver processing flow includes: analog-to-digital converter ADC - down-conversion - decimation filtering - frequency synchronization - matched filtering - demodulation - phase ambiguity resolution - bit synchronization - frame synchronization - deinterleaving - decoding - descrambling - the sink, where in the frame synchronization step, the correlation of the synchronization header is determined to determine the successful execution of phase ambiguity resolution and bit synchronization.

[0031] Among them, the goal of the receiver is to recover the original data from the radio frequency signal. The function of bit synchronization (Timing Synchronization) is to determine the optimal sampling moment. The function of phase ambiguity resolution (Phase Ambiguity Resolution) is to correct the possible 90° phase rotation of QPSK (such as 0°, 90°, 180°, 270° ambiguity). The core part of the present invention mainly includes the steps of bit synchronization and phase ambiguity resolution.

[0032] It can be seen that in digital communication, the receiver is responsible for recovering the original data from the radio frequency signal. The bit synchronization (Timing Synchronization) step refers to recovering the bit clock signal synchronized with the transmitter at the receiving end to ensure correct sampling and decision-making of the data stream, that is, its function is to determine the optimal sampling moment. Currently, the bit synchronization method generally uses the Gadner loop. The Gadner loop uses the feedback control principle to change the frequency and phase of the clock to achieve the adjustment of symbol synchronization. The Gadner loop is relatively complex, requires a large amount of hardware resources, and its convergence speed may be slow.

[0033] It can be seen that the existing bit synchronization method has problems of high computational complexity and large demand for hardware resources.

[0034] In view of this, an embodiment of the present invention provides a signal processing method. By multiplexing the input signal, at least two parallel signals are obtained. The input signal is obtained by oversampling and matched filtering of the in-phase quadrature signal; resampling each of the at least two parallel signals with different delay times to obtain at least two resampled signals. The different delay times are used to cover the periodically evenly distributed points in the symbol period corresponding to the input signal; a first target data sequence is determined according to the at least two resampled signals. The delay time of the resampled signal corresponding to the first target data sequence points to the correct sampling moment. This method uses the parallel multi-signal and multi-delay resampling method to try to cover all possible available sampling points to achieve bit synchronization, reduces the computational complexity of the bit synchronization step, thereby improving the signal processing efficiency and reducing the demand for hardware resources.

[0035] Next, the technical solutions in the embodiments of the present invention will be described with reference to the accompanying drawings in the embodiments of the present invention.

[0036] Figure 3It is a schematic flowchart of the signal processing method provided by the present invention. The signal processing method can be applied to a field programmable gate array (FPGA), and the FPGA can include logic units, DSP resources, BRAM resources, etc. As Figure 3 shown, the method may include the following steps 101 to 103: Step 101: Perform signal multiplexing on the input signal to obtain at least two parallel signals, where the input signal is obtained by oversampling and matched filtering of in-phase quadrature signals.

[0037] It should be noted that the input signal can be obtained by oversampling and matched filtering of the in-phase quadrature (IQ) signal at the receiving end. Among them, the matched filtering is used to eliminate noise and optimize the signal-to-noise ratio. Oversampling means that the sampling rate is higher than the symbol rate, usually 4-8 times the symbol rate, to determine the correct sampling point. The oversampled and matched-filtered IQ signal is multiplexed into multiple paths (such as two paths, three paths, four paths, etc.), and each path of signal can be used for a corresponding possible sampling delay situation.

[0038] Among them, there are many methods for performing signal multiplexing on the input signal to obtain at least two parallel signals. For example, it can be achieved by hardware means, that is, through multiple parallel processing units (such as DSP units, logic units, etc.) of the FPGA to copy the signal, or by software means, that is, storing the matched-filtered and oversampled IQ signal in the memory, and then multiplexing the signal into multiple buffers through memory copy operations. The present invention does not limit the manner of multiplexing the input signal to obtain at least two parallel signals.

[0039] Among them, in bit synchronization, theoretically, a usable sampling point may be found in two paths, so at least two paths are required. However, the more paths are divided, the higher the accuracy of bit synchronization. That is, theoretically, there is an optimal sampling point. The more paths are divided, the easier the found sampling point is to approach the theoretical optimal point. In practical applications, the number of paths can be determined according to the adopted communication modulation method to ensure that it is close enough to the optimal point to ensure communication.

[0040] Step 102: Resample each of the at least two parallel signals with different delay times to obtain at least two resampled signals, where the different delay times are used to cover the periodically evenly distributed points in the symbol period corresponding to the input signal.

[0041] It should be noted that in the bit synchronization step, it is necessary to accurately find the optimal sampling moment of the signal to avoid inter-symbol interference. Traditional methods (such as Gardner loop) rely on feedback loops, with slow convergence and high resource occupancy. After obtaining at least two parallel signals, the present invention can resample each of the at least two parallel signals with different delay times to obtain at least two resampled signals for finding the optimal sampling moment of the input signal.

[0042] Among them, methods for resampling the input signal with different delay times can adopt methods such as a shift register chain, BRAM cyclic buffering, etc. The method of the present invention for resampling each path of parallel signals with different delay times is not limited.

[0043] Step 103: Determine a first target data sequence according to the at least two paths of resampled signals, and the delay time of the resampled signal corresponding to the first target data sequence points to the correct sampling moment.

[0044] It should be noted that after obtaining at least two paths of resampled signals, the first target data sequence can be determined in various ways. For example, it can be determined based on peak correlation detection, based on sync header correlation, or based on comprehensive evaluation of eye diagram opening, etc. The method of the present invention for determining the first target data sequence according to the at least two paths of resampled signals is not limited.

[0045] It can be understood that the present invention reduces the computational complexity of the bit synchronization step, avoids the delay of traditional loop adjustment, reduces the demand for hardware resources, and improves the signal processing efficiency by simultaneously attempting to cover all possible available sampling points through at least two paths of parallel input signals.

[0046] In some embodiments, step 102 for resampling each path of parallel signals in the at least two paths of parallel signals with different delay times to obtain at least two paths of resampled signals may include: determining at least two delay units, where the at least two delay units are used to generate at least two phase delays evenly distributed within a symbol period; respectively passing each path of parallel signals in the at least two paths of parallel signals through the corresponding delay unit in the at least two delay units to obtain the at least two paths of resampled signals.

[0047] It should be noted that at least two different delay time resamplings can be performed through at least two delay units, that is, each path of parallel signal is respectively passed through the corresponding delay unit. For example, for QPSK, the delay units can be delay units with no delay, delay T / 4, T / 2, 3T / 4, where T is the symbol period. For other modulation methods, the delay units can be delay units with no delay and delay T / 2. Passing each path of parallel signal through the delay units that generate different delay times can obtain at least two paths of resampled signals, and the different delay times are used to cover the periodically evenly distributed points in the symbol period corresponding to the input signal.

[0048] It can be understood that the delay unit has low complexity. For example, the delay unit can be efficiently implemented by logic units in an FPGA, which can improve the signal processing efficiency.

[0049] Further, the at least two-way parallel signals include four-way parallel signals, the at least two delay units include four delay units, and the four delay units include a non-delay unit, a unit delaying a quarter symbol period, a unit delaying a half symbol period, and a unit delaying three-quarter symbol period.

[0050] It should be noted that in QPSK modulation, the delay time can be non-delay, delay T / 4, T / 2, 3T / 4 periods. Therefore, the oversampled signal can be multiplexed into four-way parallel branches, and each branch passes through different delay units (such as non-delay, delay T / 4, T / 2, 3T / 4, where T is the symbol period) to generate resampled signals with different phase offsets.

[0051] It can be understood that by corresponding each path of signal to a candidate sampling moment, the key phase points within the symbol period are covered, and it can be implemented by FPGA, that is, the delay can be implemented by a shift register. This improves the signal processing efficiency.

[0052] Figure 4 is one of the flow diagrams of the method for obtaining the first target data sequence provided by the present invention. As Figure 4 shown, step 103 of determining the first target data sequence according to the at least two-way resampled signals may include: Step 201: Demodulate each path of the at least two-way resampled signals to obtain at least two-way first data sequences; Step 202: Perform correlation detection on each path of the at least two-way first data sequences with a preset synchronization header respectively to obtain at least two first detection results; Step 203: Determine the first data sequence corresponding to the first target detection result among the at least two first detection results as the first target data sequence, where the first target detection result is a first detection result among the at least two first detection results indicating that the correlation with the preset synchronization header meets the preset correlation requirement.

[0053] It should be noted that by demodulating each path of the resampled signal (such as QPSK demodulation), at least two-way first data sequences can be obtained. Then, the first target data sequence is determined by the method of optimizing the synchronization header. A known synchronization header is preset in the frame structure, and the preset synchronization header can be a fixed bit sequence. By calculating the correlation between each path of the demodulated first data sequence and the synchronization header, the path of data sequence with the highest correlation is selected as the final output, and the corresponding delay is determined as the optimal sampling moment, and the bit synchronization step can be completed. The correlation detection can adopt methods such as cross-correlation operation peak detection.

[0054] It can be understood that the method for determining the optimal sampling point through the synchronization header matching method in the present invention has low complexity, does not require iterative convergence, realizes fast convergence of operations, and the correlation detection can be efficiently implemented through logic units in the FPGA, improving the signal processing efficiency.

[0055] The signal processing method provided by the present invention, after the IQ signal matching filtering at the receiving end, performs parallel processing on the multi-channel resampling of the oversampled signal at different delays, and selects the optimal one from the multi-channel parallel sequences by means of the correlation with the synchronization header after demodulation to achieve bit synchronization. This scheme realizes high-speed and low-resource bit synchronization through multi-channel delay resampling + synchronization header optimization, and is particularly suitable for the parallel implementation of modulation systems such as QPSK on the FPGA.

[0056] In some embodiments, the input signal not only needs to determine the optimal sampling moment, but also has a phase ambiguity problem. Therefore, while performing bit synchronization, it is also necessary to perform phase ambiguity resolution processing to improve the signal processing efficiency.

[0057] Figure 5 It is the second flowchart of the method for obtaining the first target data sequence provided by the present invention. As Figure 5 shown, the step 103 of determining the first target data sequence according to the at least two-channel resampled signals may include the following steps 301 to 304: Step 301: Multiplex each resampled signal among the at least two-channel resampled signals to obtain at least four multiplexed signals corresponding to each resampled signal.

[0058] It should be noted that each resampled signal is obtained by the in-phase quadrature IQ signal at the receiving end through matching filtering, where the matching filtering is used to eliminate noise and maximize the signal-to-noise ratio. The IQ signal after matching filtering is multiplexed into multiple channels (such as two channels, three channels, four channels, etc.), and each channel of signal can be used to correspond to a possible phase ambiguity situation. Among them, in the frequency and phase synchronization link of QPSK, all signals are gathered at the four corners, so the ambiguity resolution is to find out which one of the four angles each correct signal is. Therefore, at least four channels need to be replicated for phase ambiguity resolution, and each channel corresponds to one angle. The four-channel parallel signals are rotated by four angles to correct it. When other modulation methods are used, more rotation angles may be required, which can be set according to requirements.

[0059] Among them, there are many methods for multiplexing each resampled signal to obtain at least two multiplexed signals. For example, it can be achieved through hardware means, that is, through multiple parallel processing units of FPGA (such as DSP units, logic units, etc.) to copy the signal, or through software means, that is, storing the IQ signal after matched filtering in the memory, and then multiplexing the signal into multiple buffers through memory copy operations. The present invention does not limit the method of multiplexing the resampled signal to obtain at least two multiplexed signals.

[0060] Step 302: Perform phase rotation at different angles on each multiplexed signal among the at least four multiplexed signals corresponding to each resampled signal to obtain at least four rotated signals corresponding to each resampled signal.

[0061] It should be noted that after the IQ signal undergoes frequency synchronization, the signal may cause a fixed offset in the constellation diagram due to phase rotation (such as the four phase ambiguities of 0°, 90°, 180°, and 270° commonly seen in QPSK modulation). Therefore, after obtaining at least two multiplexed signals, each multiplexed signal can be subjected to phase rotation at different angles to obtain at least two rotated signals, which are used to restore the offset resampled signal.

[0062] Among them, there are many ways to perform phase rotation at different angles on the multiplexed signal. For example, rotation matrix multiplication, differential encoding / decoding, pilot-assisted method, etc. can be used. The present invention does not limit the method of performing phase rotation at different angles on each multiplexed signal.

[0063] Step 303: Determine the second target data sequence corresponding to each resampled signal according to the at least four rotated signals corresponding to each resampled signal, and the rotation angle of the rotated signal corresponding to the second target data sequence points to the correct restoration phase.

[0064] It should be noted that after obtaining the at least four rotated signals corresponding to each resampled signal, the second target data sequence corresponding to each resampled signal can be determined in various ways. For example, it can be determined based on peak correlation detection, based on the correlation of the synchronization header, or based on the comprehensive evaluation of the eye diagram opening degree. The present invention does not limit the method of determining the second target data sequence corresponding to each resampled signal according to the at least four rotated signals corresponding to each resampled signal.

[0065] Step 304: Determine the first target data sequence according to the second target data sequence corresponding to each resampled signal.

[0066] It should be noted that after obtaining the second target data sequence corresponding to each resampled signal, the first target data sequence can be determined in various ways. The delay time of the resampled signal corresponding to the first target data sequence points to the correct sampling moment and the phase restoration is correct. For example, it can be determined based on peak correlation detection, based on the correlation of the synchronization header, or based on the comprehensive evaluation of the eye diagram opening degree, etc. The present invention does not limit the method for determining the first target data sequence according to the second target data sequence corresponding to each resampled signal.

[0067] It can be understood that the present invention uses the parallel multiplexing method for bit synchronization and at the same time uses the parallel multiplexing method to try all possible phase ambiguity cases for phase ambiguity resolution, that is, all possible phase ambiguity cases are tried by at least two multiplexed signals, reducing the computational complexity of the phase ambiguity resolution step and avoiding the delay of the traditional iterative algorithm. Compared with the traditional method, performing bit synchronization and phase ambiguity resolution in parallel reduces the computational complexity, reduces the occupation of hardware resources, and improves the signal processing efficiency.

[0068] In some embodiments, step 302 performing phase rotation of each multiplexed signal in at least four multiplexed signals corresponding to each resampled signal at different angles to obtain at least four rotated signals corresponding to each resampled signal may include: determining the inverse matrices of at least four rotation matrices corresponding to each resampled signal, where the inverse matrices of the at least four rotation matrices are used to perform inverse rotation of at least four angles uniformly distributed in the symbol phase space; multiplying each multiplexed signal in at least four multiplexed signals corresponding to each resampled signal by the corresponding inverse matrix of the at least four rotation matrices corresponding to each resampled signal to obtain at least four rotated signals corresponding to each resampled signal.

[0069] It should be noted that through the inverse operation of the rotation matrix, that is, multiplying each multiplexed signal by the corresponding inverse matrix of the rotation matrix respectively. For example, for QPSK, the rotation matrix may be the inverse matrix of the identity matrix, the inverse matrix of the 90° rotation matrix, the inverse matrix of the 180° rotation matrix, and the inverse of the 270° rotation matrix. For other modulation methods, the rotation matrix may be the identity matrix and the inverse of the 270° rotation matrix, and phase adjustment can be achieved.

[0070] Exemplarily, assume that the mathematical expression of the original signal is S = I + jQ, where S represents the signal in complex form, I represents the in-phase component of the signal, Q represents the quadrature component of the signal, and j represents the imaginary unit. The phase ambiguity is θ ∈ {0°, 90°, 180°, 270°}, then the rotated signal is , where, Represents the complex signal after phase rotation, Represents the rotation factor, indicating the phase rotation of signal S The complex operation of. The inverse matrix operation is to multiply each path of the signal by , and attempts to restore the original phase.

[0071] It can be understood that the rotation matrix multiplication has a low complexity. For example, the rotation matrix multiplication can be efficiently implemented through logic resources in an FPGA, saving more resources compared to MLE or Kalman filtering. By reducing the computational complexity, the signal processing efficiency can be improved.

[0072] Furthermore, the at least four multiplexed signals corresponding to each path of the resampled signal include four multiplexed signals, the at least four inverse matrices of the rotation matrix corresponding to each path of the resampled signal include four inverse matrices of the rotation matrix, and the four inverse matrices of the rotation matrix include the inverse matrix of the identity matrix, the inverse matrix of the 90° rotation matrix, the inverse matrix of the 180° rotation matrix, and the inverse matrix of the 270° rotation matrix.

[0073] It should be noted that in QPSK modulation, the phase ambiguity is θ∈{0°, 90°, 180°, 270°}. Therefore, four paths of resampled signals can be copied, and the four multiplexed signals are respectively multiplied by the inverse matrix of the identity matrix, the inverse matrix of the 90° rotation matrix, the inverse matrix of the 180° rotation matrix, and the inverse matrix of the 270° rotation matrix for phase restoration.

[0074] In some embodiments, step 303 for determining the second target data sequence corresponding to each path of the resampled signal according to the at least four rotated signals corresponding to each path of the resampled signal may include: demodulating each of the at least four rotated signals corresponding to each path of the resampled signal to obtain at least four second data sequences corresponding to each path of the resampled signal; performing correlation detection on each of the at least four second data sequences corresponding to each path of the resampled signal with a preset synchronization header to obtain at least four second detection results corresponding to each path of the resampled signal; determining the second data sequence corresponding to the second target detection result among the at least four second detection results corresponding to each path of the resampled signal as the second target data sequence corresponding to each path of the resampled signal, where the second target detection result is one of the at least four second detection results indicating that the correlation with the preset synchronization header meets the preset correlation requirement.

[0075] It should be noted that by demodulating each rotated signal separately (such as QPSK demodulation), at least four second data sequences can be obtained. After obtaining at least four second data sequences, the at least four second data sequences can be screened, and the second target data sequence corresponding to the signal with correct phase rotation is selected as the result for output. The method for sequence screening can adopt methods such as synchronization header correlation detection, cyclic redundancy check method, bit error rate estimation method, etc. The present invention determines the second target data sequence by means of synchronization header optimization. A known synchronization header is preset in the frame structure, and the preset synchronization header can be a fixed bit sequence. By calculating the correlation between each demodulated second data sequence and the synchronization header, the one with the highest correlation is selected as the final output, and it is determined that the corresponding phase ambiguity has been correctly resolved, thus completing the phase ambiguity resolution. Among them, the calculation of correlation can adopt methods such as cross-correlation operation peak detection, etc.

[0076] It can be understood that by directly selecting the best using the strong correlation of the synchronization header, iterative convergence is not required, achieving fast convergence of the phase ambiguity resolution operation and improving the signal processing efficiency.

[0077] In some embodiments, step 304 of determining the first target data sequence according to the second target data sequence corresponding to each resampled signal may include: performing correlation detection on the second target data sequence corresponding to each resampled signal with a preset synchronization header to obtain at least two third detection results corresponding to the at least two resampled signals; determining the second target data sequence corresponding to the third target detection result among the at least two third detection results corresponding to the at least two resampled signals as the first target data sequence, where the third target detection result is one of the at least two third detection results indicating that the correlation with the preset synchronization header meets the preset correlation requirement.

[0078] It should be noted that after obtaining the second target data sequence corresponding to each resampled signal, it is also necessary to determine the first target data sequence at the optimal sampling moment from at least two resampled signals. The first target data sequence can be determined by means of synchronization header optimization. A known synchronization header is preset in the frame structure, and the preset synchronization header can be a fixed bit sequence. By calculating the correlation between the second target data sequence corresponding to each resampled signal and the synchronization header, the one with the highest correlation is selected as the final output, and it is determined that the corresponding delay is the optimal sampling moment, thus completing the bit synchronization step. Among them, the calculation of correlation can adopt methods such as cross-correlation operation peak detection, etc.

[0079] It is understandable that the second target data sequence corresponding to each resampled signal is the data sequence with correct phase ambiguity resolution. Then, by directly utilizing the strong correlation of the synchronization header to optimize the sequence at the best sampling moment, iterative convergence is not required, achieving fast convergence of phase ambiguity resolution operation and bit synchronization operation, and improving the signal processing efficiency.

[0080] Figure 6 It is the first part of the schematic diagram of the multi-channel parallel bit synchronization and phase ambiguity resolution processing flow provided by the present invention. Figure 7 It is the second part of the schematic diagram of the multi-channel parallel bit synchronization and phase ambiguity resolution processing flow provided by the present invention. Since the multi-channel parallel bit synchronization and phase ambiguity resolution processing flow chart is relatively large, it is divided into Figure 6 and Figure 7 for display together. Figure 6 The 1st - 16th channel output signals in Figure 7 are correspondingly connected to the 1st - 16th channel input signals in

[0081] As shown in Figure 6 and Figure 7 , by performing parallel multi-channel processing to simultaneously attempt all possible sampling point offsets and phase ambiguity situations, and using resampling with different time delays, inverse rotation matrix operation, and synchronization header correlation detection to quickly determine the best sampling moment and the correct phase, bit synchronization and phase ambiguity resolution are ultimately achieved. The overall process includes: 1. Input signal processing.

[0082] (1) Matched-filtered I / Q signals.

[0083] The baseband signal at the receiving end undergoes matched filtering (to eliminate noise and maximize the signal-to-noise ratio) to obtain clean I (In-phase) and Q (Quadrature) signals.

[0084] (2) N-fold decimation.

[0085] If the signal is oversampled (such as 4-fold oversampling), the data rate can be reduced through decimation while still maintaining sufficient sampling accuracy. For example: 4-fold oversampling → retain 4 sampling points per symbol after decimation.

[0086] 2. Duplicate into four channels.

[0087] The signal is multiplexed into 4 channels, with each channel corresponding to a different sampling moment (for bit synchronization) and phase rotation (for phase ambiguity resolution).

[0088] 3. Perform bit synchronization and phase ambiguity resolution on each channel.

[0089] The first channel: the first sampling point without delay, divided into four channels, and the first channel is multiplied by a 270-degree rotation matrix , the signal is transformed into (Q1, -I1), and the signal is demodulated into (q1, -i1); the second path is multiplied by a 180-degree rotation matrix , the signal is transformed into (-I1, -Q1), and the signal is demodulated into (-i1, -q1); the third path is multiplied by a 90-degree rotation matrix , the signal is transformed into (-Q, I), and the signal is demodulated into (-q, i); the fourth path is multiplied by a 0-degree rotation matrix , the signal is transformed into (I1, Q1), and the signal is demodulated into (i1, q1); perform synchronization header correlation calculation on (q1, -i1), (-i1, -q1), (-q1, i1), and (i1, q1), select the path signal where the correlation is greater than the threshold and the correlation is the largest, otherwise select the default first path to obtain the signal (i1’, q1’).

[0090] The second path: Delay one sampling period T / 4, that is, the second sampling point, and divide it into four paths. The first path is multiplied by a 270-degree rotation matrix , the signal is transformed into (Q2, -I2), and the signal is demodulated into (q2, -i2); the second path is multiplied by a 180-degree rotation matrix , the signal is transformed into (-I2, -Q2), and the signal is demodulated into (-i2, -q2); the third path is multiplied by a 90-degree rotation matrix , the signal is transformed into (-Q2, I2), and the signal is demodulated into (-q2, i2); the fourth path is multiplied by a 0-degree rotation matrix , the signal is transformed into (I2, Q2), and the signal is demodulated into (i2, q2); perform synchronization header correlation calculation on (q2, -i2), (-i2, -q2), (-q2, i2), and (i2, q2), select the path signal where the correlation is greater than the threshold and the correlation is the largest, otherwise select the default first path to obtain the signal (i2’, q2’).

[0091] The third path: Delay two sampling periods T / 4, that is, the third sampling point, and divide it into four paths. The first path is multiplied by a 270-degree rotation matrix , the signal is transformed into (Q3, -I3), and the signal is demodulated into (q3, -i3); the second path is multiplied by a 180-degree rotation matrix , the signal is transformed into (-I3, -Q3), and the signal is demodulated into (-i3, -q3); the third path is multiplied by a 90-degree rotation matrix , the signal is transformed into (-Q3, I3), and the signal is demodulated into (-q3, i3); the fourth path is multiplied by a 0-degree rotation matrix , the signal is transformed into (I3, Q3), and the signal is demodulated into (i3, q3); perform synchronization header correlation calculations on (q3, -i3), (-i3, -q3), (-q3, i3), and (i3, q3), and select the signal path with the largest correlation when the correlation is greater than the threshold, otherwise select the default first path to obtain the signal (i3’, q3’).

[0092] The fourth path: Delay by three sampling periods T / 4, i.e., the fourth sampling point, and divide it into four paths. The first path is multiplied by a 270-degree rotation matrix , the signal is transformed into (Q4, -I4), and the signal is demodulated into (q4, -i4); the second path is multiplied by a 180-degree rotation matrix , the signal is transformed into (-I4, -Q4), and the signal is demodulated into (-i4, -q4); the third path is multiplied by a 90-degree rotation matrix , the signal is transformed into (-Q4, I4), and the signal is demodulated into (-q4, i4); the fourth path is multiplied by a 0-degree rotation matrix , the signal is transformed into (I4, Q4), and the signal is demodulated into (i4, q4); perform synchronization header correlation calculations on (q4, -i4), (-i4, -q4), (-q4, i4), and (i4, q4), and select the signal path with the largest correlation when the correlation is greater than the threshold, otherwise select the default first path to obtain the signal (i4’, q4’).

[0093] 4. Frame synchronization.

[0094] Perform natural alignment on (i1’, q1’), (i2’, q2’), (i3’, q3’), and (i4’, q4’) at the sampling period T, and then perform synchronization header correlation calculations. Select the signal path with the largest correlation when the correlation is greater than the threshold, otherwise select the default first path to obtain the signal (i’’, q’’). Select the signal with a synchronization header correlation greater than the threshold to obtain the frame synchronization signal.

[0095] In the above embodiments, each path of the signal is multiplied by inverse rotation matrices of 0°, 90°, 180°, and 270° to correct possible phase offsets, and different sampling points (0, T / 4, T / 2, 3T / 4) are delayed for each path to find the optimal sampling moment. The synchronization header correlation calculation selects the most likely correct path by calculating the correlation between the demodulated data and the known synchronization header. Through natural alignment at the new sampling period (T), the synchronization of the signal is ensured. When the correlation exceeds the threshold, the start of the data frame is locked and confirmed.

[0096] It can be understood that parallel processing attempts all possible phases and sampling points simultaneously, avoiding the convergence delay of traditional iterative methods. The rotation matrix multiplication can be efficiently implemented using DSPs available in FPGAs, with low complexity and more resource-saving than MLE / Kalman filtering. By directly selecting the optimal based on the strong correlation of the synchronization header, iterative adjustment is not required, enabling fast synchronization. Additionally, modular design can be adopted, and the phase ambiguity resolution and bit synchronization modules can be independently optimized, suitable for FPGA pipelining implementation. Compared with traditional methods (such as MLE, Gardner loop), it has lower computational complexity, faster convergence, and less hardware resource occupancy, and is particularly suitable for high-speed real-time communication systems.

[0097] Based on the foregoing embodiments, an embodiment of the present invention provides a signal processing device. Each module included in the device, as well as each unit included in each module, can be implemented by a processor; of course, it can also be implemented by specific logic circuits; during implementation, the processor can be a central processing unit (CPU), a microprocessor (MPU), a digital signal processor (DSP), or an FPGA (FPGA), etc.

[0098] The signal processing device provided by the present invention will be described below. The signal processing device described below can be correspondingly referred to the signal processing method described above.

[0099] Figure 8 is a schematic structural diagram of the signal processing device provided by the present invention. As Figure 8 shown, the device 400 includes a signal multiplexing module 401, a signal delay module 402, and a sequence selection module 403, where: The signal multiplexing module 401 is configured to perform signal multiplexing on an input signal to obtain at least two parallel signals, where the input signal is obtained by oversampling and matched filtering of an in-phase quadrature signal; The signal delay module 402 is configured to perform resampling on each of the at least two parallel signals with different delay times to obtain at least two resampled signals, where the different delay times are used to cover the periodically evenly distributed points in the symbol period corresponding to the input signal; The sequence selection module 403 is configured to determine a first target data sequence according to the at least two resampled signals, and the delay time of the resampled signal corresponding to the first target data sequence points to the correct sampling moment.

[0100] In some embodiments, the obtained signal delay module 402 includes a delay generation unit and a delay implementation unit, where, The delay generation unit is configured to determine at least two delay units, and the at least two delay units are used to generate at least two phase delays evenly distributed within the symbol period; A delay implementation unit for respectively passing each of the at least two parallel signals through a corresponding delay unit among the at least two delay units to obtain the at least two resampled signals.

[0101] In some embodiments, the at least two parallel signals include four parallel signals, the at least two delay units include four delay units, and the four delay units include a non-delay unit, a quarter-symbol-period delay unit, a half-symbol-period delay unit, and a three-quarter-symbol-period delay unit.

[0102] In some embodiments, the sequence selection module 403 is specifically configured to: demodulate each of the at least two resampled signals to obtain at least two first data sequences; perform correlation detection on each of the at least two first data sequences with a preset synchronization header to obtain at least two first detection results; and determine the first data sequence corresponding to a first target detection result among the at least two first detection results as the first target data sequence, where the first target detection result is a first detection result among the at least two first detection results indicating that the correlation with the preset synchronization header meets a preset correlation requirement.

[0103] In some embodiments, the sequence selection module 403 includes a signal multiplexing unit, a phase rotation unit, a sequence determination unit, and a sequence selection unit, where The signal multiplexing unit is configured to perform signal multiplexing on each of the at least two resampled signals to obtain at least four multiplexed signals corresponding to each resampled signal; The phase rotation unit is configured to perform phase rotation at different angles on each of the at least four multiplexed signals corresponding to each resampled signal to obtain at least four rotated signals corresponding to each resampled signal, and the phase rotation at different angles is used to cover all phase ambiguity angles corresponding to the input signal; The sequence determination unit is configured to determine a second target data sequence corresponding to each resampled signal according to the at least four rotated signals corresponding to each resampled signal, and the rotation angle of the rotated signal corresponding to the second target data sequence points to the correct restored phase; The sequence selection unit is configured to determine the first target data sequence according to the second target data sequence corresponding to each resampled signal.

[0104] In some embodiments, the phase rotation unit is specifically configured to: determine the inverse matrices of at least four rotation matrices corresponding to each resampled signal, where the inverse matrices of the at least four rotation matrices are used to perform inverse rotations of at least four angles uniformly distributed in the symbol phase space; multiply each of the at least four multiplexed signals corresponding to each resampled signal by the corresponding inverse rotation matrix among the inverse matrices of the at least four rotation matrices corresponding to each resampled signal, to obtain at least four rotated signals corresponding to each resampled signal.

[0105] In some embodiments, the at least four multiplexed signals corresponding to each resampled signal include four multiplexed signals, the inverse matrices of the at least four rotation matrices corresponding to each resampled signal include four inverse rotation matrices, and the four inverse rotation matrices include the inverse matrix of the identity matrix, the inverse matrix of the 90° rotation matrix, the inverse matrix of the 180° rotation matrix, and the inverse matrix of the 270° rotation matrix.

[0106] In some embodiments, the sequence determination unit is specifically configured to: demodulate each of the at least four rotated signals corresponding to each resampled signal, to obtain at least four second data sequences corresponding to each resampled signal; perform correlation detection on each of the at least four second data sequences corresponding to each resampled signal with a preset synchronization header, to obtain at least four second detection results corresponding to each resampled signal; determine the second data sequence corresponding to the second target detection result among the at least four second detection results corresponding to each resampled signal as the second target data sequence corresponding to each resampled signal, where the second target detection result is one of the at least four second detection results indicating that the correlation with the preset synchronization header meets the preset correlation requirement.

[0107] In some embodiments, the sequence selection unit is specifically configured to: perform correlation detection on the second target data sequence corresponding to each resampled signal with a preset synchronization header, to obtain at least two third detection results corresponding to the at least two resampled signals; determine the second target data sequence corresponding to the third target detection result among the at least two third detection results corresponding to the at least two resampled signals as the first target data sequence, where the third target detection result is one of the at least two third detection results indicating that the correlation with the preset synchronization header meets the preset correlation requirement.

[0108] In an embodiment of the present invention, a multi-channel signal parallel and multi-delay resampling method is adopted to attempt to cover all possible available sampling points to achieve bit synchronization, which reduces the computational complexity of the bit synchronization step, thereby improving the signal processing efficiency and reducing the demand for hardware resources.

[0109] Figure 9 It is a schematic diagram of the physical structure of the FPGA provided by the present invention. As Figure 9 shown, the FPGA may include: a processor 510, a communication interface 520, a memory 530, and a communication bus 540. Among them, the processor 510, the communication interface 520, and the memory 530 complete mutual communication through the communication bus 540. The processor 510 can call the logical instructions in the memory 530 to execute a signal processing method, which includes: performing signal multiplexing on an input signal to obtain at least two parallel signals, where the input signal is obtained by oversampling and matched filtering of an in-phase quadrature signal; performing resampling on each of the at least two parallel signals with different delay times to obtain at least two resampled signals, where the different delay times are used to cover the periodically uniformly distributed points in the symbol period corresponding to the input signal; determining a first target data sequence according to the at least two resampled signals, and the delay time of the resampled signal corresponding to the first target data sequence points to the correct sampling moment.

[0110] In addition, when the logical instructions in the above-mentioned memory 530 are implemented in the form of software functional units and sold or used as an independent product, they can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), magnetic disks, or optical discs that can store program codes.

[0111] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. A person of ordinary skill in the art can understand and implement it without creative labor.

[0112] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on such an understanding, the essence of the above technical solution, or the part that contributes to the prior art, can be embodied in the form of a software product. The computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0113] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A signal processing method, characterized in that, Including: Performing signal multiplexing on an input signal to obtain at least two parallel signals, where the input signal is obtained by oversampling and matched filtering on an in-phase quadrature signal; Performing resampling on each of the at least two parallel signals with different delay times to obtain at least two resampled signals, where the different delay times are used to cover the periodically evenly distributed points in the symbol period corresponding to the input signal; Determining a first target data sequence according to the at least two resampled signals, where the delay time of the resampled signal corresponding to the first target data sequence points to the correct sampling moment.

2. The signal processing method according to claim 1, characterized in that The performing resampling on each of the at least two parallel signals with different delay times to obtain at least two resampled signals includes: Determining at least two delay units, where the at least two delay units are used to generate at least two time delays evenly distributed within the symbol period; Passing each of the at least two parallel signals through the corresponding delay unit among the at least two delay units respectively to obtain the at least two resampled signals.

3. The signal processing method according to claim 2, wherein The at least two parallel signals include four parallel signals, the at least two delay units include four delay units, and the four delay units include a unit without delay, a unit delaying a quarter of the symbol period, a unit delaying half of the symbol period, and a unit delaying three quarters of the symbol period.

4. The signal processing method according to claim 1, characterized in that The determining a first target data sequence according to the at least two resampled signals includes: Demodulating each of the at least two resampled signals to obtain at least two first data sequences; Performing correlation detection on each of the at least two first data sequences with a preset synchronization header respectively to obtain at least two first detection results; Determining the first data sequence corresponding to the first target detection result among the at least two first detection results as the first target data sequence, where the first target detection result is a first detection result among the at least two first detection results indicating that the correlation with the preset synchronization header meets the preset correlation requirement.

5. The signal processing method according to claim 1, wherein The determining a first target data sequence according to the at least two resampled signals includes: Performing signal multiplexing on each of the at least two resampled signals to obtain at least four multiplexed signals corresponding to each resampled signal; Performing phase rotation at different angles on each of the at least four multiplexed signals corresponding to each resampled signal to obtain at least four rotated signals corresponding to each resampled signal, where the phase rotation at different angles is used to cover all phase ambiguity angles corresponding to the input signal; Determining a second target data sequence corresponding to each resampled signal according to the at least four rotated signals corresponding to each resampled signal, where the rotation angle of the rotated signal corresponding to the second target data sequence points to the correct restored phase; Determining the first target data sequence according to the second target data sequence corresponding to each resampled signal.

6. The signal processing method according to claim 5, wherein Performing phase rotation at different angles on each of the at least four multiplexed signals corresponding to each resampled signal to obtain at least four rotated signals corresponding to each resampled signal, includes: Determining the inverse matrices of at least four rotation matrices corresponding to each resampled signal, where the inverse matrices of the at least four rotation matrices are used to perform inverse rotations at at least four angles uniformly distributed in the symbol phase space; Multiplying each of the at least four multiplexed signals corresponding to each resampled signal by the corresponding inverse rotation matrix among the inverse matrices of the at least four rotation matrices corresponding to each resampled signal to obtain at least four rotated signals corresponding to each resampled signal.

7. The signal processing method according to claim 6, characterized in that The at least four multiplexed signals corresponding to each resampled signal include four multiplexed signals, the at least four inverse rotation matrices corresponding to each resampled signal include four inverse rotation matrices, and the four inverse rotation matrices include the inverse matrix of the identity matrix, the inverse matrix of the 90° rotation matrix, the inverse matrix of the 180° rotation matrix, and the inverse matrix of the 270° rotation matrix.

8. The signal processing method according to claim 5, wherein Determining the second target data sequence corresponding to each resampled signal according to the at least four rotated signals corresponding to each resampled signal, includes: Demodulating each of the at least four rotated signals corresponding to each resampled signal to obtain at least four second data sequences corresponding to each resampled signal; Performing correlation detection on each of the at least four second data sequences corresponding to each resampled signal with a preset synchronization header to obtain at least four second detection results corresponding to each resampled signal; Determining the second data sequence corresponding to the second target detection result among the at least four second detection results corresponding to each resampled signal as the second target data sequence corresponding to each resampled signal, where the second target detection result is a second detection result among the at least four second detection results indicating that the correlation with the preset synchronization header meets the preset correlation requirement.

9. A signal processing device, characterized in that, Includes: A signal multiplexing module, configured to perform signal multiplexing on an input signal to obtain at least two parallel signals, where the input signal is obtained by oversampling and matched filtering on an in-phase quadrature signal; A signal delay module, configured to perform resampling on each of the at least two parallel signals with different delay times to obtain at least two resampled signals, where the different delay times are used to cover the periodically uniformly distributed points in the symbol period corresponding to the input signal; A sequence selection module, configured to determine a first target data sequence according to the at least two resampled signals, where the delay time of the resampled signal corresponding to the first target data sequence points to the correct sampling moment.

10. An FPGA includes a memory, a processor, and instructions stored on the memory and running on the processor, characterized in that, When the processor executes the instructions, it implements the signal processing method according to any one of claims 1 to 8.

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