Phase ambiguity analysis method, phase ambiguity analysis device and FPGA

Abstract

The invention provides a phase ambiguity analysis method, an analysis device and an FPGA (Field Programmable Gate Array), and relates to the technical field of digital communication. The method comprises the following steps: performing signal multiplexing on an input signal to obtain at least four paths of parallel signals; phase rotation of different angles is carried out on each path of parallel signal in the at least four paths of parallel signals to obtain at least four paths of rotated signals, and the phase rotation of different angles is used for covering all phase ambiguity angles corresponding to the input signal; and determining a first target data sequence according to the at least four paths of rotated signals, wherein the rotation angle of the rotated signal corresponding to the first target data sequence points to a correct recovery phase. According to the method, a parallel multiplexing mode is adopted to carry out phase rotation of different angles on the signals after frequency phase synchronization so as to realize phase restoration, the calculation complexity of a phase ambiguity analysis step is reduced, the processing efficiency of phase ambiguity analysis is improved, and the requirement for hardware resources is reduced.

Description

Technical Field

[0001] The present invention relates to the field of digital communication technologies, and in particular, to a phase ambiguity resolution method, a resolution device, and an FPGA. Background Art

[0002] In digital communication, a receiver is responsible for recovering original data from a radio frequency signal. The signal processing steps of the receiver include down-conversion, decimation filtering, frequency synchronization, matched filtering, demodulation, phase ambiguity resolution, bit synchronization, frame synchronization, etc. Among them, the role of the phase ambiguity resolution (Phase Ambiguity Resolution) step is to correct possible phase rotations of digital modulation methods, such as 0°, 90°, 180°, 270° ambiguities. Currently, phase ambiguity resolution methods generally use the maximum likelihood estimation (MLE) algorithm to estimate the parameters of phase ambiguity by constructing a statistical model of the signal, or use a phase ambiguity resolution method based on a Kalman filter.

[0003] However, the phase ambiguity resolution methods in the prior art have problems of relatively high computational complexity and large requirements for hardware resources. Summary of the Invention

[0004] The present invention provides a phase ambiguity resolution method, a resolution device, and an FPGA to solve the defects of high computational complexity and large requirements for hardware resources of the phase ambiguity resolution method in the prior art. By using a parallel multiplexing method, the signal after frequency synchronization is phase-rotated at different angles to achieve phase restoration, reducing the computational complexity of the phase ambiguity resolution step, thereby improving the processing efficiency of phase ambiguity resolution and reducing the requirements for hardware resources.

[0005] The present invention provides a phase ambiguity resolution method, including the following steps: Perform signal multiplexing on the input signal to obtain at least four parallel signals, where the input signal is obtained by performing matched filtering on an in-phase quadrature signal; Perform phase rotations at different angles on each of the at least four parallel signals to obtain at least four rotated signals, where the phase rotations at different angles are used to cover all phase ambiguity angles corresponding to the input signal; Determine a first target data sequence according to the at least four rotated signals, where the rotation angle of the rotated signal corresponding to the first target data sequence points to the correct restored phase.

[0006] According to the phase ambiguity resolution method provided by the present invention, the performing phase rotations at different angles on each of the at least four parallel signals to obtain at least four rotated signals includes: Determine the inverse matrices of at least four rotation matrices, where the inverse matrices of the at least four rotation matrices are used to perform inverse rotations of at least four angles uniformly distributed in the symbol phase space; Multiply each of the at least four parallel signals by the corresponding inverse rotation matrix among the inverse matrices of the at least four rotation matrices to obtain the at least four rotated signals.

[0007] According to a phase ambiguity resolution method provided by the present invention, the at least four parallel signals include four parallel signals, the inverse matrices of the at least four rotation matrices include four inverse rotation matrices, and the four inverse rotation matrices include the inverse matrix of the identity matrix, the inverse matrix of the 90° rotation matrix, the inverse matrix of the 180° rotation matrix, and the inverse matrix of the 270° rotation matrix.

[0008] According to a phase ambiguity resolution method provided by the present invention, determining the first target data sequence based on the at least four rotated signals includes: Demodulate each of the at least four rotated signals to obtain at least four first data sequences; Perform correlation detection on each of the at least four first data sequences with a preset synchronization header to obtain at least four first detection results; Determine the first data sequence corresponding to the first target detection result among the at least four first detection results as the first target data sequence, where the first target detection result is a first detection result among the at least four first detection results indicating that the correlation with the preset synchronization header meets the preset correlation requirement.

[0009] According to a phase ambiguity resolution method provided by the present invention, determining the first target data sequence based on the at least four rotated signals includes: Perform signal multiplexing on each of the at least four rotated signals to obtain at least two multiplexed signals corresponding to each rotated signal; Perform resampling on each of the at least two multiplexed signals corresponding to each rotated signal with different delay times to obtain at least two resampled signals corresponding to each rotated signal, where the different delay times are used to cover the periodically uniformly distributed points in the symbol period corresponding to the input signal; Determine the second target data sequence corresponding to each rotated signal based on the at least two resampled signals corresponding to each rotated signal, where the delay time of the resampled signal corresponding to the second target data sequence points to the correct sampling moment; Determine the first target data sequence based on the second target data sequence corresponding to each rotated signal.

[0010] A phase ambiguity resolution method provided by the present invention, wherein resampling each multiplexing signal of at least two multiplexing signals corresponding to each rotated signal with different delay times to obtain at least two resampled signals corresponding to each rotated signal includes: Determine at least two delay units corresponding to each rotated signal, and the at least two delay units are used to generate at least two time delays uniformly distributed within the symbol period; Respectively pass each multiplexing signal of at least two multiplexing signals corresponding to each rotated signal through the corresponding delay unit among the at least two delay units to obtain at least two resampled signals corresponding to each rotated signal.

[0011] A phase ambiguity resolution method provided by the present invention, wherein the at least two multiplexing signals corresponding to each rotated signal include four multiplexing signals, the at least two delay units corresponding to each rotated signal include four delay units, and the four delay units include a non-delay unit, a delay quarter-symbol-period unit, a delay half-symbol-period unit, and a delay three-quarter-symbol-period unit.

[0012] A phase ambiguity resolution method provided by the present invention, wherein determining the second target data sequence corresponding to each rotated signal according to the at least two resampled signals corresponding to each rotated signal includes: Demodulate each resampled signal of at least two resampled signals corresponding to each rotated signal to obtain at least two second data sequences corresponding to each rotated signal; Perform correlation detection on each second data sequence of at least two second data sequences corresponding to each rotated signal with a preset synchronization header to obtain at least two second detection results corresponding to each rotated signal; Determine that the second data sequence corresponding to the second target detection result among the at least two second detection results corresponding to each rotated signal is the second target data sequence corresponding to each rotated signal, and the second target detection result is a second detection result among the at least two second detection results that indicates that the correlation with the preset synchronization header meets the preset correlation requirement.

[0013] A phase ambiguity resolution method provided by the present invention, wherein determining the first target data sequence according to the second target data sequence corresponding to each rotated signal includes: Perform correlation detection on the second target data sequences corresponding to each of the rotated signals respectively with a preset synchronization header to obtain at least four third detection results corresponding to the at least four rotated signals; Determine that the second target data sequence corresponding to the third target detection result among the at least four third detection results corresponding to the at least four rotated signals is the first target data sequence, where the third target detection result is a third detection result among the at least four third detection results indicating that the correlation with the preset synchronization header meets the preset correlation requirement.

[0014] The present invention also provides a phase ambiguity resolution device, including the following modules: A signal multiplexing module, configured to perform signal multiplexing on an input signal to obtain at least four parallel signals, where the input signal is obtained by performing matched filtering on an in-phase quadrature signal; A signal rotation module, configured to perform phase rotation at different angles on each of the at least four parallel signals to obtain at least four rotated signals, where the phase rotation at different angles is used to cover all phase ambiguity angles corresponding to the input signal; A sequence selection module, configured to determine a first target data sequence according to the at least four rotated signals, where the rotation angle of the rotated signal corresponding to the first target data sequence points to the correct restored phase.

[0015] The present invention also provides an FPGA, including a memory, a processor, and a computer program stored on the memory and running on the processor, where when the processor executes the computer program, it implements the phase ambiguity resolution method as described in any one of the above.

[0016] The phase ambiguity resolution method, resolution device, and FPGA provided by the present invention rotate the signals after frequency synchronization at different angles by adopting a parallel multiplexing method to achieve phase restoration, reduce the computational complexity of the phase ambiguity resolution step, thereby improving the processing efficiency of phase ambiguity resolution and reducing the demand for hardware resources. Description of the Drawings

[0017] To more clearly illustrate the technical solutions in the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0018] Figure 1 It is a schematic diagram of the transmitter processing flow provided by the present invention.

[0019] Figure 2It is a schematic diagram of the receiver processing flow provided by the present invention.

[0020] Figure 3 It is a schematic flowchart of the phase ambiguity resolution method provided by the present invention.

[0021] Figure 4 It is one of the schematic flowcharts of the method for obtaining the first target data sequence provided by the present invention.

[0022] Figure 5 It is the second schematic flowchart of the method for determining the first target data sequence provided by the present invention.

[0023] Figure 6 It is the first part of the schematic diagram of the multi-channel parallel phase ambiguity resolution and bit synchronization processing flow provided by the present invention.

[0024] Figure 7 It is the second part of the schematic diagram of the multi-channel parallel phase ambiguity resolution and bit synchronization processing flow provided by the present invention.

[0025] Figure 8 It is the structural schematic diagram of the phase ambiguity resolution device provided by the present invention.

[0026] Figure 9 It is the physical structure schematic diagram of the FPGA provided by the present invention. Detailed implementation manners

[0027] To make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions in the present invention will be clearly and completely described below with reference to the accompanying drawings in the present invention. Obviously, the described embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present invention without creative efforts shall fall within the protection scope of the present invention.

[0028] First, the application scenario of the phase ambiguity resolution method provided by the present invention is introduced. Exemplarily, in an orthogonal phase shift keying QPSK modulation communication implemented based on a field programmable gate array (FPGA), the QPSK modulation communication includes a transmitter and a receiver.

[0029] Figure 1 It is the schematic diagram of the transmitter processing flow provided by the present invention. As Figure 1 shown, the transmitter processing flow includes: data source - scrambling - encoding - interleaving - framing - phase modulation - shaping filtering - interpolation filtering - upconversion - DAC (digital-to-analog converter). Among them, the objective of the transmitter is to convert the original data into a QPSK modulation signal suitable for wireless transmission.

[0030] Figure 2 This is a schematic diagram of the receiver processing flow provided by the present invention. As Figure 2 shown, the receiver processing flow includes: analog-to-digital converter ADC - down-conversion - decimation filtering - frequency synchronization - matched filtering - demodulation - phase ambiguity resolution - timing synchronization - frame synchronization - deinterleaving - decoding - descrambling - sink, where in the frame synchronization step, the correlation of the synchronization header is determined to determine the successful execution of phase ambiguity resolution and timing synchronization.

[0031] Among them, the goal of the receiver is to recover the original data from the radio frequency signal. The role of the phase ambiguity resolution (PhaseAmbiguity Resolution) step is to correct the possible 90° phase rotation of QPSK (such as 0°, 90°, 180°, 270° ambiguity). The role of timing synchronization is to determine the optimal sampling moment. The core part of the present invention mainly includes the phase ambiguity resolution step and the timing synchronization step.

[0032] It can be seen that in digital communication, the receiver is responsible for recovering the original data from the radio frequency signal. The role of phase ambiguity resolution (PhaseAmbiguity Resolution) is to correct the possible phase rotation of the digital modulation method, such as 0°, 90°, 180°, 270° ambiguity. Currently, the phase ambiguity resolution method generally uses the maximum likelihood estimation (MLE) algorithm to estimate the parameters of the phase ambiguity by constructing a statistical model of the signal, or the phase ambiguity resolution method based on the Kalman filter. Among them, using the maximum likelihood estimation (MLE) algorithm to estimate the parameters of the phase ambiguity by constructing a statistical model of the signal, this method can theoretically provide the optimal estimation performance. However, the MLE algorithm has a high computational complexity and a large demand for hardware resources in practical applications. The dynamic model and noise statistical characteristics of the Kalman filter are crucial for the algorithm performance. Therefore, precise modeling and parameter adjustment are required during design, which is relatively complex, has a large demand for hardware resources, and its convergence speed may be slow.

[0033] It can be seen that the phase ambiguity resolution methods adopted in the prior art have the problems of high computational complexity and large demand for hardware resources.

[0034] In view of this, an embodiment of the present invention provides a phase ambiguity resolution method. By performing signal multiplexing on an input signal, at least four parallel signals are obtained. The input signal is obtained by performing matched filtering on an in-phase quadrature signal. Each of the at least four parallel signals is subjected to phase rotation at different angles to obtain at least four rotated signals. The different-angle phase rotation is used to cover all phase ambiguity angles corresponding to the input signal. A first target data sequence is determined according to the at least four rotated signals. The rotation angle of the rotated signal corresponding to the first target data sequence points to the correct restored phase. This method uses a parallel multiplexing method to perform phase rotation on the frequency-synchronized signals at different angles to achieve phase restoration, reducing the computational complexity of the phase ambiguity resolution step, thereby improving the processing efficiency of phase ambiguity resolution and reducing the demand for hardware resources.

[0035] Next, the technical solutions in the embodiments of the present invention will be described with reference to the accompanying drawings in the embodiments of the present invention.

[0036] Figure 3 It is a schematic flowchart of the phase ambiguity resolution method provided by the present invention. The phase ambiguity resolution method can be applied to a field programmable gate array. The FPGA can include logic units, DSP resources, BRAM resources, etc. As Figure 3 shown, the method can include the following steps 101 to step 103: Step 101: Perform signal multiplexing on an input signal to obtain at least four parallel signals. The input signal is obtained by performing matched filtering on an in-phase quadrature signal.

[0037] It should be noted that the input signal can be obtained by performing matched filtering on the in-phase quadrature IQ signal at the receiving end. The matched filtering is used to eliminate noise and maximize the signal-to-noise ratio. The matched-filtered IQ signal is multiplexed into multiple paths (such as four paths, five paths, etc.). Each path of the signal can be used to correspond to a possible phase ambiguity situation. Among them, in the frequency phase synchronization link of QPSK, all signals are gathered at the four corners. Therefore, to resolve the ambiguity is to find out which one of the four angles each correct signal is. Therefore, at least four copies are required to resolve the phase ambiguity. Each path corresponds to an angle, and the four parallel signals are rotated by four angles to correct it. When other modulation methods are used, more rotation angles may be required, which can be set according to requirements.

[0038] Among them, there are many methods for signal multiplexing of the input signal to obtain at least four parallel signals. For example, it can be achieved through hardware means, that is, through multiple parallel processing units of FPGA (such as DSP units, logic units, etc.) to copy the signal, or through software means, that is, storing the IQ signal after matched filtering in the memory, and then multiplexing the signal into multiple buffers through memory copy operations. The present invention does not limit the method of signal multiplexing of the input signal to obtain at least four parallel signals.

[0039] Step 102: Perform phase rotation at different angles on each of the at least four parallel signals to obtain at least four rotated signals, and the phase rotation at different angles is used to cover all phase ambiguity angles corresponding to the input signal.

[0040] It should be noted that after the IQ signal is frequency synchronized, the signal may cause a fixed offset of the constellation diagram due to phase rotation (such as the four phase ambiguities of 0°, 90°, 180°, and 270° commonly seen in QPSK modulation). Therefore, after obtaining at least four parallel signals, each parallel signal can be subjected to phase rotation at different angles to obtain at least four rotated signals for restoring the offset signal. Among them, the phase rotation at different angles is used to cover all possible phase ambiguity angles corresponding to the input signal. For example, commonly, it can cover the four phase ambiguities of 0°, 90°, 180°, and 270°.

[0041] Among them, there are many ways to perform phase rotation at different angles on the parallel signal. For example, it can adopt rotation matrix multiplication, differential encoding / decoding, pilot-assisted method, etc. The present invention does not limit the method of performing phase rotation at different angles on each parallel signal.

[0042] Step 103: Determine a first target data sequence according to the at least four rotated signals, and the rotation angle of the rotated signal corresponding to the first target data sequence points to the correct restored phase.

[0043] It should be noted that after obtaining at least four rotated signals, the first target data sequence can be determined in various ways. For example, it can be determined by performing peak correlation detection on the data sequence corresponding to the rotated signal, or by comprehensive evaluation based on the correlation of the synchronization header or based on the eye diagram opening degree. The present invention does not limit the method of determining the first target data sequence according to the at least four rotated signals.

[0044] It can be understood that the present invention tries various possible phase ambiguity cases through at least four parallel signals respectively. Compared with the prior art that tries all possible phase ambiguity cases simultaneously, it reduces the computational complexity of the phase ambiguity resolution step, avoids the delay of the traditional iterative algorithm, reduces the demand for hardware resources, and improves the processing efficiency of phase ambiguity resolution.

[0045] In some embodiments, performing phase rotation on each of the at least four parallel signals at different angles to obtain at least four rotated signals may include: determining inverse matrices of at least four rotation matrices, where the inverse matrices of the at least four rotation matrices are used to perform inverse rotations of at least four angles uniformly distributed in the symbol phase space; multiplying each of the at least four parallel signals by the corresponding inverse matrix of the rotation matrix among the inverse matrices of the at least four rotation matrices to obtain the at least four rotated signals.

[0046] It should be noted that through the inverse operation of the rotation matrix, that is, multiplying each parallel signal by the corresponding inverse matrix of the rotation matrix. For example, for QPSK, the inverse matrices of the rotation matrix may include the inverse matrix of the identity matrix, the inverse matrix of the 90° rotation matrix, the inverse matrix of the 180° rotation matrix, and the inverse matrix of the 270° rotation matrix. For other modulation methods, the rotation matrix can be the inverse matrices of rotation matrices corresponding to more rotation angles, and all can achieve phase adjustment.

[0047] Exemplarily, assume the mathematical expression of the original signal is S = I + jQ, where S represents the signal in complex form, I represents the in-phase component of the signal, Q represents the quadrature component of the signal, and j represents the imaginary unit. The phase ambiguity is θ ∈ {0°, 90°, 180°, 270°}, then the rotated signal is , where, represents the complex signal after phase rotation, represents the rotation factor, indicating the complex operation of performing phase rotation on the signal S θ The inverse matrix operation is to multiply each signal by , and try to restore the original phase.

[0048] It can be understood that the rotation matrix multiplication has a low complexity. For example, the rotation matrix multiplication can be efficiently implemented through logic resources in an FPGA, and it saves more resources compared with the MLE or Kalman filtering method. By reducing the computational complexity, it can improve the processing efficiency of phase ambiguity resolution and reduce the demand for hardware resources.

[0049] Further, the at least four-way parallel signals include four-way parallel signals, the at least four inverse matrices of rotation matrices include four inverse matrices of rotation matrices, and the four inverse matrices of rotation matrices include the inverse matrix of the identity matrix, the inverse matrix of the 90° rotation matrix, the inverse matrix of the 180° rotation matrix, and the inverse matrix of the 270° rotation matrix.

[0050] It should be noted that in QPSK modulation, the phase ambiguity is θ∈{0°, 90°, 180°, 270°}. Therefore, four input signals can be replicated, and the obtained four-way parallel signals are respectively multiplied by the inverse matrix of the identity matrix, the inverse matrix of the 90° rotation matrix, the inverse matrix of the 180° rotation matrix, and the inverse matrix of the 270° rotation matrix to achieve phase restoration.

[0051] Figure 4 It is one of the flow diagrams of the method for obtaining the first target data sequence provided by the present invention. As Figure 4 shown, step 103 of determining the first target data sequence according to the at least four-way rotated signals may include: Step 201: Demodulate each of the at least four-way rotated signals to obtain at least four first data sequences.

[0052] Step 202: Perform correlation detection on each of the at least four first data sequences with a preset synchronization header to obtain at least four first detection results.

[0053] Step 203: Determine the first data sequence corresponding to the first target detection result among the at least four first detection results as the first target data sequence, where the first target detection result is a first detection result among the at least four first detection results that indicates that the correlation with the preset synchronization header meets the preset correlation requirement.

[0054] It should be noted that by demodulating each of the rotated signals (such as QPSK demodulation), at least four first data sequences can be obtained. After obtaining at least four first data sequences, sequence screening can be performed on the at least four first data sequences, and the data sequence corresponding to the rotated signal with correct phase rotation is selected as the result output. The method of sequence screening can adopt methods such as synchronization header correlation detection method, cyclic redundancy check method, bit error rate estimation method, etc. The present invention determines the first target data sequence by the method of selecting the optimal synchronization header. A known synchronization header is preset in the frame structure, and the preset synchronization header can be a fixed bit sequence. By calculating the correlation between each demodulated data sequence and the synchronization header, the one with the highest correlation is selected as the final output, and it is determined that the corresponding phase ambiguity has been correctly resolved, completing the phase ambiguity resolution step. Among them, the correlation calculation can adopt methods such as cross-correlation operation peak detection method, etc.

[0055] It is understandable that by directly selecting the optimal sequence using the strong correlation of the synchronization header, iterative convergence is not required, rapid convergence of the operation is achieved, and the processing efficiency of phase ambiguity resolution is improved.

[0056] For the phase ambiguity resolution method provided by the present invention, after the IQ signal at the receiving end is matched and filtered, through a parallel multiplexing method, by multiplying with the inverse matrix of the rotation matrix, the possible phase ambiguity situations after frequency synchronization are restored, and after demodulation, the multiplexed parallel sequences are optimized by means of the correlation with the synchronization header to achieve the resolution of phase ambiguity. That is, through the method of parallel inverse rotation + synchronization header optimization, with a simple and clear algorithm, low operation delay and low convergence delay, the phase ambiguity problem of digital signal modulation is efficiently solved, with both algorithm clarity and hardware friendliness, and is suitable for high-speed parallel implementation on FPGA.

[0057] In some embodiments, the input signal not only has a phase ambiguity problem but also has an incorrect sampling time problem. Therefore, while performing phase ambiguity resolution, bit synchronization processing is also required to improve the signal processing efficiency.

[0058] Figure 5 It is the second flowchart of the method for determining the first target data sequence provided by the present invention. As Figure 5 shown, step 103 of determining the first target data sequence according to the at least four rotated signals may include the following steps 301 to step 304: Step 301: Perform signal multiplexing on each of the at least four rotated signals to obtain at least two multiplexed signals corresponding to each rotated signal.

[0059] It should be noted that there are many methods for performing signal multiplexing on each rotated signal to obtain at least two multiplexed signals corresponding to each rotated signal. For example, it can be achieved by hardware means, that is, through multiple parallel processing units (such as DSP units, logic units, etc.) of FPGA to copy the signal, or by software means, that is, storing the IQ signal after matched filter oversampling in the memory, and then copying the signal to multiple buffers through memory copy operations. The present invention does not limit the method of performing signal multiplexing on each rotated signal to obtain at least two multiplexed signals corresponding to each rotated signal.

[0060] Among them, theoretically, a usable sampling point may be found in two paths for bit synchronization, so at least two paths are required. However, the more paths are divided, the higher the accuracy of bit synchronization. That is, theoretically, there is an optimal sampling point. The more paths are divided, the easier the found sampling point is to approach the theoretical optimal point. In practical applications, the number of paths can be determined according to the communication modulation method adopted to ensure sufficient proximity to the optimal point to ensure communication.

[0061] Step 302: Resample each of the at least two multiplexed signals corresponding to each rotated signal with different delay times to obtain at least two resampled signals corresponding to each rotated signal, where the different delay times are used to cover the periodically evenly distributed points in the symbol period corresponding to the input signal.

[0062] It should be noted that the bit synchronization step needs to accurately find the optimal sampling moment of the signal to avoid inter-symbol interference. Traditional methods (such as Gardner loop) rely on feedback loops, with slow convergence and high resource occupancy. After obtaining at least two multiplexed signals, the present invention can resample each multiplexed signal with different delay times to obtain at least two resampled signals corresponding to each rotated signal, which are used to find the optimal sampling moment of the input signal.

[0063] Among them, the method of resampling each multiplexed signal with different delay times can adopt methods such as shift register chain, BRAM circular buffer, etc. The present invention does not limit the method of resampling each multiplexed signal with different delay times.

[0064] Step 303: Determine the second target data sequence corresponding to each rotated signal according to the at least two resampled signals corresponding to each rotated signal, where the delay time of the resampled signal corresponding to the second target data sequence points to the correct sampling moment.

[0065] It should be noted that after obtaining at least two resampled signals corresponding to each rotated signal, the second target data sequence can be determined in various ways. For example, it can be determined based on peak correlation detection, based on the correlation of the synchronization header, or based on the comprehensive evaluation of the eye diagram opening degree, etc. The present invention does not limit the method of determining the second target data sequence corresponding to each rotated signal according to the at least two resampled signals corresponding to each rotated signal.

[0066] It can be understood that by simultaneously trying to cover all possible available sampling points with at least two resampled signals, the computational complexity of the bit synchronization step is reduced, the delay of traditional loop adjustment is avoided, the demand for hardware resources is also reduced, and the signal processing efficiency is improved.

[0067] Step 304: Determine the first target data sequence according to the second target data sequence corresponding to each rotated signal.

[0068] It should be noted that after obtaining the second target data sequence corresponding to each rotated signal, the first target data sequence can be determined in various ways. The rotation angle of the rotated signal corresponding to the first target data sequence points to the correct restored phase, and the delay time points to the correct sampling moment. Determining the first target data sequence can be based on peak correlation detection, or on synchronization header correlation detection, or on comprehensive evaluation of eye diagram opening degree, etc. The present invention does not limit the method for determining the first target data sequence according to the second target data sequence corresponding to each rotated signal.

[0069] It can be understood that while the present invention uses the parallel multiplexing method for phase ambiguity resolution, it also uses the parallel multiplexing method to attempt bit synchronization for all possible delay times, that is, by resampling at least two replicated signals simultaneously for all possible delay times, reducing the computational complexity of the phase ambiguity resolution step and the bit synchronization step, and also avoiding the delay of the traditional iterative algorithm. Compared with the traditional method, performing parallel calculation of phase ambiguity resolution and bit synchronization reduces the computational complexity, reduces the occupancy of hardware resources, and improves the signal processing efficiency.

[0070] In some embodiments, resampling each multiplexed signal in at least two multiplexed signals corresponding to each rotated signal with different delay times to obtain at least two resampled signals corresponding to each rotated signal may include: determining at least two delay units corresponding to each rotated signal, where the at least two delay units are used to generate at least two time delays evenly distributed within the symbol period; respectively passing each multiplexed signal in at least two multiplexed signals corresponding to each rotated signal through the corresponding delay unit in the at least two delay units to obtain at least two resampled signals corresponding to each rotated signal.

[0071] It should be noted that at least two different delay time resamplings can be performed through at least two delay units, that is, by passing each multiplexed signal through the corresponding delay unit respectively. For example, for QPSK, the delay units can be delay units with no delay, delay of T / 4 symbol period, T / 2 symbol period, and 3T / 4 symbol period, where T is the symbol period. For other modulation methods, there can be more delay units. By passing each multiplexed signal through the delay units that generate different delay times, at least two resampled signals corresponding to each rotated signal can be obtained.

[0072] It can be understood that the delay unit has low complexity. For example, the delay unit can be efficiently implemented in an FPGA through logic units, which can improve the signal processing efficiency.

[0073] In some embodiments, the at least two multiplexed signals corresponding to each rotated signal include four multiplexed signals, the at least two delay units corresponding to each rotated signal include four delay units, and the four delay units include a non-delay unit, a unit delaying a quarter symbol period, a unit delaying a half symbol period, and a unit delaying three quarter symbol periods.

[0074] It should be noted that in QPSK modulation, the delay time can be non-delay, delay T / 4, T / 2, 3T / 4 periods. Therefore, the rotated signals can be multiplexed into four multiplexed signals, and each multiplexed signal passes through different delay units (such as non-delay, delay T / 4, T / 2, 3T / 4, where T is the symbol period) to generate resampled signals with different phase offsets.

[0075] It can be understood that by corresponding each multiplexed signal to a candidate sampling moment, the key phase points within the symbol period are covered, and it can be implemented by FPGA, that is, the delay can be implemented by a shift register, improving the signal processing efficiency.

[0076] In some embodiments, determining the second target data sequence corresponding to each rotated signal according to the at least two resampled signals corresponding to each rotated signal may include: demodulating each resampled signal among the at least two resampled signals corresponding to each rotated signal to obtain at least two second data sequences corresponding to each rotated signal; performing correlation detection on each second data sequence among the at least two second data sequences corresponding to each rotated signal with a preset synchronization header to obtain at least two second detection results corresponding to each rotated signal; determining the second data sequence corresponding to the second target detection result among the at least two second detection results corresponding to each rotated signal as the second target data sequence corresponding to each rotated signal, where the second target detection result is a second detection result among the at least two second detection results indicating that the correlation with the preset synchronization header meets the preset correlation requirement.

[0077] It should be noted that by demodulating (such as QPSK demodulation) each resampled signal among the at least two resampled signals corresponding to each rotated signal, at least two second data sequences corresponding to each rotated signal can be obtained. Then, the second target data sequence is determined by the method of selecting the optimal synchronization header. A known synchronization header is preset in the frame structure, and the preset synchronization header can be a fixed bit sequence. By calculating the correlation between each demodulated second data sequence and the synchronization header, the data sequence with the highest correlation is selected as the final output, and the corresponding delay is determined as the optimal sampling moment, and the bit synchronization step can be completed. The correlation detection can adopt methods such as cross-correlation operation peak detection.

[0078] It can be understood that the method of determining the optimal sampling point through the synchronization header matching method has low complexity and does not require iterative convergence, achieving fast convergence of the operation. Moreover, the correlation detection can be efficiently implemented through logic units in the FPGA, improving the signal processing efficiency.

[0079] The bit synchronization processing method provided by the present invention performs parallel processing on the multi-channel resampling of each rotated signal at different delays, and selects the optimal one from the multi-channel parallel sequences by means of the correlation with the synchronization header after demodulation to achieve bit synchronization. This solution realizes high-speed and low-resource bit synchronization through multi-channel delayed resampling + synchronization header optimization, and is particularly suitable for the parallel implementation of modulation systems such as QPSK on the FPGA.

[0080] In some embodiments, the determining the first target data sequence according to the second target data sequence corresponding to each rotated signal may include: performing correlation detection on the second target data sequence corresponding to each rotated signal with a preset synchronization header respectively to obtain at least four third detection results corresponding to the at least four rotated signals; determining the second target data sequence corresponding to the third target detection result among the at least four third detection results corresponding to the at least four rotated signals as the first target data sequence, where the third target detection result is a third detection result among the at least four third detection results indicating that the correlation with the preset synchronization header meets the preset correlation requirement.

[0081] It should be noted that after obtaining the second target data sequence corresponding to each rotated signal, it is also necessary to determine the first target data sequence at the optimal sampling moment from at least four rotated signals. The first target data sequence can be determined by means of synchronization header optimization. A known synchronization header is preset in the frame structure, and the preset synchronization header can be a fixed bit sequence. By calculating the correlation between the second target data sequence corresponding to each rotated signal and the synchronization header, the one with the highest correlation is selected as the final output, and the corresponding delay is determined as the optimal sampling moment, and the bit synchronization step can be completed. Among them, the calculation of the correlation can adopt methods such as cross-correlation operation peak detection.

[0082] It can be understood that the second target data sequence corresponding to each rotated signal is the correct data sequence after phase ambiguity resolution. Then, by directly selecting the optimal sequence at the sampling moment by using the strong correlation of the synchronization header, iterative convergence is not required, achieving fast convergence of the phase ambiguity resolution operation and the bit synchronization operation, and improving the signal processing efficiency.

[0083] Figure 6 It is the first part of the schematic diagram of the multi-channel parallel phase ambiguity resolution and bit synchronization processing flow provided by the present invention. Figure 7This is the second part of the schematic diagram of the multi-channel parallel phase ambiguity resolution and bit synchronization processing flow provided by the present invention. Since the multi-channel parallel phase ambiguity resolution and bit synchronization processing flow chart is large, it is divided into Figure 6 and Figure 7 for display together. Figure 6 The output signals of the 1st to 16th channels in Figure 7 are correspondingly connected to the input signals of the 1st to 16th channels in

[0084] As shown in Figure 6 and Figure 7 , by performing parallel multi-channel processing to simultaneously attempt all possible phase ambiguity cases and sampling point offsets, and using the inverse operation of the rotation matrix, different time delays, and correlation detection of the synchronization header to quickly determine the correct phase and the optimal sampling moment, finally, phase ambiguity resolution and bit synchronization are achieved. The overall process includes: 1. Input signal processing.

[0085] (1) Matched-filtered I / Q signals.

[0086] The baseband signal at the receiving end undergoes matched filtering (to eliminate noise and maximize the signal-to-noise ratio) to obtain clean I (In-phase) and Q (Quadrature) signals.

[0087] (2) N-fold decimation.

[0088] If the signal is oversampled (such as 4-fold oversampling), the data rate can be reduced by decimation while still maintaining sufficient sampling accuracy. For example: 4-fold oversampling → retain 4 sampling points per symbol after decimation.

[0089] 2. Duplicate into four channels.

[0090] Multiplex the signal into 4 channels, and each channel is used for phase rotation at different angles (for phase ambiguity resolution) and sampling moments at different delay times (for bit synchronization).

[0091] 3. Perform phase ambiguity resolution and bit synchronization on each channel.

[0092] The first channel: Multiply by the inverse matrix of the 270-degree rotation matrix , the signal is transformed into (Q, -I), which is copied into four paths. The first path is quadruple downsampled, that is, the first sampling point is not delayed, to obtain the signal (Q1’, I1’), and then signal demodulation is performed to obtain the signal (q1, -i1); the second path is delayed by one sampling period, that is, one-quarter sampling period, to obtain the signal (Q2’, I2’), and then signal demodulation is performed to obtain the signal (q2, -i2); the third path is delayed by two sampling periods, that is, two-quarters sampling period, to obtain the signal (Q3’, I3’), and then signal demodulation is performed to obtain the signal (q3, -i3); the fourth path is delayed by three sampling periods, that is, three-quarters sampling period, to obtain the signal (Q4’, I4’), and then signal demodulation is performed to obtain the signal (q4, -i4); the synchronization header correlation calculation is performed on (q1, -i1), (q2, -i2), (q3, -i3) and (q4, -i4), and the path signal with the correlation greater than the threshold and the maximum correlation is selected, otherwise the default first path is selected.

[0093] The second path: Multiply by the inverse matrix of the 180-degree rotation matrix , the signal is transformed into (-I, -Q), which is copied into four paths. The first path is quadruple downsampled, that is, the first sampling point is not delayed, to obtain the signal (-I1’, -Q1’), and then signal demodulation is performed to obtain the signal (-i1, -q1); the second path is delayed by one sampling period, that is, one-quarter sampling period, to obtain the signal (-I2’, -Q2’), and then signal demodulation is performed to obtain the signal (-i2, -q2); the third path is delayed by two sampling periods, that is, two-quarters sampling period, to obtain the signal (-I3’, -Q3’), and then signal demodulation is performed to obtain the signal (-i3, -q3); the fourth path is delayed by three sampling periods, that is, three-quarters sampling period, to obtain the signal (-I4’, -Q4’), and then signal demodulation is performed to obtain the signal (-i4, -q4); the synchronization header correlation calculation is performed on (-i1, -q1), (-i2, -q2), (-i3, -q3) and (-i4, -q4), and the path signal with the correlation greater than the threshold and the maximum correlation is selected, otherwise the default first path is selected.

[0094] The third path: Multiply by the inverse matrix of the 90-degree rotation matrix , the signal is transformed into (-Q, I), which is copied into four paths. The first path is quadruple downsampled, i.e., no delay is applied to the first sampling point, to obtain the signal (-Q1’, I1’), and then signal demodulation is performed to obtain the signal (-q1, i1); the second path is delayed by one sampling period, i.e., one-quarter sampling period, to obtain the signal (-Q2’, I2’), and then signal demodulation is performed to obtain the signal (-q2, i2); the third path is delayed by two sampling periods, i.e., two-quarters sampling period, to obtain the signal (-Q3’, I3’), and then signal demodulation is performed to obtain the signal (-q3, i3); the fourth path is delayed by three sampling periods, i.e., three-quarters sampling period, to obtain the signal (-Q4’, I4’), and then signal demodulation is performed to obtain the signal (-q4, i4); the synchronization header correlation is calculated for (-q1, i1), (-q2, i2), (-q3, i3), and (-q4, i4), and the path with the signal where the correlation is greater than the threshold and has the maximum correlation is selected; otherwise, the default first path is selected.

[0095] Fourth path: Multiply by the inverse matrix of the 0-degree rotation matrix , the signal is transformed into (I, Q), which is copied into four paths. The first path is quadruple downsampled, i.e., no delay is applied to the first sampling point, to obtain the signal (I1’, Q1’), and then signal demodulation is performed to obtain the signal (i1, q1); the second path is delayed by one sampling period, i.e., one-quarter sampling period, to obtain the signal (I2’, Q2’), and then signal demodulation is performed to obtain the signal (i2, q2); the third path is delayed by two sampling periods, i.e., two-quarters sampling period, to obtain the signal (I3’, Q3’), and then signal demodulation is performed to obtain the signal (i3, q3); the fourth path is delayed by three sampling periods, i.e., three-quarters sampling period, to obtain the signal (I4’, Q4’), and then signal demodulation is performed to obtain the signal (i4, q4); the synchronization header correlation is calculated for (i1, q1), (i2, q2), (i3, q3), and (i4, q4), and the path with the signal where the correlation is greater than the threshold and has the maximum correlation is selected; otherwise, the default first path is selected.

[0096] 4. Frame synchronization.

[0097] For the four paths of signals output by 3, the path with the signal where the correlation is greater than the threshold and has the maximum correlation is selected; otherwise, the default first path is selected to obtain the signal (i’’, q’’). If its synchronization header correlation is greater than the threshold, a frame synchronization signal is obtained.

[0098] In the above embodiments, each path of signal is multiplied by inverse rotation matrices of 0°, 90°, 180°, and 270° to correct possible phase offsets, and different sampling points (T / 4, T / 2, 3T / 4, 0) are delayed for each path to find the optimal sampling moment. The correlation calculation of the synchronization header selects the most likely correct path by calculating the correlation between the demodulated data and the known synchronization header. The total number of delay points of the signal after rotation for each path is three, ensuring the output synchronization of each path of signal. When the correlation exceeds the threshold, the start of the data frame is locked and confirmed.

[0099] It can be understood that parallel processing attempts all possible phases and sampling points simultaneously, avoiding the convergence delay of traditional iterative methods. The multiplication of the rotation matrix can be efficiently implemented by DSP in FPGA, with low complexity and more resource-saving than MLE / Kalman filtering. The strong correlation of the synchronization header is directly used for optimization, without iterative adjustment, to achieve fast synchronization. In addition, a modular design can be adopted, and the phase ambiguity resolution and bit synchronization modules can be independently optimized, which is suitable for FPGA pipeline implementation. Compared with traditional methods (such as MLE, Gardner loop), it has lower computational complexity, faster convergence, and less hardware resource occupancy, and is especially suitable for high-speed real-time communication systems.

[0100] Based on the foregoing embodiments, an embodiment of the present invention provides a phase ambiguity resolution device. Each module included in the device, as well as each unit included in each module, can be implemented by a processor; of course, it can also be implemented by specific logic circuits; in the implementation process, the processor can be a central processing unit (CPU), a microprocessor (MPU), a digital signal processor (DSP), or a field programmable gate array (FPGA), etc.

[0101] The phase ambiguity resolution device provided by the present invention will be described below. The phase ambiguity resolution device described below can be correspondingly referred to the phase ambiguity resolution method described above.

[0102] Figure 8 It is a schematic structural diagram of the phase ambiguity resolution device provided by the present invention. As Figure 8 shown, the device 400 includes a signal multiplexing module 401, a signal rotation module 402, and a sequence selection module 403, where: The signal multiplexing module 401 is configured to perform signal multiplexing on the input signal to obtain at least four paths of parallel signals, and the input signal is obtained by performing matched filtering on the in-phase quadrature signal; The signal rotation module 402 is configured to perform phase rotation at different angles on each path of the at least four paths of parallel signals to obtain at least four paths of rotated signals, and the phase rotation at different angles is used to cover all phase ambiguity angles corresponding to the input signal; A sequence selection module 403 is configured to determine a first target data sequence according to the at least four rotated signals, and the rotation angles of the rotated signals corresponding to the first target data sequence point to correct restoration phases.

[0103] In some embodiments, the signal rotation module 402 includes a matrix determination unit and a signal rotation unit, wherein, The matrix determination unit is configured to determine inverse matrices of at least four rotation matrices, and the inverse matrices of the at least four rotation matrices are used to perform inverse rotations of at least four angles evenly distributed in the symbol phase space; The signal rotation unit is configured to multiply each parallel signal in the at least four parallel signals by the corresponding inverse rotation matrix in the inverse matrices of the at least four rotation matrices to obtain the at least four rotated signals.

[0104] In some embodiments, the at least four parallel signals include four parallel signals, the inverse matrices of the at least four rotation matrices include inverse matrices of four rotation matrices, and the inverse matrices of the four rotation matrices include the inverse matrix of the identity matrix, the inverse matrix of the 90° rotation matrix, the inverse matrix of the 180° rotation matrix, and the inverse matrix of the 270° rotation matrix.

[0105] In some embodiments, the sequence selection module 403 is specifically configured to: demodulate each rotated signal in the at least four rotated signals to obtain at least four first data sequences; perform correlation detection on each first data sequence in the at least four first data sequences with a preset synchronization header respectively to obtain at least four first detection results; determine the first data sequence corresponding to the first target detection result among the at least four first detection results as the first target data sequence, and the first target detection result is a first detection result among the at least four first detection results indicating that the correlation with the preset synchronization header meets a preset correlation requirement.

[0106] In some embodiments, the sequence selection module 403 includes a signal multiplexing unit, a signal delay unit, a sequence determination unit, and a sequence selection unit, wherein, The signal multiplexing unit is configured to perform signal multiplexing on each rotated signal in the at least four rotated signals to obtain at least two multiplexed signals corresponding to each rotated signal; The signal delay unit is configured to resample each multiplexed signal in the at least two multiplexed signals corresponding to each rotated signal with different delay times to obtain at least two resampled signals corresponding to each rotated signal, and the different delay times are used to cover periodically evenly distributed points in the symbol period corresponding to the input signal; The sequence determination unit is configured to determine a second target data sequence corresponding to each rotated signal according to at least two resampled signals corresponding to each rotated signal, and the delay time of the resampled signal corresponding to the second target data sequence points to the correct sampling moment; The sequence selection unit is configured to determine the first target data sequence according to the second target data sequence corresponding to each rotated signal.

[0107] In some embodiments, the signal delay unit is specifically configured to: Determine at least two delay units corresponding to each rotated signal, and the at least two delay units are used to generate at least two time delays evenly distributed within the symbol period; Pass each multiplexed signal in at least two multiplexed signals corresponding to each rotated signal through the corresponding delay unit in the at least two delay units, respectively, to obtain at least two resampled signals corresponding to each rotated signal.

[0108] In some embodiments, the at least two multiplexed signals corresponding to each rotated signal include four multiplexed signals, the at least two delay units corresponding to each rotated signal include four delay units, and the four delay units include a non-delay unit, a quarter-symbol-period delay unit, a half-symbol-period delay unit, and a three-quarter-symbol-period delay unit.

[0109] In some embodiments, the sequence determination unit is specifically configured to: Demodulate each resampled signal in at least two resampled signals corresponding to each rotated signal, respectively, to obtain at least two second data sequences corresponding to each rotated signal; Perform correlation detection on each second data sequence in at least two second data sequences corresponding to each rotated signal with a preset synchronization header, respectively, to obtain at least two second detection results corresponding to each rotated signal; Determine that the second data sequence corresponding to the second target detection result among at least two second detection results corresponding to each rotated signal is the second target data sequence corresponding to each rotated signal, and the second target detection result is a second detection result among the at least two second detection results that indicates that the correlation with the preset synchronization header meets the preset correlation requirement.

[0110] In some embodiments, the sequence selection unit is specifically configured to: Perform correlation detection on the second target data sequence corresponding to each rotated signal with a preset synchronization header, respectively, to obtain at least four third detection results corresponding to at least four rotated signals; Determine that the second target data sequence corresponding to the third target detection result among the at least four third detection results corresponding to the at least four rotated signals is the first target data sequence, where the third target detection result is one of the at least four third detection results indicating that the correlation with the preset synchronization header meets the preset correlation requirement.

[0111] In the embodiments of the present invention, a parallel multiplexing method is adopted to perform phase rotation on the frequency-synchronized signals at different angles to achieve phase restoration, reducing the computational complexity of the phase ambiguity resolution step, thereby improving the processing efficiency of phase ambiguity resolution and reducing the demand for hardware resources.

[0112] Figure 9 It is a schematic diagram of the physical structure of the FPGA provided by the present invention. As Figure 9 shown, the FPGA may include: a processor 510, a communication interface 520, a memory 530, and a communication bus 540. Among them, the processor 510, the communication interface 520, and the memory 530 communicate with each other through the communication bus 540. The processor 510 can call the logical instructions in the memory 530 to execute the phase ambiguity resolution method, which includes: performing signal multiplexing on the input signal to obtain at least four parallel signals, where the input signal is obtained by performing matched filtering on the in-phase quadrature signal; performing phase rotation at different angles on each of the at least four parallel signals to obtain at least four rotated signals, where the different angle phase rotations are used to cover all the phase ambiguity angles corresponding to the input signal; determining the first target data sequence according to the at least four rotated signals, and the rotation angle of the rotated signal corresponding to the first target data sequence points to the correct restored phase.

[0113] In addition, when the logical instructions in the above-mentioned memory 530 can be implemented in the form of software functional units and sold or used as an independent product, they can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. And the aforementioned storage medium includes: USB flash drives, mobile hard disks, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), magnetic disks, or optical disks, etc., which can store program codes.

[0114] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art can understand and implement it without creative work.

[0115] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the essence of the above technical solution, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0116] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments or equivalently replace some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of each embodiment of the present invention.

Claims

1. A phase ambiguity resolution method, characterized in that, Including: Performing signal multiplexing on an input signal to obtain at least four parallel signals, where the input signal is obtained by performing matched filtering on an in-phase quadrature signal; Performing phase rotation at different angles on each of the at least four parallel signals to obtain at least four rotated signals, where the phase rotation at different angles is used to cover all phase ambiguity angles corresponding to the input signal; Determining a first target data sequence according to the at least four rotated signals, where the rotation angle of the rotated signal corresponding to the first target data sequence points to the correct restored phase.

2. The phase ambiguity resolution method according to claim 1, wherein The performing phase rotation at different angles on each of the at least four parallel signals to obtain at least four rotated signals includes: Determining the inverse matrices of at least four rotation matrices, where the inverse matrices of the at least four rotation matrices are used to perform inverse rotations at at least four angles uniformly distributed in the symbol phase space; Multiplying each of the at least four parallel signals by the corresponding inverse matrix of the at least four rotation matrices to obtain the at least four rotated signals.

3. The phase ambiguity resolution method according to claim 2, characterized in that The at least four parallel signals include four parallel signals, the at least four inverse matrices of rotation matrices include four inverse matrices of rotation matrices, and the four inverse matrices of rotation matrices include the inverse matrix of the identity matrix, the inverse matrix of the 90° rotation matrix, the inverse matrix of the 180° rotation matrix, and the inverse matrix of the 270° rotation matrix.

4. The phase ambiguity resolution method according to claim 1, wherein The determining a first target data sequence according to the at least four rotated signals includes: Demodulating each of the at least four rotated signals to obtain at least four first data sequences; Performing correlation detection on each of the at least four first data sequences with a preset synchronization header to obtain at least four first detection results; Determining the first data sequence corresponding to the first target detection result among the at least four first detection results as the first target data sequence, where the first target detection result is a first detection result among the at least four first detection results indicating that the correlation with the preset synchronization header meets the preset correlation requirement.

5. The phase ambiguity resolution method according to claim 1, wherein The determining a first target data sequence according to the at least four rotated signals includes: Performing signal multiplexing on each of the at least four rotated signals to obtain at least two multiplexed signals corresponding to each rotated signal; Performing resampling with different delay times on each of the at least two multiplexed signals corresponding to each rotated signal to obtain at least two resampled signals corresponding to each rotated signal, where the different delay times are used to cover the periodically uniformly distributed points in the symbol period corresponding to the input signal; Determining a second target data sequence corresponding to each rotated signal according to the at least two resampled signals corresponding to each rotated signal, where the delay time of the resampled signal corresponding to the second target data sequence points to the correct sampling moment; Determining the first target data sequence according to the second target data sequence corresponding to each rotated signal.

6. The phase ambiguity resolution method according to claim 5, wherein Resampling each of the at least two multiplexed signals corresponding to each rotated signal with different delay times to obtain at least two resampled signals corresponding to each rotated signal, including: Determining at least two delay units corresponding to each rotated signal, where the at least two delay units are used to generate at least two time delays evenly distributed within the symbol period; Passing each of the at least two multiplexed signals corresponding to each rotated signal through the corresponding delay unit among the at least two delay units to obtain at least two resampled signals corresponding to each rotated signal.

7. The phase ambiguity resolution method according to claim 6, characterized in that, The at least two multiplexed signals corresponding to each rotated signal include four multiplexed signals, the at least two delay units corresponding to each rotated signal include four delay units, and the four delay units include a unit with no delay, a unit with a quarter-symbol-period delay, a unit with a half-symbol-period delay, and a unit with a three-quarter-symbol-period delay.

8. The phase ambiguity resolution method according to claim 5, wherein Determining the second target data sequence corresponding to each rotated signal according to the at least two resampled signals corresponding to each rotated signal, including: Demodulating each of the at least two resampled signals corresponding to each rotated signal to obtain at least two second data sequences corresponding to each rotated signal; Performing correlation detection on each of the at least two second data sequences corresponding to each rotated signal with a preset synchronization header to obtain at least two second detection results corresponding to each rotated signal; Determining the second data sequence corresponding to the second target detection result among the at least two second detection results corresponding to each rotated signal as the second target data sequence corresponding to each rotated signal, where the second target detection result is a second detection result among the at least two second detection results that indicates that the correlation with the preset synchronization header meets the preset correlation requirement.

9. A phase ambiguity resolution device, characterized in that, Including: A signal multiplexing module for multiplexing an input signal to obtain at least four parallel signals, where the input signal is obtained by performing matched filtering on an in-phase quadrature signal; A signal rotation module for performing phase rotation at different angles on each of the at least four parallel signals to obtain at least four rotated signals, where the phase rotation at different angles is used to cover all phase ambiguity angles corresponding to the input signal; A sequence selection module for determining a first target data sequence according to the at least four rotated signals, where the rotation angle of the rotated signal corresponding to the first target data sequence points to the correct restored phase.

10. An FPGA includes a memory, a processor, and instructions stored on the memory and running on the processor, characterized in that, When the processor executes the instructions, it implements the phase ambiguity resolution method according to any one of claims 1 to 8.

Images