Error code detection method and device, electronic equipment and storage medium
By integrating the code control module in the error detection device, link state detection is used to eliminate interference, the problem of low detection accuracy of the bit error rate of the signal transceiver and receive equipment is solved, and a higher detection accuracy and a simplified test environment is achieved.
Patent Information
- Application Number
- CN202510412896.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-02
- Publication Date
- 2025-07-04
AI Technical Summary
In the prior art, when the signal transmitting and receiving equipment detects the bit error rate, the accuracy of the bit error rate detection is low due to link interference, and the complexity of the test environment increases.
By integrating the code type control module in the error detection device, after transmitting the signal by the first link, it determines whether the link state is normal based on the first signal and the second signal, and only performs bit error rate detection when the link state is normal, and eliminates the influence of link interference.
It improves the accuracy of bit error rate detection, simplifies the test environment, reduces interference from other equipment, and ensures the reliability of the detection results.
Smart Images
Figure CN120263698A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of communication technologies, and in particular, to an error code detection method, apparatus, electronic device, and storage medium. Background Art
[0002] During the signal transmission process of a signal transceiver device, error codes may occur. Therefore, it is necessary to detect the signal transceiver device to determine the error rate of the signals transmitted by the signal transceiver device.
[0003] In the related art, an error code detector can send a first detection signal to a signal transceiver device. When the signal transceiver device receives the first detection signal, it obtains a second detection signal, and then sends the second detection signal to the error code detector. After receiving the second detection signal, the error code detector detects the error rate of the signals transmitted by the signal transceiver device according to the first detection signal and the second detection signal. During the detection process, to eliminate the influence of the link from the signal transceiver device to the error code detector on the accuracy of determining the error rate of the signals transmitted by the device to be detected, a split detection method is usually adopted. This method is to split the second detection signal into two paths at the receiving end of the error code detector. One path transmits the second detection signal to an oscilloscope to detect whether the link from the signal transceiver device to the error code detector interferes with the second detection signal; the other path transmits the second detection signal to the error code detector to detect the signal transceiver device and determine the error rate of the signals transmitted by the signal transceiver device.
[0004] However, since the signal received by the oscilloscope is the signal transmitted after being split by a power divider, the power divider will divide the voltage of the second detection signal. Therefore, the signal quality received by the oscilloscope is poor, and it is impossible to accurately eliminate the influence of the link from the signal transceiver device to the error code detector on the accuracy of determining the error rate of the signals transmitted by the device to be detected, resulting in a low accuracy of determining the error rate of the signals transmitted by the signal transceiver device. Summary of the Invention
[0005] This application provides an error code detection method, apparatus, electronic device, and storage medium to improve the accuracy of determining the error rate of the signals transmitted by the device to be detected.
[0006] This application provides an error code detection method, including:
[0007] Receiving a first signal, where the first signal is the signal received by an error code detection device after a second signal is transmitted through a first link, and the second signal is the signal sent by a pattern control module to the error code detection device; the pattern control module is integrated in a fixture, the fixture is connected to the error code detection device through the first link, and the fixture is connected to the device to be detected through an interface on the device to be detected;
[0008] Determining whether the state of the first link is normal according to the first signal and the second signal;
[0009] In response to the normal state of the first link, perform an error rate detection on the device to be detected, and determine the error rate of the signal transmitted by the device to be detected.
[0010] This application provides an error code detection device, including:
[0011] A receiving module, configured to receive a first signal, where the first signal is the signal received by the error code detection device after the second signal is transmitted through the first link, and the second signal is the signal sent by the code pattern control module to the error code detection device; the code pattern control module is integrated in the fixture, the fixture is connected to the error code detection device through the first link, and the fixture is connected to the device to be detected through the interface on the device to be detected;
[0012] A determination module, configured to determine whether the state of the first link is normal according to the first signal and the second signal;
[0013] A detection module, in response to the normal state of the first link, performs an error rate detection on the device to be detected, and determines the error rate of the signal transmitted by the device to be detected.
[0014] This application also provides an electronic device, including: a memory, configured to store a computer program; a processor, configured to implement the steps of any of the above error code detection methods when executing the computer program.
[0015] This application also provides a computer-readable storage medium, in which a computer program is stored, and when the computer program is executed by a processor, the steps of any of the above error code detection methods are implemented.
[0016] The error code detection method, device, electronic device, and storage medium provided by the embodiments of the present application. The code pattern control module sends a second signal to the error code detection device. After the second signal is transmitted to the error code detection device through the first link, the signal received by the error code detection device is the first signal. After receiving the first signal, the error code detection device determines the degree of interference of the first link on the second signal based on the first signal and the second signal. When the degree of interference of the first link on the second signal is small, it is determined that the state of the first link is normal. Then, in response to the normal state of the first link, the error rate of the device to be detected is detected, and the error rate of the signal transmitted by the device to be detected is determined. In the above method, the error code detection device first determines whether the state of the first link is normal. In response to the normal state of the first link, the error rate of the device to be detected is detected, and the error rate of the signal transmitted by the device to be detected is determined. In this way, the influence of the first link on determining the error rate of the signal transmitted by the device to be detected can be excluded in advance, thereby improving the accuracy of determining the error rate of the signal transmitted by the device to be detected. Moreover, since the device to be detected and the error code detection device are connected through the first link, the process of detecting the error rate of the device to be detected will not be interfered by other devices, further improving the accuracy of determining the error rate of the signal transmitted by the device to be detected. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] To more clearly illustrate the embodiments of the present application, the following will briefly introduce the drawings required in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.
[0018] Figure 1 It is a schematic diagram of the application scenario provided by the embodiments of the present application;
[0019] Figure 2 It is a schematic flowchart of an error code detection method provided by the embodiments of the present application;
[0020] Figure 3 It is a schematic diagram of a code pattern control module provided by the embodiments of the present application;
[0021] Figure 4 It is a schematic flowchart of determining the state of the first link provided by the embodiments of the present application;
[0022] Figure 5 It is a schematic flowchart of determining the error rate of the signal transmitted by the device to be detected provided by the embodiments of the present application;
[0023] Figure 6 It is a schematic diagram of receiving the fourth signal sent by the device to be detected provided by the embodiments of the present application;
[0024] Figure 7 Structural schematic diagram of an error code detection device provided by an embodiment of the present application;
[0025] Figure 8 Structural schematic diagram of an electronic device provided by the present application. Specific embodiments
[0026] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.
[0027] It should be noted that in the description of the present application, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects, rather than to describe a specific order or sequence.
[0028] The device to be detected may have error codes during the signal transmission process. Therefore, it is necessary to detect the device to be detected to determine the error rate of the signal transmitted by the device to be detected.
[0029] In the related art, a third signal can be sent by an error code detection device to a device to be detected. When receiving the third signal, the device to be detected obtains a fourth signal and then sends the fourth signal to the error code detection device. After receiving the fourth signal, the error code detection device determines the bit error rate of the signal transmitted by the device to be detected according to the third signal and the fourth signal. However, when the device to be detected sends the fourth signal to the error code detection device, the fourth signal is transmitted through a first link. The first link may interfere with the fourth signal during the transmission process of the fourth signal, resulting in a low accuracy of the bit error rate of the signal transmitted by the device to be detected determined by the error code detection device according to the third signal and the fourth signal. Therefore, a method of split detection can be used to detect the bit error rate of the device to be detected. At the receiving end of the error code detection device, the fourth signal is divided into two paths by a power splitter. One path transmits the fourth signal to an oscilloscope for the bit error rate caused by the interference of the first link on the fourth signal; the other path transmits the fourth signal to the error code detection device for detecting the bit error rate of the signal transmitted by the device to be detected. Then, when the fourth signal is divided into two paths by the power splitter at the receiving end of the error code detection device, the power splitter will divide the voltage of the fourth signal. In this way, the signal quality of the fourth signal received by the transmission oscilloscope is poor, and the bit error rate caused by the interference of the link from the device to be detected to the error code detection device on the fourth signal cannot be accurately determined, resulting in a low accuracy of determining the bit error rate of the signal transmitted by the signal transceiver device. In addition, during the process of determining the bit error rate of the signal transmitted by the signal transceiver device as described above, an oscilloscope needs to be combined for detection, increasing the complexity of the test environment.
[0030] An embodiment of the present application provides an error code detection method. The error code detection device first determines whether the state of the first link is normal. If the state of the first link is normal, it means that the influence of the first link on determining the bit error rate of the signal transmitted by the device to be detected is small and can be ignored. Therefore, in response to the normal state of the first link, the bit error rate of the device to be detected is detected to determine the bit error rate of the signal transmitted by the device to be detected. In this way, the influence of the first link on determining the bit error rate of the signal transmitted by the device to be detected is excluded, and the accuracy of determining the bit error rate of the signal transmitted by the device to be detected is improved. In addition, the device to be detected and the error code detection device are connected through the first link. In this way, during the process of detecting the bit error rate of the device to be detected, it will not be interfered by other devices, further improving the accuracy of determining the bit error rate of the signal transmitted by the device to be detected.
[0031] To enable those skilled in the art of this technology to better understand the solution of the present application, the following further details the present application in conjunction with the accompanying drawings and specific embodiments.
[0032] Combined with the specific application environment architecture or specific hardware architecture on which the execution of the error code detection method depends, the specific application environment architecture or specific hardware architecture is described herein. Refer to Figure 1, Figure 1 is a schematic diagram of an application scenario provided by an embodiment of the present application. As Figure 1 shown, it includes a device to be detected 11, a fixture 12, and an error code detection device 13. Among them, the device to be detected 11 can be, for example, a device with signal transceiver functions such as a mobile phone or a computer.
[0033] In the actual application process, the device to be detected 11 is connected to the fixture 12 through the interface of the device to be detected 11, and the fixture 12 is connected to the error code detection device 13 through a first link. The device to be detected 11 and the error code detection device 13 are connected through two different links. Among them, one link is from the device to be detected 11 to the error code detection device 13, and the other link is from the error code detection device 13 to the device to be detected 11. It should be noted that the link from the device to be detected 11 to the error code detection device 13 is the first link, that is, the link from the device to be detected 11 to the error code detection device 13 is the same link as the link from the fixture 12 to the error code detection device 13. Therefore, the device to be detected 11 is also connected to the error code detection device 13 through the first link. The link from the error code detection device 13 to the device to be detected 11 is the first link.
[0034] It should be noted that Figure 1 only schematically shows an application scenario in the form of an example, and does not limit the application scenario.
[0035] The technical solution of the present application and how the technical solution of the present application solves the above technical problems will be described in detail below with specific embodiments. These several specific embodiments below can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below with reference to the accompanying drawings.
[0036] Figure 2 is a schematic flow chart of an error code detection method provided by an embodiment of the present application. As Figure 2 shown, an embodiment of the present application provides an error code detection method, and a detailed description of this method is as follows:
[0037] S201: Receive a first signal. The first signal is the signal received by the error code detection device after the second signal is transmitted through the first link. The second signal is the signal sent by the code pattern control module to the error code detection device; the code pattern control module is integrated in the fixture, the fixture is connected to the error code detection device through the first link, and the fixture is connected to the device to be detected through the interface on the device to be detected.
[0038] The execution subject of the present application can be the error code detection device or an error code detection device provided in the error code detection device. The error code detection device can be implemented through software or through a combination of software and hardware.
[0039] The pattern control module is integrated in the fixture, and the fixture can be a compliance test fixture. For example, the compliance test fixture can be a high-speed Peripheral Component Interconnect Express (PCIe) 5.0 Compliance Load Board (CLB) fixture. The PCIe 5.0 CLB fixture is a tool for electrically testing the PCIe interface according to the specifications of the electrical characteristics, mechanical dimensions, signal protocols, etc. of the PCIe interface defined by the Peripheral Component Interconnect Special Interest Group (PCI-SIG). Taking the fixture as a compliance test fixture as an example, combined with Figure 3 for understanding, Figure 3 The following is a schematic diagram of a pattern control module provided by an embodiment of the present application. Please refer to Figure 3 , the pattern control module 31 is integrated in the compliance test fixture 30. In this way, introducing other devices between the device to be detected and the error code detection device is avoided, and the complexity of the test environment is simplified.
[0040] The pattern control module has an independent power supply. After the power supply of the pattern control module is turned on, the pattern control module sends a second signal to the error code detection device. It should be noted that after the pattern control module sends the second signal to the error code detection device, the second signal is transmitted to the error code detection device through the first link. In some embodiments, the first link will interfere with the second signal. In this way, when the second signal is transmitted to the error code detection device, the signal received by the error code detection device is the first signal, that is, the first signal is the signal received by the error code detection device after the first link interferes with the second signal.
[0041] It should be noted that the fixture can be connected to the device to be detected through the interface on the device to be detected, and the fixture and the error code detection device are connected through the first link. Therefore, the device to be detected is directly connected to the error code detection device through the first link.
[0042] The error code detection device refers to a device that detects the bit error rate of the device to be detected and determines the bit error rate of the signal transmitted by the device to be detected. The error code detection device can be, for example, an error code tester.
[0043] S202: Determine whether the state of the first link is normal according to the first signal and the second signal.
[0044] The state of the first link can be a normal state or an abnormal state. When the state of the first link is the normal state, it is determined that the state of the first link is normal. The normal state of the first link means that the interference degree of the first link on the second signal is small and can be ignored, or the first link does not interfere with the second signal. At this time, when detecting the bit error rate of the device to be detected and determining the bit error rate of the signal transmitted by the device to be detected, the influence of the first link on determining the bit error rate of the signal transmitted by the device to be detected is small and can be ignored. When the state of the first link is the abnormal state, it is determined that the state of the first link is abnormal. The abnormal state of the first link means that the interference degree of the first link on the second signal is large. At this time, when detecting the bit error rate of the device to be detected and determining the bit error rate of the signal transmitted by the device to be detected, the influence of the first link on determining the bit error rate of the signal transmitted by the device to be detected is large.
[0045] It should be noted that the second signal is a signal preset by the code pattern control module and the bit error detection device. Therefore, after receiving the first signal, the bit error detection device can determine the interference degree of the first link on the second signal according to the first signal and the second signal. When the interference degree of the first link on the second signal is small, it is determined that the state of the first link is normal; when the interference degree of the first link on the second signal is large, it is determined that the state of the first link is abnormal.
[0046] S203: In response to the normal state of the first link, detect the bit error rate of the device to be detected and determine the bit error rate of the signal transmitted by the device to be detected.
[0047] When the state of the first link is normal, the influence of the first link on determining the bit error rate of the signal transmitted by the device to be detected is small and can be ignored. Therefore, in response to the normal state of the first link, the bit error rate of the device to be detected can be detected, and then the bit error rate of the signal transmitted by the device to be detected can be determined.
[0048] At Figure 2In the illustrated embodiment, the code pattern control module sends a second signal to the error code detection device. After the second signal is transmitted to the error code detection device through the first link, the signal received by the error code detection device is the first signal. After receiving the first signal, the error code detection device determines the degree of interference of the first link on the second signal based on the first signal and the second signal. When the degree of interference of the first link on the second signal is small, it is determined that the state of the first link is normal. Then, in response to the normal state of the first link, the error rate of the device under test is detected to determine the error rate of the signal transmitted by the device under test. In the above method, the error code detection device first determines the state of the first link. In response to the normal state of the first link, the error rate of the device under test is detected to determine the error rate of the signal transmitted by the device under test. In this way, the influence of the first link on determining the error rate of the signal transmitted by the device under test can be excluded in advance, thereby improving the accuracy of determining the error rate of the signal transmitted by the device under test. In addition, the device under test and the error code detection device are connected through the first link, that is, there are no other devices between the device under test and the error code detection device. In this way, during the process of detecting the error rate of the device under test, it will not be interfered by other devices, further improving the accuracy of determining the error rate of the signal transmitted by the device under test, and at the same time, simplifying the complexity of the test environment.
[0049] Based on the illustrated embodiment, below, in combination with Figure 2 the following, a further description will be given of the method for determining the state of the first link in the embodiments of the present application. Figure 4
[0050] Figure 4 Figure 4 FIG. is a schematic flowchart of a method for determining the state of the first link provided by an embodiment of the present application. As shown, the process may include the following steps:
[0051] S401: Generate a first eye diagram of the first signal according to the received waveform of the first signal.
[0052] The eye diagram is a tool used to evaluate signal integrity in digital communication. It overlaps the periodic waveforms of digital signals on the horizontal time axis to observe signal integrity. For any signal, after receiving the signal, the error detection device overlaps the waveforms of each symbol of the signal to form the eye diagram of the signal. Among them, the vertical opening degree of the eye diagram is the maximum opening degree of the eye diagram in the vertical direction, which is used to represent the stability of the signal amplitude. The larger the vertical opening degree of the eye diagram, the stronger the stability of the signal amplitude; the smaller the vertical opening degree of the eye diagram, the weaker the stability of the signal amplitude. The horizontal opening degree of the eye diagram is the maximum opening degree of the eye diagram in the horizontal direction, which is used to represent the stability of signal timing. The larger the horizontal opening degree of the eye diagram, the stronger the stability of signal timing; the smaller the horizontal opening degree of the eye diagram, the weaker the stability of signal timing. The edge smoothness of the eye diagram is the smoothness of the edge of the eye diagram, which is used to represent signal quality. The larger the edge smoothness of the eye diagram, the better the signal quality; the smaller the edge smoothness of the eye diagram, the worse the signal quality. The center position of the eye diagram is the geometric center of the eye diagram, which is used to represent the decision level of the signal. Therefore, the integrity of the signal can be intuitively evaluated through the eye diagram.
[0053] The first eye diagram is the eye diagram of the first signal. After receiving the first signal, the error detector generates the first eye diagram of the first signal according to the received waveforms of multiple cycles of the first signal.
[0054] S402: Generate the second eye diagram of the second signal according to the preset code pattern.
[0055] Since the second signal is a signal preset by the code pattern control module and the error detection device, the code pattern of the second signal is the preset code pattern. Exemplarily, assuming the preset code pattern is 1001, then the second signal is 1001.
[0056] The error detection device can generate the waveform of the second signal according to the preset code pattern of the second signal, and then generate the second eye diagram of the second signal according to the waveforms of multiple cycles of the second signal.
[0057] S403: Determine whether the state of the first link is normal.
[0058] If so, execute S404;
[0059] If not, execute S405.
[0060] In some embodiments, the state of the first link can be determined according to the first eye diagram and the second eye diagram. The method for determining the state of the first link according to the first eye diagram and the second eye diagram can be as follows: obtain multiple parameters according to the first eye diagram and the second eye diagram, and the multiple parameters are used to indicate the interference of the first link on the second signal; determine the state of the first link according to the multiple parameters.
[0061] The multiple parameters respectively include: the vertical opening degree difference between the vertical opening degree of the first eye diagram and the vertical opening degree of the second eye diagram, the horizontal opening degree difference between the horizontal opening degree of the first eye diagram and the horizontal opening degree of the second eye diagram, the edge smoothness difference between the edge smoothness of the first eye diagram and the edge smoothness of the second eye diagram, and the offset degree between the center position of the first eye diagram and the center position of the second eye diagram.
[0062] The vertical opening degree of the first eye diagram indicates the signal amplitude stability of the first signal, and the vertical opening degree of the second eye diagram indicates the signal amplitude stability of the second signal. The vertical opening degree difference between the vertical opening degree of the first eye diagram and the vertical opening degree of the second eye diagram can be represented by the absolute value of the difference between the vertical opening degree of the first eye diagram and the vertical opening degree of the second eye diagram. Therefore, the vertical opening degree difference between the vertical opening degree of the first eye diagram and the vertical opening degree of the second eye diagram can represent the difference between the signal amplitude stability of the first signal and the signal amplitude stability of the second signal after the first link interferes with the second signal, that is, the influence degree of the first link on the signal amplitude stability of the second signal. The larger the vertical opening degree difference, the greater the influence degree of the first link on the signal amplitude stability of the second signal; the smaller the vertical opening degree difference, the smaller the influence degree of the first link on the signal amplitude stability of the second signal.
[0063] The horizontal opening degree of the first eye diagram indicates the signal timing stability of the first signal, and the horizontal opening degree of the second eye diagram indicates the signal timing stability of the second signal. The horizontal opening degree difference between the horizontal opening degree of the first eye diagram and the horizontal opening degree of the second eye diagram can be represented by the absolute value of the difference between the horizontal opening degree of the first eye diagram and the horizontal opening degree of the second eye diagram. Therefore, the horizontal opening degree difference between the horizontal opening degree of the first eye diagram and the horizontal opening degree of the second eye diagram can represent the difference between the signal timing stability of the first signal and the signal timing stability of the second signal after the first link interferes with the second signal, that is, the influence degree of the first link on the signal timing stability of the second signal. The larger the horizontal opening degree difference, the greater the influence degree of the first link on the signal timing stability of the second signal; the smaller the horizontal opening degree difference, the smaller the influence degree of the first link on the signal timing stability of the second signal.
[0064] The smoothness of the eye diagram edge of the first eye diagram indicates the signal quality of the first signal, and the smoothness of the eye diagram edge of the second eye diagram indicates the signal quality of the second signal. The difference in edge smoothness between the smoothness of the eye diagram edge of the first eye diagram and the smoothness of the eye diagram edge of the second eye diagram can be represented by the absolute value of the difference between the smoothness of the eye diagram edge of the first eye diagram and the smoothness of the eye diagram edge of the second eye diagram. Therefore, the difference in edge smoothness between the smoothness of the eye diagram edge of the first eye diagram and the smoothness of the eye diagram edge of the second eye diagram can represent the difference in signal quality between the first signal obtained after the first link interferes with the second signal and the signal quality of the second signal, that is, the degree of influence of the first link on the signal quality of the second signal. The larger the difference in edge smoothness, the greater the degree of influence of the first link on the signal quality of the second signal; the smaller the difference in edge smoothness, the smaller the degree of influence of the first link on the signal quality of the second signal.
[0065] The central position of the first eye diagram indicates the decision level of the first signal, and the central position of the second eye diagram indicates the decision level of the second signal. The degree of offset between the central position of the first eye diagram and the central position of the second eye diagram can be represented by the horizontal distance between the position of the decision level of the first signal and the position of the decision level of the second signal. Therefore, the degree of offset between the central position of the first eye diagram and the central position of the second eye diagram can represent the position difference between the decision level of the first signal and the decision level of the second signal obtained after the first link interferes with the second signal, that is, the degree of influence of the first link on the position of the decision level of the second signal. The larger the degree of offset, the greater the degree of influence of the first link on the position of the decision level of the second signal; the smaller the degree of offset, the smaller the degree of influence of the first link on the position of the decision level of the second signal.
[0066] The method for determining the state of the first link according to multiple parameters can be as follows: determine whether the multiple parameters meet the preset conditions; when the multiple parameters meet the preset conditions, determine that the state of the first link is abnormal; when the multiple parameters do not meet the preset conditions, determine that the state of the first link is normal; where the preset conditions include at least one of the following:
[0067] The difference in vertical opening degree is greater than or equal to the first preset threshold;
[0068] The difference in horizontal opening degree is greater than or equal to the second preset threshold;
[0069] The difference in edge smoothness is greater than or equal to the third preset threshold;
[0070] The degree of offset is greater than or equal to the fourth preset threshold.
[0071] When multiple parameters meet the preset conditions, it indicates that the interference degree of the first link on the second signal is relatively large, and bit errors may be generated due to the interference of the first link on the second signal. Therefore, when multiple parameters meet the preset conditions, it is determined that the state of the first link is abnormal. When multiple parameters do not meet the preset conditions, it indicates that the interference degree of the first link on the second signal is relatively small, and bit errors will not be generated due to the interference of the first link on the second signal. Therefore, when multiple parameters do not meet the preset conditions, it is determined that the state of the first link is normal.
[0072] It should be noted that in the preset conditions, the first preset threshold, the second preset threshold, the third preset threshold, and the fourth preset threshold may be the same or different.
[0073] Exemplarily, assume that multiple parameters include: the vertical opening degree difference is 10, the horizontal opening degree difference is 5, the edge smoothness difference is 4, and the offset degree is 2; the first preset threshold, the second preset threshold, the third preset threshold, and the fourth preset threshold are all 3, and the preset conditions include: the vertical opening degree difference is greater than or equal to the first preset threshold, the horizontal opening degree difference is greater than or equal to the second preset threshold, the edge smoothness difference is greater than or equal to the third preset threshold, and the offset degree is greater than or equal to the fourth preset threshold. Since the vertical opening degree difference is greater than the first preset threshold, the horizontal opening degree difference is greater than the second preset threshold, and the edge smoothness difference is equal to the third preset threshold. Therefore, it is determined that multiple parameters meet the preset conditions, and at this time, it is determined that the state of the first link is abnormal.
[0074] S404: Perform bit error rate detection on the device to be detected, and determine the bit error rate of the signal transmitted by the device to be detected.
[0075] In response to the normal state of the first link, the method of performing bit error rate detection on the device to be detected and determining the bit error rate of the signal transmitted by the device to be detected can refer to Figure 2 S203 in the illustrated embodiment, which will not be elaborated here.
[0076] It should be noted that when determining the normal state of the first link, turn off the power of the pattern control module, and then perform bit error rate detection on the device to be detected to determine the bit error rate of the signal transmitted by the device to be detected.
[0077] In some embodiments, after determining the normal state of the first link, display a test success message, and the test success message is used to indicate the normal state of the first link.
[0078] S405: Determine at least one signal index according to multiple parameters, and at least one signal index is the signal index of the interference of the first link on the second signal.
[0079] Among them, when the vertical opening degree difference is greater than or equal to the first preset threshold, at least one signal index includes the signal amplitude stability of the second signal; when the horizontal opening degree difference is greater than or equal to the second preset threshold, at least one signal index is the signal timing stability of the second signal; when the edge smoothness difference is greater than or equal to the third preset threshold, at least one signal index includes the signal quality of the second signal; when the offset degree is greater than or equal to the fourth preset threshold, at least one signal index includes the position of the decision level of the second signal.
[0080] Therefore, at least one signal index refers to the signal index of the interference of the first link on the second signal. When at least one signal index includes the signal amplitude stability of the second signal, the signal index of the interference of the first link on the second signal is determined as the signal amplitude stability of the second signal. When at least one index includes the signal timing stability of the second signal, the signal index of the interference of the first link on the second signal is determined as the timing stability of the second signal. When at least one signal index includes the signal quality of the second signal, the signal index of the interference of the first link on the second signal is determined as the signal quality of the second signal. When at least one signal index includes the position of the judgment level of the second signal, the signal index of the interference of the first link on the second signal is determined as the position of the decision level of the second signal.
[0081] Exemplarily, the multiple parameters include: the vertical opening degree difference is 10, the horizontal opening degree difference is 5, the edge smoothness difference is 4, the offset degree is 2, and the first preset threshold, the second preset threshold, the third preset threshold, and the fourth preset threshold are all 3. The preset conditions include: the vertical opening degree difference is greater than or equal to the first preset threshold, the horizontal opening degree difference is greater than or equal to the second preset threshold, the edge smoothness difference is greater than or equal to the third preset threshold, and the offset degree is greater than or equal to the fourth preset threshold. Since the vertical opening degree difference is greater than the first preset threshold, the horizontal opening degree difference is greater than the second preset threshold, and the edge smoothness difference is equal to the third preset threshold, it is determined that at least one signal index includes: the signal amplitude stability of the second signal, the signal timing stability of the second signal, and the signal quality of the second signal. At this time, it can be determined that the signal indexes of the interference of the first link on the second signal include the signal amplitude stability of the second signal, the signal timing stability of the second signal, and the signal quality of the second signal.
[0082] S406: Display a prompt message, which is used to prompt that the state of the first link is abnormal and at least one signal index.
[0083] Exemplarily, assume that the state of the first link is abnormal and at least one signal metric includes: the signal amplitude stability of the second signal, the signal timing stability of the second signal, and the signal quality of the second signal. At this time, the prompt message can be: "The state of the first link is abnormal, and the signal metrics for which the first link interferes with the second signal include: the signal amplitude stability of the second signal, the signal timing stability of the second signal, and the signal quality of the second signal".
[0084] After the prompt message is displayed, the staff can determine the cause of the interference of the first link on the second signal based on the signal metrics for which the first link interferes with the second signal in the prompt message, and then repair the first link accordingly to restore the state of the first link to normal or replace the first link.
[0085] Exemplarily, assume that the signal metric for which the first link interferes with the second signal includes the signal amplitude stability of the second signal. Then, the staff can determine that the reason for the interference of the first link on the second signal is high noise based on the fact that the signal metric for which the first link interferes with the second signal is the signal amplitude stability of the second signal, and then repair the first link accordingly to solve the situation where the first link interferes with the second signal due to high noise and restore the state of the first link to normal.
[0086] In Figure 4In the illustrated embodiment, based on the first eye diagram of the first signal and the second eye diagram of the second signal, a plurality of parameters are determined. The interference degree of the first link on the second signal during the transmission of the second signal can be determined through the plurality of parameters. Then, by determining whether the plurality of parameters meet the preset conditions, the state of the first link is determined. When the plurality of parameters do not meet the preset conditions, it is determined that the state of the first link is normal; when the plurality of parameters meet the preset conditions, it is determined that the state of the first link is abnormal. And in response to the normal state of the first link, a bit error rate detection is performed on the device to be detected to determine the bit error rate of the signal transmitted by the device to be detected; in response to the abnormal state of the first link, at least one signal index of the interference of the first link on the second signal is determined, and then a prompt message is displayed to prompt the abnormal state of the first link and at least one signal index. In the above manner, according to the plurality of parameters, it is determined whether the state of the first link is normal. When the state of the first link is normal, it indicates that the interference degree of the first link on the second signal is small. Therefore, in response to the normal state of the first link, the bit error rate detection device performs a bit error rate detection on the device to be detected to determine the bit error rate of the signal transmitted by the device to be detected. When the state of the first link is abnormal, it indicates that the interference degree of the first link on the second signal is large. Therefore, in response to the abnormal state of the first link, a prompt message is displayed to prompt the abnormal state of the first link and at least one signal index. In this way, when performing a bit error rate detection on the device to be detected, the influence of the first link on determining the bit error rate of the signal transmitted by the device to be detected can be excluded in advance, and the accuracy of determining the bit error rate of the signal transmitted by the device to be detected is improved.
[0087] In Figure 4 the illustrated embodiment, a method for determining the state of the first link is introduced. After determining the first link, the bit error rate detection device performs a bit error rate detection on the device to be detected in response to the normal state of the first link to determine the bit error rate of the signal transmitted by the device to be detected. Next, in combination with Figure 5 , the process of determining the bit error rate of the signal transmitted by the device to be detected will be further described.
[0088] Figure 5 FIG. is a schematic flowchart of a method for determining the bit error rate of a signal transmitted by a device to be detected provided by an embodiment of the present application. Please refer to Figure 5 , and the process may include the following steps:
[0089] S501: Send a third signal to the device to be detected through a second link; the second link is the link from the bit error rate detection device to the device to be detected.
[0090] The second link is the link from the error detection device to the device to be detected. The error detection device can send signals to the device to be detected through the second link. During the process of the error detection device detecting the bit error rate of the device to be detected, the error detection device can send a third signal to the device to be detected through the second link.
[0091] It should be noted that the second link is a link after verification. When the verified link transmits signals, it will not interfere with the signals. Therefore, during the process of the second link transmitting the third signal, it will not interfere with the third signal.
[0092] In some embodiments, the third signal can be a signal with a preset code pattern. Exemplarily, assuming that the preset code pattern of the third signal is 1000, then the error detection device sends 1000 to the device to be detected through the second link.
[0093] S502: Receive the fourth signal sent by the device to be detected. The fourth signal is the signal obtained by the device to be detected after receiving the third signal.
[0094] After transmitting the third signal to the device to be detected through the second link, when the device to be detected receives the third signal, bit errors may occur, resulting in the signal received by the device to be detected being the fourth signal. Therefore, the fourth signal is the signal obtained after bit errors occur when the device to be detected receives the third signal.
[0095] Exemplarily, assuming that the third signal is 1000 and bit errors occur when the device to be detected receives the third signal, and the bit errors generated when the device to be detected receives the third signal are 1001. At this time, the fourth signal received by the device to be detected is 1001.
[0096] After receiving the fourth signal, the device to be detected sends the fourth signal to the error detection device through the first link.
[0097] It can be understood in combination with Figure 6 For understanding, Figure 6 FIG. is a schematic diagram for receiving the fourth signal sent by the device to be detected provided by the embodiment of the present application. Please refer to Figure 6 , the device to be detected 11 and the error detection device 13 are connected through link A and link B. Among them, link A is the link from the device to be detected 11 to the error detection device 13, that is, link A is the first link; line B is the link from the error detection device 13 to the device to be detected 11, that is, link B is the second link. The error detection device 13 sends a third signal to the device to be detected 11 through link B. When the device to be detected receives the third signal, bit errors occur, resulting in the signal received by the detection device being the fourth signal. After receiving the fourth signal, the device to be detected sends the device to be detected to the error detection device through link A.
[0098] S503: Determine the bit error rate of the transmission signal of the device to be detected according to the third signal and the fourth signal.
[0099] The third signal includes a plurality of first code elements, and the fourth signal includes a plurality of second code elements corresponding to the respective first code elements. It should be noted that the number of the plurality of first code elements included in the third signal is the same as the number of the plurality of second code elements corresponding to the respective first code elements included in the fourth signal.
[0100] Exemplarily, assume that the third signal is 1000. Then the plurality of first code elements included in the third signal are 1, 0, 0, 0 respectively, and the number of the plurality of first code elements included in the third signal is 4. Assume that the fourth signal is 1011. Then the plurality of second code elements included in the fourth signal are 1, 0, 1, 1 respectively. Among them, the first second code element "1" in the fourth signal is the second code element corresponding to the first first code element "1" in the third signal; the two second code elements "0" in the fourth signal are the second code elements corresponding to the two first code elements "0" in the third signal; the third second code element "1" in the fourth signal is the second code element corresponding to the third first code element "0" in the third signal; the fourth second code element "1" in the fourth signal is the second code element corresponding to the fourth first code element "0" in the third signal.
[0101] The method for determining the bit error rate of the transmission signal of the device to be detected according to the third signal and the fourth signal can be as follows: Determine at least one target code element among the plurality of first code elements according to the second code elements corresponding to the respective first code elements. Among them, for each target code element, the target code element is different from the corresponding second code element of the target code element. Determine the bit error rate of the transmission signal of the device to be detected according to the number of the plurality of first code elements and the number of at least one target code element.
[0102] Exemplarily, assume that the third signal is 1000. Then the plurality of first code elements included in the third signal are 1, 0, 0, 0 respectively, and the number of the plurality of first code elements included in the third signal is 4. Assume that the fourth signal is 1011. Then the second code element corresponding to the first first code element "1" in the third signal is "1", the second code element corresponding to the second first code element "0" in the third signal is "0", the second code element corresponding to the third first code element "0" in the third signal is "1", and the second code element corresponding to the fourth first code element "0" in the third signal is "1". Therefore, determining at least one target code element among the plurality of first code elements includes: the third first code element "0" and the fourth first code element "0" in the third signal, and the number of at least one target code element is 2.
[0103] Since the number of the plurality of first code elements is 4 and the number of at least one target code element is 2, the bit error rate of the transmission signal of the device to be detected is determined to be 2 / 4 * 100% = 50%.
[0104] InFigure 5 In the illustrated embodiment, after the error detection device sends the third signal to the device under test through the second link, the device under test generates an error when receiving the third signal. Therefore, the signal received by the device under test is the fourth signal, and after the device under test receives the fourth signal, it sends the fourth signal to the error detection device through the first link. Then, the error detection device determines the bit error rate of the signal transmitted by the device under test based on the third signal and the fourth signal. In the above method for detecting the bit error rate of the device under test, since the second link does not interfere with the third signal during the transmission of the third signal, and the first link does not interfere with the fourth signal during the transmission of the fourth signal, or the interference degree on the fourth signal is small and can be ignored. Therefore, during the process of the error detection device detecting the bit error rate of the device under test, the determined bit error rate of the signal transmitted by the device under test will not be affected by the signal transmission link, thereby improving the accuracy of determining the bit error rate of the signal transmitted by the device under test.
[0105] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases the former is a better implementation method.
[0106] Figure 7 It is a schematic structural diagram of an error detection device provided by an embodiment of the present application. As Figure 7 shown, an embodiment of the present application further provides an error detection device 70, and the device includes a receiving module 71, a determining module 72, and a detecting module 73, wherein:
[0107] The receiving module 71 is configured to receive a first signal, where the first signal is a signal received by the error detection device after the second signal is transmitted through the first link, and the second signal is a signal sent by the pattern control module to the error detection device; the pattern control module is integrated in the fixture, the fixture is connected to the error detection device through the first link, and the fixture is connected to the device under test through an interface on the device under test;
[0108] The determining module 72 is configured to determine whether the state of the first link is normal according to the first signal and the second signal;
[0109] The detecting module 73, in response to the state of the first link being normal, performs a bit error rate detection on the device under test to determine the bit error rate of the signal transmitted by the device under test.
[0110] In a possible implementation manner, the determining module 72 is specifically configured to:
[0111] Generate a first eye diagram of the first signal according to the received waveform of the first signal;
[0112] Generate the second eye diagram of the second signal according to a preset code pattern;
[0113] Determine the state of the first link according to the first eye diagram and the second eye diagram.
[0114] In a possible implementation manner, the determining module 72 is specifically configured to:
[0115] Obtain a plurality of parameters according to the first eye diagram and the second eye diagram, and the plurality of parameters are used to indicate the interference of the first link on the second signal;
[0116] Determine the state of the first link according to the plurality of parameters.
[0117] In a possible implementation manner, the plurality of parameters respectively include: the vertical opening degree difference between the vertical opening degree of the first eye diagram and the vertical opening degree of the second eye diagram, the horizontal opening degree difference between the horizontal opening degree of the first eye diagram and the horizontal opening degree of the second eye diagram, the edge smoothness difference between the edge smoothness of the first eye diagram and the edge smoothness of the second eye diagram, and the offset degree between the center position of the first eye diagram and the center position of the second eye diagram;
[0118] The determining module 72 is specifically configured to:
[0119] Determine whether the plurality of parameters meet a preset condition;
[0120] When the plurality of parameters meet the preset condition, determine that the state of the first link is abnormal;
[0121] When the plurality of parameters do not meet the preset condition, determine that the state of the first link is normal;
[0122] Wherein, the preset condition includes at least one of the following:
[0123] The vertical opening degree difference is greater than or equal to a first preset threshold;
[0124] The horizontal opening degree difference is greater than or equal to a second preset threshold;
[0125] The edge smoothness difference is greater than or equal to a third preset threshold;
[0126] The offset degree is greater than or equal to a fourth preset threshold.
[0127] In a possible implementation manner, the error code detection device 70 further includes a processing module, and the processing module is specifically configured to:
[0128] In response to the abnormal state of the first link, determine at least one signal index according to the plurality of parameters, and the at least one signal index is a signal index of the interference of the first link on the second signal;
[0129] Display a prompt message, which is used to prompt the abnormal state of the first link and at least one signal metric;
[0130] Among them, when the vertical opening difference is greater than or equal to the first preset threshold, at least one signal metric includes the signal amplitude stability of the second signal;
[0131] When the horizontal opening difference is greater than or equal to the second preset threshold, at least one signal metric includes the signal timing stability of the second signal;
[0132] When the edge smoothness difference is greater than or equal to the third preset threshold, at least one signal metric includes the signal quality of the second signal;
[0133] When the offset is greater than or equal to the fourth preset threshold, at least one signal metric includes the position of the decision level of the second signal.
[0134] In a possible implementation manner, the detection module 73 is specifically configured to:
[0135] Send a third signal to the device to be detected through the second link; the second link is the link from the error code detection device to the device to be detected;
[0136] Receive a fourth signal sent by the device to be detected, where the fourth signal is the signal obtained by the device to be detected after receiving the third signal;
[0137] Determine the bit error rate of the signal transmitted by the device to be detected according to the third signal and the fourth signal.
[0138] In a possible implementation manner, the third signal includes a plurality of first code elements, and the fourth signal includes second code elements corresponding to the respective first code elements; the detection module 73 is specifically configured to:
[0139] Determine at least one target code element among the plurality of first code elements according to the second code elements corresponding to the respective first code elements; wherein, for each target code element, the target code element is different from the corresponding second code element of the target code element;
[0140] Determine the bit error rate of the signal transmitted by the device to be detected according to the number of the plurality of first code elements and the number of at least one target code element.
[0141] For the description of the features in the embodiments corresponding to the error code detection device 70, reference can be made to the relevant descriptions in the embodiments corresponding to the error code detection method, which will not be elaborated here one by one.
[0142] Figure 8 It is a schematic structural diagram of the electronic device provided by this application. As Figure 8As shown, the electronic device 80 provided in this embodiment includes: at least one processor 81 and a memory 82. Optionally, the electronic device 80 further includes a communication component 83. Among them, the processor 81, the memory 82, and the communication component 83 are connected through a bus.
[0143] In a specific implementation process, at least one processor 81 executes the computer-executable instructions stored in the memory 82, so that at least one processor 81 executes the above-described embodiment of the error code detection method.
[0144] For the specific implementation process of the processor 81, reference can be made to the above method embodiment. The implementation principle and technical effect are similar, and will not be elaborated here in this embodiment.
[0145] In the above embodiment, it should be understood that the processor may be a central processing unit (Central Processing Unit, abbreviated as: CPU), or other general-purpose processors, digital signal processors (Digital Signal Processor, abbreviated as: DSP), application specific integrated circuits (Application Specific Integrated Circuit, abbreviated as: ASIC), etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. The steps of the method disclosed in combination with the application can be directly embodied as being executed by a hardware processor, or executed by a combination of hardware and software modules in the processor.
[0146] The memory may include a high-speed memory (Random Access Memory, RAM), and may also include a non-volatile memory (Non-volatile Memory, NVM), such as at least one disk memory.
[0147] The bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For the convenience of representation, the bus in the drawings of this application is not limited to only one bus or one type of bus.
[0148] An embodiment of the present application also provides a computer-readable storage medium, in which a computer program is stored, and the computer program is configured to execute the steps in any one of the above-described embodiments of the error code detection method when running.
[0149] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to: various media such as USB flash drives, read-only memory (ROM for short), random access memory (RAM for short), mobile hard disks, magnetic disks, or optical discs that can store computer programs.
[0150] An embodiment of the present application also provides a computer program product. The computer program product includes a computer program, and when the computer program is executed by a processor, the steps in any of the embodiments of the above error code detection method are implemented.
[0151] Another embodiment of the present application also provides a computer program product, including a non-volatile computer-readable storage medium. The non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the embodiments of the above error code detection method are implemented.
[0152] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.
[0153] The above has introduced in detail an error code detection method, device, electronic device, and storage medium provided by this application. Specific examples are used in this article to elaborate on the principle and implementation manner of this application. The description of the above embodiments is only used to help understand the method and its core idea of this application. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the principle of this application, several improvements and modifications can still be made to this application, and these improvements and modifications also fall within the protection scope of the claims of this application.
Claims
1. An error code detection method, characterized in that, The method includes: Receiving a first signal, where the first signal is the signal received by the error detection device after the second signal is transmitted through the first link, and the second signal is the signal sent by the pattern control module to the error detection device; the pattern control module is integrated in a fixture, the fixture is connected to the error detection device through the first link, and the fixture is connected to the device under test through an interface on the device under test; Determining whether the state of the first link is normal according to the first signal and the second signal; In response to the state of the first link being normal, performing an error rate detection on the device under test to determine the error rate of the signal transmitted by the device under test.
2. The method according to claim 1, wherein The second signal is a signal of a preset pattern; determining the state of the first link according to the first signal and the second signal includes: Generating a first eye diagram of the first signal according to the received waveform of the first signal; Generating a second eye diagram of the second signal according to the preset pattern; Determining the state of the first link according to the first eye diagram and the second eye diagram.
3. The method according to claim 2, characterized in that, Determining the state of the first link according to the first eye diagram and the second eye diagram includes: Obtaining a plurality of parameters according to the first eye diagram and the second eye diagram, where the plurality of parameters are used to indicate the interference of the first link on the second signal; Determining the state of the first link according to the plurality of parameters.
4. The method according to claim 3, characterized in that, The plurality of parameters respectively include: the vertical opening degree difference between the vertical opening degree of the first eye diagram and the vertical opening degree of the second eye diagram, the horizontal opening degree difference between the horizontal opening degree of the first eye diagram and the horizontal opening degree of the second eye diagram, the edge smoothness difference between the edge smoothness of the first eye diagram and the edge smoothness of the second eye diagram, and the offset degree between the center position of the first eye diagram and the center position of the second eye diagram; Determining the state of the first link according to the plurality of parameters includes: Determining whether the plurality of parameters meet a preset condition; When the plurality of parameters meet the preset condition, determining that the state of the first link is abnormal; When the plurality of parameters do not meet the preset condition, determining that the state of the first link is normal; Wherein, the preset condition includes at least one of the following: The vertical opening degree difference is greater than or equal to a first preset threshold; The horizontal opening degree difference is greater than or equal to a second preset threshold; The edge smoothness difference is greater than or equal to a third preset threshold; The offset degree is greater than or equal to a fourth preset threshold.
5. The method according to claim 4, wherein The method further includes: In response to the state of the first link being abnormal, determining at least one signal index according to the plurality of parameters, where the at least one signal index is the signal index of the interference of the first link on the second signal; Displaying a prompt message, where the prompt message is used to prompt that the state of the first link is abnormal and the at least one signal index; Wherein, when the vertical opening degree difference is greater than or equal to the first preset threshold, the at least one signal index includes the signal amplitude stability of the second signal; When the difference in the horizontal opening degree is greater than or equal to a second preset threshold, the at least one signal metric includes the signal timing stability of the second signal; When the difference in the edge smoothness is greater than or equal to a third preset threshold, the at least one signal metric includes the signal quality of the second signal; When the degree of offset is greater than or equal to a fourth preset threshold, the at least one signal metric includes the position of the decision level of the second signal.
6. The method according to any one of claims 1-5, characterized in that, The performing error rate detection on the device to be detected and determining the error rate of the signal transmitted by the device to be detected includes: Sending a third signal to the device to be detected through a second link; the second link is the link from the error detection device to the device to be detected; Receiving a fourth signal sent by the device to be detected, where the fourth signal is a signal obtained by the device to be detected receiving the third signal; Determining the error rate of the signal transmitted by the device to be detected according to the third signal and the fourth signal.
7. The method according to claim 6, characterized in that, The third signal includes a plurality of first code elements, and the fourth signal includes second code elements corresponding to the respective first code elements; the determining the error rate of the signal transmitted by the device to be detected includes: Determining at least one target code element among the plurality of first code elements according to the second code elements corresponding to the respective first code elements; wherein, for each target code element, the target code element is different from the second code element corresponding to the target code element; Determining the error rate of the signal transmitted by the device to be detected according to the number of the plurality of first code elements and the number of the at least one target code element.
8. An error code detection device, characterized in that, The apparatus includes: A receiving module, configured to receive a first signal, where the first signal is a signal received by the error detection device after the second signal is transmitted through a first link, and the second signal is a signal sent by a pattern control module to the error detection device; the pattern control module is integrated in a fixture, the fixture is connected to the error detection device through the first link, and the fixture is connected to the device to be detected through an interface on the device to be detected; A determining module, configured to determine whether the state of the first link is normal according to the first signal and the second signal; A detecting module, in response to the state of the first link being normal, performing error rate detection on the device to be detected and determining the error rate of the signal transmitted by the device to be detected.
9. An electronic device, characterized in that, including: A memory, configured to store a computer program; A processor, configured to implement the steps of the error detection method according to any one of claims 1 to 7 when executing the computer program.
10. A computer-readable storage medium, characterized in that, A computer program is stored in the computer-readable storage medium, where the computer program, when executed by a processor, implements the steps of the error detection method according to any one of claims 1 to 7.