Display panel and display device

Abstract

A display panel and a display device, the display panel comprises a pixel driving circuit, the pixel driving circuit comprises a driving transistor (T3), a fifth transistor (T5) and an eighth transistor (T8), a first electrode of the fifth transistor (T5) is connected with a first power line (VDD), a second electrode of the fifth transistor (T5) is connected with a first electrode of the driving transistor (T3), and a second electrode of the eighth transistor (T8) is connected with a second electrode of the driving transistor (T3). The second pole of the eighth transistor (T8) is connected with the first pole of the driving transistor (T3); the display panel comprises a substrate, an enable signal line (EM) and a third initial signal line (Vinit3), the enable signal line (EM) is located on one side of the substrate, the enable signal line (EM) is connected to the grid electrode of the fifth transistor (T5), and the orthographic projection of the enable signal line (EM) on the substrate extends in the first direction (X); the third initial signal line (Vinit3) is located on one side of the substrate, the third initial signal line (Vinit3) is connected to the first pole of the eighth transistor (T8), the third initial signal line (Vinit3) comprises a first extension part (Vinit31), a second extension part (Vinit32) and a third extension part (Vinit33), and the third extension part (Vinit33) is connected between the first extension part (Vinit31) and the second extension part (Vinit32); wherein the orthographic projection of the first extension part (Vinit31) on the substrate and the orthographic projection of the second extension part (Vinit32) on the substrate extend along a first direction (X) and are staggered in a second direction (Y), and the first direction (X) and the second direction (Y) intersect; the orthographic projection of the first extension part (Vinit31) on the substrate does not intersect with the orthographic projection of the enable signal line (EM) on the substrate, the orthographic projection of the second extension part (Vinit32) on the substrate does not intersect with the orthographic projection of the enable signal line (EM) on the substrate, and the display quality can be improved by the display panel.

Description

Display panel and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In related technologies, enable signal lines can output multiple pulse signals within a single pixel drive cycle to improve the display quality of a display panel. However, these lines can couple with other conductive layer structures, leading to unstable voltages on these structures and, in turn, causing issues like horizontal stripes or poor split-screen display on the display panel.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field.

[0004] Summary of the Invention

[0005] According to one aspect of the present disclosure, a display panel is provided, the display panel including a pixel driving circuit, the pixel driving circuit including a driving transistor, a fifth transistor, and an eighth transistor, wherein a first electrode of the fifth transistor is connected to a first power line, a second electrode of the fifth transistor is connected to the first electrode of the driving transistor, and a second electrode of the eighth transistor is connected to the first electrode of the driving transistor;

[0006] The display panel includes:

[0007] substrate;

[0008] an enable signal line located on one side of the base substrate, the enable signal line being connected to the gate of the fifth transistor, and an orthographic projection of the enable signal line on the base substrate extending along a first direction;

[0009] a third initial signal line, located on one side of the substrate, connected to the first electrode of the eighth transistor, comprising a first extension portion, a second extension portion, and a third extension portion, wherein the third extension portion is connected between the first extension portion and the second extension portion;

[0010] The orthographic projection of the first extension portion on the base substrate and the orthographic projection of the second extension portion on the base substrate extend along the first direction and are staggered in the second direction, and the first direction and the second direction intersect;

[0011] The orthographic projection of the first extension portion on the base substrate does not intersect with the orthographic projection of the enable signal line on the base substrate, and the orthographic projection of the second extension portion on the base substrate does not intersect with the orthographic projection of the enable signal line on the base substrate.

[0012] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0013] a first active layer located on one side of the base substrate, the first active layer comprising a fifth active portion, the fifth active portion being used to form a channel region of the fifth transistor;

[0014] A first conductive layer is located on a side of the first active layer facing away from the base substrate, the first conductive layer includes the enable signal line, the orthographic projection of the enable signal line on the base substrate covers the orthographic projection of the fifth active portion on the base substrate, and a partial structure of the enable signal line is used to form the gate of the fifth transistor.

[0015] In an exemplary embodiment of the present disclosure, an orthographic projection of the third extending portion on the base substrate intersects with an orthographic projection of the enable signal line on the base substrate.

[0016] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a second transistor, a first electrode of the second transistor being connected to the gate electrode of the driving transistor, and a second electrode being connected to the second electrode of the driving transistor, and the display panel further includes:

[0017] a fourth conductive layer, located on one side of the base substrate, the fourth conductive layer comprising a first bridge portion, the first bridge portion being connected to the gate of the driving transistor and the first electrode of the second transistor through via holes;

[0018] In the same pixel driving circuit, an orthographic projection of the first extending portion on the base substrate is located between an orthographic projection of the enable signal line on the base substrate and an orthographic projection of the first bridge portion on the base substrate.

[0019] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0020] a first active layer comprising an eighth active portion, wherein the eighth active portion is used to form a channel region of the eighth transistor;

[0021] a first conductive layer comprising a second reset signal line, wherein an orthographic projection of the second reset signal line on the base substrate extends along the first direction and covers an orthographic projection of the eighth active portion on the base substrate, and a portion of the second reset signal line is used to form a gate of the eighth transistor;

[0022] In the same pixel driving circuit, at least part of the orthographic projection of the second extension portion on the base substrate is located on a side of the orthographic projection of the second reset signal line on the base substrate away from the orthographic projection of the enable signal line on the base substrate.

[0023] In an exemplary embodiment of the present disclosure, the display panel further includes a light-emitting unit, the pixel driving circuit is used to drive the light-emitting unit to emit light, and the pixel driving circuit further includes a sixth transistor, a first electrode of the sixth transistor is connected to the second electrode of the driving transistor, and a second electrode of the sixth transistor is connected to the first electrode of the light-emitting unit;

[0024] The display panel further includes:

[0025] a first active layer comprising a sixth active portion and an eighth active portion, wherein the sixth active portion is used to form a channel region of the sixth transistor, and the eighth active portion is used to form a channel region of the eighth transistor;

[0026] In the same pixel driving circuit, in the first direction, an orthographic projection of at least part of the third extending portion on the base substrate is located between an orthographic projection of the sixth active portion on the base substrate and an orthographic projection of the eighth active portion on the base substrate.

[0027] In an exemplary embodiment of the present disclosure, the orthographic projection of the first power line on the base substrate and the orthographic projection of the third extension portion on the base substrate both extend along the second direction, and the orthographic projection of the first power line on the base substrate and the orthographic projection of the third extension portion on the base substrate do not overlap.

[0028] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0029] a first active layer including a third active portion, wherein the third active portion is used to form a channel region of the driving transistor;

[0030] a first conductive layer, comprising a first conductive portion, wherein an orthographic projection of the first conductive portion on the base substrate covers an orthographic projection of the third active portion on the base substrate, and the first conductive portion is used to form a gate of the driving transistor;

[0031] In the same pixel driving circuit, the orthographic projection of the third initial signal line on the base substrate is located on a side of the orthographic projection of the enable signal line on the base substrate away from the orthographic projection of the first conductive portion on the base substrate.

[0032] In an exemplary embodiment of the present disclosure, the first active layer further includes:

[0033] an eighth active portion, the eighth active portion being configured to form a channel region of the eighth transistor;

[0034] The first conductive layer further comprises:

[0035] a second reset signal line, an orthographic projection of the second reset signal line on the base substrate extending along the first direction and covering an orthographic projection of the eighth active portion on the base substrate, and a portion of the second reset signal line forming a gate of the eighth transistor;

[0036] The orthographic projection of the first extension portion on the base substrate and the orthographic projection of the second reset signal line in the pixel driving circuit of the same row on the base substrate at least partially overlap.

[0037] In an exemplary embodiment of the present disclosure, the display panel further includes a light-emitting unit, the pixel driving circuit is used to drive the light-emitting unit to emit light, and the pixel driving circuit further includes a first transistor and a seventh transistor;

[0038] A first electrode of the first transistor is connected to a first initial signal line, and a second electrode of the first transistor is connected to a second electrode of the driving transistor;

[0039] A first electrode of the seventh transistor is connected to the second initial signal line, and a second electrode is connected to the first electrode of the light emitting unit;

[0040] The display panel further includes:

[0041] a first active layer located on one side of the base substrate, the first active layer comprising a first active portion, a third active portion, and a seventh active portion, the first active portion being used to form a channel region of the first transistor, the third active portion being used to form a channel region of the driving transistor, and the seventh active portion being used to form a channel region of the seventh transistor;

[0042] a first conductive layer, located on a side of the first active layer facing away from the base substrate, the first conductive layer comprising a first reset signal line, a second reset signal line, and a first conductive portion, an orthographic projection of the first reset signal line on the base substrate extending along the first direction and covering an orthographic projection of the first active portion on the base substrate, a portion of the first reset signal line forming a gate of the first transistor, an orthographic projection of the second reset signal line on the base substrate extending along the first direction and covering an orthographic projection of the seventh active portion on the base substrate, a portion of the second reset signal line forming a gate of the seventh transistor, an orthographic projection of the first conductive portion on the base substrate covering an orthographic projection of the third active portion on the base substrate, and the first conductive portion forming a gate of the driving transistor;

[0043] The orthographic projection of the second extension portion on the base substrate is located between the orthographic projection of the first reset signal line in the adjacent next row of pixel driving circuits on the base substrate and the orthographic projection of the second reset signal line in the current row of pixel driving circuits on the base substrate.

[0044] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a second transistor, a first electrode of the second transistor being connected to a gate of the driving transistor, and the display panel further includes:

[0045] a fourth conductive layer, located on a side of the first conductive layer facing away from the base substrate, the fourth conductive layer comprising a first bridge portion, the first bridge portion connecting the gate of the driving transistor and the first electrode of the second transistor through via holes;

[0046] Wherein, the fourth conductive layer further includes the third initial signal line.

[0047] In an exemplary embodiment of the present disclosure, the display panel further includes a light-emitting unit, the pixel driving circuit is used to drive the light-emitting unit to emit light, and the pixel driving circuit further includes a first transistor and a seventh transistor;

[0048] A first electrode of the first transistor is connected to a first initial signal line, and a second electrode of the first transistor is connected to a second electrode of the driving transistor;

[0049] A first electrode of the seventh transistor is connected to the second initial signal line, and a second electrode is connected to the first electrode of the light emitting unit;

[0050] The display panel further includes:

[0051] a first active layer located on one side of the base substrate, the first active layer comprising a first active portion, a third active portion, and a seventh active portion, the first active portion being used to form a channel region of the first transistor, the third active portion being used to form a channel region of the driving transistor, and the seventh active portion being used to form a channel region of the seventh transistor;

[0052] a first conductive layer, located on a side of the first active layer facing away from the base substrate, the first conductive layer comprising a first reset signal line, a second reset signal line, and a first conductive portion, an orthographic projection of the first reset signal line on the base substrate extending along the first direction and covering an orthographic projection of the first active portion on the base substrate, a portion of the first reset signal line forming a gate of the first transistor, an orthographic projection of the second reset signal line on the base substrate extending along the first direction and covering an orthographic projection of the seventh active portion on the base substrate, a portion of the second reset signal line forming a gate of the seventh transistor, an orthographic projection of the first conductive portion on the base substrate covering an orthographic projection of the third active portion on the base substrate, and the first conductive portion forming a gate of the driving transistor;

[0053] In the same pixel driving circuit, an orthographic projection of the first conductive portion on the base substrate is located between an orthographic projection of the first reset signal line on the base substrate and an orthographic projection of the second reset signal line on the base substrate;

[0054] At least part of the orthographic projection of the third initial signal line on the substrate is located between the orthographic projection of the second reset signal line in the pixel driving circuit of the current row on the substrate and the orthographic projection of the first reset signal line in the pixel driving circuit of the next adjacent row on the substrate.

[0055] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0056] a fifth conductive layer, located on a side of the first conductive layer facing away from the base substrate, the fifth conductive layer comprising a ninth bridge portion, the ninth bridge portion being connected to the first electrode of the fifth transistor through a via hole;

[0057] a sixth conductive layer, located on a side of the fifth conductive layer away from the fifth conductive layer, the sixth conductive layer comprising the first power line, and the first power line being connected to the ninth bridge portion through a via hole;

[0058] The seventh conductive layer is located on a side of the sixth conductive layer away from the base substrate, and the seventh conductive layer includes the third initial signal line.

[0059] In an exemplary embodiment of the present disclosure, the fifth conductive layer includes a plurality of the ninth bridge portions and a plurality of first connecting portions, wherein the plurality of the ninth bridge portions are distributed in the first direction and the second direction, and the first connecting portion is connected between two adjacent ninth bridge portions in the first direction;

[0060] The sixth conductive layer includes a plurality of first power lines, and the orthographic projections of the plurality of first power lines on the base substrate extend along the second direction and are spaced apart along the first direction;

[0061] The first power line is connected to the ninth bridge portion intersecting with its orthographic projection on the base substrate through a via hole.

[0062] In an exemplary embodiment of the present disclosure, the conductive layer where the third initial signal line is located is located on the side of the conductive layer where the enable signal line is located away from the base substrate, and the square resistance of the conductive layer where the third initial signal line is located is smaller than the square resistance of the conductive layer where the enable signal line is located.

[0063] In an exemplary embodiment of the present disclosure, the display panel further includes a plurality of repeating units distributed along the first direction and the second direction, the repeating units including a first pixel driving circuit and a second pixel driving circuit distributed in the first direction, and the first pixel driving circuit and the second pixel driving circuit are at least partially mirror-symmetrically arranged.

[0064] In an exemplary embodiment of the present disclosure, the first extension portion includes a first sub-extension portion and a second sub-extension portion, and a size of an orthographic projection of the first sub-extension portion on the base substrate in the second direction is smaller than a size of an orthographic projection of the second sub-extension portion on the base substrate in the second direction;

[0065] An orthographic projection of the first power line on the base substrate extends along the second direction and at least partially overlaps with an orthographic projection of the first sub-extension portion on the base substrate.

[0066] In an exemplary embodiment of the present disclosure, the display panel further includes a light-emitting unit, the pixel driving circuit is used to drive the light-emitting unit, and the pixel driving circuit further includes a first transistor and a seventh transistor;

[0067] A first electrode of the first transistor is connected to a first initial signal line, and a second electrode of the first transistor is connected to a second electrode of the driving transistor;

[0068] A first electrode of the seventh transistor is connected to the second initial signal line, and a second electrode is connected to the first electrode of the light emitting unit;

[0069] The display panel further includes:

[0070] a first active layer located on one side of the base substrate, the first active layer comprising a first active portion and a seventh active portion, the first active portion being used to form a channel region of the first transistor, and the seventh active portion being used to form a channel region of the seventh transistor;

[0071] a first conductive layer located on a side of the first active layer facing away from the base substrate, the first conductive layer comprising a first reset signal line and a second reset signal line, an orthographic projection of the first reset signal line on the base substrate extending along the first direction and covering an orthographic projection of the first active portion on the base substrate, a portion of the first reset signal line forming a gate of the first transistor, an orthographic projection of the second reset signal line on the base substrate extending along the first direction and covering an orthographic projection of the seventh active portion on the base substrate, and a portion of the second reset signal line forming a gate of the seventh transistor;

[0072] The orthographic projection of the first initial signal line on the substrate and the orthographic projection of the second reset signal line in the adjacent previous row of pixel driving circuits on the substrate at least partially overlap;

[0073] The orthographic projection of the second initial signal line on the base substrate at least partially overlaps with the orthographic projection of the first reset signal line in an adjacent row of pixel driving circuits on the base substrate.

[0074] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a second transistor, a first electrode of the second transistor being connected to the gate electrode of the driving transistor, and a second electrode being connected to the second electrode of the driving transistor, and the display panel further includes:

[0075] A first active layer is located on one side of the base substrate;

[0076] a first conductive layer, located on a side of the first active layer facing away from the substrate;

[0077] a second active layer, located on a side of the first conductive layer away from the first active layer, the second active layer comprising a second active portion, the second active portion being used to form a channel region of the second transistor;

[0078] a third conductive layer, located on a side of the second active layer facing away from the base substrate, the third conductive layer comprising a first gate line, an orthographic projection of the first gate line on the base substrate extending along the first direction and covering an orthographic projection of the second active portion on the base substrate, and a portion of the first gate line forming a gate of the second transistor;

[0079] The fourth conductive layer is located on a side of the third conductive layer away from the base substrate.

[0080] The fifth conductive layer is located on a side of the fourth conductive layer away from the base substrate.

[0081] In an exemplary embodiment of the present disclosure, the display panel further includes a light-emitting unit, the pixel driving circuit is used to drive the light-emitting unit to emit light, and the pixel driving circuit further includes:

[0082] a first transistor, a first electrode of which is connected to the first initial signal line, and a second electrode of which is connected to the second electrode of the driving transistor;

[0083] a second transistor, a first electrode of which is connected to the gate electrode of the driving transistor, and a second electrode of which is connected to the second electrode of the driving transistor;

[0084] a fourth transistor, a first electrode of which is connected to the data line, and a second electrode of which is connected to the first electrode of the driving transistor;

[0085] a sixth transistor, a first electrode of which is connected to the second electrode of the driving transistor, and a second electrode of which is connected to the first electrode of the light-emitting unit;

[0086] a seventh transistor, a first electrode connected to the second initial signal line, and a second electrode connected to the first electrode of the light-emitting unit;

[0087] a capacitor, a first electrode of which is connected to the gate of the driving transistor, and a second electrode of which is connected to the first power line;

[0088] The first transistor, the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are P-type transistors, and the second transistor is an N-type transistor.

[0089] In an exemplary embodiment of the present disclosure, within one driving cycle of the pixel driving circuit, the enable signal line outputs a plurality of pulse signals.

[0090] According to one aspect of the present disclosure, a display device is provided, comprising the above-mentioned display panel.

[0091] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0092] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0093] FIG1 is a schematic structural diagram of an exemplary embodiment of a pixel driving circuit disclosed herein;

[0094] FIG2 is a timing diagram of some nodes in an exemplary embodiment of the pixel driving circuit shown in FIG1 ;

[0095] FIG3 is a structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0096] FIG4 is a structural diagram of the first active layer in FIG3 ;

[0097] FIG5 is a structural diagram of the first conductive layer in FIG3 ;

[0098] FIG6 is a structural diagram of the second conductive layer in FIG3 ;

[0099] FIG7 is a structural diagram of the second active layer in FIG3;

[0100] FIG8 is a structural diagram of the third conductive layer in FIG3 ;

[0101] FIG9 is a structural diagram of the fourth conductive layer in FIG3 ;

[0102] FIG10 is a structural diagram of the fifth conductive layer in FIG3 ;

[0103] FIG11 is a structural diagram of the sixth conductive layer in FIG3 ;

[0104] FIG12 is a structural layout diagram of the first active layer and the first conductive layer in FIG3;

[0105] FIG13 is a structural layout diagram of the first active layer, the first conductive layer, and the second conductive layer in FIG3 ;

[0106] FIG14 is a structural layout diagram of the first active layer, the first conductive layer, the second conductive layer, and the second active layer in FIG3 ;

[0107] FIG15 is a structural layout diagram of the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer in FIG3 ;

[0108] FIG16 is a structural layout diagram of the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer in FIG3;

[0109] FIG17 is a structural layout diagram of the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer in FIG3 ;

[0110] FIG18 is a partial cross-sectional view of the display panel shown in FIG3 taken along dotted line BB;

[0111] FIG19 is a schematic structural diagram of another exemplary embodiment of a display panel disclosed herein;

[0112] FIG20 is a structural layout diagram of the fourth conductive layer in the display panel shown in FIG19 ;

[0113] FIG21 is a schematic structural diagram of another exemplary embodiment of a display panel disclosed herein;

[0114] FIG22 is a structural layout diagram of the conductive layer where the third initial signal line is located in the display panel shown in FIG21 . DETAILED DESCRIPTION

[0115] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent like or similar structures, and thus their detailed description will be omitted.

[0116] The terms "a", "an", and "said" are used to indicate that there are one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc.

[0117] This exemplary embodiment first provides a pixel driving circuit, as shown in Figures 1 and 2. Figure 1 is a structural diagram of an exemplary embodiment of the pixel driving circuit disclosed in the present invention, and Figure 2 is a timing diagram of some nodes in an exemplary embodiment of the pixel driving circuit shown in Figure 1.

[0118] The pixel driving circuit may include: a driving transistor T3, a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a capacitor C. A first electrode of the fourth transistor T4 is connected to the data signal terminal Da, a second electrode of the fourth transistor T4 is connected to the first electrode of the driving transistor T3, and a gate of the fourth transistor T4 is connected to the second gate driving signal terminal G2; a first electrode of the fifth transistor T5 is connected to the first power supply terminal VDD, a second electrode of the fifth transistor T5 is connected to the first electrode of the driving transistor T3, and a gate of the fifth transistor T5 is connected to the enable signal terminal EM; a gate of the driving transistor T3 is connected to a node N; a first electrode of the second transistor T2 is connected to the node N, a second electrode of the second transistor T2 is connected to the second electrode of the driving transistor T3, and a gate of the second transistor T2 is connected to the first gate driving signal terminal G1; a first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T3, and a second electrode of the sixth transistor T6 is connected to the seventh transistor T8. The second electrode of transistor T7 and the gate of the sixth transistor T6 are connected to the enable signal terminal EM, the first electrode of the seventh transistor T7 is connected to the second initial signal terminal Vinit2, and the gate of the seventh transistor T7 is connected to the second reset signal terminal Re2; the first electrode of the first transistor T1 is connected to the first initial signal terminal Vinit1, the second electrode of the first transistor T1 is connected to the second electrode of the driving transistor T3, and the gate of the first transistor T1 is connected to the first reset signal terminal Re1; the first electrode of the eighth transistor T8 is connected to the third initial signal terminal Vinit3, the second electrode of the eighth transistor T8 is connected to the first electrode of the driving transistor T3, and the gate of the eighth transistor T8 is connected to the second reset signal terminal Re2; the first electrode of the capacitor C is connected to the node N, and the second electrode of the capacitor C is connected to the first power supply terminal VDD. This pixel driving circuit can be used to drive a light-emitting unit OLED. The first electrode of the light-emitting unit OLED can be connected to the second electrode of the sixth transistor T6, and the second electrode of the light-emitting unit can be connected to the second power supply terminal VSS. The first electrode of the light-emitting unit can be the anode of the light-emitting unit, and the second electrode of the light-emitting unit can be the cathode of the light-emitting unit. The second transistor T2 may be an N-type transistor, for example, an N-type metal oxide transistor. N-type transistors have a relatively low leakage current, thereby preventing leakage of power from the node N through the second transistor T2 during the light-emitting phase. Meanwhile, the first transistor T1, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may be P-type transistors, for example, P-type low-temperature polysilicon transistors. P-type transistors have a relatively high carrier mobility, thereby facilitating the realization of display panels with high resolution, high response speed, high pixel density, and high aperture ratio.The first initial signal terminal, the second initial signal terminal, and the third initial signal terminal can output the same or different voltage signals according to actual conditions.

[0119] As shown in Figure 2, where G1 represents the timing of the first gate drive signal terminal G1, G2 represents the timing of the second gate drive signal terminal G2, Re2 represents the timing of the second reset signal terminal Re2, Re1 represents the timing of the first reset signal terminal Re1, and EM represents the timing of the enable signal terminal EM, a driving cycle of the pixel driving circuit may include a first reset phase t1, a second reset phase t2, a data writing phase t3, a third reset phase t5, and a light-emitting phase t6.

[0120] During the first reset phase t1, the second reset signal terminal Re2 outputs a low-level signal, the seventh transistor T7 and the eighth transistor T8 are turned on, the second initial signal terminal Vinit2 inputs a second initial signal to the first electrode of the light-emitting unit OLED, and the third initial signal terminal Vinit3 inputs a third initial signal to the first electrode of the driving transistor T3 to improve the hysteresis problem of the driving transistor T3. During the second reset phase t2, the first gate drive signal terminal G1 outputs a high-level signal, the first reset signal terminal Re1 outputs a low-level signal, the first transistor T1 and the second transistor T2 are turned on, and the first initial signal terminal Vinit1 inputs the first initial signal to the node N through the first transistor T1 and the second transistor T2. During the data writing phase t3, the second gate drive signal terminal G2 outputs a low-level signal, the first gate drive signal terminal G1 outputs a high-level signal, the fourth transistor T4 and the second transistor T2 are turned on, and the data signal terminal Da writes the compensation voltage Vdata+Vth to the node N through the fourth transistor T4 and the second transistor T2, where Vdata is the voltage of the data signal on the data signal terminal and Vth is the threshold voltage of the driving transistor T3. In the third reset phase t5: the second reset signal terminal RE2 outputs a low-level signal, the seventh transistor T7 and the eighth transistor T8 are turned on, the second initial signal terminal Vinit2 inputs the second initial signal to the first electrode of the light-emitting unit OLED, and the third initial signal terminal Vinit3 inputs the third initial signal to the first electrode of the driving transistor T3. In the light-emitting phase t6: the enable signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 drives the light-emitting unit to emit light under the action of the compensation voltage Vdata + Vth stored in the capacitor C. The output current formula of the driving transistor is as follows: I = (μWCox / 2L)(Vgs-Vth) 2

[0121] Where I is the output current of the driver transistor; μ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the driver transistor channel, L is the length of the driver transistor channel, Vgs is the gate-source voltage difference of the driver transistor, and Vth is the threshold voltage of the driver transistor. The output current of the driver transistor in the above pixel driving circuit is I = (μWCox / 2L)(Vdata+Vth-Vdd-Vth) 2 The pixel driving circuit can avoid the influence of the driving transistor threshold on its output current.

[0122] In related art, the display quality of a display panel can be improved by increasing the number of high-level pulse signals at the enable signal terminal EM within a driving cycle of a pixel driving circuit. In related art, the enable signal terminal is provided via an enable signal line. A large parasitic capacitance is formed between the third initial signal line used to provide the third initial signal terminal and the enable signal line. When the number of pulse signals on the enable signal line is large, the enable signal line will couple with the third initial signal line, causing the voltage on the third initial signal line to fluctuate frequently, thereby causing problems such as horizontal stripes on the display panel or poor split-screen performance.

[0123] Based on this, this exemplary embodiment also provides a display panel, which may include a base substrate, a first active layer, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer stacked in sequence. Among them, an insulating layer may be provided between the above-mentioned adjacent layers. As shown in Figures 3-17, Figure 3 is a structural layout of an exemplary embodiment of the display panel disclosed in the present invention, Figure 4 is a structural layout of the first active layer in Figure 3, Figure 5 is a structural layout of the first conductive layer in Figure 3, Figure 6 is a structural layout of the second conductive layer in Figure 3, Figure 7 is a structural layout of the second active layer in Figure 3, Figure 8 is a structural layout of the third conductive layer in Figure 3, Figure 9 is a structural layout of the fourth conductive layer in Figure 3, Figure 10 is a structural layout of the fifth conductive layer in Figure 3, Figure 11 is a structural layout of the sixth conductive layer in Figure 3, Figure 12 is a structural layout of the first active layer and the first conductive layer in Figure 3, and Figure 13 is a structural layout of the first active layer and the first conductive layer in Figure 3. FIG14 is a structural layout of the first active layer, the first conductive layer, the second conductive layer, and the second active layer in FIG3 ; FIG15 is a structural layout of the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer in FIG3 ; FIG16 is a structural layout of the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer in FIG3 ; FIG17 is a structural layout of the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer in FIG3 . The display panel may include multiple pixel driving circuits shown in FIG1 . As shown in FIG3 , the display panel may include multiple repeating units distributed in a first direction X and a second direction Y. The repeating units may include a first pixel driving circuit Pix1 and a second pixel driving circuit Pix2 adjacently distributed in the first direction X. At least portions of the structures of the first pixel driving circuit Pix1 and the second pixel driving circuit Pix2 may be arranged in mirror symmetry about a mirror symmetry plane AA. The mirror symmetry plane AA may be perpendicular to the base substrate. Furthermore, the orthographic projection of the first pixel driving circuit Pix1 on the base substrate and the orthographic projection of the second pixel driving circuit Pix2 on the base substrate may be at least partially symmetrically arranged with the intersection of the mirror symmetry plane AA and the base substrate as the axis of symmetry. The first direction X and the second direction Y intersect. For example, the first direction X may be a row direction, and the second direction Y may be a column direction.

[0124] As shown in Figures 3, 4, and 12, the first active layer may include: a first active portion 71, a third active portion 73, a fourth active portion 74, a fifth active portion 75, a sixth active portion 76, a seventh active portion 77, an eighth active portion 78, a ninth active portion 79, a tenth active portion 710, an eleventh active portion 711, a twelfth active portion 712, a thirteenth active portion 713, a fourteenth active portion 714, a fifteenth active portion 715, a sixteenth active portion 716, a nineteenth active portion 719, and a twentieth active portion 720. The first active portion 71 is used to form the channel region of the first transistor T1; the third active portion 73 can be used to form the channel region of the driving transistor T3; the fourth active portion 74 can be used to form the channel region of the fourth transistor T4; the fifth active portion 75 can be used to form the channel region of the fifth transistor T5; the sixth active portion 76 can be used to form the channel region of the sixth transistor T6; the seventh active portion 77 can be used to form the channel region of the seventh transistor T7; the eighth active portion 78 can be used to form the channel region of the eighth transistor T8; the ninth active portion 79 is connected between the third active portion 73 and the sixth active portion 76; the tenth active portion 710 and the tenth active portion 720 are connected to each other. The twelfth active portion 712 is connected to both ends of the eighth active portion 78; the eleventh active portion 711 is connected between the fourth active portion 74 and the third active portion 73; the thirteenth active portion 713 is connected to a side of the fourth active portion 74 away from the third active portion 73; the fourteenth active portion 714 is connected to a side of the seventh active portion 77 away from the sixth active portion 76; the fifteenth active portion 715 is connected to a side of the fifth active portion 75 away from the third active portion 73; the sixteenth active portion 716 is connected between the seventh active portion 77 and the sixth active portion 76; and the nineteenth active portion 719 and the twentieth active portion 720 are connected to both ends of the first active portion 71. The first active layer may be formed of polysilicon material. Accordingly, the first transistor T1, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may be P-type low-temperature polysilicon thin film transistors.

[0125] As shown in Figures 3, 5, and 12, the first conductive layer may include: a first conductive portion 11, a second gate line G2, an enable signal line EM, a first reset signal line Re1, and a second reset signal line Re2. The second gate line G2 can be used to provide the second gate drive signal terminal in Figure 1; the enable signal line EM can be used to provide the enable signal terminal in Figure 1; the first reset signal line Re1 can be used to provide the first reset signal terminal in Figure 1; and the second reset signal line Re2 can be used to provide the second reset signal terminal in Figure 1. The orthographic projection of the second gate line G2 on the base substrate, the orthographic projection of the enable signal line EM on the base substrate, the orthographic projection of the first reset signal line Re1 on the base substrate, and the orthographic projection of the second reset signal line Re2 on the base substrate can all extend along the first direction X. The orthographic projection of the second gate line G2 on the base substrate covers the orthographic projection of the fourth active portion 74 on the base substrate, and a portion of the structure of the second gate line G2 is used to form the gate of the fourth transistor. The orthographic projection of the enable signal line EM on the substrate overlaps the orthographic projection of the fifth active portion 75 and the orthographic projection of the sixth active portion 76 on the substrate. Portions of the enable signal line EM can be used to form the gates of the fifth transistor T5 and the sixth transistor T6, respectively. The orthographic projection of the first reset signal line Re1 on the substrate overlaps the orthographic projection of the first active portion 71 on the substrate. Portions of the first reset signal line Re1 can be used to form the gate of the first transistor T1. The orthographic projection of the second reset signal line Re2 on the substrate overlaps the orthographic projection of the seventh active portion 77 and the orthographic projection of the eighth active portion 78 on the substrate. Portions of the first reset signal line Re1 can be used to form the gates of the seventh transistor T7 and the eighth transistor T8, respectively. The orthographic projection of the first conductive portion 11 on the substrate overlaps the orthographic projection of the third active portion 73 on the substrate. The first conductive portion 11 can be used to form the gate of the drive transistor T3 and the first electrode of the capacitor C. The display panel can use the first conductive layer as a mask to conduct conductor processing on the first active layer, that is, the area of ​​the first active layer covered by the first conductive layer can form the channel region of the transistor, and the area of ​​the first active layer not covered by the first conductive layer forms a conductor structure.

[0126] As shown in Figures 3, 6, and 13, the second conductive layer may include: a third gate line 2G1 and a second conductive portion 22. The orthographic projection of the third gate line 2G1 on the base substrate extends along the first direction X, and the third gate line 2G1 can be used to provide the first gate drive signal terminal in Figure 1. The orthographic projection of the second conductive portion 22 on the base substrate can at least partially overlap with the orthographic projection of the first conductive portion 11 on the base substrate, and the second conductive portion 22 is used to form a second electrode of the capacitor C. The second conductive layer may also include a second connecting portion 23, and adjacent second conductive portions 22 in the first direction X can be connected via the second connecting portion 23.

[0127] As shown in Figures 3, 7, and 14, the second active layer may include an active portion 9, which may include: a second active portion 92, a seventeenth active portion 917 connected to both ends of the second active portion 92, and an eighteenth active portion 918. The second active portion 92 is used to form the channel region of the second transistor T2. The second active layer may be formed of indium gallium zinc oxide, and accordingly, the second transistor T2 may be an N-type metal oxide thin film transistor. The orthographic projection of the third gate line 2G1 on the base substrate may cover the orthographic projection of the second active portion 92 on the base substrate, and a portion of the structure of the third gate line 2G1 may be used to form the bottom gate of the second transistor T2.

[0128] As shown in Figures 3, 8, and 15, the third conductive layer may include a first gate line 3G1, a first initial signal line Vinit1, and a second initial signal line Vinit2. The orthographic projection of the first gate line 3G1 on the base substrate, the orthographic projection of the first initial signal line Vinit1 on the base substrate, and the orthographic projection of the second initial signal line Vinit2 on the base substrate may all extend along the first direction X. The first gate line 3G1 may be used to provide the first gate drive signal terminal in Figure 1, the orthographic projection of the first gate line 3G1 on the base substrate may cover the orthographic projection of the second active portion 92 on the base substrate, and a partial structure of the first gate line 3G1 may be used to form the top gate of the second transistor T2. At the same time, the first gate line 3G1 may be connected to the third gate line 2G1 through a via located in the frame area of ​​the display panel. The first initial signal line Vinit1 may be used to provide the first initial signal terminal in Figure 1, and the second initial signal line Vinit2 may be used to provide the second initial signal terminal in Figure 1. The orthographic projection of the first initial signal line Vinit1 on the substrate can at least partially overlap with the orthographic projection of the second reset signal line Re2 in the pixel driving circuit in the adjacent previous row. The orthographic projection of the second initial signal line Vinit2 on the substrate can at least partially overlap with the orthographic projection of the first reset signal line Re1 in the pixel driving circuit in the adjacent next row. This arrangement can improve the light transmittance and integration of the display panel. In addition, the display panel can use the third conductive layer as a mask to perform a conductor processing on the second active layer. Specifically, the area of ​​the second active layer covered by the third conductive layer can form the channel region of the transistor, and the area of ​​the second active layer not covered by the third conductive layer forms a conductor structure.

[0129] As shown in Figures 3, 9, and 16, the fourth conductive layer may include a first bridge portion 41, a second bridge portion 42, a third bridge portion 43, a fourth bridge portion 44, a fifth bridge portion 45, a sixth bridge portion 46, a seventh bridge portion 47, an eighth bridge portion 48, and a third initial signal line Vinit3. The first bridge portion 41 is connected to the seventeenth active portion 917 and the first conductive portion 11 through vias, respectively, to connect the gate of the driving transistor T3 and the first electrode of the second transistor T2. The second conductive portion 22 may have an opening 221 formed therein, and a via connected between the first bridge portion 41 and the first conductive portion 11 is provided through the opening 221. The second bridge portion 42 may be connected to the ninth active portion 79, the eighteenth active portion 918, and the nineteenth active portion 719 through vias, respectively, to connect the second electrode of the first transistor T1, the second electrode of the second transistor T2, and the second electrode of the driving transistor T3. The third bridge portion 43 connects the twentieth active portion 720 and the first initial signal line Vinit1 through vias, thereby connecting the first electrode of the first transistor T1 to the first initial signal terminal. The fourth bridge portion 44 connects the fourteenth active portion 714 and the second initial signal line Vinit2 through vias, thereby connecting the first electrode of the seventh transistor T7 to the second initial signal line. The fifth bridge portion 45 connects the thirteenth active portion 713 through vias, thereby connecting the first electrode of the fourth transistor T4. The sixth bridge portion 46 connects the eleventh active portion 711 and the tenth active portion 710 through vias, thereby connecting the second electrode of the eighth transistor T8 to the first electrode of the driving transistor T3. The seventh bridge portion 47 connects the second connection portion 23 and the fifteenth active portion 715 through vias, thereby connecting the second electrode of the capacitor C to the first electrode of the fifth transistor T5. The eighth bridge portion 48 connects the sixteenth active portion 716 through vias, thereby connecting the second electrode of the seventh transistor T7 to the second electrode of the sixth transistor T6.

[0130] As shown in Figures 3, 9, and 16, the orthographic projection of the third initial signal line Vinit3 on the substrate extends along a first direction X. The third initial signal line Vinit3 includes a first extension portion Vinit31, a second extension portion Vinit32, and a third extension portion Vinit33. The third extension portion Vinit33 is connected between the first extension portion Vinit31 and the second extension portion Vinit32. The orthographic projection of the first extension portion Vinit31 on the substrate and the orthographic projection of the second extension portion Vinit32 on the substrate extend along the first direction X and are offset in the second direction Y. The orthographic projection of the first extension portion Vinit31 on the substrate does not intersect with the orthographic projection of the enable signal line EM on the substrate, and the orthographic projection of the second extension portion Vinit32 on the substrate does not intersect with the orthographic projection of the enable signal line EM on the substrate. This setting can reduce the overlapping area between the third initial signal line Vinit3 and the enable signal line EM, thereby reducing the parasitic capacitance between the third initial signal line Vinit3 and the enable signal line EM, and further improving problems such as horizontal stripes on the display panel or poor screen splitting caused by voltage changes on the third initial signal line Vinit3.

[0131] As shown in Figures 3, 9, and 16, the orthographic projection of the enable signal line EM on the base substrate is located between the orthographic projection of the first extension portion Vinit31 on the base substrate and the orthographic projection of the second extension portion Vinit32 on the base substrate, and the orthographic projection of the third extension portion Vinit33 on the base substrate may intersect with the orthographic projection of the enable signal line EM on the base substrate.

[0132] In this exemplary embodiment, the enable signal line EM is located in the first conductive layer. It should be understood that in other exemplary embodiments, the enable signal line EM may also be located in other conductive layers. For example, the enable signal line EM may be connected to the gate of the fifth transistor through a via.

[0133] In this exemplary embodiment, in the same pixel driving circuit, the orthographic projection of the first extension portion Vinit31 on the base substrate may be located between the orthographic projection of the enable signal line EM on the base substrate and the orthographic projection of the first bridge portion 41 on the base substrate.

[0134] In this exemplary embodiment, in the same pixel driving circuit, at least a portion of the orthogonal projection of the second extension portion Vinit32 on the substrate is located on a side of the orthogonal projection of the second reset signal line Re2 on the substrate that is away from the orthogonal projection of the enable signal line EM on the substrate. This arrangement can reduce the coupling effect of the second reset signal line Re2 on the second extension portion Vinit32.

[0135] In this exemplary embodiment, in the same pixel driving circuit, in the first direction X, the orthographic projection of at least part of the third extending portion Vinit33 on the base substrate is located between the orthographic projections of the sixth active portion 76 and the eighth active portion 78 on the base substrate.

[0136] As shown in Figures 3, 10, and 17, the fifth conductive layer may include: a ninth bridge portion, a first connection portion 51, a tenth bridge portion 510, an eleventh conductive portion 511, a twelfth bridge portion 512, and a first fan-out line FIPH. The orthographic projection of the first fan-out line FIPH on the substrate may extend along the first direction X, and the first fan-out line FIPH may serve as a row-direction fan-out line connecting the data line in the FIP (Fanout In Pixel, fan-out area in a pixel). The ninth bridge portion may be connected to the seventh bridge portion 47 through a via to connect to the first electrode of the fifth transistor T5. The fifth conductive layer includes a plurality of ninth bridge portions 59 and a plurality of first connection portions 51. The plurality of ninth bridge portions 59 are distributed in the first direction X and the second direction Y. The first connection portion 51 is connected between two adjacent ninth bridge portions 59 in the first direction X. The tenth bridge portion 510 may be connected to the fifth bridge portion 45 through a via to connect to the first electrode of the fourth transistor. The twelfth bridge portion 512 can be connected to the eighth bridge portion 48 via a via, thereby connecting to the second electrode of the sixth transistor T6. A portion of the eleventh conductive portion 511 can be connected to the same layer as the first fan-out line FIPH. The first fan-out line FIPH can be connected to the column-direction data fan-out line via the eleventh conductive portion 511. The portion of the eleventh conductive portion 511 can be spaced apart from the first fan-out line FIPH. The column-direction data fan-out line can also be connected to the portion of the eleventh conductive portion 511 via a via. The portion of the eleventh conductive portion 511 can ensure uniform light reflection and light transmission properties at different locations on the display panel.

[0137] As shown in Figures 3 and 11, the sixth conductive layer may include: a data line Da, a first power line VDD, a second fan-out line FIPV, and a thirteenth bridge portion 613. The orthographic projections of the data line Da, the first power line VDD, and the second fan-out line FIPV on the base substrate may extend along the second direction Y. The data line Da is used to provide the data signal terminal shown in Figure 1, and the first power line VDD is used to provide the first power terminal shown in Figure 1. The data line Da may be connected to the tenth bridge portion 510 via a via to connect the data signal terminal to the first electrode of the fourth transistor. There may be multiple first power lines VDD, with the orthographic projections of the multiple first power lines VDD on the base substrate extending along the second direction Y and spaced apart along the first direction X. The first power line VDD may be connected to the ninth bridge portion intersecting with its orthographic projection on the base substrate via a via. The first power line VDD and the ninth bridge portion 59 connected in the first direction X may form a grid structure. This arrangement can reduce the voltage difference between the first power lines at different locations on the display panel, thereby improving the display uniformity of the display panel.

[0138] The second fan-out line FIPV can be used as a column-direction fan-out line connecting the data line in the FIP (Fanout In Pixel). The second fan-out line FIPV can be connected to the eleventh conductive portion 511 through a via. The thirteenth bridge portion 613 can be connected to the twelfth bridge portion 512 through a via. The thirteenth bridge portion 613 can also be connected to the first electrode of the light-emitting unit.

[0139] As shown in Figures 3 and 11 , the orthographic projection of the ninth bridge portion 59 on the substrate can overlap the orthographic projection of the second active portion 92 on the substrate. The ninth bridge portion 59 can reduce the impact of light on the characteristics of the second transistor T2. The orthographic projection of the ninth bridge portion 59 on the substrate can also at least partially overlap with the orthographic projection of the first bridge portion 41 on the substrate. The ninth bridge portion 59 can shield the first bridge portion 41 from noise interference from other signals, thereby improving the stability of the gate voltage of the driving transistor T3.

[0140] As shown in Figures 3 and 11 , the orthographic projection of the first power line VDD on the substrate and the orthographic projection of the third extension portion Vinit33 on the substrate both extend along the second direction Y, and the orthographic projection of the first power line VDD on the substrate and the orthographic projection of the third extension portion Vinit33 on the substrate do not overlap. This arrangement can reduce parasitic capacitance between the third initial signal line Vinit3 and the first power line VDD, thereby reducing the effect of mutual coupling between the third initial signal line Vinit3 and the first power line VDD.

[0141] As shown in Figures 3, 9, and 11, the first extension Vinit31 includes a first sub-extension Vinit311 and a second sub-extension Vinit312. The orthographic projection of the first sub-extension Vinit311 on the substrate in the second direction Y is smaller than the orthographic projection of the second sub-extension Vinit312 on the substrate in the second direction Y. The orthographic projection of the first power line VDD on the substrate at least partially overlaps with the orthographic projection of the first sub-extension Vinit311 on the substrate. This arrangement can further reduce parasitic capacitance between the third initial signal line Vinit3 and the first power line VDD.

[0142] It should be noted that, as shown in Figures 3, 16, and 17, the black squares drawn on the side of the fourth conductive layer facing away from the substrate represent vias connecting the fourth conductive layer to other layers facing the substrate; the black squares drawn on the side of the fifth conductive layer facing away from the substrate represent vias connecting the fifth conductive layer to other layers facing the substrate; and the black squares drawn on the side of the sixth conductive layer facing away from the substrate represent vias connecting the sixth conductive layer to other layers facing the substrate. Different vias represented by black squares in different locations can penetrate different insulating layers.

[0143] FIG18 is a partial cross-sectional view of the display panel shown in FIG3 taken along dotted line BB. The display panel may further include a buffer layer 101, a second insulating layer 102, a third insulating layer 103, a fourth insulating layer 104, a fifth insulating layer 105, a first dielectric layer 106, a passivation layer 107, a first planarization layer 108, and a second planarization layer 109. The substrate 100, the buffer layer 101, the first active layer, the second insulating layer 102, the first conductive layer, the third insulating layer 103, the second conductive layer, the fourth insulating layer 104, the second active layer, the fifth insulating layer 105, the third conductive layer, the first dielectric layer 106, the fourth conductive layer, the passivation layer 107, the first planarization layer 108, the fifth conductive layer, the second planarization layer 109, and the sixth conductive layer are stacked in sequence. The buffer layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105 can be a single-layer structure or a multi-layer structure. The materials of the buffer layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105 can be at least one of silicon nitride, silicon oxide, and silicon oxynitride. The first dielectric layer 106 can be a silicon nitride layer. The materials of the first planarizing layer 108 and the second planarizing layer 109 can be organic materials, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonding structure (SOG), etc. The passivation layer 97 can be a silicon oxide layer. The base substrate 90 can include a glass substrate, a barrier layer, and a polyimide layer stacked in sequence. The barrier layer can be an inorganic material. The material of the first conductive layer, the second conductive layer, and the third conductive layer can be one of molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy or a laminate thereof. The material of the fourth conductive layer, the fifth conductive layer, and the sixth conductive layer can include a metal material, for example, one of molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy or a laminate thereof, or a titanium / aluminum / titanium laminate thereof. The square resistance of any one of the fourth conductive layer, the fifth conductive layer, and the sixth conductive layer can be less than the square resistance of any one of the first conductive layer, the second conductive layer, and the third conductive layer. The display panel may further include an electrode layer, a light-emitting unit layer, etc., located on the side of the sixth conductive layer facing away from the base substrate.

[0144] In this exemplary embodiment, the third initial signal line Vinit3 is disposed in the fourth conductive layer, which has a relatively low sheet resistance. This arrangement reduces the internal resistance of the third initial signal line Vinit3, thereby reducing the voltage difference at different locations on the third initial signal line Vinit3 and, in turn, improving the display uniformity of the display panel. Furthermore, the distance between the third initial signal line Vinit3 and the enable signal line EM is relatively large, which reduces the parasitic capacitance between the third initial signal line Vinit3 and the enable signal line EM, thereby reducing the coupling effect of the enable signal line EM on the third initial signal line Vinit3.

[0145] It should be understood that in other exemplary embodiments, the third initial signal line Vinit3 can also be set in other conductive layers. For example, the conductive layer where the third initial signal line Vinit3 is located can be located on the side of the conductive layer where the enable signal line EM is located away from the substrate, and the square resistance of the conductive layer where the third initial signal line Vinit3 is located is smaller than the square resistance of the conductive layer where the enable signal line EM is located.

[0146] As shown in Figures 19 and 20, Figure 19 is a schematic structural diagram of another exemplary embodiment of a display panel according to the present disclosure, and Figure 20 is a structural layout diagram of the fourth conductive layer in the display panel shown in Figure 19. The display panel shown in Figure 19 differs from the display panel shown in Figure 3 only in the fourth conductive layer. As shown in Figures 19 and 20, in the same pixel drive circuit, the orthographic projection of the third initial signal line Vinit3 on the base substrate is located on the side of the orthographic projection of the enable signal line EM on the base substrate that is away from the orthographic projection of the first conductive portion 11 on the base substrate. This arrangement can also reduce the parasitic capacitance between the third initial signal line Vinit3 and the enable signal line EM, thereby improving the display quality of the display panel.

[0147] As shown in Figures 19 and 20, the orthographic projection of the first extension portion Vinit31 on the substrate at least partially overlaps with the orthographic projection of the second reset signal line Re2 in the pixel driving circuit of the current row on the substrate. The orthographic projection of at least part of the second extension portion Vinit32 on the substrate is located between the orthographic projection of the first reset signal line Re1 in the pixel driving circuit of the next adjacent row on the substrate and the orthographic projection of the second reset signal line Re2 in the pixel driving circuit of the current row on the substrate. This arrangement allows the third initial signal line Vinit3 to avoid the third bridge portion 43 and the fourth bridge portion 44, while also reducing the overlapping area between the third initial signal line Vinit3 and the first reset signal line Re1 and the second reset signal line Re2, thereby reducing the coupling effect of the first reset signal line Re1 and the second reset signal line Re2 on the third initial signal line Vinit3.

[0148] As shown in Figures 21 and 22, Figure 21 is a schematic structural diagram of another exemplary embodiment of a display panel according to the present disclosure, and Figure 22 is a structural layout diagram of the conductive layer where the third initial signal line is located in the display panel shown in Figure 21. Figure 21 is a schematic structural diagram of another exemplary embodiment of a display panel according to the present disclosure. The main difference between the display panel shown in Figure 21 and the display panel shown in Figure 3 lies in the third initial signal line Vinit3. As shown in Figure 21, in the same pixel drive circuit, the orthographic projection of the first conductive portion 11 on the substrate is located between the orthographic projection of the first reset signal line Re1 on the substrate and the orthographic projection of the second reset signal line Re2 on the substrate; and the orthographic projection of the third initial signal line Vinit3 on the substrate is at least partially located between the orthographic projection of the second reset signal line Re2 on the substrate in the pixel drive circuit of the current row and the orthographic projection of the first reset signal line Re1 on the substrate in the pixel drive circuit of the next adjacent row. This arrangement can also reduce the parasitic capacitance between the third initial signal line Vinit3 and the enable signal line EM, thereby improving the display effect of the display panel.

[0149] Compared to the display panel shown in FIG3 , the display panel shown in FIG21 includes a seventh conductive layer on the side of the sixth conductive layer facing away from the base substrate. The third initial signal line Vinit3 can be located in the seventh conductive layer, and the sheet resistance of the seventh conductive layer can be smaller than the sheet resistance of the first conductive layer. It should be understood that in other exemplary embodiments, the third initial signal line Vinit3 can also be located in other conductive layers.

[0150] In this exemplary embodiment, the display panel shown in FIG21 can directly add a seventh conductive layer to the display panel shown in FIG3. It should be noted that due to the obstruction of the second fan-out line FIPV, the third initial signal line Vinit3 cannot be connected to the via hole of the twelfth active portion 712. In this exemplary embodiment, the second fan-out line FIPV can be made to avoid the connection via hole of the third initial signal line Vinit3 by means of winding, jumper, etc. In addition, the other structures of the display panel shown in FIG21 can be the same as those of the display panel shown in FIG3.

[0151] It should be noted that the proportions of the drawings in this disclosure can be used as a reference in actual processes, but are not limited to this. For example, the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The drawings described in this disclosure are only structural schematics. In addition, qualifiers such as first and second are only used to limit different structural names, and they do not have a specific order of meaning. The same structural layer can be formed by the same composition process. In this exemplary embodiment, the orthographic projection of a certain structure on the base substrate extends in a certain direction, which can be understood as the orthographic projection of the structure on the base substrate extending in a straight line or bending along that direction.

[0152] This exemplary embodiment also provides a display device, which includes the above-mentioned display panel. The display device can be a mobile phone, a tablet computer, a television, or other display device.

[0153] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

[0154] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

[0155] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A display panel, wherein: The display panel includes a pixel driving circuit, the pixel driving circuit includes a driving transistor, a fifth transistor, and an eighth transistor, a first electrode of the fifth transistor is connected to a first power line, a second electrode of the fifth transistor is connected to a first electrode of the driving transistor, and a second electrode of the eighth transistor is connected to the first electrode of the driving transistor; The display panel comprises: substrate substrate; An enable signal line, located at one side of the base substrate, the enable signal line is connected to the gate of the fifth transistor, and the orthographic projection of the enable signal line on the base substrate extends along a first direction; a third initial signal line, located at one side of the substrate, the third initial signal line connected to the first electrode of the eighth transistor, the third initial signal line comprising a first extension portion, a second extension portion, and a third extension portion, the third extension portion being connected between the first extension portion and the second extension portion; Wherein, the orthographic projection of the first extension portion on the base substrate and the orthographic projection of the second extension portion on the base substrate extend along the first direction and are staggered in the second direction, and the first direction and the second direction intersect; The orthographic projection of the first extension portion on the base substrate does not intersect with the orthographic projection of the enable signal line on the base substrate, and the orthographic projection of the second extension portion on the base substrate does not intersect with the orthographic projection of the enable signal line on the base substrate.

2. The display panel according to claim 1, wherein: The display panel further includes: A first active layer, located on one side of the base substrate, the first active layer comprising a fifth active portion, the fifth active portion being used to form a channel region of the fifth transistor; A first conductive layer is located on a side of the first active layer away from the substrate, the first conductive layer includes the enable signal line, the orthographic projection of the enable signal line on the substrate covers the orthographic projection of the fifth active portion on the substrate, and a partial structure of the enable signal line is used to form a gate of the fifth transistor.

3. The display panel according to claim 1, wherein: An orthographic projection of the third extension portion on the base substrate intersects with an orthographic projection of the enable signal line on the base substrate.

4. The display panel according to claim 3, wherein: The pixel driving circuit further includes a second transistor, a first electrode of the second transistor is connected to the gate of the driving transistor, and a second electrode is connected to the second electrode of the driving transistor. The display panel further includes: a fourth conductive layer, located on one side of the base substrate, the fourth conductive layer comprising a first bridge portion, the first bridge portion connecting the gate of the driving transistor and the first electrode of the second transistor through via holes; In the same pixel driving circuit, the orthographic projection of the first extending portion on the base substrate is located between the orthographic projection of the enable signal line on the base substrate and the orthographic projection of the first bridge portion on the base substrate.

5. The display panel according to claim 3, wherein: The display panel further includes: A first active layer, comprising an eighth active portion, wherein the eighth active portion is used to form a channel region of the eighth transistor; a first conductive layer, comprising a second reset signal line, an orthographic projection of the second reset signal line on the base substrate extending along the first direction and covering an orthographic projection of the eighth active portion on the base substrate, and a partial structure of the second reset signal line being used to form a gate of the eighth transistor; In the same pixel driving circuit, at least part of the orthographic projection of the second extension portion on the base substrate is located on a side where the orthographic projection of the second reset signal line on the base substrate is away from the orthographic projection of the enable signal line on the base substrate.

6. The display panel according to claim 3, wherein: The display panel further includes a light-emitting unit, the pixel driving circuit is used to drive the light-emitting unit to emit light, and the pixel driving circuit further includes a sixth transistor, a first electrode of the sixth transistor is connected to a second electrode of the driving transistor, and a second electrode of the sixth transistor is connected to a first electrode of the light-emitting unit; The display panel further includes: a first active layer, comprising a sixth active portion and an eighth active portion, wherein the sixth active portion is used to form a channel region of the sixth transistor, and the eighth active portion is used to form a channel region of the eighth transistor; In the same pixel driving circuit, in the first direction, an orthographic projection of at least part of the third extending portion on the base substrate is located between an orthographic projection of the sixth active portion on the base substrate and an orthographic projection of the eighth active portion on the base substrate.

7. The display panel according to claim 3, wherein: The orthographic projection of the first power line on the base substrate and the orthographic projection of the third extension portion on the base substrate both extend along the second direction, and the orthographic projection of the first power line on the base substrate and the orthographic projection of the third extension portion on the base substrate do not overlap.

8. The display panel according to claim 1, wherein: The display panel further includes: A first active layer, comprising a third active portion, wherein the third active portion is used to form a channel region of the driving transistor; a first conductive layer, comprising a first conductive portion, wherein an orthographic projection of the first conductive portion on the base substrate covers an orthographic projection of the third active portion on the base substrate, and the first conductive portion is used to form a gate of the driving transistor; In the same pixel driving circuit, the orthographic projection of the third initial signal line on the base substrate is located on a side of the orthographic projection of the enable signal line on the base substrate away from the orthographic projection of the first conductive portion on the base substrate.

9. The display panel according to claim 8, wherein: The first active layer further comprises: an eighth active portion, the eighth active portion being used to form a channel region of the eighth transistor; The first conductive layer also includes: a second reset signal line, wherein an orthographic projection of the second reset signal line on the base substrate extends along the first direction and covers an orthographic projection of the eighth active portion on the base substrate, and a partial structure of the second reset signal line is used to form a gate of the eighth transistor; The orthographic projection of the first extension portion on the base substrate at least partially overlaps with the orthographic projection of the second reset signal line in the pixel driving circuit of the same row on the base substrate.

10. The display panel according to claim 8, wherein: The display panel further includes a light emitting unit, the pixel driving circuit is used to drive the light emitting unit to emit light, and the pixel driving circuit further includes a first transistor and a seventh transistor; A first electrode of the first transistor is connected to a first initial signal line, and a second electrode of the first transistor is connected to a second electrode of the driving transistor; A first electrode of the seventh transistor is connected to the second initial signal line, and a second electrode is connected to the first electrode of the light emitting unit; The display panel further includes: The first active layer is located on one side of the substrate, the first active layer includes a first active portion, a third active portion, and a seventh active portion, the first active portion is used to form the first crystal The third active portion is used to form a channel region of the driving transistor, the third active portion is used to form a channel region of the driving transistor, and the seventh active portion is used to form a channel region of the seventh transistor; a first conductive layer, located on a side of the first active layer away from the base substrate, the first conductive layer comprising a first reset signal line, a second reset signal line, and a first conductive portion, an orthographic projection of the first reset signal line on the base substrate extending along the first direction and covering an orthographic projection of the first active portion on the base substrate, a partial structure of the first reset signal line used to form a gate of the first transistor, an orthographic projection of the second reset signal line on the base substrate extending along the first direction and covering an orthographic projection of the seventh active portion on the base substrate, a partial structure of the second reset signal line used to form a gate of the seventh transistor, an orthographic projection of the first conductive portion on the base substrate covering an orthographic projection of the third active portion on the base substrate, and the first conductive portion used to form a gate of the driving transistor; The orthographic projection of the second extension portion on the base substrate is located between the orthographic projection of the first reset signal line in the adjacent next row of pixel driving circuits on the base substrate and the orthographic projection of the second reset signal line in the current row of pixel driving circuits on the base substrate.

11. The display panel according to any one of claims 1 to 10, wherein: The pixel driving circuit further includes a second transistor, a first electrode of the second transistor is connected to a gate of the driving transistor, and the display panel further includes: a fourth conductive layer, located on one side of the base substrate, the fourth conductive layer comprising a first bridge portion, the first bridge portion connecting the gate of the driving transistor and the first electrode of the second transistor through via holes; Wherein, the fourth conductive layer also includes the third initial signal line.

12. The display panel according to claim 1, wherein: The display panel further includes a light emitting unit, the pixel driving circuit is used to drive the light emitting unit to emit light, and the pixel driving circuit further includes a first transistor and a seventh transistor; A first electrode of the first transistor is connected to a first initial signal line, and a second electrode of the first transistor is connected to a second electrode of the driving transistor; A first electrode of the seventh transistor is connected to the second initial signal line, and a second electrode is connected to the first electrode of the light emitting unit; The display panel further includes: The first active layer is located on one side of the substrate, and the first active layer includes a first a source portion, a third active portion, and a seventh active portion, wherein the first active portion is used to form a channel region of the first transistor, the third active portion is used to form a channel region of the driving transistor, and the seventh active portion is used to form a channel region of the seventh transistor; a first conductive layer, located on a side of the first active layer away from the base substrate, the first conductive layer comprising a first reset signal line, a second reset signal line, and a first conductive portion, an orthographic projection of the first reset signal line on the base substrate extending along the first direction and covering an orthographic projection of the first active portion on the base substrate, a partial structure of the first reset signal line used to form a gate of the first transistor, an orthographic projection of the second reset signal line on the base substrate extending along the first direction and covering an orthographic projection of the seventh active portion on the base substrate, a partial structure of the second reset signal line used to form a gate of the seventh transistor, an orthographic projection of the first conductive portion on the base substrate covering an orthographic projection of the third active portion on the base substrate, and the first conductive portion used to form a gate of the driving transistor; In the same pixel driving circuit, the orthographic projection of the first conductive portion on the base substrate is located between the orthographic projection of the first reset signal line on the base substrate and the orthographic projection of the second reset signal line on the base substrate; At least part of the orthographic projection of the third initial signal line on the substrate is located between the orthographic projection of the second reset signal line in the pixel driving circuit of the current row on the substrate and the orthographic projection of the first reset signal line in the pixel driving circuit of the next adjacent row on the substrate.

13. The display panel according to claim 12, wherein: The display panel further includes: a fifth conductive layer, located on a side of the first conductive layer away from the base substrate, the fifth conductive layer comprising a ninth bridge portion, and the ninth bridge portion is connected to the first electrode of the fifth transistor through a via hole; a sixth conductive layer, located at a side of the fifth conductive layer away from the fifth conductive layer, the sixth conductive layer comprising the first power line, and the first power line is connected to the ninth bridge portion through a via hole; The seventh conductive layer is located on a side of the sixth conductive layer away from the base substrate, and the seventh conductive layer includes the third initial signal line.

14. The display panel according to claim 13, wherein: The fifth conductive layer includes a plurality of the ninth bridging portions and a plurality of first connecting portions, wherein the plurality of the ninth bridging portions are distributed in the first direction and the second direction, and the first connecting portion is connected between two adjacent ninth bridging portions in the first direction; The sixth conductive layer includes a plurality of the first power lines, and the orthographic projections of the plurality of the first power lines on the base substrate extend along the second direction and are spaced apart along the first direction; The first power line is connected to the ninth bridge portion intersecting with its orthographic projection on the base substrate through a via hole.

15. The display panel according to claim 1, wherein: The conductive layer where the third initial signal line is located is located on a side of the conductive layer where the enable signal line is located away from the substrate, and the square resistance of the conductive layer where the third initial signal line is located is smaller than the square resistance of the conductive layer where the enable signal line is located.

16. The display panel according to claim 1, wherein: The display panel also includes a plurality of repeating units distributed along the first direction and the second direction, and the repeating units include a first pixel driving circuit and a second pixel driving circuit distributed in the first direction, and at least part of the structure of the first pixel driving circuit and the second pixel driving circuit are arranged in mirror symmetry.

17. The display panel according to claim 1, wherein: The first extension portion includes a first sub-extension portion and a second sub-extension portion, wherein a size of an orthographic projection of the first sub-extension portion on the substrate in the second direction is smaller than a size of an orthographic projection of the second sub-extension portion on the substrate in the second direction; An orthographic projection of the first power line on the base substrate extends along the second direction, and at least partially overlaps with an orthographic projection of the first sub-extension portion on the base substrate.

18. The display panel according to claim 1, wherein: The display panel further includes a light emitting unit, the pixel driving circuit is used to drive the light emitting unit, and the pixel driving circuit further includes a first transistor and a seventh transistor; A first electrode of the first transistor is connected to a first initial signal line, and a second electrode of the first transistor is connected to a second electrode of the driving transistor; A first electrode of the seventh transistor is connected to the second initial signal line, and a second electrode is connected to the first electrode of the light emitting unit; The display panel further includes: a first active layer, located on one side of the base substrate, the first active layer comprising a first active portion and a seventh active portion, the first active portion being used to form a channel region of the first transistor, The seventh active portion is used to form a channel region of the seventh transistor; a first conductive layer, located on a side of the first active layer away from the base substrate, the first conductive layer comprising a first reset signal line and a second reset signal line, an orthographic projection of the first reset signal line on the base substrate extending along the first direction and covering an orthographic projection of the first active portion on the base substrate, a partial structure of the first reset signal line being used to form a gate of the first transistor, an orthographic projection of the second reset signal line on the base substrate extending along the first direction and covering an orthographic projection of the seventh active portion on the base substrate, and a partial structure of the second reset signal line being used to form a gate of the seventh transistor; The orthographic projection of the first initial signal line on the substrate and the orthographic projection of the second reset signal line in the adjacent previous row of pixel driving circuits on the substrate at least partially overlap; The orthographic projection of the second initial signal line on the substrate at least partially overlaps with the orthographic projection of the first reset signal line in an adjacent previous row of pixel driving circuits on the substrate.

19. The display panel according to claim 1, wherein: The pixel driving circuit further includes a second transistor, a first electrode of the second transistor is connected to the gate of the driving transistor, and a second electrode of the second transistor is connected to the second electrode of the driving transistor. The display panel further includes: A first active layer is located on one side of the substrate; A first conductive layer, located on a side of the first active layer away from the substrate; a second active layer, located on a side of the first conductive layer away from the first active layer, the second active layer comprising a second active portion, and the second active portion is used to form a channel region of the second transistor; a third conductive layer, located on a side of the second active layer away from the substrate, the third conductive layer comprising a first gate line, an orthographic projection of the first gate line on the substrate extending along the first direction and covering an orthographic projection of the second active portion on the substrate, and a partial structure of the first gate line being used to form a gate of the second transistor; a fourth conductive layer, located on a side of the third conductive layer away from the substrate; The fifth conductive layer is located on a side of the fourth conductive layer away from the base substrate.

20. The display panel according to claim 1, wherein: The display panel further includes a light emitting unit, the pixel driving circuit is used to drive the light emitting unit to emit light, and the pixel driving circuit further includes: a first transistor, a first electrode of which is connected to the first initial signal line, and a second electrode of which is connected to the second electrode of the driving transistor; a second transistor, a first electrode of which is connected to the gate electrode of the driving transistor, and a second electrode of which is connected to the second electrode of the driving transistor; a fourth transistor, a first electrode of which is connected to the data line, and a second electrode of which is connected to the first electrode of the driving transistor; a sixth transistor, a first electrode of which is connected to the second electrode of the driving transistor, and a second electrode of which is connected to the first electrode of the light-emitting unit; a seventh transistor, a first electrode of which is connected to the second initial signal line, and a second electrode of which is connected to the first electrode of the light emitting unit; a capacitor, a first electrode of which is connected to the gate of the driving transistor, and a second electrode of which is connected to the first power line; Among them, the first transistor, the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are P-type transistors, and the second transistor is an N-type transistor.

21. The display panel according to claim 1, wherein: In one driving cycle of the pixel driving circuit, the enable signal line outputs a plurality of pulse signals.

22. A display device, wherein: The display device comprises the display panel according to any one of claims 1-21.

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