Display substrate and display device

Abstract

The embodiment of the invention provides a display substrate and a display device. The display substrate comprises a first metal layer and a second metal layer, the first metal layer comprises a plurality of first metal wires, and the second metal layer comprises a plurality of first data lines and a plurality of second data lines; the first data line is electrically connected with the first metal wire through the first through hole; the sides, close to the binding area, of the first metal wires and the second data wires are connected with the first binding electrodes of the binding area in a fan-out wiring mode. According to the display substrate, the two metal layers are used for arranging the Fan out wires, compared with the wiring mode of one metal layer in the prior art, the number of the Fan out wires in each layer is reduced, the wiring angle of the Fan out wires can be reduced through reduction of the number of the Fan out wires, and therefore the space of a fan-out type wiring area can be saved, and the wiring efficiency is improved. And the width of the frame of the display substrate is reduced.

Description

Technical Field

[0001] This application relates to the field of display technologies, and particularly to a display substrate and a display device. Background Art

[0002] With the emergence of various terminal products with display functions (such as smart phones, smart watches, computers, TVs, monitors, etc.), people increasingly pursue narrower borders for display products to increase the visible area of the screen. The narrow borders of display products can be achieved through the narrow borders of the display substrate.

[0003] However, due to the integration of various traces on the bottom side of the current display substrate, a large amount of space is occupied, making it wider than the other three sides. Moreover, in terms of technology, it has approached the limit and is difficult to further narrow, resulting in a wider bottom side border of the display substrate. Summary of the Invention

[0004] The purpose of the embodiments of this application is to provide a display substrate and a display device to reduce the width of the bottom side border of the display substrate. The specific technical solutions are as follows:

[0005] In a first aspect, the embodiments of this application provide a display substrate, including:

[0006] A first metal layer and a second metal layer;

[0007] The first metal layer includes multiple first metal traces, and the second metal layer includes multiple first data lines and multiple second data lines;

[0008] The first data lines are electrically connected to the first metal traces through first vias; on the side of the first metal traces and the second data lines close to the bonding area, a fan-out wiring method is used to connect the first bonding electrodes in the bonding area.

[0009] In a possible implementation, each of the first data lines and each of the second data lines are arranged along the column direction, and each of the first data lines is arranged on both sides of each of the second data lines.

[0010] In a possible implementation, the first metal trace includes a first row direction part arranged along the row direction and a first column direction part arranged along the column direction. The orthographic projection of the first column direction part on the substrate is located within the orthographic projection of the light-shielding area on the substrate.

[0011] In a possible implementation, there is an overlap between the orthographic projection of the first column direction part and the orthographic projection of the second data lines on the substrate.

[0012] In a possible implementation, the orthographic projection of the first row direction part on the substrate is located within the orthographic projection of the light-shielding area on the substrate.

[0013] In a possible implementation, the positive projection of the first row direction portion on the substrate is located within the positive projection of the pixel low light efficiency region on the substrate.

[0014] In a possible implementation, the display substrate further includes a substrate, a first insulating layer, a third metal layer, and a second insulating layer; the third metal layer includes a plurality of gate traces, and the gate traces are arranged along the row direction;

[0015] The first metal layer is located on one side of the substrate, the first insulating layer is located on the side of the first metal layer away from the substrate, the third metal layer is located on the side of the first insulating layer away from the substrate, the second insulating layer is located on the side of the third metal layer away from the substrate, and the second metal layer is located on the side of the second insulating layer away from the substrate;

[0016] The first insulating layer and the second insulating layer are provided with first through holes, and the first data line is electrically connected to the first metal trace through the first through holes.

[0017] In a possible implementation, the thickness of the first insulating layer is 0.2 μm - 0.8 μm.

[0018] In a possible implementation, the display substrate further includes a fourth metal layer, and the fourth metal layer includes a plurality of first touch lines and a plurality of second touch lines;

[0019] The first metal layer further includes a plurality of second metal traces, and the first touch line is electrically connected to the second metal trace through a second through hole; on the side of the second metal trace and the second touch line close to the bonding area, a fan-out wiring method is used to connect the second bonding electrode of the bonding area.

[0020] In a possible implementation, each of the first touch lines and each of the second touch lines are arranged along the column direction, and each of the first touch lines is arranged on both sides of each of the second touch lines.

[0021] In a possible implementation, the second metal trace includes a second row direction portion arranged along the row direction and a second column direction portion arranged along the column direction, and the positive projection of the second column direction portion on the substrate is located within the positive projection of the light shielding region on the substrate.

[0022] In a possible implementation, there is an overlap between the positive projection of the second column direction portion and the positive projection of the second touch line on the substrate.

[0023] In a possible implementation, the positive projection of the second row direction portion on the substrate is located within the positive projection of the light shielding region on the substrate.

[0024] In a possible implementation manner, the positive projection of the second row direction part on the substrate is located within the positive projection of the pixel low light efficiency area on the substrate.

[0025] In a second aspect, an embodiment of the present application provides a display device, including the display substrate according to any one of the first aspect.

[0026] Beneficial effects of the embodiments of the present application:

[0027] The display substrate and the display device provided by the embodiments of the present application, the display substrate includes a first metal layer and a second metal layer; the first metal layer includes a plurality of first metal traces, and the second metal layer includes a plurality of first data lines and a plurality of second data lines; the first data lines are electrically connected to the first metal traces through first vias; on one side of the first metal traces and the second data lines close to the bonding area, a fan-out wiring method is used to connect the first bonding electrodes in the bonding area. The display substrate provided by the present application uses two metal layers to lay out the Fan out traces (fan-out traces). Compared with the wiring method of one metal layer in the prior art, the number of Fan out traces in each layer is reduced, and the reduction in the number of Fan out traces can reduce the wiring angle of the Fan out traces, thereby saving the space of the fan-out wiring area, and further reducing the width of the border of the display substrate.

[0028] Of course, implementing any product or method of the present application does not necessarily need to achieve all the above-mentioned advantages at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other embodiments can also be obtained according to these drawings.

[0030] Figure 1 It is a schematic structural diagram of traces in a display substrate in the related art;

[0031] Figure 2 It is a schematic cross-sectional structural diagram of the first display substrate provided by an embodiment of the present application;

[0032] Figure 3 It is a schematic cross-sectional structural diagram of the second display substrate provided by an embodiment of the present application;

[0033] Figure 4 It is a schematic structural diagram of a display substrate provided by an embodiment of the present application;

[0034] Figure 5aSchematic diagram of the first type of first metal trace provided by an embodiment of the present application;

[0035] Figure 5b Schematic diagram of the second type of first metal trace provided by an embodiment of the present application;

[0036] Figure 6a For Figure 5b Schematic cross-sectional structure diagram of part (1) in

[0037] Figure 6b For Figure 5b Schematic cross-sectional structure diagram of part (2) in

[0038] Figure 6c For Figure 5b Schematic cross-sectional structure diagram of part (3) in

[0039] Figure 6d For Figure 5b Schematic cross-sectional structure diagram of part (4) in

[0040] Figure 7a Schematic diagram of the first routing method of the first metal trace provided by an embodiment of the present application;

[0041] Figure 7b Schematic diagram of the second routing method of the first metal trace provided by an embodiment of the present application;

[0042] Figure 7c Schematic diagram of the third routing method of the first metal trace provided by an embodiment of the present application;

[0043] Figure 7d Schematic diagram of the fourth routing method of the first metal trace provided by an embodiment of the present application;

[0044] Figure 7e Schematic diagram of the fifth routing method of the first metal trace provided by an embodiment of the present application.

[0045] Description of reference numerals:

[0046] 100 - First metal layer; 110 - First metal trace; 111 - First row direction part; 112 - First column direction part; 113 - First via; 200 - Second metal layer; 210 - First data line; 220 - Second data line; 300 - Bonding area; 400 - Substrate; 500 - First insulating layer; 600 - Third metal layer; 610 - Gate trace; 700 - Second insulating layer; 800 - Active layer; 900 - Liquid crystal. Detailed implementation manners

[0047] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field based on the present application belong to the scope of protection of the present application.

[0048] With the emergence of various terminal products with display functions (such as smart phones, smart watches, computers, TVs, monitors, etc.), people are increasingly pursuing narrower borders for display products to increase the visible area of ​​the screen. The narrow borders of display products can be achieved through the narrow borders of the display substrate.

[0049] However, the bottom side of the current display substrate occupies a lot of space due to the integration of various wirings, making it wider than the other three sides. In addition, the process has reached its limit and it is difficult to further narrow it, resulting in a wider bottom side frame of the display substrate. Figure 1 , is a schematic diagram of the structure of the wiring in the display substrate in the related art, wherein the wires arranged in the column direction are Data wires, and the data wires are connected to the binding area through the wiring in the fan out wiring area. It can be seen that the bottom side frame of the display substrate and the number of data wires and the distribution width of the data wire wiring ( Figure 1 When the number of data lines is large, the distribution width of the data line routing will be larger, and the fan out wiring area needs to have a larger upper and lower width ( Figure 1 The size of b in FIG. 4 ) results in a wider bottom side frame of the display substrate.

[0050] In order to reduce the width of the bottom frame of the display substrate, the embodiment of the present application provides a display substrate and a display device. The following is a detailed description:

[0051] In a first aspect of the present application, a display substrate is provided. Figure 2 , Figure 3 , Figure 4 and Figure 5b , Figure 4 A schematic diagram of the structure of a display substrate provided in an embodiment of the present application, Figure 5b for Figure 4 The enlarged image of the dotted ellipse. Figure 2 Based Figure 5b The cross-sectional view of part (3) in Figure 3 for Figure 5b The cross-sectional view of part (1) in FIG. 1 , wherein the display substrate comprises:

[0052] A first metal layer 100 and a second metal layer 200;

[0053] The first metal layer 100 includes a plurality of first metal traces 110, and the second metal layer 200 includes a plurality of first data lines 210 and a plurality of second data lines 220;

[0054] The first data line 210 is electrically connected to the first metal trace 110 through a first via 113; on one side of the first metal trace 110 and the second data line 220 close to the bonding area 300, a fan-out wiring method is adopted to connect the first bonding electrode of the bonding area 300.

[0055] Wherein, the first metal layer 100 and the second metal layer 200 are insulated by a first insulating layer 500, and the first metal layer 100 is located on the substrate 400.

[0056] In the embodiment of the present application, the display substrate includes two metal layers, namely the first metal layer 100 and the second metal layer 200. Among them, the materials of the first metal layer 100 and the second metal layer 200 can be metal elements and their alloys, such as copper (Cu), aluminum (Al), Mo (molybdenum), etc. and their alloys, or can be a composite metal layer, such as a composite metal layer of Mo / Al / Mo combination, a composite metal layer of Ti / Cu / Ti combination, etc. The present application does not limit the specific materials of the first metal layer 100 and the second metal layer 200. The first data line 210, the second data line 220 and the first metal trace 110 are located in the display area, the bonding area 300 is located in the non-display area, the bonding area 300 includes a plurality of bonding electrodes, and on one side of the first metal trace 110 and the second data line 220 close to the bonding area 300, a fan-out wiring method is adopted to connect the first bonding electrode of the bonding area 300.

[0057] As Figure 4 shown, the first metal layer 100 includes a plurality of first metal traces 110, the second metal layer 200 includes a plurality of first data lines 210 and a plurality of second data lines 220; the first data line 210 is electrically connected to the first metal trace 110 through a first via 113, and on one side of the first metal trace 110 and the second data line 220 close to the bonding area 300, a fan-out wiring method is adopted to connect the first bonding electrode of the bonding area 300, wherein, a' represents the total distribution width of the first data line 210 and the second data line 220, and b' represents the vertical width of the fan-out wiring area.

[0058] For the display substrate provided by the embodiment of the present application, since the first metal layer 100 where the first metal trace 110 is located and the second metal layer 200 where the second data line 220 is located are two different metal layers, the first data line 210 can be electrically connected to the first metal trace 110 through the first via 113, compared with Figure 1Compared with the shown wire routing method, the number of data line wire routings in each layer becomes smaller, and the size of a is reduced to a', so that the space of the fan-out wiring area can be saved, the vertical width of the fan-out wiring area is reduced (the size of b is reduced to b'), and further the width of the bottom side frame of the display substrate is reduced.

[0059] In a possible implementation manner, refer to Figure 3 , which is a schematic cross-sectional structure diagram of a second display substrate provided by an embodiment of the present application. The display substrate further includes a substrate 400, a first insulating layer 500, a third metal layer 600, and a second insulating layer 700; as Figure 4 shown, the third metal layer 600 includes a plurality of gate wirings 610, and the gate wirings 610 are arranged along the row direction;

[0060] The first metal layer 100 is located on one side of the substrate 400, the first insulating layer 500 is located on the side of the first metal layer 100 away from the substrate 400, the third metal layer 600 is located on the side of the first insulating layer 500 away from the substrate 400, the second insulating layer 700 is located on the side of the third metal layer 600 away from the substrate 400, and the second metal layer 200 is located on the side of the second insulating layer 700 away from the substrate 400;

[0061] The first insulating layer 500 and the second insulating layer 700 are provided with first through holes 113 ( Figure 3 not shown in the figure), and the first data line 210 is electrically connected to the first metal wiring 110 through the first through holes 113.

[0062] In the embodiment of the present application, the display substrate further includes a substrate 400, a first insulating layer 500, a third metal layer 600, and a second insulating layer 700. Among them, the substrate 400 is used to support the entire display structure, and its material can be glass, PI (Polyimide), Si (silicon), etc., or a composite substrate, such as glass + PI, etc., which can balance flexibility and durability; the third metal layer 600 can be used to arrange the gate wirings 610, and its material can be a metal element and its alloy, such as Cu (copper), Al (aluminum), Mo (molybdenum), etc. and their alloys, or a composite metal layer, such as a composite metal layer of Mo / Al / Mo combination, a composite metal layer of Ti / Cu / Ti combination, etc.; the first insulating layer 500 and the second insulating layer 700 are used to insulate each metal layer to prevent short circuits between metal wirings or electrodes, and their materials can be inorganic insulating materials, such as SiO2 (silicon dioxide), SiN x(Silicon nitride), Al2O3 (aluminum oxide), etc., can also be organic insulating materials, such as PI, photoresist, acrylic resin, etc., and can also be a composite insulating structure. The present application does not limit the specific materials of the substrate 400, the first insulating layer 500, the third metal layer 600, and the second insulating layer 700.

[0063] The display substrate provided by the embodiment of the present application further includes a substrate 400, a first insulating layer 500, a third metal layer 600, and a second insulating layer 700. The substrate 400 can support the entire display structure. The first insulating layer 500 can insulate between the first metal layer 100 and the third metal layer 600. The second insulating layer 700 can insulate between the third metal layer 600 and the second metal layer 200. The first insulating layer 500 and the second insulating layer 700 can insulate between the first metal layer 100 and the second metal layer 200. And first through holes 113 are formed in the first insulating layer 500 and the second insulating layer 700. The first data line 210 can be electrically connected to the first metal trace 110 through the first through holes 113, so that the trace of the first data line 210 is not directly led out from the non-display area, but is led out from another metal layer through the first metal trace 110 in the display area, saving the space of the fan-out wiring area.

[0064] In a possible implementation manner, the thickness of the first insulating layer 500 is 0.2 μm - 0.8 μm.

[0065] For the display substrate provided by the embodiment of the present application, the thickness of the first insulating layer 500 can be adjusted according to actual requirements. For example, using a first insulating layer 500 with a larger thickness can reduce the parasitic capacitance between the first metal layer 100 and the third metal layer 600, and between the first metal layer 100 and the second metal layer 200, thereby improving the response speed.

[0066] In a possible implementation manner, each of the first data lines 210 and each of the second data lines 220 are arranged in the column direction, and each of the first data lines 210 is arranged on both sides of each of the second data lines 220.

[0067] Specifically, the display substrate includes n columns of sub-pixels, and each column of sub-pixels is connected to a data line; the sub-pixels in the first column to the i-th column are connected to the first data line 210, the sub-pixels in the (i + 1)-th column to the j-th column are connected to the second data line 220, and the sub-pixels in the (j + 1)-th column to the n-th column are connected to the first data line 210; where n > j > i > 1. The arrangement of the first data line 210 and the second data line 220 can be referred to Figure 4 , the first data line 210 is located on both sides of the display substrate, and the second data line 220 is located in the middle of the display substrate.

[0068] It should be noted that Figure 4It is only a schematic structural diagram of a wiring, and the number of data lines, the number of pixels, and the number of gate wirings 610 arranged in the row direction in the substrate shall be subject to the actual application. In addition, the arrangement of the first metal wiring 110 in the display area does not necessarily have to be the same as Figure 4 shown exactly, taking Figure 4 as an example, the first metal wiring 110 connected to the leftmost first data line 210 can also be close to the leftmost second data line 220, and the first metal wiring 110 connected to the rightmost first data line 210 can be close to the rightmost second data line 220, and so on. As long as it is ensured that one first metal wiring 110 is connected to one first data line 210, and different first metal wirings 110 are connected to different first data lines 210, it is okay.

[0069] For the display substrate provided by the embodiment of the present application, each first data line 210 is arranged on both sides of each second data line 220. The fan-out wirings of the second data lines 220 on both sides and the first data line 210 in the middle can be arranged in the middle of the fan-out wiring area, without the need to route on both sides of the non-display area, saving the space of the fan-out wiring area, and thus the width of the bottom border of the display substrate can be reduced.

[0070] In a possible implementation manner, referring to Figure 5a , it is a schematic structural diagram of the first type of first metal wiring provided by the embodiment of the present application. The first metal wiring 110 includes a first row direction part 111 arranged in the row direction and a first column direction part 112 arranged in the column direction. The orthographic projection of the first column direction part 112 on the substrate 400 is located within the orthographic projection of the light-shielding area on the substrate 400. Among them, the area within the black dotted line frame is a part of the light-shielding area, 113 is the first through hole, 210 is the first data line, 220 is the second data line, 610 is the gate wiring, 800 is the active layer, and 900 is the liquid crystal.

[0071] In the display area of the display substrate, it usually includes an opening area (light-emitting area) and a light-shielding area. Among them, the opening area includes a normal light-emitting area and a pixel low-light-efficiency area. The light-shielding area is used to define each pixel in the display area. Usually, the light-shielding area includes a pixel defining structure and a black matrix structure. The pixel low-light-efficiency area is an area in the opening area where the brightness of the emitted light is less than the average brightness (the average brightness of the emitted light in the opening area). For example, for a liquid crystal sub-pixel, the pixel low-light-efficiency area of this sub-pixel is located on the center line of the opening area of this sub-pixel.

[0072] In the display substrate provided by the embodiment of the present application, the first metal trace 110 includes a first row-direction part 111 arranged along the row direction and a first column-direction part 112 arranged along the column direction, and the orthographic projection of the first column-direction part 112 on the substrate 400 is located within the orthographic projection of the light-shielding area on the substrate 400. Therefore, on the basis of saving the space of the fan-out wiring area, the wiring of the first column-direction part 112 will not affect the light emission of the pixels.

[0073] In a possible implementation manner, refer to Figure 5b , which is a schematic structural diagram of the second first metal trace provided by the embodiment of the present application, and the orthographic projection of the first column-direction part 112 and the second data line 220 on the substrate 400 overlaps.

[0074] Among them, 111 is the first row-direction part, 113 is the first via hole, 210 is the first data line, 610 is the gate trace, 800 is the active layer, and 900 is the liquid crystal. Figure 5b The schematic cross-sectional structural diagrams of the (3) part, (2) part, (1) part, and (4) part in Figure 6a 、 Figure 6b 、 Figure 6c 、 Figure 6d are shown in sequence. Among them, the active layer 800 is used to control the light emission of the liquid crystal 900. In Figure 6a 、 Figure 6b 、 Figure 6c and Figure 6d , the structures included are: the first metal layer 100, the second metal layer 200, the substrate 400, the first insulating layer 500, the third metal layer 600, the second insulating layer 700, and the active layer 800.

[0075] In the display substrate provided by the embodiment of the present application, the orthographic projection of the first column-direction part 112 and the second data line 220 on the substrate 400 overlaps, which can make the first column-direction part 112 of the first metal trace 110 overlap with the second data line 220, further saving the space occupied by the column-direction wiring, thereby further reducing the distribution width of the data line in the column direction, and further reducing the area of the fan-out wiring area and narrowing the bottom border of the display substrate.

[0076] In a possible implementation manner, the number of the first data lines 210 is equal to the number of the second data lines 220. On the basis of the overlap between the first column-direction part 112 and the second data line 220, the space occupied by the column-direction wiring can be saved to the greatest extent.

[0077] In a possible implementation manner, the orthographic projection of the first row-direction part 111 on the substrate 400 is located within the orthographic projection of the light-shielding area on the substrate 400.

[0078] In the first example, refer to Figure 7a , which is a schematic structural diagram of the first routing method of the first metal trace provided by the embodiment of the present application. The area within the upper black dashed box is a part of the light-shielding area, and the orthographic projection of the first row direction part 111 on the substrate 400 is located within the orthographic projection of the light-shielding area on the substrate 400. Figure 7a The structures included in

[0079] are: the first row direction part 111, the first column direction part 112, the first via 113, the first data line 210, the second data line 220, the gate trace 610, the active layer 800, and the liquid crystal 900. Figure 7b In the second example, refer to Figure 7b , which is a schematic structural diagram of the second routing method of the first metal trace provided by the embodiment of the present application. The area within the lower black dashed box is a part of the light-shielding area, and the orthographic projection of the first row direction part 111 on the substrate 400 is located within the orthographic projection of the light-shielding area on the substrate 400.

[0080] It should be noted that Figure 7a and Figure 7b the routing methods of the first metal trace in Figure 7a and Figure 7b are only two examples, and it does not mean that the routing method of the first metal trace provided by the embodiment of the present application can only be as shown in

[0081] In this embodiment, as long as it is ensured that the orthographic projection of the first row direction part 111 on the substrate 400 is located within the orthographic projection of the light-shielding area on the substrate 400.

[0082] In a possible implementation manner, the orthographic projection of the first row direction part 111 on the substrate 400 is located within the orthographic projection of the pixel low light efficiency area on the substrate 400.

[0083] In the third example, refer to Figure 7c , which is a schematic structural diagram of the third routing method of the first metal trace provided by the embodiment of the present application. The area within the middle black dashed box is a part of the pixel low light efficiency area, and the orthographic projection of the first row direction part 111 on the substrate 400 is located within the orthographic projection of the pixel low light efficiency area on the substrate 400.Figure 7c The structures included therein are: a first row direction portion 111, a first column direction portion 112, a first through hole 113, a first data line 210, a second data line 220, a gate trace 610, an active layer 800, and a liquid crystal 900.

[0084] In the fourth example, refer to Figure 7d , which is a schematic structural diagram of a fourth routing method of the first metal trace provided by the embodiment of the present application. The area within the middle black dashed box is a part of the pixel low light - efficiency area. The orthographic projection of the first row direction portion 111 on the substrate 400 is located within the orthographic projection of the pixel low light - efficiency area on the substrate 400. Figure 7d The structures included therein are: a first row direction portion 111, a first column direction portion 112, a first through hole 113, a first data line 210, a second data line 220, a gate trace 610, an active layer 800, and a liquid crystal 900.

[0085] In the fifth example, refer to Figure 7e , which is a schematic structural diagram of a fifth routing method of the first metal trace provided by the embodiment of the present application. The area within the middle black dashed box is a part of the pixel low light - efficiency area. The orthographic projection of the first row direction portion 111 on the substrate 400 is located within the orthographic projection of the pixel low light - efficiency area on the substrate 400. Figure 7e The structures included therein are: a first row direction portion 111, a first column direction portion 112, a first through hole 113, a first data line 210, a second data line 220, a gate trace 610, an active layer 800, and a liquid crystal 900.

[0086] It should be noted that Figure 7c , Figure 7d and Figure 7e The routing methods of the first metal trace in Figure 7c , Figure 7d and Figure 7e are only three examples, and do not mean that the routing methods of the first metal trace provided by the embodiments of the present application can only be as shown in

[0087] In the embodiments of the present application, as long as it is ensured that the orthographic projection of the first row direction portion 111 on the substrate 400 is located within the orthographic projection of the pixel low light - efficiency area on the substrate 400.

[0088] In a possible implementation manner, the display substrate further includes a fourth metal layer, and the fourth metal layer includes a plurality of first touch lines and a plurality of second touch lines;

[0089] The first metal layer further includes a plurality of second metal traces, and the first touch line is electrically connected to the second metal traces through a second via hole; on the side of the second metal traces and the second touch line close to the bonding area 300, a fan-out routing method is adopted to connect the second bonding electrodes of the bonding area 300.

[0090] In the embodiment of the present application, the display substrate further includes a fourth metal layer. The fourth metal layer includes a plurality of first touch lines and a plurality of second touch lines. The first metal layer further includes a plurality of second metal traces. The first touch line is electrically connected to the second metal traces through a second via hole, and on the side of the second metal traces and the second touch line close to the bonding area 300, a fan-out routing method is adopted to connect the second bonding electrodes of the bonding area 300.

[0091] For the display substrate provided by the embodiment of the present application, in addition to data lines, it further includes a plurality of touch lines. Connecting a part of the touch lines to the second metal traces in the first metal layer through second via holes can reduce the number of touch line traces in the fourth metal layer where the touch lines are located, thereby saving the space in the fan-out routing area, and further reducing the width of the bottom side frame of the display substrate with touch function.

[0092] In a possible implementation manner, each of the first touch lines and each of the second touch lines are arranged in the column direction, and each of the first touch lines is arranged on both sides of each of the second touch lines.

[0093] For the display substrate provided by the embodiment of the present application, each of the first touch lines is arranged on both sides of each of the second touch lines. The fan-out traces of the second touch lines on both sides and the first touch line in the middle can be arranged in the middle of the fan-out routing area, without the need to route on both sides of the non-display area, saving the space in the fan-out routing area, and further reducing the width of the bottom side frame of the display substrate with touch function.

[0094] In a possible implementation manner, the second metal trace includes a second row direction part arranged in the row direction and a second column direction part arranged in the column direction. The orthographic projection of the second column direction part on the substrate 400 is located within the orthographic projection of the light shielding area on the substrate 400.

[0095] For the display substrate provided by the embodiment of the present application, the second metal trace includes a second row direction part arranged in the row direction and a second column direction part arranged in the column direction, and the orthographic projection of the second column direction part on the substrate 400 is located within the orthographic projection of the light shielding area on the substrate 400. Therefore, on the basis of saving the space in the fan-out routing area, the routing of the second column direction part connecting the touch lines will not affect the light emission of the pixels.

[0096] In a possible implementation, an overlap exists between the positive projection of the second column direction portion and the second touch line on the substrate 400.

[0097] For the display substrate provided by an embodiment of the present application, an overlap exists between the positive projection of the second column direction portion and the second touch line on the substrate 400, which can cause the second column direction portion of the second metal trace to overlap with the second touch line, further saving the space occupied by the columnar wiring, thereby further reducing the distribution width of the touch line in the column direction, and further reducing the area of the fan-out wiring region and narrowing the bottom side frame of the display substrate with touch function.

[0098] In a possible implementation, the number of the first touch lines is equal to that of the second touch lines. On the basis of the overlap between the second column direction portion and the second touch line, the space occupied by the columnar wiring can be saved to the greatest extent.

[0099] In a possible implementation, the positive projection of the second row direction portion on the substrate 400 is located within the positive projection of the light-shielding region on the substrate 400.

[0100] For the display substrate provided by an embodiment of the present application, the positive projection of the second row direction portion on the substrate 400 is located within the positive projection of the light-shielding region on the substrate 400. Therefore, on the basis of saving the space of the fan-out wiring region, the wiring of the second row direction portion will not affect the light emission of the pixels.

[0101] In a possible implementation, the positive projection of the second row direction portion on the substrate 400 is located within the positive projection of the low light efficiency region of the pixels on the substrate 400.

[0102] For the display substrate provided by an embodiment of the present application, the positive projection of the second row direction portion on the substrate 400 is located within the positive projection of the low light efficiency region of the pixels on the substrate 400. Therefore, on the basis of saving the space of the fan-out wiring region, the influence of the wiring of the second row direction portion 111 on the pixel light emission can be reduced.

[0103] In a second aspect of the embodiments of the present application, a display device is provided, including the display substrate according to any one of the first aspect.

[0104] The display device provided by the embodiments of the present application can be any display device including the display substrate according to any one of the first aspect.

[0105] The display device provided by the present application includes the display substrate according to any one of the first aspect, and thus has the advantages of the display substrate according to any one of the first aspect.

[0106] It should be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising one..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the said element.

[0107] Each embodiment in this specification is described in a related manner. For the same or similar parts among the embodiments, reference can be made to each other. Each embodiment focuses on the differences from other embodiments. In particular, for the display device, since it is basically similar to the display substrate embodiment, the description is relatively simple. For the related parts, reference can be made to the partial description of the display substrate embodiment.

[0108] The above are only the preferred embodiments of the present application and are not intended to limit the protection scope of the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application are all included in the protection scope of the present application.

Claims

1. A display substrate, characterized in that, Comprising: A first metal layer and a second metal layer; The first metal layer includes a plurality of first metal traces, and the second metal layer includes a plurality of first data lines and a plurality of second data lines; The first data lines are electrically connected to the first metal traces through first vias; on one side of the first metal traces and the second data lines close to the bonding area, a fan-out routing method is adopted to connect a first bonding electrode of the bonding area.

2. The display substrate according to claim 1, characterized in that, Each of the first data lines and each of the second data lines are arranged along the column direction, and each of the first data lines is arranged on both sides of each of the second data lines.

3. The display substrate according to claim 1, wherein The first metal traces include a first row direction part arranged along the row direction and a first column direction part arranged along the column direction, and a positive projection of the first column direction part on the substrate is located within a positive projection of the light shielding area on the substrate.

4. The display substrate according to claim 3, wherein There is an overlap between a positive projection of the first column direction part and a positive projection of the second data lines on the substrate.

5. The display substrate according to claim 3, characterized in that, A positive projection of the first row direction part on the substrate is located within a positive projection of the light shielding area on the substrate.

6. The display substrate according to claim 3, wherein A positive projection of the first row direction part on the substrate is located within a positive projection of a pixel low luminous efficiency area on the substrate.

7. The display substrate according to claim 1, wherein The display substrate further includes a substrate, a first insulating layer, a third metal layer, and a second insulating layer; the third metal layer includes a plurality of gate traces, and the gate traces are arranged along the row direction; The first metal layer is located on one side of the substrate, the first insulating layer is located on a side of the first metal layer away from the substrate, the third metal layer is located on a side of the first insulating layer away from the substrate, the second insulating layer is located on a side of the third metal layer away from the substrate, and the second metal layer is located on a side of the second insulating layer away from the substrate; First vias are formed in the first insulating layer and the second insulating layer, and the first data lines are electrically connected to the first metal traces through the first vias.

8. The display substrate according to claim 7, wherein The thickness of the first insulating layer is 0.2μm - 0.8μm.

9. The display substrate according to claim 1, wherein, The display substrate further includes a fourth metal layer, and the fourth metal layer includes a plurality of first touch lines and a plurality of second touch lines; The first metal layer further includes a plurality of second metal traces, and the first touch lines are electrically connected to the second metal traces through second vias; on one side of the second metal traces and the second touch lines close to the bonding area, a fan-out routing method is adopted to connect a second bonding electrode of the bonding area.

10. A display device, characterized in that, Including the display substrate according to any one of claims 1 - 9.

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