Array substrate, display panel and display device

Abstract

The invention discloses an array substrate, a display panel and a display device, and aims to solve the problem that cross grains are easy to appear near grid lines when the transmittance of a display panel in the prior art is improved. The array substrate comprises a substrate, a plurality of grid line groups and a plurality of transistor groups, wherein the grid line groups are positioned on one side of the substrate, extend along a first direction and are arranged along a second direction; wherein the grid line group comprises at least two grid lines which are laminated and arranged in an insulating manner, and orthographic projections of the two grid lines on the substrate are overlapped; the transistor group comprises at least two transistors which are electrically connected with the two grid lines of the grid line group respectively; the transistor comprises a grid electrode; and the minimum distance between the grid electrode of at least one transistor in the same transistor group and the electrically connected grid line in the second direction is greater than zero.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and in particular, to an array substrate, a display panel, and a display device. Background Art

[0002] Today, with the increasing popularity of liquid crystal displays, in order to achieve sustainable development, the world advocates green and low-carbon life, and pays more and more attention to energy conservation and emission reduction. Therefore, high transmittance requirements are put forward for thin-film transistor liquid crystal display panels. However, in the existing display panels, when the transmittance is improved, there is a problem that horizontal stripes are likely to appear near the gate lines. Summary of the Invention

[0003] The present invention provides an array substrate, a display panel, and a display device to improve the problem that horizontal stripes are likely to appear near the gate lines in the existing display panels when the transmittance is improved.

[0004] An embodiment of the present invention provides an array substrate, including: a substrate, a plurality of gate line groups extending along a first direction and arranged along a second direction on one side of the substrate, and a plurality of transistor groups;

[0005] Wherein, each of the gate line groups includes: at least two gate lines stacked and insulated from each other, and the orthographic projections of the two gate lines on the substrate overlap; each of the transistor groups includes: at least two transistors electrically connected to the two gate lines of the gate line group respectively; each of the transistors includes a gate electrode;

[0006] For at least one transistor in the same transistor group, the minimum distance between the gate electrode and the gate line to which it is electrically connected in the second direction is greater than zero.

[0007] In a possible implementation manner, the array substrate further includes: a first connection portion extending along the second direction;

[0008] For at least one transistor in the same transistor group, the gate electrode is connected to the gate line through the first connection portion.

[0009] In a possible implementation manner, the array substrate includes: a plurality of data lines extending along the second direction;

[0010] The orthographic projection of the first connection portion on the substrate overlaps with the orthographic projection of the data line on the substrate.

[0011] In a possible implementation manner, the array substrate includes: a plurality of pixel electrodes;

[0012] The gate of only one of the transistors in the same transistor group is connected to the gate line through the first connecting portion; the length of the first connecting portion in the second direction is greater than or equal to the length of the pixel electrode in the second direction, and less than twice the length of the pixel electrode in the second direction.

[0013] In a possible implementation, the array substrate includes: a plurality of pixel electrodes;

[0014] The gates of the two transistors in the same transistor group are both connected to the gate line through the first connecting portion, and the lengths of the first connecting portions connected to the gates of different transistors are equal.

[0015] In a possible implementation manner, a length of the first connecting portion in the second direction is one quarter to three quarters of a length of the pixel electrode in the second direction.

[0016] In a possible embodiment, the pixel electrode has a notch at a position opposite to the transistor; the notch has two outer boundaries extending along the first direction, and the extension lines of the two outer boundaries overlap with the central area of ​​the pixel electrode's orthographic projection on the substrate in an area enclosed by the orthographic projection of the substrate.

[0017] In a possible implementation, the gate line group includes: a first gate line, and a second gate line located on a side of the first gate line away from the substrate; the transistor group includes: a first transistor connected to the first gate line, and a second transistor connected to the second gate line;

[0018] The first connection portion and the first gate line are made of the same layer and material, and the two are insulated from each other; at least a portion of the first connection portion is electrically connected to the second gate line through a via hole.

[0019] In a possible implementation manner, the array substrate further includes: a second connecting portion integrally connected to the second gate line and extending along the second direction;

[0020] At least a portion of the first connection portion overlaps with the second connection portion in an orthographic projection on the substrate, and the first connection portion and the second connection portion are connected at the overlapping position through a via.

[0021] In a possible implementation manner, the gate extends along the second direction;

[0022] The gate has a first outer edge extending along the second direction, and the first connecting portion has a second outer edge extending along the second direction; an orthographic projection of the first outer edge on the substrate does not overlap with an orthographic projection of the second outer edge on the substrate.

[0023] In a possible implementation manner, the array substrate further includes: a plurality of data line groups extending along the second direction and arranged along the first direction;

[0024] The data line group includes: at least two data lines that are stacked and insulated, and the orthographic projections of the two data lines on the substrate overlap.

[0025] In a possible implementation manner, the array substrate includes: a plurality of pixel electrodes distributed in an array; in the same row of pixel electrodes, two pixel electrodes located on both sides of the same data line group are respectively connected to different data lines in the data line group through different transistors.

[0026] In a possible implementation manner, in the same row of pixel electrodes, two pixel electrodes located on different sides of the same data line group are respectively connected to different gate lines in the same gate line group through different transistors.

[0027] In a possible implementation manner, in the same row of pixel electrodes, each pixel electrode is electrically connected to the same gate line through the transistor.

[0028] In a possible implementation manner, the array substrate includes: a plurality of rows of pixel electrodes extending along the first direction and arranged along the second direction;

[0029] In the scanning direction of the gate line, the orthographic projection of the first gate line group on the substrate is located between the orthographic projection of the first row of pixel electrodes on the substrate and the orthographic projection of the second row of pixel electrodes on the substrate; the orthographic projection of the last gate line group on the substrate is located between the orthographic projections of the last two rows of pixel electrodes on the substrate.

[0030] An embodiment of the present application further provides a display panel, including the array substrate provided in the embodiment of the present application.

[0031] An embodiment of the present application further provides a display device, including the display panel provided in the embodiment of the present application.

[0032] The beneficial effects of the embodiments of the present invention are as follows: The gate line group includes at least two gate lines that are stacked and insulated from each other, and the orthographic projections of the two gate lines on the substrate overlap. In this way, the light-shielding area caused by the gate lines in half of the display area can be reduced, which is helpful for the design of a high aperture ratio and improves the panel transmittance. Moreover, the minimum distance in the second direction between the gate of at least one transistor in the same transistor group and the electrically connected gate line is greater than zero. In this way, at least one transistor in the same transistor group is enabled to be far away from the electrically connected gate line, avoiding the problem that when transistors are concentrated on both sides of the gate line, since the transistors themselves are also light-impermeable, the light-impermeable areas are easily concentrated near the gate line, and it is easy to show display streaks. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 FIG. 1 is one of the schematic diagrams of the pixel architecture of the array substrate provided by the embodiment of the present invention;

[0034] Figure 2A FIG. 2 is one of the schematic diagrams of the array substrate provided by the embodiment of the present application;

[0035] Figure 2B is Figure 2A the single-layer film diagram of the layer where the first gate line is located in FIG. 1;

[0036] Figure 2C is Figure 2A the single-layer film diagram of the layer where the second gate line is located in FIG. 2;

[0037] Figure 2D is Figure 2A the single-layer film diagram of the layer where the data line is located in FIG. 3;

[0038] Figure 2E is Figure 2A the single-layer film diagram of the layer where the pixel electrode is located in FIG. 4;

[0039] Figure 3A is Figure 2A the cross-sectional schematic diagram at the dotted line e1 in FIG. 5;

[0040] Figure 3B is Figure 2A the cross-sectional schematic diagram at the dotted line e2 in FIG. 6;

[0041] Figure 3C is Figure 2A the cross-sectional schematic diagram at the dotted line e3 in FIG. 7;

[0042] Figure 3D is Figure 2A the cross-sectional schematic diagram at the dotted line e4 in FIG. 8;

[0043] Figure 4 FIG. 9 is another schematic diagram of the pixel architecture of the array substrate provided by the embodiment of the present invention;

[0044] Figure 5A Schematic diagram II of the array substrate provided by the embodiment of the present application;

[0045] Figure 5B It is Figure 5A Schematic diagram of the single film layer of the layer where the first gate line is located in

[0046] Figure 5C It is Figure 5A Schematic diagram of the single film layer of the layer where the second gate line is located in

[0047] Figure 5D It is Figure 5A Schematic diagram of the single film layer of the layer where the data line is located in

[0048] Figure 5E It is Figure 5A Schematic diagram of the single film layer of the layer where the pixel electrode is located in

[0049] Figure 5F It is Figure 6C Schematic diagram after forming the first gate layer;

[0050] Figure 5G It is Figure 6C Schematic diagram after forming the protective layer 91 of the first gate layer;

[0051] Figure 5H It is Figure 6C Schematic diagram after forming the second gate layer;

[0052] Figure 5I It is Figure 6C Schematic diagram of the protective layer of the second gate layer after formation;

[0053] Figure 6A It is Figure 5A Cross-sectional schematic diagram at the dotted line e1;

[0054] Figure 6B It is Figure 5A Cross-sectional schematic diagram at the dotted line e2;

[0055] Figure 6C It is Figure 5A Cross-sectional schematic diagram at the dotted line e3;

[0056] Figure 6D It is Figure 5A Cross-sectional schematic diagram at the dotted line e4;

[0057] Figure 7 Schematic diagram III of the pixel architecture of the array substrate provided by the embodiment of the present invention;

[0058] Figure 8A Schematic diagram III of the array substrate provided by the embodiment of the present application;

[0059] Figure 8B is Figure 8A a schematic diagram of a single film layer of the layer where the first gate line is located in

[0060] Figure 8C is Figure 8A a schematic diagram of a single film layer of the layer where the second gate line is located in

[0061] Figure 8D is Figure 8A a schematic diagram of a single film layer of the layer where the first data line is located in

[0062] Figure 8E is Figure 8A a schematic diagram of a single film layer of the layer where the second data line is located in

[0063] Figure 8F is Figure 8A a schematic diagram of a single film layer of the layer where the pixel electrode is located in

[0064] Figure 9A is Figure 8A a schematic cross - sectional view at the dashed line e1;

[0065] Figure 9B is Figure 8A a schematic cross - sectional view at the dashed line e2;

[0066] Figure 9C is Figure 8A a schematic cross - sectional view at the dashed line e3;

[0067] Figure 9D is Figure 8A a schematic cross - sectional view at the dashed line e4. Specific embodiments

[0068] In order to make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some, rather than all, of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.

[0069] Unless otherwise defined, technical terms or scientific terms used in this disclosure shall have the ordinary meanings as understood by those of ordinary skill in the art to which this disclosure pertains. The "first", "second" and similar terms used in this disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. Words such as "comprising" or "including" mean that the elements or items appearing before this word cover the elements or items listed after this word and their equivalents, without excluding other elements or items. Words such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Upper", "lower", "left", "right", etc. are only used to indicate relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0070] As used herein, "about" or "substantially the same" includes the stated value and means within an acceptable deviation range for the specific value as determined by those of ordinary skill in the art in view of the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "substantially the same" may mean that the difference relative to the stated value is within one or more standard deviation ranges, or within ±30%, 20%, 10%, 5%.

[0071] In the drawings, the thicknesses of layers, films, panels, regions, etc. are enlarged for clarity. Exemplary embodiments are described herein with reference to cross-sectional views that are schematic illustrations of idealized embodiments. Thus, deviations from the shapes of the figures can be expected as a result of, for example, manufacturing techniques and / or tolerances. Accordingly, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but include deviations in shape resulting from, for example, manufacturing. For example, regions illustrated or described as flat may typically have rough and / or non-linear features. Additionally, the sharp corners shown may be rounded. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the exact shape of the regions and are not intended to limit the scope of the claims.

[0072] To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted in this disclosure.

[0073] Embodiments of the present invention provide an array substrate. Refer to Figure 1 , Figures 2A - 2E , Figures 3A - 3D as shown, wherein, Figure 1 is Figure 2A the corresponding equivalent circuit diagram, Figure 2B is Figure 2A the single film layer schematic diagram of the layer where the first gate line is located in Figure 2Cis Figure 2A a schematic diagram of a single film layer of the layer where the second gate line is located in Figure 2C is Figure 2A a schematic diagram of a single film layer of the layer where the data line is located in Figure 2D is Figure 2A a schematic diagram of a single film layer of the layer where the pixel electrode is located in Figure 3A is Figure 2A a schematic cross-sectional view at the dotted line e1, Figure 3B is Figure 2A a schematic cross-sectional view at the dotted line e2, Figure 3C is Figure 2A a schematic cross-sectional view at the dotted line e3, Figure 3D is Figure 2A a schematic cross-sectional view at the dotted line e4. The array substrate includes: a substrate 1, a plurality of gate line groups 200 extending along a first direction X and arranged along a second direction Y on one side of the substrate 1, and a plurality of transistor groups T00;

[0074] Among them, the gate line group 200 includes: at least two gate lines 2 stacked and insulated. For example, the gate line group 200 includes: a first gate line 21, and a second gate line 22 located on the side of the first gate line 21 away from the substrate 1; the orthographic projections of the two gate lines 2 on the substrate 1 overlap; the transistor group T00 includes: at least two transistors T electrically connected to the two gate lines 2 of the gate line group 200 respectively. For example, the transistor group T00 includes: a first transistor T1 connected to the first gate line 21, and a second transistor T2 connected to the second gate line 22; the transistor T includes a gate TA; in addition, the transistor T may further include: a first pole TB, a second pole TC, and an active pattern 5; among them, the first pole TB may be connected to the data line 3 and may be a source electrode; the second pole TC may be a drain electrode and may be electrically connected to the pixel electrode 4 through a first via K1;

[0075] The minimum distance d in the second direction Y between the gate TA of at least one transistor T in the same transistor group T00 and the connected gate line 2 is greater than zero. For example, in combination with Figure 2A 、 Figure 2B As shown, in the same transistor group T00, the gate TA of the first transistor T1 is on the same layer as and in direct electrical contact with the first gate line 21, and the minimum distance between them in the second direction Y is zero; the gate TA of the second transistor T2 is on a different layer from the second gate line 22, and the minimum distance in the second direction Y between the orthographic projection of the gate TA of the second transistor T2 on the substrate 1 and the orthographic projection of the second gate line 22 on the substrate 1 is d, and d is greater than zero.

[0076] In the embodiment of the present application, the gate line group 200 includes: at least two gate lines 2 that are stacked and insulated, and the two gate lines 2 overlap in their orthographic projections on the substrate 1. In this way, the shading area caused by the gate lines in half of the display area can be reduced, which is conducive to high aperture ratio design and improves the panel transmittance; moreover, the gate TA of at least one transistor T in the same transistor group T00 has a minimum distance d from the electrically connected gate line 2 in the second direction Y that is greater than zero. In this way, at least one transistor T in the same transistor group T00 is kept away from the electrically connected gate line 2, avoiding the problem of concentrated distribution of transistors on both sides of the gate line. Since the transistors T themselves are also not transparent, it is easy to cause the non-transparent area to be concentrated near the gate line 2, which is easy to show the problem of display horizontal stripes.

[0077] In a possible implementation, two transistors T of the same transistor group T00 are respectively located on different sides of the gate line group 200, and are used to drive two adjacent pixel electrodes on the same pixel electrode column. For example, one transistor T is located on the upper side of the gate line group 200, and the other transistor T is located on the lower side of the gate line group 200. The transistors T of the upper and lower rows of sub-pixels are distributed on both sides of the gate line 2, which can reduce interference between different signals.

[0078] In one possible embodiment, combining 2A- Figure 2B , the array substrate further includes: a first connection portion L1 extending along the second direction Y; a gate TA of at least one transistor T in the same transistor group T00 is connected to the gate line 2 through the first connection portion L1. The first connection portion L1 is provided so that the transistor connected to the gate line 2 through the first connection portion L1 is spaced a certain distance from the gate line 2 in the second direction Y, so that at least one transistor T in the same transistor group T00 is kept away from the electrically connected gate line 2, and the transistors T in the same transistor group T00 are prevented from being concentrated around the gate line.

[0079] In one possible embodiment, combining 2A- Figure 2B As shown, in the same transistor group T00, the first connection portion L1 can be of the same layer and material as one of the gate lines 2 in the gate line group T00, and they are spaced and insulated from each other, and electrically connected to another gate line 2 through a via. For example, it can be of the same layer and material as the first gate line 21, and the two can be spaced and insulated from each other and not connected, and electrically connected to the second gate line 22 through a second via K2. In this way, when two gate lines 2 of the same gate line group 200 are stacked, and two transistors connected to the same gate line group 200 are spaced apart, and the spaced arrangement of the two transistors can be achieved while avoiding a significant change in the original process as much as possible.

[0080] In one possible embodiment, combining 2A- Figure 2BAs shown, the array substrate further includes: a first connection part D1, and the first connection part L1 is electrically connected to the gate TA of the second transistor T2 through the first connection part D1; the first connection part L1, the first connection part D1, and the gate TA of the second transistor T2 can be an integrally connected structure located on the same layer. That is, the first connection part L1, the first connection part D1, the gate TA of the second transistor T2, the first gate line 21, and the gate TA of the first transistor T1 connected to the first gate 21 are all located on the same layer. In the embodiment of the present disclosure, the first connection part L1, the first connection part D1, the gate TA of the second transistor T2, and the gate TA of the first transistor T1 are all located on the same layer, which can avoid the situation where the gate TAs of two transistors in the same transistor group T00 are located on different layers, while the source and drain electrodes (i.e., the first pole TB and the second pole TC) are on the same layer. In this case, due to the different thicknesses of the dielectric layers between the gate TA and the source and drain electrodes, the performances of the two transistors T in the same transistor group T00 may be different, affecting normal display.

[0081] In another possible implementation manner, the first connection part L1 can also be located on the same layer as the connected gate line 2. For example, the first connection part L1 can be on the same layer and made of the same material as the second gate line 22, and is directly in electrical contact with the second gate line 22.

[0082] In a possible implementation manner, refer to Figures 2A - 2E As shown, the array substrate includes: a plurality of data lines 3 extending along the second direction Y; the orthographic projection of the first connection part L1 on the substrate 1 overlaps with the orthographic projection of the data line 3 on the substrate 1. In the embodiment of the present application, the orthographic projection of the first connection part L1 on the substrate 1 overlapping with the orthographic projection of the data line 3 on the substrate 1 can avoid the problem of the aperture ratio of the display panel being reduced due to the setting of the first connection part L1.

[0083] In a possible implementation manner, refer to Figures 2A - 2E As shown, the array substrate includes: a plurality of pixel electrodes 4; only the gate TA of one of the transistors T in the same transistor group T00 is connected to the gate line 2 through the first connection part L1; the length b1 of the first connection part L1 in the second direction Y is greater than or equal to the length b2 of the pixel electrode 4 in the second direction Y and less than twice the length b2 of the pixel electrode 4 in the second direction Y. That is, in the embodiment of the present application, by setting one of the transistors in the transistor group T00 away from the gate line 2, the two transistors electrically connected to the same gate group 200 can be separately arranged. That is, the positions of the transistors T in the even rows are moved, and the uniform distribution of the transistors is achieved on the basis of improving the aperture ratio through the double-layer gate line design.

[0084] In a possible implementation manner, refer to Figures 2A - 2EAs shown, it is possible to keep the transistor T driving the odd-numbered gate lines 2 in the original design, and set the transistors T driving the even-numbered gate lines 2 at the same pixel positions as those of the transistors T driving the odd-numbered gate lines 2. That is, for example, as Figure 2A shown, the first transistor T1 is arranged at the lower left corner of the pixel electrode 4, and the second transistor T2 is arranged at the lower left corner of the next pixel electrode 4 in the column direction; moreover, in combination with Figures 3A - 3D shown, there is a vertical overlapping area between the layer where the first gate line 21 is located, the layer where the second gate line 22 is located and the layer where the data line 3 is located, and there is an insulating layer in the middle to separate them, which can avoid interference between signals. When transmitting signals, the first output terminal (Gout1) of the gate driving circuit transmits signals through the trace of the layer where the first gate line 21 is located to drive the first transistor T1, and the data signal charges the voltage into the pixel electrode 4 electrically connected to the first transistor T1 through the trace of the layer where the data line 3 is located; the second output terminal (Gout2) of the gate driving circuit transmits signals to the layer where the first gate line 21 is located through the via hole of the insulating layer from the layer where the second gate line 22 is located to drive the second transistor T2, and the data signal charges the voltage into the pixel electrode 4 electrically connected to the second transistor T2 through the trace of the layer where the data line 3 is located.

[0085] In a possible implementation manner, referring to Figure 4 、 Figures 5A - 5E 、 Figures 6A - 6D shown, the array substrate includes: a plurality of pixel electrodes 4; the gate electrodes TA of two transistors T in the same transistor group T00 are both connected to the gate line 2 through the first connection portion L1, and the lengths b1 of the first connection portions L1 connected to the gate electrodes TA of different transistors T are equal. In the embodiments of the present application, the gate electrodes TA of two transistors T in the same transistor group T00 are both connected to the gate line 2 through the first connection portion L1. That is, two transistors T in the same transistor group T00 are both arranged at intervals with the gate line 2, and it is also possible to avoid the problem of horizontal stripes when the transistors T on both sides of the gate line 2 are concentrated around the gate line 2 when two gate lines 2 are stacked; moreover, the lengths b1 of the first connection portions L1 connected to the gate electrodes TA of different transistors T are equal, which can make the distances between the two transistors T on both sides of the same gate line group 200 and the gate line 2 electrically connected to them the same, and the overlapping areas with the data line 3 the same, reducing the possible signal delay (delay) or inconsistent load caused by the inconsistent distances between the two transistors T and the gate line 2 or the inconsistent overlapping areas with the data line 3, and further reducing the problem of inconsistent charging rates.

[0086] In a possible implementation manner, referring to Figure 5A 、 Figure 5BAs shown, the first gate line 21 and the first transistor T1, and the second gate line 22 and the second transistor T2 are both connected after having an overlapping area with a certain equal spacing from the data line 3 (that is, the gate electrodes TA of the two transistors T are both connected to the gate line 2 through the first connection part L1). The first transistor T1 and the second transistor T2 are located at positions with an equal spacing from the gate line group 200 and at the middle positions corresponding to the pixel electrodes 4, so as to ensure the uniform distribution of the transistors T; moreover, combined with Figures 6A - 6D As shown, there is still an insulating layer separating different metal layers. For example, there is an insulating layer between the layer where the first gate line 21 is located and the layer where the second gate line 22 is located, and there is an insulating layer between the layer where the second gate line 22 is located and the layer where the data line 3 is located, which can avoid the mutual interference between signals of different layers. When transmitting signals, the first output terminal (Gout1) of the gate driving circuit transmits signals through the trace of the layer where the first gate line 21 is located to drive the first transistor T1, and the data signal charges the voltage into the pixel electrode 4 connected to the first transistor T1 through the trace of the layer where the data line 3 is located; the second output terminal (Gout2) of the gate driving circuit transmits signals from the layer where the second gate line 22 is located to the layer where the first gate line 21 is located through the vias in the insulating layer to drive the second transistor T2, and the data signal charges the voltage into the pixel electrode 4 connected to the second transistor T2 through the trace of the layer where the data line 3 is located.

[0087] In a possible implementation manner, referring to Figure 5A 、 Figure 5B 、 Figure 5E As shown, the length b1 of the first connection part L in the second direction Y is one-fourth to three-fourths of the length b2 of the pixel electrode 4 in the second direction Y. For example, the length b1 of the first connection part L in the second direction Y is one-fourth, one-half, or three-fourths of the length b2 of the pixel electrode 4 in the second direction Y. In this way, the transistors T on both sides of the same gate line group 200 are distributed at intervals, and at the same time, the transistors T between adjacent gate line groups 200 are also prevented from being concentratedly distributed.

[0088] In a possible implementation manner, referring to Figure 5A 、 Figure 5B As shown, the two first connection parts L1 connected to the same gate line group 200 can be both located in the same layer, and can be of the same layer and the same material as the first gate line 21; the first connection part L1 electrically connected to the gate electrode TA of the first transistor T1 can be directly in contact and electrically connected to the first gate line 21; the first connection part L1 electrically connected to the gate electrode TA of the second transistor T2 can be insulated from the first gate line 21 at intervals. The orthographic projections of the two first connection parts L1 on the substrate 1 both overlap with the orthographic projection of the data line 3 on the substrate 1 to avoid increasing the aperture ratio of the display panel.

[0089] In a possible implementation manner, referring to Figure 5A 、 Figure 5EAs shown, the pixel electrode 4 has a notch Q at a position opposite to the transistor T; the notch Q has two outer boundaries w1 extending along the first direction X, and the region enclosed by the extension lines of the two outer boundaries w1 in the orthographic projection on the substrate 1 overlaps with the central region of the orthographic projection of the pixel electrode 4 on the substrate 1. In the embodiment of the present application, the pixel electrode 4 has a notch Q at a position opposite to the transistor T, so as to provide space for the arrangement of the transistor T.

[0090] In a possible implementation manner, referring to Figure 2A 、 Figure 2B 、 Figure 3C 、 Figure 5A 、 Figure 5B 、 Figure 6C As shown, the array substrate further includes: a second connection part L2 integrally connected to the second gate line 22 and extending along the second direction Y; the orthographic projection of at least part of the first connection part L1 on the substrate overlaps with the orthographic projection of the second connection part L2 on the substrate, and they are connected by vias at the overlapping position. For example, as shown in combination with Figure 2A The orthographic projection of the first connection part L1 below the gate line group 200 on the substrate overlaps with the orthographic projection of the second connection part L2 on the substrate, and they are connected by the second via K2 at the overlapping position. In the embodiment of the present application, by providing the second connection part L2, the first connection part L1 is electrically connected to the second gate line 22 through the second connection L2, which can be adapted to the situation where there is a gap between the first connection part L1 and the first gate line 21. By the second connection part L2 spanning the gap region between the first connection part L1 and the first gate line 21, the connection between the second gate line 22 and the first connection part L1 is realized.

[0091] In a possible implementation manner, referring to Figure 2A 、 Figure 2B 、 Figure 5A 、 Figure 5B As shown, the gate TA extends along the second direction Y; the gate TA has a first outer edge f1 extending along the second direction Y, and the first connection part L1 has a second outer edge f2 extending along the second direction Y; the orthographic projection of the first outer edge f1 on the substrate 1 does not overlap with the orthographic projection of the second outer edge f2 on the substrate 1.

[0092] In a possible implementation manner, in combination with 5A- Figure 5B As shown, the array substrate includes: a first connection part D1, and the first connection part L1 is electrically connected to the gate TA of the transistor T through the first connection part D1; the first connection part L1, the first connection part D1, and the gate TA can be an integrally connected structure.

[0093] In a possible implementation manner, referring to Figure 1 、 Figures 2A - 2E 、 Figures 3A - 3D 、 Figure 4 、Figures 5A - 5F , Figures 6A - 6D As shown in Figures 6A - 6D , each data line 3 can be located on the same layer without being stacked.

[0094] In another possible implementation, referring to Figure 7 , Figures 8A - 8F , Figures 9A - 9D As shown in Figures 9A - 9D , the array substrate further includes: a plurality of data line groups 300 extending along the second direction Y and arranged along the first direction X; the data line group 300 includes: at least two data lines 3 that are stacked and insulated, and the orthographic projections of the two data lines 3 on the substrate 1 overlap. For example, the two data lines 3 of the data line group 300 are respectively: a first data line 31 and a second data line 32; wherein, the second data line 32 is located on the side of the first data line 31 away from the substrate 11. That is, in the embodiments of the present application, the data lines 3 can also be stacked in pairs to further reduce the area of the metal traces in the display area. That is, in the present application, it can be a design combining double-layer data lines and double-layer gate lines, so as to reduce half of the trace area of the data lines on the display panel, further improve the transmittance effect, and without sacrificing the pixel charging rate compared with the double-gate pixel architecture.

[0095] In one possible implementation, referring to Figure 7 , Figures 8A - 8F , Figures 9A - 9D As shown in Figures 9A - 9D , when the data lines 3 are also stacked in pairs, the transistor group T00 can include four transistors respectively electrically connected to the two gate lines 2 of the gate line group 200. For example, it can include: a first transistor T1 and a second transistor T2 electrically connected to the first gate line 21, and a third transistor T3 and a fourth transistor T4 electrically connected to the second gate line 22; wherein, the first data line 31 can be electrically connected to the first transistor T1 and the third transistor T3; the second data line 32 can be electrically connected to the second transistor T2 and the fourth transistor T4.

[0096] In one possible implementation, in combination with Figure 8A , Figure 8B , Figure 8C As shown in Figure 8C , the array substrate can include: two first connection parts L1, the two first connection parts L1 are of the same layer and the same material as the first gate line 21, wherein, one first connection part L1 (for example, the first connection part L1 above the first gate line 21) is directly in contact and electrically connected to the first gate line 21, and the other first connection part L1 (for example, the first connection part L1 below the first gate line 21) is spaced from the first gate line 21 and not connected, and is electrically connected to the second gate line 22 through a second via K2. Optionally, the first connection part L1 can be electrically connected to the second gate line 22 through a second connection part L2 integrally connected to the second gate line 22.

[0097] In one possible implementation, in combination withFigure 8A , Figure 8D , Figure 8E As shown in Figure 8E , the array substrate may include a third connection portion L3 and a fourth connection portion L4. The third connection portion L3 may be on the same layer as the first pole TB and the second pole TC of the transistor T, and may be located between the second pole TC and the first data line 31, and is spaced apart and not connected to both the second pole TC and the first data line 31. The fourth connection portion L4 may be on the same layer as the second data line 32 and is directly in electrical contact therewith. The second data line 32 may be electrically connected to the third connection portion L3 through the fourth connection portion L4 and via a third via K3, realizing the electrical connection between the second data line 32 and the second transistor T2 and the fourth transistor T4.

[0098] Combined with Figure 7 , Figure 8A , Figure 9A As shown in Figure 9A , two adjacent gate lines 2 are vertically and overlappingly arranged in space, and the two are separated by an insulating layer. Two adjacent columns of data lines 3 are vertically and overlappingly arranged in space, and the two are separated by an intermediate insulating layer (for example, there is a fourth insulating layer 94 between the two). There may also be a fifth insulating layer 95 between the layer where the second data line 32 is located and the layer where the pixel electrode 4 is located. Combined with Figures 9A - 9D As shown in Figures 9A - 9D , the multiple pixel electrodes 4 of the array substrate include a first pixel electrode 41, a second pixel electrode 42, a third pixel electrode 43, and a fourth pixel electrode 44. The first output terminal (Gout1) of the gate driving circuit drives the first transistor T1 and the second transistor T2 by transmitting a signal through the first gate line 21 layer. The first data signal charges a voltage into the first pixel electrode 41 through the first transistor T1 by routing through the layer where the first data line 31 is located. The second data signal charges a voltage into the second pixel electrode 42 through the second transistor T2 by routing through the layer where the second data line 32 is located. The second output terminal (Gout2) of the gate driving circuit drives the third transistor T3 and the fourth transistor T4 by routing through the second gate line 22 layer and transferring through an insulating layer via hole to the layer where the first gate line 21 is located. The third data signal charges a voltage into the third pixel electrode 43 through the third transistor T3 by routing through the layer where the first data line 31 is located. The fourth data signal charges a voltage into the fourth pixel electrode 44 through the fourth transistor T4 by routing through the layer where the second data line 32 is located.

[0099] In a possible implementation manner, combined with Figure 7 , Figure 8A As shown in Figure 8A , the array substrate includes multiple pixel electrodes 4 arranged in an array. In the same pixel electrode row, two pixel electrodes 4 located on both sides of the same data line group 300 are respectively connected to different data lines 3 in the data line group 300 through different transistors T. For example, combined with Figure 8AAs shown, the first pixel electrode 41 on the left is electrically connected to the first data line 31 through the first transistor T1; the second pixel electrode 42 on the right is electrically connected to the second data line 32 through the second transistor T2.

[0100] In a possible implementation, referring to Figure 7 and Figure 8A shown, in the same row of pixel electrodes, two pixel electrodes 4 on different sides of the same data line group 300 are respectively connected to different gate lines 2 in the same gate line group 200 through different transistors T. For example, referring to Figure 8A shown, the first pixel electrode 41 on the upper side is electrically connected to the first gate line 21 through the first transistor T1; the third pixel electrode 43 on the lower side is electrically connected to the second gate line 22 through the third transistor T3.

[0101] In a possible implementation, referring to Figure 1 and Figure 2A and Figure 3A and Figure 4 and Figure 7 and Figure 8A shown, in the same row of pixel electrodes, each pixel electrode 4 is electrically connected to the same gate line 2 through the transistor T; in the same column of pixel electrodes, each pixel electrode 4 is electrically connected to the same data line 3 through the transistor T. In some prior art architectures, when the pixel electrodes are alternately connected to the gate lines on the upper and lower sides of the pixel electrode row, if a row of pixels is to be lit, signals need to be input simultaneously to the gate lines on the upper and lower sides of the pixel electrode row. However, in the present application, in the same row of pixel electrodes, each pixel electrode 4 is electrically connected to the same gate line 2 through the transistor T, that is, each row of sub-pixels is connected to the same gate line, and the gate line scanning time is shortened by half. That is, when achieving the same display effect, the related technology requires 120 Hz while the present application only requires 60 Hz for driving, which has the effect of reducing power consumption.

[0102] In a possible implementation, referring to Figure 1 and Figure 2A and Figure 3A and Figure 4 and Figure 7 and Figure 8A shown, in the same column of pixel electrodes, each pixel electrode 4 is electrically connected to the same data line 3 through the transistor T.

[0103] In a possible implementation, referring to Figure 1 and Figure 3A and Figure 7As shown, the array substrate includes: a plurality of pixel electrode rows 400 extending along the first direction X and arranged along the second direction Y; in the scanning direction of the gate lines (for example, the scanning direction is from top to bottom), the orthographic projection of the first gate line group 200 on the substrate 1 is located between the orthographic projection of the first pixel electrode row 400 on the substrate 4 and the orthographic projection of the second pixel electrode row 400 on the substrate 1; the orthographic projection of the last gate line group 200 on the substrate 1 is located between the orthographic projections of the last two pixel electrode rows 400 on the substrate 1. In this way, the occupied area of the gate lines 2 on the array substrate can be reduced, and the aperture ratio of the display panel can be increased.

[0104] In this application, in addition to the double-layer gate line structure mentioned above, it is also possible to have a three-layer to multi-layer structure, which is to place the gate line metal layer with light-shielding effects in a vertical space, reduce the light-shielding area on the plane, improve the pixel aperture ratio, and achieve the effect of increasing the transmittance.

[0105] In this application, the above mainly uses the Column pixel architecture for illustration. In specific implementation, this application can also be other pixel architecture designs (for example, it can be a Zigzag architecture design); the insulating layer between the layer where the first gate line is located and the layer where the second gate line is located can be a whole surface, or only in the horizontal wiring area, and the patterns in the non-overlapping areas are connected through vias for signal connection.

[0106] To more clearly understand the array substrate structure provided by the embodiments of the present disclosure, the following is combined with Figures 5A - 5I The manufacturing process of the array substrate provided by the embodiments of the present application is described as follows:

[0107] Step 1: Fabricate the first gate layer; after depositing the gate metal layer material, through photolithography and etching processes, form the pattern of the first gate layer, including the gate of the transistor device, the odd gate lines (the first gate lines 21), the first connection part L1, and the first connection part D1, as shown in Figure 5B and Figure 5F wherein, Figure 5F is Figure 6C a schematic diagram after forming the first gate layer;

[0108] Step 2: Fabricate the protective layer of the first gate layer; deposit a transparent insulating material (such as SiNx) as the insulating layer of the first gate layer, that is, the first gate insulating layer 91, and through photolithography and etching, form the pattern of the insulating layer, in which the second via is etched out, as shown in Figure 5G wherein, Figure 5G is Figure 6C a schematic diagram after forming the protective layer 91 of the first gate layer;

[0109] Step 3: Fabricate the second gate layer; after depositing the second gate layer material, through photolithography and etching processes, form the pattern of the second gate layer, including the second gate line 22 and the second connection part L2, where the second connection part L2 is electrically connected to the first connection part L1 through the second via K2, as Figure 5C and Figure 5H shown, where Figure 5H is Figure 6C a schematic diagram after forming the second gate layer;

[0110] Step 4: Fabricate the protective layer of the second gate layer; deposit a transparent insulating material (such as SiNx) as the insulating layer of the second gate layer, that is, the second gate insulating layer 92, and through photolithography and etching, form the pattern of the insulating layer, as Figure 5I shown, where Figure 5I is Figure 6C a schematic diagram after forming the protective layer of the second gate layer;

[0111] Step 5: Fabricate the semiconductor layer; deposit the material of the semiconductor layer, and through photolithography and etching, form the semiconductor channel;

[0112] Step 6: Fabricate the source-drain layer; deposit the material of the source-drain layer, and through photolithography and etching processes, form the pattern of the source-drain layer to transmit data signals, as Figure 5D and Figure 6C shown;

[0113] Step 7: Deposit a transparent protective layer material (such as SiNx), and through photolithography and etching processes, form the pattern of the protective layer, that is, the third insulating layer 93;

[0114] Step 8: Fabricate the pixel electrode layer; deposit indium tin oxide, a transparent electrode, and through photolithography and etching processes, form the pattern of the pixel electrode, as Figure 5E shown.

[0115] Based on the same inventive concept, an embodiment of the present application further provides a display panel, including the array substrate provided by the embodiment of the present application.

[0116] The beneficial effects of the embodiments of the present invention are as follows: In the embodiments of the present application, the gate line group 200 includes at least two gate lines 2 that are stacked and insulated. The orthographic projections of the two gate lines 2 on the substrate 1 overlap. In this way, the light-shielding area brought by the gate lines in half of the display area can be reduced, which is helpful for the design of a high aperture ratio and can improve the panel transmittance. Moreover, the minimum distance d between the gate TA of at least one transistor T in the same transistor group T00 and the connected gate line 2 in the second direction Y is greater than zero. In this way, at least one transistor T in the same transistor group T00 can be made to be away from the connected gate line 2, avoiding the problem that when the transistors are concentrated on both sides of the gate line, since the transistors T themselves are also light-impermeable, the light-impermeable regions are easily concentrated near the gate line 2, and it is easy to show the problem of display stripes.

[0117] Based on the same inventive concept, the embodiments of the present disclosure also provide a display device, including the above-mentioned display panel provided by the embodiments of the present disclosure. The implementation of this display device can refer to the embodiments of the above-mentioned display panel, and the repeated parts will not be described again.

[0118] In specific implementation, in the embodiments of the present disclosure, the display device can be: any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc. Other essential components of this display device are understood by those of ordinary skill in the art to have, and will not be described here, nor should it be regarded as a limitation to the present disclosure.

[0119] Although the preferred embodiments of the present disclosure have been described, those skilled in the art can make additional changes and modifications to these embodiments once they know the basic creative concept. Therefore, the appended claims are intended to be construed as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0120] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention also intends to include these changes and modifications.

Claims

1. An array substrate, characterized in that, Comprising: a substrate, a plurality of gate line groups extending along a first direction and arranged along a second direction on one side of the substrate, and a plurality of transistor groups; wherein, each of the gate line groups includes at least two gate lines which are stacked and insulated, and the orthographic projections of the two gate lines on the substrate overlap; each of the transistor groups includes at least two transistors respectively electrically connected to the two gate lines of the gate line group; each of the transistors includes a gate; For at least one of the transistors in the same transistor group, the minimum distance between the gate and the electrically connected gate line in the second direction is greater than zero.

2. The array substrate according to claim 1, wherein The array substrate further includes: a first connection portion extending along the second direction; For at least one of the transistors in the same transistor group, the gate is connected to the gate line through the first connection portion.

3. The array substrate according to claim 2, wherein The array substrate includes: a plurality of data lines extending along the second direction; The orthographic projection of the first connection portion on the substrate overlaps with the orthographic projection of the data line on the substrate.

4. The array substrate according to claim 2, wherein, The array substrate includes: a plurality of pixel electrodes; For only one of the transistors in the same transistor group, the gate is connected to the gate line through the first connection portion; the length of the first connection portion in the second direction is greater than or equal to the length of the pixel electrode in the second direction and less than twice the length of the pixel electrode in the second direction.

5. The array substrate according to claim 2, wherein The array substrate includes: a plurality of pixel electrodes; For two of the transistors in the same transistor group, the gates are both connected to the gate line through the first connection portion, and the lengths of the first connection portions connected to the gates of different transistors are equal.

6. The array substrate according to claim 5, wherein The length of the first connection portion in the second direction is one-fourth to three-fourths of the length of the pixel electrode in the second direction.

7. The array substrate according to claim 6, wherein The pixel electrode has a notch at a position opposite to the transistor; the notch has two outer boundaries extending along the first direction, and the region enclosed by the extension lines of the two outer boundaries in the orthographic projection on the substrate overlaps with the central region of the orthographic projection of the pixel electrode on the substrate.

8. The array substrate according to claim 2, wherein The gate line group includes: a first gate line, and a second gate line located on a side of the first gate line away from the substrate; the transistor group includes: a first transistor connected to the first gate line, and a second transistor connected to the second gate line; The first connection portion is of the same layer and the same material as the first gate line, and the two are insulated from each other at intervals; at least a part of the first connection portion is electrically connected to the second gate line through a via hole.

9. The array substrate according to claim 8, wherein The array substrate further includes: a second connection portion integrally connected to the second gate line and extending along the second direction; At least a part of the orthographic projection of the first connection portion on the substrate overlaps with the orthographic projection of the second connection portion on the substrate, and they are connected through a via hole at the overlapping position.

10. The array substrate according to claim 2, wherein, The gate extends along the second direction; The gate has a first outer edge extending along the second direction, and the first connection portion has a second outer edge extending along the second direction; The orthographic projection of the first outer edge on the substrate does not overlap with the orthographic projection of the second outer edge on the substrate.

11. The array substrate according to any one of claims 1 to 10, characterized in that, The array substrate further includes: a plurality of data line groups extending along the second direction and arranged along the first direction; Each data line group includes: at least two data lines that are stacked and insulated, and the orthographic projections of the two data lines on the substrate overlap.

12. The array substrate according to claim 11, wherein The array substrate includes: a plurality of pixel electrodes arranged in an array; in the same pixel electrode row, two pixel electrodes located on both sides of the same data line group are respectively connected to different data lines in the data line group through different transistors.

13. The array substrate according to claim 12, characterized in that, In the same pixel electrode row, two pixel electrodes located on different sides of the same data line group are respectively connected to different gate lines in the same gate line group through different transistors.

14. The array substrate according to claim 1, wherein In the same pixel electrode row, each pixel electrode is electrically connected to the same gate line through a transistor.

15. The array substrate according to claim 1, wherein The array substrate includes: a plurality of pixel electrode rows extending along the first direction and arranged along the second direction; In the scanning direction of the gate line, the orthographic projection of the first gate line group on the substrate is located between the orthographic projection of the first pixel electrode row on the substrate and the orthographic projection of the second pixel electrode row on the substrate; the orthographic projection of the last gate line group on the substrate is located between the orthographic projections of the last two pixel electrode rows on the substrate.

16. A display panel, characterized in that, It includes the array substrate according to any one of claims 1-15.

17. A display device, characterized in that, It includes the display panel according to claim 16.

Images