Processing method for equipment startup exception, electronic equipment and storage medium

Abstract

The invention provides an equipment startup exception processing method, electronic equipment and a storage medium, and relates to the technical field of computers. And under the condition that the initialization of the memory fails when the electronic equipment is booted to start up through the BIOS, the electronic equipment modifies the channel state information according to the identification result of the channel state information, triggers restart, reads the modified channel state information, and executes the initialization of the memory according to the modified channel state information. According to the scheme, the channel enabling / disabling state of the memory can be set, and multiple retries are executed for initialization of the memory. When the initialization retry of the memory is executed every time, the damaged channel is set to be in the forbidden state, and initialization is performed based on the non-forbidden channel, so that the damaged channel can be avoided, the initialization of the memory can be completed, and the electronic equipment can be guided to be normally started; in addition, according to the scheme, which channels in the DDR are likely to be damaged can be found out, the user is prompted, and therefore the use experience of the user is improved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular, to a method for processing abnormal device startup, an electronic device, and a storage medium. Background Art

[0002] During the process of a user using an electronic device such as a personal computer (PC), if a memory such as a double data rate synchronous dynamic random access memory (DDR) in the electronic device is damaged, it will cause the electronic device to malfunction and freeze, or display a blue screen or a black screen. At this time, if the user triggers a restart of the electronic device, the PC will execute the BIOS (basic input output system) startup boot process. During the startup boot process, due to the damaged memory, the memory initialization (Training) will fail, and further cause the electronic device to be unable to start up and present a black screen phenomenon, seriously affecting the user experience. Summary of the Invention

[0003] This application provides a method for processing abnormal device startup and an electronic device, which solves the problem that the memory initialization during the BIOS boot process in the electronic device fails, resulting in the electronic device being unable to start up.

[0004] In a first aspect, this application provides a method for processing abnormal device startup, and the method includes: detecting first fault information; obtaining channel status information of a memory of the electronic device; modifying the channel status information according to an identification result of the channel status information; triggering a restart; reading the modified channel status information, and performing initialization on channels in an enabled state in the memory.

[0005] Among them, the first fault information indicates that the memory initialization fails. For example, the first fault information can be information such as a code, a character, or a log that can indicate the failure of the memory initialization.

[0006] Among them, the channel status information of the memory is used to indicate the channel status of each channel in the memory, and the channel status is an enabled state or a disabled state. Among them, the electronic device can perform initialization on channels in an enabled state in the memory according to the modified channel status information.

[0007] Through the method for handling abnormal device startup provided by the embodiments of the present application, when the memory initialization fails during the startup of an electronic device through BIOS boot, the electronic device modifies the channel status information according to the recognition result of the channel status information, triggers a restart, then reads the modified channel status information, and performs memory initialization according to the modified channel status information. Thus, by setting the channel enable / disable status of the memory, multiple retries can be performed for memory initialization. Each time a memory initialization retry is performed, since the damaged channel is set to the disabled state, initialization is performed based on the non-disabled channels, so that the damaged channel can be avoided and the memory initialization can be completed to boot the electronic device normally, thereby improving the user experience.

[0008] In some possible implementation manners, the memory is DDR, and the memory initialization failure is DDR Training failure. Among them, DDR Training refers to the initialization of DDR after entering the BIOS boot. DDR Training failure means the failure of the initialization of DDR. Through the above solution, when the electronic device detects that DDR Training fails, it can modify the channel status information, trigger the electronic device to restart, and perform DDR Training on some channels of the DDR during the restart process to avoid the damaged channels and complete the memory initialization to boot the electronic device normally. Among them, the restart is a cold restart.

[0009] Taking the electronic device PC as an example, on the BIOS side, the PC startup process (or called the BIOS boot process) includes security verification, EFI pre-initialization, driver execution environment, selection of the startup device, loading of the operating system, running of the operating system, and system failure repair. Among them, the EFI pre-initialization includes: CPU initialization, chip initialization, memory initialization, and motherboard initialization, etc. Among them, the memory initialization includes performing Training on the channels of the DDR. After DDR Training is successful, the BIOS boot process further includes motherboard initialization, driver execution environment, selection of the startup device, loading and running of the operating system.

[0010] In the solution of the present application, during the hardware initialization stage of system startup, the electronic device detects the DDR Training result. If the electronic device determines that the result of DDR Training is a failure, the electronic device attempts to disable (shield) some damaged channels, triggers the electronic device to restart, and then performs DDR Training. During DDR Training, the disabled channels are automatically avoided, and the system is normally booted in the case of successful DDR Training. Therefore, in the scenario where the black screen and non-booting are caused by abnormal DDR channels, the system can be normally booted through the solution of the present application.

[0011] In some possible implementation manners, the method further includes: when the electronic device detects first fault information, selecting a manner of modifying the channel status information according to a startup speed requirement, a startup memory requirement, and / or a startup success rate requirement. Through the solution of the present application, channels can be selectively disabled according to the DDR initialization result during the PC startup, and the DDR initialization is completed by disabling some faulty channels, so that the PC can be normally started up.

[0012] In some possible implementation manners, modifying the channel status information according to the recognition result of the channel status information includes: recognizing that the channel status information is a first value; modifying the first value to a second value. Wherein, the second value and the first value respectively represent the channel statuses of different channels of the memory, and the channel status is an enabled state or a disabled state.

[0013] In some possible implementation manners, the channel status information (first value) before modification indicates that all channels in the memory are in an enabled state. It should be noted that all channels in the memory being in an enabled state is the initial default state of each channel in the memory. It can be understood that when the memory is initialized for the first time, all channels in the memory are in an enabled state.

[0014] In some other possible implementation manners, the channel status information (first value) before modification indicates that some channels in the memory are in a disabled state. This means that the memory initialization retry has been performed, but the restart fails. In this case, continue the memory initialization retry.

[0015] Wherein, the modified channel status information (second value) indicates that a first channel set in the memory is in a disabled state and a second channel set is in an enabled state, and the second channel set is the other channels in the memory except the first channel set.

[0016] For how to modify the channel status information according to the recognition result of the channel status information, and then perform the memory initialization retry according to the modified channel status information, the present application provides the following several possible implementation manners:

[0017] Method 1: Disable all channels corresponding to one controller each time, trigger the electronic device to restart, and then initialize the non-disabled channels in the memory. That is, traverse each controller among the M controllers.

[0018] In some possible implementations, the electronic device includes M controllers, and each controller correspondingly controls multiple channels of the memory. For example, when M is 2, the electronic device includes 2 controllers. For another example, assuming the memory includes 8 channels, each controller controls 4 channels respectively; or one controller controls 2 channels and the other controller controls 6 channels; this application does not limit the number of memory channels controlled by each controller.

[0019] Among them, the modified channel status information indicates that the disabled status of the channels corresponding to the first controller (the first channel set) is; the channels corresponding to the M - 1 controllers other than the first controller (the second channel set) are in the enabled status. Wherein, the first controller is any one of the M controllers.

[0020] In this case, the range of the restart count x is 1 ≤ x ≤ M.

[0021] In Method 1, traverse each of the M controllers, and each time disable all the channels of one of the M controllers. That is to say, considering the actual boot efficiency, each time disable all the channels of 1 controller, and traverse each controller for a boot retry. The advantage of this method is that the number of retries is small and the boot speed is fast, improving the user experience. Exemplarily, assuming the electronic device includes two controllers, and each controller correspondingly controls 4 channels, then each time use one controller as the processing object for a boot retry, the minimum number of retries is 1 and the maximum number of retries is 2, so the boot time is relatively short.

[0022] It can be understood that in the case where a PC includes multiple controllers and each controller correspondingly controls multiple DDR channels, if DDR Training fails, it may be caused by the damage of the DDR channels corresponding to a certain one of the controllers, or it may be caused by the damage of the DDR channels corresponding to both controllers. In view of this, this application disables the DDR channels corresponding to one controller each time, then performs a cold restart and conducts DDR Training on the non - disabled channels. In the case of Training failure, restore the disabled channels to the enabled state, disable the DDR channels corresponding to another controller, then perform a cold restart and conduct DDR Training on the non - disabled channels; execute this way for each controller in a traversal manner, avoid the damaged channels during DDR Training, complete DDR initialization, and boot the electronic device normally.

[0023] Through the solution of this application, when DDR Training fails during the BIOS boot-up after the electronic device is started, the electronic device can disable the DDR channels corresponding to each controller one by one, perform DDR Training based on the non-disabled channels after a cold start. In case of training failure, the disabled channels are restored and enabled, the DDR channels corresponding to another controller are disabled, and then the device is cold restarted and DDR Training is performed on the non-disabled channels. In case of successful training, the memory initialization is completed, the electronic device is booted up normally, and a DDR failure can be prompted after booting. Through this solution, not only can the electronic device be quickly booted up when DDR Training fails, but also it can find out which channels in the DDR may be damaged and prompt the user to send it for repair or perform data backup in time, thus improving the user experience.

[0024] Method 2: Disable one channel each time, trigger the restart of the electronic device, and then initialize the non-disabled channels in the memory. That is, traverse each channel in the memory.

[0025] In some possible implementation manners, the electronic device includes N channels. The N channels can be divided into a first channel set and a second channel set. The first channel set refers to one channel, called the first channel. Among them, the first channel is any one of the N channels.

[0026] Among them, the modified channel status information indicates that the first channel among the N channels is in the disabled state. The N-1 channels (the second channel set) other than the first channel among the N channels are in the enabled state.

[0027] In this case, the range of the number of restarts x is 1 ≤ x ≤ N.

[0028] In Method 2, traverse each channel in the DDR and disable one channel in the DDR each time. The electronic device can disable one channel at a time and perform DDR Training on the non-disabled channels after a cold restart. Specifically, the electronic device first disables one channel and performs DDR Training on the non-disabled channels after a cold restart. If the training fails, the disabled channel is restored and enabled, another channel is disabled, and DDR Training is performed on the non-disabled channels after a cold restart. This is performed for each channel in turn.

[0029] With the above solution, in the case where the PC includes multiple controllers and each controller corresponds to controlling multiple DDR channels, if the DDR Training fails, it may be due to a damage to a certain DDR channel corresponding to a certain controller, which causes the DDR Training to fail. Accordingly, in this application, one DDR channel is disabled each time, then a cold restart is performed, and then the DDR Training is performed on the non-disabled channels. In the case of a training failure, the disabled channel is restored and enabled, another DDR channel is disabled, then a cold restart is performed and the DDR Training is performed on the non-disabled channels; this process is iteratively executed for each channel, avoiding the damaged channel during the DDR Training, completing the DDR initialization, and guiding the electronic device to boot up normally.

[0030] In Method 2, one DDR channel is disabled each time, and each channel of each controller is traversed for a power-on retry. Since the number of retries is relatively large in this method, the power-on time is relatively long. The advantage is that the available storage capacity can be increased. Exemplarily, it is still assumed that the electronic device includes two controllers, each controller corresponds to controlling 4 channels, and there are a total of 8 channels. Each time, one channel is used as the processing object for a power-on retry, with a minimum of 1 retry and a maximum of 8 retries.

[0031] Method 3: Traverse according to any combination of the enable states of N channels.

[0032] In some possible implementation manners, the memory includes N channels, and the channel status information is an N-bit binary value. The values 0 and 1 of the N-bit binary value respectively represent the enabled state or the disabled state of the N channels.

[0033] Among them, the first value and the second value are respectively 2 N different N-bit binary values among the N-bit binary values.

[0034] In this case, the range of the number of restarts x is 1 ≤ x ≤ 2 N -1.

[0035] Among them, for different startup memory requirements, the preset quantity thresholds are different.

[0036] In some possible implementation manners, determining that at least one channel disabled each time is less than or equal to a preset quantity threshold according to the startup memory requirement of the operating system of the electronic device includes: for an operating system with a first startup memory requirement, determining that at least one channel disabled each time is less than or equal to a first preset quantity threshold; for an operating system with a second startup memory requirement, determining that at least one channel disabled each time is less than or equal to a second preset quantity threshold; wherein, the first startup memory requirement is less than the second startup memory requirement, and the first preset quantity threshold is greater than the second preset quantity threshold.

[0037] Through the above solution, for operating systems with different startup memory requirements, the number of channels disabled each time can be limited to ensure that the DDR can provide sufficient memory for the operating system to complete startup.

[0038] In Mode 3, it is still assumed that the electronic device includes two controllers, and each controller correspondingly controls 4 channels. Then, the state combinations of all 8 channels are traversed. The state of each channel includes an enabled state and a disabled state. When retrying, all combined states of the 8 channels will be traversed, that is, 2 8 types. The minimum number of retries is 1 time, and the maximum number of retries is 256 times. Since the number of retries in this way is more than that in other implementation manners, the boot time is longer. The advantage is that it can find out the situation where channels of both controllers are damaged.

[0039] In some possible implementation manners, the electronic device can record the number of reboots x, and determine the DDR damage frequency or severity according to the number of reboots x.

[0040] In some possible implementation manners, modifying the channel status information of the memory includes: modifying the channel status information according to the startup memory requirement of the operating system of the electronic device, so that the number of channels in the enabled state is greater than or equal to a preset quantity threshold.

[0041] In some possible implementation manners, detecting the first fault information includes: performing memory initialization based on the basic input / output system (BIOS) boot process; during the memory initialization process, detecting the first fault information.

[0042] With this solution, memory initialization is performed based on the basic input / output system (BIOS) boot process. When the first fault information is detected, it indicates that the memory initialization has failed. In the case of a failed memory initialization, multiple retries are performed for memory initialization: obtaining the channel status information of the memory; modifying the channel status information according to the recognition result of the channel status information; triggering a restart; reading the modified channel status information, and initializing the enabled channels in the memory. In the case of a successful retry of memory initialization, the BIOS boot process is continued to enable the electronic device to boot up normally.

[0043] In some possible implementation manners, after the initialization is performed, the method further includes: in the case of successful memory initialization, the electronic device boots up normally.

[0044] In some possible implementation manners, after the electronic device boots up normally, the method further includes: obtaining the channel status information of the memory; in the case where the channel status information indicates that some channels of the memory are in a disabled state, the electronic device displays a damage prompt message, and the damage prompt message is used to prompt that there are damaged channels in the memory.

[0045] In some possible implementation manners, the damage prompt message is determined according to the channel status information of the memory.

[0046] For example, in the case where the channel status information of the memory indicates that the channel corresponding to the first controller is in a disabled state and the memory initialization is successful, it indicates that there is a damaged channel in the channel corresponding to the first controller.

[0047] For example, in the case where the channel status information of the memory indicates that the first channel is in a disabled state and the memory initialization is successful, it indicates that the first channel is a damaged channel.

[0048] For example, in the case where the channel status information of the memory indicates that the first channel and the second channel are in a disabled state and the memory initialization is successful, it indicates that there are damaged channels in the first channel and the second channel.

[0049] In some possible implementation manners, the channel status information of the memory is stored at the first register address of a complementary metal-oxide-semiconductor (CMOS) memory, and the number of restarts is stored at the second register address of the CMOS. Exemplarily, the first register address is 0x4E, and the second register address is 0x4F.

[0050] Exemplarily, channel status information 0x00, or other possible channel status information, is stored at the first register address 0x4E. Among them, 0x00 indicates that all channels of the memory are in an enabled state.

[0051] Through the solution of this application, after successful startup, the computer manager reads the channel status information at the 0x4E position of the CMOS. If the value at the 0x4E position is not 0x00, the computer manager determines that some channels of the DDR have been disabled. In this case, the computer manager performs a pop-up window process to remind the user through the pop-up window that the DDR is damaged and the DDR needs to be sent for repair or data backup.

[0052] In a second aspect, the present application also provides a method for processing abnormal device startup, which is applied to an electronic device. The electronic device includes a first memory, a CMOS, a first controller, and a second controller, and the first controller and the second controller respectively control different channels of the first memory.

[0053] The method includes: detecting a first fault message, where the first fault message indicates that the initialization of the first memory fails; in the case of detecting the first fault message, writing a first value to the first register address in the CMOS; in the case of writing the first value, triggering the electronic device to restart; during the restart process of the electronic device, initializing the channels corresponding to the second controller and not initializing the channels corresponding to the first controller. Wherein, the first value indicates that the channels corresponding to the first controller are in a disabled state.

[0054] In the case where the electronic device includes two controllers, through the solution of this application, it is necessary to restart one or two times.

[0055] Case of successful first restart: In the case where the initialization of the channels corresponding to the second controller is successful, after the initialization of the channels corresponding to the second controller is successful, the electronic device boots up. In this case, the electronic device can determine that there are damaged channels in the channels corresponding to the first controller. After the electronic device boots up, the electronic device can display a damage prompt message, and the damage prompt message is used to prompt that there are damaged channels in the channels corresponding to the first controller.

[0056] Through the above solution, the electronic device boots up successfully after restarting once.

[0057] If the first restart fails, then perform a second restart: During the initialization process of the channels corresponding to the second controller, detect the first fault message; in the case of detecting the first fault message, write a second value to the first register address in the CMOS; in the case of writing the second value, trigger the electronic device to restart; during the restart process of the electronic device, initialize the channels corresponding to the first controller and not initialize the channels corresponding to the second controller. Wherein, the second value indicates that the channels corresponding to the second controller are in a disabled state.

[0058] Case of successful second restart: When the initialization of the channels corresponding to the first controller is successful, after the initialization of the channels corresponding to the first controller is successful, the electronic device is powered on. In this case, the electronic device can determine that there are damaged channels in the channels corresponding to the second controller. After the electronic device is powered on, the electronic device can display a damage prompt message, and the damage prompt message is used to prompt that there are damaged channels in the channels corresponding to the second controller.

[0059] After restarting twice through the above solution, the electronic device is powered on successfully.

[0060] Case of failed second restart: During the initialization of the channels corresponding to the first controller, the first fault information is detected, and the electronic device fails to power on. In this case, the electronic device can determine that there are damaged channels in the channels corresponding to each of the two controllers.

[0061] In some possible implementation manners, when the electronic device includes a first controller, a second controller, and a third controller, the above method includes:

[0062] Detect the first fault information; when the first fault information is detected, write a first value to the first register address in the CMOS; when the first value is written, trigger the electronic device to restart; during the restart of the electronic device, initialize the channels corresponding to the second controller and the third controller respectively, and do not initialize the channels corresponding to the first controller.

[0063] When the electronic device includes three controllers, the solution of the present application needs to be restarted once or twice or three times.

[0064] Case of successful first restart: When the initialization of the channels corresponding to the second controller and the third controller respectively is successful, after the initialization is successful, the electronic device is powered on. In this case, the electronic device can determine that there are damaged channels in the channels corresponding to the first controller. After the electronic device is powered on, the electronic device can display a damage prompt message, and the damage prompt message is used to prompt that there are damaged channels in the channels corresponding to the first controller.

[0065] After restarting once through the above solution, the electronic device is powered on successfully.

[0066] If the first restart fails, perform a second restart: During the process of initializing the channels corresponding to the second controller and the third controller respectively and failing, a first fault message is detected; in the case of detecting the first fault message, a second value is written to the first register address in the CMOS; in the case of writing the second value, the electronic device is triggered to restart; during the restart process of the electronic device, the channels corresponding to the first controller and the third controller are initialized respectively, and the channels corresponding to the second controller are not initialized.

[0067] The situation of successful second restart: In the case of successfully initializing the channels corresponding to the first controller and the third controller respectively, after the initialization is successful, the electronic device powers on. In this case, the electronic device can determine that there is a damaged channel in the channels corresponding to the second controller. After the electronic device powers on, the electronic device can display a damage prompt message, which is used to prompt that there is a damaged channel in the channels corresponding to the second controller.

[0068] After restarting twice through the above solution, the electronic device powers on successfully.

[0069] If the second restart fails, perform a third restart: During the process of initializing the channels corresponding to the first controller and the third controller respectively, a first fault message is detected; in the case of detecting the first fault message, a third value is written to the first register address in the CMOS; in the case of writing the third value, the electronic device is triggered to restart; during the restart process of the electronic device, the channels corresponding to the first controller and the second controller are initialized respectively, and the channels corresponding to the third controller are not initialized. Among them, the third value indicates that the channels corresponding to the third controller are in a disabled state.

[0070] The situation of successful third restart: In the case of successfully initializing the channels corresponding to the first controller and the second controller respectively, after the initialization is successful, the electronic device powers on. In this case, the electronic device can determine that there is a damaged channel in the channels corresponding to the third controller. After the electronic device powers on, the electronic device can display a damage prompt message, which is used to prompt that there is a damaged channel in the channels corresponding to the third controller.

[0071] After restarting three times through the above solution, the electronic device powers on successfully.

[0072] The situation of failed third restart: During the process of initializing the channels corresponding to the first controller and the second controller respectively, a first fault message is detected; the electronic device fails to power on. In this case, the electronic device can determine that there are damaged channels in the channels corresponding to all three controllers.

[0073] In some possible implementation manners, the first memory is a DDR, and the initialization failure is a DDR Training failure.

[0074] In a third aspect, the present application provides a device startup anomaly processing apparatus, and the apparatus includes a unit for executing the method in the first aspect above. The apparatus can correspond to executing the method described in the first aspect above. For the relevant descriptions of the units in the apparatus, please refer to the description in the first aspect above. For the sake of brevity, they will not be repeated here.

[0075] Among them, the method described in the first aspect above can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more modules or units corresponding to the above functions. For example, a processing module or unit, a display module or unit, etc.

[0076] In a fourth aspect, the present application provides an electronic device, and the electronic device includes a processor, and a computer program or instruction stored in the processor and the memory. The processor is used to execute the computer program or instruction so that the method in the first aspect is executed.

[0077] In a fifth aspect, the present application provides a computer-readable storage medium, on which a computer program (which can also be referred to as an instruction or code) for implementing the method in the first aspect is stored. For example, when the computer program is executed by the computer, the computer can execute the method in the first aspect.

[0078] In a sixth aspect, the present application provides a chip, including a processor. The processor is used to read and execute a computer program stored in the memory to execute the method in the first aspect and any possible implementation manners thereof. Optionally, the chip further includes a memory, and the memory is connected to the processor through a circuit or a wire.

[0079] In a seventh aspect, the present application provides a chip system, including a processor. The processor is used to read and execute a computer program stored in the memory to execute the method in the first aspect and any possible implementation manners thereof. Optionally, the chip system further includes a memory, and the memory is connected to the processor through a circuit or a wire.

[0080] In an eighth aspect, the present application provides a computer program product, and the computer program product includes a computer program (which can also be referred to as an instruction or code). When the computer program is executed by an electronic device, the electronic device implements the method in the first aspect.

[0081] It can be understood that the beneficial effects of the second aspect to the eighth aspect above can refer to the relevant descriptions in the first aspect above, and will not be repeated here. Description of the Drawings

[0082] Figure 1Schematic diagram of the BIOS startup process provided by the embodiments of the present application;

[0083] Figure 2 Schematic diagram of the startup process of the electronic device provided by the embodiments of the present application;

[0084] Figure 3 Schematic diagram of the corresponding relationship between the CPU, controller and DDR channels provided by the embodiments of the present application;

[0085] Figure 4 Schematic diagram of the process of a black screen and non-booting in the case of BIOS startup failure;

[0086] Figure 5 Schematic diagram of the structure of an electronic device provided by the embodiments of the present application;

[0087] Figure 6 Schematic diagram of the software architecture of an electronic device provided by the embodiments of the present application;

[0088] Figure 7 Schematic diagram of the process of the method for handling abnormal device startup provided by the first embodiment of the present application Figure 1 ;

[0089] Figure 8 Schematic diagram of the process of the method for handling abnormal device startup provided by the first embodiment of the present application Figure 2 ;

[0090] Figure 9 Schematic diagram of the process of the method for handling abnormal device startup provided by the first embodiment of the present application Figure 3 ;

[0091] Figure 10 Schematic diagram of the module interaction timing of the method for handling abnormal device startup provided by the first embodiment of the present application;

[0092] Figure 11 Schematic diagram of the process of the method for handling abnormal device startup provided by the second embodiment of the present application Figure 1 ;

[0093] Figure 12 Schematic diagram of the process of the method for handling abnormal device startup provided by the second embodiment of the present application Figure 2 ;

[0094] Figure 13 Schematic diagram of the module interaction timing of the method for handling abnormal device startup provided by the second embodiment of the present application Figure 2 ;

[0095] Figure 14 Schematic diagram of the process of the method for handling abnormal device startup provided by the third embodiment of the present application Figure 1 ;

[0096] Figure 15 Schematic flow of the method for handling abnormal device startup provided in the third embodiment of the present application Figure 2 。 Detailed implementation manners

[0097] To make the objectives, technical solutions and advantages of the present application clearer and more understandable, the following further describes the embodiments of the present application in detail with reference to specific embodiments and the accompanying drawings.

[0098] To facilitate the understanding of the embodiments of the present application, the following explains some terms in the embodiments of the present application to facilitate the understanding of those skilled in the art.

[0099] 1. BIOS

[0100] BIOS (basic input output system, basic input / output system), refers to the functional operation interface for detecting hardware functions and booting the operating system when the device is powered on. Exemplarily, Figure 1 shows the BIOS operation process. The BIOS operation process includes power-on, BIOS initialization, BIOS self-check, booting the operating system, and running the operating system.

[0101] 2. UEFI

[0102] UEFI (unified extensible firmware interface, unified extensible firmware interface), is a standard that details a new type of interface. The UEFI interface is a standard firmware interface applicable to electronic devices such as PCs (personal computers), aiming to improve software interoperability and solve the limitations of BIOS. As Figure 1 shown, the UEFI initialization process can be adopted in the BIOS operation process. Among them, the UEFI initialization process is used for the operating system to be automatically loaded from the pre-boot operation environment to an operating system, thus saving the boot time.

[0103] Figure 2 Details the boot process of the electronic device. As Figure 2 shown, the boot process of the electronic device can include the following four stages: power-on, UEFI initialization stage, loading and running the operating system (operating system, OS), and system fault repair stage. In these four stages, the following actions are sequentially completed: security verification → EFI pre-initialization → driver execution environment → boot device selection → pre-operating system loading → operating system running stage → system fault repair (booting or shutting down).

[0104] In the UEFI initialization stage, it includes CPU initialization, chip initialization, motherboard initialization, etc. This initialization process is called pre-EFI initialization or hardware initialization. After completing the UEFI initialization, the driver execution environment and the boot device selection are executed, and the operating system is booted by calling the UEFI interface. After completing the system boot, the operating system is loaded and run.

[0105] 3. CMOS

[0106] CMOS (complementary metal oxide semiconductor) is an important chip in the computer system and stores the most basic data for system boot.

[0107] 4. Cold start

[0108] Cold start, also known as cold reboot, is a startup method for electronic devices. Once cold started, all the memory information will be lost, the hardware will be re-detected, the system boot data will be obtained from the CMOS, and then the operating system will be started based on the system boot data. After the operating system is started, the electronic device will be powered on.

[0109] 5. DDR Training

[0110] DDR (double data rate) refers to synchronous dynamic random access memory, which transfers data twice within one clock cycle to improve the memory transfer rate. The pre-EFI initialization stage of an electronic device involves the process of DDR Training. DDR Training refers to the process of calibrating and adjusting the memory subsystem during the DDR interface initialization stage to ensure the stability and performance of data transfer. The main goal of DDR Training is to solve data transfer problems that may be caused by factors such as signal integrity, timing issues, and noise.

[0111] Currently, the boot process of electronic devices such as PCs follows the standard UEFI initialization process. Among them, DDR Training is located in the pre-EFI initialization stage of the UEFI initialization process. DDR Training is used to calibrate and compensate key parameters such as timing and voltage for each link between the CPU and DDR channels respectively, so that the DDR working state reaches the optimal.

[0112] It should be noted that during the user's use of electronic devices such as PCs, if the DDR particles or DDR communication links of the electronic device are irreversibly damaged, it will cause the electronic device to malfunction and freeze, display a blue screen, or go black. At this moment, if the electronic device is cold restarted, the DDR Training during the PC BIOS boot process will fail due to the DDR damage, resulting in the phenomenon that the electronic device permanently goes black and cannot be powered on, seriously affecting the user experience.

[0113] For example, as Figure 3 shown, in a certain PC product, the host CPU includes controller Mc0 and controller Mc1, and each controller controls 4 DDR channels correspondingly, that is, these two controllers correspond to a total of 8 DDR channels.

[0114] Figure 4 shows the execution logics on the BIOS side and the Windows side after the electronic device is cold restarted. As Figure 4 shown, the execution logics on the BIOS side and the Windows side include S1 to S4.

[0115] S1: On the BIOS side, the system boots and enters the pre-initialization stage of EFI. During the DDR initialization process, Training will be performed on all 8 DDR channels by default.

[0116] S2: After the Training results of all these 8 channels are passed or successful (corresponding to the "yes" branch in the figure), the system will enter the next stage to execute the subsequent boot process.

[0117] S3: If the Training result of any one of the 8 channels is failed (corresponding to the "no" branch in the figure), it will cause the system to freeze at this stage, that is, the system has an exception and the boot process ends.

[0118] S4: If the Training result of any one of the 8 channels is failed, it will be shown as the electronic device going black and not being able to be powered on on the Windows side (human-computer interaction side).

[0119] Thus, it can be seen that when the user uses a PC product, if the DDR particles or DDR communication links of the electronic device are irreversibly damaged, it will cause the PC product to freeze, display a blue screen, or go black. At this time, if the electronic device is cold restarted, the DDR Training will fail, resulting in the phenomenon that the electronic device permanently goes black and cannot be powered on, seriously affecting the user experience.

[0120] In view of this, the present application proposes a method for handling abnormal device startup. When the memory initialization fails during the BIOS boot startup of an electronic device, the electronic device modifies the channel status information according to the recognition result of the channel status information, triggers a restart, then reads the modified channel status information, and performs memory initialization according to the modified channel status information. Thus, by setting the channel enable / disable status of the memory, multiple retries can be performed for memory initialization. Each time a memory initialization retry is performed, since the damaged channel is set to the disabled state and the initialization is performed based on the non-disabled channels, the damaged channels can be avoided and the memory initialization can be completed to boot the electronic device normally, thereby improving the user experience.

[0121] Specifically, during the hardware initialization stage when the system boots up, the electronic device detects the result of "DDR Training". If the electronic device determines that the result of "DDR Training" is a failure, the electronic device attempts to disable (shield) some damaged channels, then triggers the restart of the electronic device and performs DDR Training, automatically avoiding the disabled channels during DDR Training, thereby achieving normal system boot. Through the solution of the present application, in the scenario where the black screen fails to boot due to some DDR anomalies, the system can be booted normally.

[0122] Improvements of the present application compared with the related art: By judging the DDR initialization status of the PC, if the initialization fails, each channel is disabled respectively for startup retry, and the problem of failure to boot caused by physical damage of DDR particles can be solved.

[0123] The solution of the present application can be applied not only to PC products but also to other electronic devices, including but not limited to mobile phones, tablets, smart screens, smart watches, etc. The following embodiments do not make special restrictions on the specific form of the electronic device.

[0124] Please refer to Figure 5 , which is a schematic structural diagram of the electronic device 100 provided by the embodiment of the present application.

[0125] As Figure 5 shown, the electronic device 100 may include: a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, a wireless communication module 150, a display screen 160, etc.

[0126] It can be understood that the structure illustrated in this embodiment does not constitute a specific limitation on the electronic device 100. In some other embodiments, the electronic device 100 may include more or fewer components than shown in the figure, or combine certain components, or split certain components, or have different component arrangements. The illustrated components can be implemented in hardware, software, or a combination of software and hardware.

[0127] The processor 110 may include one or more processing units. For example, the processor 110 may include an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a memory, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU), etc. Among them, different processing units may be independent devices or integrated in one or more processors. The processor 110 can implement the method for processing abnormal device startup provided in the embodiments of the present application.

[0128] The controller may be the nerve center and command center of the electronic device 100. The controller can generate operation control signals according to the instruction operation code and timing signals to complete the control of fetching and executing instructions.

[0129] A memory may also be provided in the processor 110 for storing instructions and data. In some embodiments, the memory in the processor 110 is a cache memory. This memory can save the instructions or data that the processor 110 has just used or recycled. If the processor 110 needs to use the instruction or data again, it can directly call it from the memory. This avoids repeated accesses, reduces the waiting time of the processor 110, and thus improves the efficiency of the system.

[0130] In some embodiments, the processor 110 may include one or more interfaces. The interfaces may include an I2C interface, an inter-integrated circuit sound (I2S) interface, a pulse-code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a USB interface, etc.

[0131] It can be understood that the interface connection relationships between the modules illustrated in this embodiment are only illustrative descriptions and do not constitute a structural limitation on the electronic device 100. In other embodiments, the electronic device 100 may also adopt different interface connection methods in the above embodiments, or a combination of multiple interface connection methods.

[0132] The electronic device 100 realizes the display function through the GPU, the display screen 160, and the application processor, etc. The GPU is a microprocessor for image processing, connecting the display screen 160 and the application processor. The GPU is used to execute mathematical and geometric calculations for graphics rendering. The processor 110 may include one or more GPUs, which execute program instructions to generate or change display information.

[0133] The display screen 160 is used to display images, videos, etc. The display screen 160 includes a display panel.

[0134] The external memory interface 120 may be used to connect to an external memory card, such as a Micro SD card, to expand the storage capacity of the electronic device 100. The external memory card communicates with the processor 110 through the external memory interface 120 to achieve the data storage function. For example, files such as music and videos are saved in the external memory card.

[0135] The internal memory 121 may be used to store computer-executable program codes, and the executable program codes include instructions. The processor 110 executes various functional applications and data processing of the electronic device 100 by running the instructions stored in the internal memory 121. For example, in the embodiments of the present application, the processor 110 may execute the instructions stored in the internal memory 121. The internal memory 121 may include a program storage area and a data storage area.

[0136] Among them, the storage program area can store the operating system, application programs required for at least one function (such as the sound playback function, image playback function, etc.), and so on. The storage data area can store the data created during the use of the electronic device 100 (such as audio data, phone book, etc.), and so on. In addition, the internal memory 121 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, a universal flash storage (UFS), etc.

[0137] Specifically, in the solution of this application, the internal memory includes DDR. The internal memory also includes CMOS.

[0138] In this application, the operating system applied by the electronic device may be the Windows system, or any other possible system. The software system of the above-mentioned electronic device 100 may adopt a layered architecture, an event-driven architecture, a microkernel architecture, a microservices architecture, or a cloud architecture. In this embodiment of the application, taking the Windows system with a layered architecture as an example, the software structure of the electronic device 100 is exemplarily described.

[0139] Figure 6 It is the software structure block diagram of the electronic device 100 in this embodiment of the application.

[0140] The layered architecture divides the software into several layers, and each layer has a clear role and division of labor. The layers communicate with each other through software interfaces. In some embodiments, the Windows system is divided into a user mode and a kernel mode. Among them, the user mode includes an application layer and a subsystem dynamic link library. The kernel mode is divided into a firmware layer, a hardware abstraction layer (HAL), a kernel and a driver layer, and an executive body from bottom to top. The above software architecture runs on top of the hardware layer of the electronic device, and the hardware layer may include a GPU, a CPU, a mouse, a microphone, a camera, a keyboard, etc.

[0141] As Figure 6 shown, the application layer includes the computer manager. Among them, only some application programs are shown in the figure, and the application layer may also include other application programs, such as music, video, game, office, social and other application programs, which are not limited in this application.

[0142] The application layer also includes an environment subsystem. The environment subsystem can present certain subsets of the basic executive system services to the application programs in a specific form, and provide an execution environment for the application programs. The subsystem dynamic link library includes an application programming interface (API) module, and this API module can provide system call entry and internal function support for the application programs.

[0143] The execution body includes a parameter acquisition module, a DDR Training module, a failure count accumulation module, a channel status setting module, etc.

[0144] The parameter acquisition module is used to acquire DDR initialization parameters when the electronic device is powered on.

[0145] The DDR Training module is used to initialize the DDR based on the acquired parameters when the electronic device is powered on.

[0146] The failure count accumulation module is used to accumulate the failure times of DDR Training when the electronic device is restarted.

[0147] The channel status setting module is used to set the enable status of the DDR channels. For example, when DDR Training fails, the enable status of some DDR channels is set to the disabled state, that is, these DDR channels are disabled, triggering the restart of the electronic device. When the electronic device is restarted, Training is performed on the non-disabled DDR channels, and Training is not performed on the disabled DDR channels, thereby ensuring that the next stage can be normally entered to boot the system.

[0148] The kernel and driver layer includes the kernel and device drivers.

[0149] The kernel is an abstraction of the processor architecture, isolating the differences between the execution body and the processor architecture, and ensuring the portability of the system. The kernel can perform thread arrangement and scheduling, trap handling and exception scheduling, interrupt handling and scheduling, etc.

[0150] The device driver runs in kernel mode and is an interface between the I / O system and related hardware. The device driver can include a graphics driver, a system driver, a mouse driver, an audio / video driver, a camera driver, a keyboard driver, etc. For example, the graphics driver can drive the GPU to run, and the system driver can drive the CPU to run.

[0151] HAL is a kernel-mode module that can hide various hardware-related details, such as I / O interfaces, interrupt controllers, and multiprocessor communication mechanisms, etc., providing a unified service interface for different hardware platforms running Windows, and achieving portability on multiple hardware platforms. It should be noted that in order to maintain the portability of Windows, the internal components of Windows and the device drivers written by users do not directly access the hardware, but call the routines in HAL.

[0152] The firmware layer can include BIOS, which is a set of programs fixed to a read-only memory (ROM) chip on the computer motherboard. BIOS stores the most important basic input and output programs of the computer, the self-test program after power-on, and the system self-starting program. BIOS can read and write specific information of system settings from CMOS. The main function of BIOS is to provide the lowest-level and most direct hardware settings and control for the computer. The system driver can send instructions to the CPU through BIOS.

[0153] It should be noted that the embodiments of the present application are only illustrated using the Windows system as an example. In other operating systems (such as the Android system, the IOS system, etc.), as long as the functions implemented by each functional module are similar to those in the embodiments of the present application, the solutions of the present application can also be implemented.

[0154] The execution subject of the method for processing the abnormal startup of the device provided in the embodiment of the present application can be the above-mentioned electronic device, or it can be a functional module and / or functional entity in the electronic device that can implement the method for processing the abnormal startup of the device, and the scheme of the present application can be implemented by hardware and / or software, which can be determined according to actual use requirements, and the embodiment of the present application is not limited. Taking an electronic device as an example, the method for processing the abnormal startup of the device provided in the embodiment of the present application is exemplarily described in combination with the accompanying drawings.

[0155] The following will be combined with the accompanying drawings to illustrate the embodiments of the present application through the following multiple exemplary embodiments. The methods in the following embodiments can be implemented in an electronic device with the above hardware structure and software architecture. The hardware structure diagram of the electronic device can be as follows: Figure 5 As shown, the software structure diagram of the electronic device can be as follows Figure 6 For the sake of convenience, the embodiments of the present application are all based on electronic devices as examples.

[0156] In order to better understand the embodiments of the present application, the embodiments of the present application are briefly described below:

[0157] The method for processing device startup abnormality provided in the embodiment of the present application is applied to an electronic device, the operating system applied by the electronic device may be a Windows system, the electronic device may include one or more controllers and one or more DDR channels, and each controller may control one or more DDR channels. For ease of explanation, the following is an example in which the electronic device includes two controllers, and each controller corresponds to four DDR channels.

[0158] Table 1

[0159]

[0160] As shown in Table 1, the two controllers are respectively denoted as Mc0 and Mc1, where controller Mc0 correspondingly controls four channels Ch0, Ch1, Ch2, and Ch3. Controller Mc1 correspondingly controls another four channels Ch0, Ch1, Ch2, and Ch3.

[0161] Return to reference Figure 3 , Figure 3 shows the corresponding relationship among the host, the controller, and the DDR channels. As Figure 3 shown, the host CPU of the electronic device includes controller Mc0 and controller Mc1. Controller Mc0 can control four DDR channels. Similarly, controller Mc1 can also control four DDR channels. Among them, different controllers respectively control different DDR channels.

[0162] It should be noted that here, taking the electronic device including two controllers and each controller corresponding to four DDR channels as an example for exemplary illustration, it can be understood that in actual implementation, the electronic device may further include more controllers, and the number of DDR channels controlled by each controller is not limited to four, and can be specifically determined according to actual usage requirements, which is not limited in this application.

[0163] For the "DDR Training" in the PC BIOS boot process, the solution of this application can include two stages:

[0164] The first stage: At the starting stage of "DDR Training", the PC reads the current DDR channel status information, and then selects the channels with the current DDR channel status as enabled and performs "DDR Training".

[0165] The second stage: At the end stage of "DDR Training", the PC judges the result of "DDR Training". If the result of "DDR Training" is a failure, then set some channels to the disabled state and save the set channel status to the CMOS, and trigger the PC to restart. The solution of this application can selectively disable channels according to the result of DDR Training during PC startup. By disabling some faulty channels, DDR initialization is completed, enabling the PC to boot normally. This application exemplarily provides the following three methods:

[0166] Method 1: Disable the four channels corresponding to one controller at a time, and traverse each controller.

[0167] Exemplarily, taking two controllers Mc0 and Mc1 as an example, in the DDR initialization Training mechanism when the electronic device starts up, the electronic device detects the DDR Training result. If the DDR Training result is a failure, it means that there may be abnormalities in the Training of some DDR channels. In this case, all channels of the controller Mc0 are first disabled, then the electronic device is triggered to restart, and then the non-disabled channels (all channels of the controller Mc1) are trained. If the DDR Training is successful, it can normally enter the next stage to boot the system. If the DDR Training still fails, the disabled channels (all channels of the controller Mc0) are restored and enabled, and all channels of the controller Mc1 are disabled, then the electronic device is triggered to restart, and the non-disabled channels (all channels of the controller Mc1) are trained.

[0168] 1) Retry count n: For 2 controllers, 1 ≤ n ≤ 2.

[0169] 2) DDR storage capacity after restart: Assume the total DDR storage capacity is 16G, and the DDR storage capacity corresponding to 4 channels is 8G. Disabling 4 channels at a time means disabling a DDR storage capacity of 8G. Therefore, the DDR storage capacity after restart is 8G.

[0170] Considering the actual boot efficiency, all channels of one controller are disabled each time, and each controller is traversed for a boot retry. The advantage of this method is fewer retry times and faster boot speed. Method 1 will be described in detail through the first embodiment below.

[0171] Method 2: Disable 1 channel at a time and traverse each channel.

[0172] Exemplarily, taking a total of eight channels as an example, in the DDR initialization Training mechanism when the electronic device starts up, the electronic device detects the DDR Training result. If the DDR Training result is a failure, it means that there may be abnormalities in the Training of some DDR channels; in this case, one of the eight channels is disabled, then the electronic device is triggered to restart, and then the other seven non-disabled channels are trained. If the DDR Training is successful, it can normally enter the next stage to boot the system. If the DDR Training still fails, the disabled channel is restored and enabled, and one of the other seven channels is disabled, then the electronic device is triggered to restart, and the non-disabled channels are trained; in this way, 1 channel is disabled at a time and each channel is traversed.

[0173] 1) Number of retries n: For 8 channels, 1 ≤ n ≤ 8.

[0174] 2) DDR storage capacity after restart: Assume the total DDR storage capacity is 16G, and the DDR storage capacity corresponding to each channel is 2G. Disabling 1 channel at a time means disabling a DDR storage capacity of 2G. Therefore, correspondingly, the DDR storage capacity after the first successful cold restart is 14G.

[0175] Each time a DDR channel is disabled, power-on retries are performed for each channel of each controller. Since the number of retries is relatively large in this way, the power-on time is relatively long. The advantage is that the available memory capacity is relatively large compared to Method 1. Method 2 will be described in detail in the second embodiment below.

[0176] In some embodiments, it is also possible to enable one channel at a time and traverse each channel. Exemplarily, taking a total of eight channels as an example, in the DDR initialization Training mechanism when the electronic device starts up, the electronic device detects the DDR Training result. If the DDR Training result is a failure, it means that there may be an abnormality in the Training of some DDR channels; in this case, one of the eight channels is enabled and the other seven channels are disabled, then the electronic device is triggered to restart, and then Training is performed on the enabled channel. If the DDR Training is successful, it can normally enter the next stage to boot the system. If the DDR Training still fails, the enabled channel is disabled, and one of the other seven channels is enabled, then the electronic device is triggered to restart, and Training is performed on the enabled channel; in this way, one channel is enabled at a time and each channel is traversed. The advantage of this method is that the number of retries is relatively small, and the disadvantage is that the available memory capacity is relatively small.

[0177] Method 3: Disable 1 or more channels at a time and traverse all 8-channel state combinations.

[0178] The state of each channel includes an enabled state and a disabled state. All combined states of 8 channels are 2 8 = 256.

[0179] 1) Number of retries n: For 8 channels, 1 ≤ n ≤ 255.

[0180] 2) DDR storage capacity after restart: Assume the total DDR storage capacity is 16G, and the DDR storage capacity corresponding to each channel is 2G. Disabling 1 channel at a time means disabling a DDR storage capacity of 2G. Therefore, correspondingly, the DDR storage capacity after the first successful cold restart is 14G.

[0181] Among them, for an operating system with specific startup memory requirements, the number of DDR channels disabled by the electronic device each time is less than or equal to a preset number threshold. For different startup memory requirements, the preset number threshold is different.

[0182] For an operating system that requires less startup memory, the number of DDR channels disabled by the electronic device each time is less than or equal to the first preset number threshold, so as to ensure that the DDR can provide enough memory for the operating system to complete startup. For an operating system that requires more startup memory, the number of DDR channels disabled by the electronic device each time is less than or equal to the second preset number threshold, so as to ensure that the DDR can provide enough memory for the operating system to complete startup.

[0183] Among them, the second preset number threshold is less than the first preset number threshold.

[0184] For example, assume that the electronic device includes 8 DDR channels, and each DDR channel provides 2G of memory. For an operating system that requires more startup memory (for example, requires at least 6G of startup memory), the number of DDR channels disabled by the electronic device each time is less than or equal to 5, so as to ensure that at least 3 DDR channels are in the startup state, thereby ensuring that the DDR can provide at least 6G of memory for the operating system to complete startup.

[0185] The number of retries in Method 3 is more than that in Method 2, so the boot time is longer. The advantage is that it can find out the situation where channels of both controllers are damaged. Method 3 will be described in detail in the following third embodiment.

[0186] In some embodiments, when the electronic device detects that a DDR Training exception occurs, it can determine a suitable DDR status control method according to the startup speed requirement, startup memory requirement, and / or startup success rate requirement, and perform DDR Training retry. In actual use, according to different usage requirements, one of the above three methods or a combination of at least two methods can be selected.

[0187] For example, in some embodiments, when the electronic device detects that a DDR Training exception occurs, the electronic device can determine a suitable DDR status control method according to the startup speed requirement and perform DDR Training retry. For example, if the startup speed requirement is high, Method 1 can be selected for DDR Training retry. If the startup speed requirement is low, the electronic device can select Method 2 for DDR Training retry.

[0188] For example, in some other embodiments, when the electronic device detects that a DDR Training exception has occurred, it can determine an appropriate DDR status control method according to the startup memory requirements and perform a DDR Training retry. For example, if the startup memory requirement is high, Method 2 can be selected for the DDR Training retry. If the startup memory requirement is low, the electronic device can select Method 1 for the DDR Training retry.

[0189] For example, in some other embodiments, when the electronic device detects that a DDR Training exception has occurred, it can determine an appropriate DDR status control method according to the startup success rate requirements and perform a DDR Training retry. For example, if the startup success rate requirement is high, the electronic device can select Method 3 for the DDR Training retry.

[0190] The following introduces the method for handling abnormal device startup provided by the embodiments of the present application in combination with specific embodiments.

[0191] First Embodiment

[0192] In the first embodiment, when the electronic device detects that a DDR Training exception has occurred, the electronic device can disable all channels of one controller at a time, perform DDR Training on the non-disabled channels after a cold restart. If the DDR Training fails, then the electronic device enables the disabled channels and disables all channels of another controller, and performs DDR Training on the non-disabled channels after a cold restart; in this way, each controller is traversed.

[0193] Reference Figure 7 As shown, it is assumed that the electronic device includes a first controller Mc0 and a second controller Mc1, and each controller controls 4 DDR channels. The electronic device can disable 4 channels of one controller at a time.

[0194] Table 2

[0195]

[0196] Combined with Table 2, as shown in (a) of Figure 7 , when the electronic device detects that a DDR Training exception has occurred, the electronic device first disables all channels corresponding to the first controller Mc0 and performs DDR Training after a cold restart; in the case of training failure, as shown in (b) of Figure 7 , all channels corresponding to the first controller Mc0 are restored and enabled, and all channels corresponding to the second controller Mc1 are disabled, and DDR Training is performed after a cold restart.

[0197] Figure 8 It is a schematic flowchart of a method for handling abnormal device startup provided by the first embodiment of this application. Refer to Figure 8 As shown, this method includes the following steps S201 - S212.

[0198] S201. After the electronic device starts, it enters the first stage of BIOS boot startup, and the electronic device detects DDR Training abnormality.

[0199] Among them, DDR Training refers to the initialization of DDR after entering the BIOS boot startup. DDR Training abnormality means the failure of DDR initialization.

[0200] For example, assume that the DDR includes 8 channels. After entering the BIOS boot startup, the 8 channels are initialized. Since at least one of the 8 channels fails, the DDR initialization fails. In this case, the electronic device detects DDR Training abnormality.

[0201] Among them, the early stage (the first stage) of BIOS boot startup can include CPU initialization, chip initialization, and memory initialization. Memory initialization includes DDR parameter initialization and Training of the DDR channels.

[0202] DDR Training refers to the process of calibrating and adjusting the memory subsystem during the DDR interface initialization stage to ensure the stability and performance of data transmission. The main goal of DDR Training is to solve data transmission problems that may be caused by factors such as signal integrity, timing issues, and noise.

[0203] After DDR Training passes or succeeds, the electronic device continues to execute the next stage of BIOS boot startup, such as motherboard initialization, loading, and running the operating system. Exemplarily, the operating system applied by the electronic device can be the Windows system.

[0204] S202. The electronic device sets all channels corresponding to the first controller to the disabled state.

[0205] In order to solve the problem that the electronic device cannot start up due to DDR Training abnormality, the electronic device randomly selects the first controller, disables all channels corresponding to the first controller, then performs a cold restart, and then conducts DDR Training.

[0206] In the embodiment of this application, the electronic device can modify the DDR channel status information to a first preset value, and this first preset value is defined to represent that all channels corresponding to the first controller are in the disabled state.

[0207] In the embodiments of the present application, the DDR channel status information can be stored in a CMOS or other memory.

[0208] Exemplarily, the first preset value can be defined as 0x0F. When the DDR channel status information is set to 0x0F, it means that all channels corresponding to the first controller are set to the disabled state.

[0209] S203. The electronic device performs a cold restart and conducts Training on all DDR channels corresponding to the second controller.

[0210] Among them, once a cold start occurs, the hardware is redetected, system boot data is obtained from the CMOS, and then the operating system is started based on the system boot data.

[0211] Among them, the Training of the DDR channels can be abbreviated as DDR Training.

[0212] After the cold restart of the electronic device, the electronic device can obtain the DDR channel status information from the CMOS. The electronic device can determine that all channels corresponding to the first controller in the DDR have been disabled and all channels corresponding to the second controller have not been disabled according to the DDR channel status information. Accordingly, the electronic device conducts Training on all channels corresponding to the second controller in the DDR.

[0213] S204. The electronic device determines whether the Training is successful.

[0214] S205 - S206. In the case where the Training is successful (corresponding to "yes" in S204), the electronic device enters the second stage of BIOS boot to power on the electronic device normally. The electronic device prompts, through the computer management application, that at least one channel corresponding to the first controller has a fault.

[0215] Among them, the second stage of BIOS boot can include motherboard initialization, and loading and running the operating system. When the operating system is loaded and runs normally, the electronic device will power on normally.

[0216] After the electronic device is powered on, it automatically starts the computer management application, displays the user interface of the computer management application, and presents the first information through the user interface to prompt that there is a fault in the DDR channel.

[0217] In the embodiment of the present application, all channels corresponding to the first controller are disabled, and all channels corresponding to the second controller are not disabled. Then, the electronic device is cold restarted, and all channels corresponding to the second controller are trained. If the training is successful, the electronic device can determine that none of the channels corresponding to the second controller are damaged, while at least one channel corresponding to the first controller may be damaged. The electronic device displays a fault prompt message on the user interaction interface to prompt the user that a DDR channel has a fault.

[0218] Through the solution of the present application, not only can the electronic device be guided to boot up normally when DDR training is abnormal, but also it can find out which channels in the DDR may be damaged and prompt the user to send it for repair in time or perform data backup, thereby improving the user experience.

[0219] S207 - S208. When the training of all channels corresponding to the second controller fails (corresponding to "no" in S204), the electronic device restores all channels corresponding to the first controller to the enabled state, and sets all channels corresponding to the second controller to the disabled state. The electronic device is cold restarted, and all channels corresponding to the first controller are trained.

[0220] In the embodiment of the present application, the electronic device can modify the DDR channel status information in the CMOS settings. Exemplarily, when the DDR channel status information is set to 0xF0, it means that all channels corresponding to the first controller are restored to the enabled state, and all channels of the second controller are set to the disabled state.

[0221] S209. The electronic device determines whether the training of all channels corresponding to the first controller is successful.

[0222] S210 - S211. When the training of all channels corresponding to the first controller is successful (corresponding to "yes" in S209), the electronic device enters the second stage of BIOS boot to enable the electronic device to boot up normally. The electronic device prompts through the computer management application that at least one channel corresponding to the second controller has a fault.

[0223] After the electronic device is powered on, it automatically starts the computer management application, displays the user interaction interface of the computer management application, and presents the second information through this user interaction interface to prompt that at least one channel corresponding to the second controller has a fault.

[0224] In an embodiment of the present application, the electronic device disables all channels of the second controller, then performs a cold restart on the electronic device, and then performs Training on all channels corresponding to the first controller. If the Training is successful, then the electronic device can determine that none of the channels corresponding to the first controller are damaged, while at least one channel corresponding to the second controller may be damaged. The electronic device displays a fault prompt message on the user interaction interface to prompt the user that a DDR channel has failed. In this way, not only can the electronic device be guided to boot normally when DDR Training is abnormal, but also it can be found out which channels in the DDR may be damaged and prompt the user to send it for repair in time or perform data backup, thereby enhancing the user experience.

[0225] S212. In the case of Training failure (corresponding to "no" in S209), the electronic device fails to boot and determines that at least one channel corresponding to the first controller and at least one channel corresponding to the second controller are faulty.

[0226] In an embodiment of the present application, after the electronic device disables all channels of the first controller and then performs a cold restart, it performs Training on all channels of the second controller; in the case of Training failure for all channels of the second controller, the electronic device disables all channels corresponding to the second controller, restores the enabling of all channels corresponding to the first controller, and then after a cold restart, the electronic device performs Training on all channels corresponding to the first controller.

[0227] If the Training for the channels corresponding to the first controller is successful, then the electronic device can determine that none of the channels corresponding to the first controller are damaged, and at least one channel corresponding to the second controller may be damaged. Accordingly, the electronic device can display a fault prompt message on the user interaction interface, that is, prompt the user that the second controller has failed or at least one channel corresponding to the second controller has failed.

[0228] Through the solution of the present application, when DDR Training is abnormal during the BIOS-guided boot after the electronic device starts up, the electronic device can disable all channels corresponding to one controller at a time, and perform DDR Training based on the non-disabled channels after a cold start, and perform traversal execution in this way to avoid the damaged channels during DDR Training, complete DDR initialization, and guide the electronic device to boot normally. Through the solution of the present application, not only can the electronic device be guided to boot normally by disabling a part of the DDR channels and then attempting DDR Training after a restart when DDR Training is abnormal, but also it can be found out which channels in the DDR may be damaged and prompt the user to send it for repair in time or perform data backup, thereby enhancing the user experience.

[0229] It should be noted that the above Figure 8 has described the DDR Training exception handling solution in the case where the electronic device includes two controllers. In actual implementation, the method provided by the embodiments of the present application can also be applied to electronic devices with more controllers. To better understand the solution of the present application, the DDR Training exception handling solution in the case where the electronic device includes four controllers will be briefly described below.

[0230] Exemplarily, the electronic device includes a first controller, a second controller, a third controller, and a fourth controller. Through the solution of the present application, when the electronic device detects that a DDR Training exception occurs, the electronic device disables the channel corresponding to the first controller, and performs DDR Training on the non-disabled channels (i.e., the channels corresponding to the second controller, the third controller, and the fourth controller respectively) after a cold restart. If the DDR Training fails, the channel corresponding to the second controller is disabled and the channel corresponding to the first controller is restored and enabled, and DDR Training is performed on the non-disabled channels (i.e., the channels corresponding to the first controller, the third controller, and the fourth controller respectively) after a cold restart. If the DDR Training still fails, the channel corresponding to the third controller is disabled and the channel corresponding to the second controller is restored and enabled, and DDR Training is performed on the non-disabled channels (i.e., the channels corresponding to the first controller, the second controller, and the fourth controller respectively) after a cold restart. If the DDR Training still fails, the channel corresponding to the fourth controller is disabled and the channel corresponding to the third controller is restored and enabled, and DDR Training is performed on the non-disabled channels (i.e., the channels corresponding to the first controller, the second controller, and the third controller respectively) after a cold restart. It can be understood that the granularity or unit of each disablement is one controller.

[0231] Through the solution of the present application, in the case where a DDR Training exception occurs when the BIOS boots the electronic device after startup, the electronic device can disable the DDR channel corresponding to one controller at a time, perform DDR Training based on the non-disabled channels after a cold start, and in the case of Training failure, restore and enable the disabled channel, disable the DDR channel corresponding to another controller, then perform a cold restart and perform DDR Training on the non-disabled channels; perform traversal execution on each controller in this way, avoid the damaged channels during DDR Training, complete DDR initialization, and boot the electronic device to start up normally.

[0232] It should be noted that in the above first embodiment, the DDR Training exception handling solutions in the cases where the electronic device includes two, four, or more controllers are described. For the case of four or more controllers, the DDR Training exception handling solution can specifically refer to the DDR Training exception handling solution in the case of two controllers above, which will not be elaborated here.

[0233] Next, refer to Figure 9 , and the logical functions of the method for handling device startup exceptions provided in the first embodiment of the present application will be described from the BIOS side. On the BIOS side, referring to S31 to S37, the PC startup process includes security verification, EFI pre-initialization, driver execution environment, selecting a startup device, loading the operating system, running the operating system, and powering on. Among them, the EFI pre-initialization (S32) includes S321 to S324, that is, CPU initialization, chip initialization, memory initialization, and motherboard initialization, etc.

[0234] In the embodiment of the present application, the memory initialization stage (S323) may include S3231 to S3242.

[0235] First DDR Training:

[0236] S3231 and S3232, obtain DDR parameters and perform DDR parameter initialization.

[0237] Among them, the DDR parameters include DDR channel status information.

[0238] During DDR initialization, the parameter acquisition module is responsible for reading the DDR channel status information saved in the CMOS. The initial DDR channel status information by default indicates that all DDR channels are in the open state. Then, the parameter initialization module is responsible for passing the DDR channel status information to the DDR Training module to trigger the start of the first DDR Training.

[0239] S3233 and S3234, perform DDR Training and judge the Training result.

[0240] During the first DDR Training, all DDR channels are in the open state. In this case, all DDR channels are initialized.

[0241] In the case of successful Training, enter the subsequent stage of the PC startup process.

[0242] In the case of failed Training, the present application continues with Training retries. For details, see the following steps.

[0243] S3235 and S3236, in the case of Training failure, accumulate the number of failures and save the accumulated number of failures (such as 1) to the CMOS.

[0244] S3236, in the case of Training failure, obtain the DDR channel status information, which is used to indicate the status of each channel.

[0245] S3237 and S3238, in the case where the DDR channel status information is not 0xF0, modify the DDR channel status information to 0xF0. The modified DDR channel status information 0xF0 indicates that all channels corresponding to Mc0 are in the disabled state and all channels corresponding to Mc1 are in the enabled state, and store the modified DDR channel status information in the CMOS.

[0246] S3239, trigger a cold start, then return to execute S31 and S32 to re - execute DDR Training.

[0247] Specifically, after the cold start, the PC performs a security check and pre - initializes EFI. When pre - initializing EFI, CPU initialization, chip initialization, and memory initialization are performed. When initializing the memory, DDR Training is re - executed, that is, the second DDR Training.

[0248] The second DDR Training:

[0249] S3231 and S3232, obtain DDR parameters and perform DDR parameter initialization.

[0250] Among them, the DDR parameters include the latest DDR channel status information. This DDR channel status information is used to indicate that all channels corresponding to Mc0 are in the disabled state and all channels corresponding to Mc1 are in the enabled state.

[0251] During DDR initialization, the parameter acquisition module is responsible for reading the DDR channel status information saved in the CMOS. Then, the parameter initialization module is responsible for passing the DDR channel status information to the DDR Training module to trigger the start of the second DDR Training.

[0252] S3233 and S3234, execute DDR Training and judge the Training result.

[0253] During the second DDR Training, all channels corresponding to Mc0 are in the disabled state and all channels corresponding to Mc1 are in the enabled state. In this case, initialize all channels corresponding to Mc1.

[0254] In the case of successful Training, enter the subsequent stage of the PC boot process.

[0255] In the case of failed Training, the present application can retry Training again. For details, see the following steps.

[0256] S3235 and S3236: In the case of failed Training, accumulate the number of failed attempts and update the accumulated number of failed attempts in the CMOS (such as updating to 2).

[0257] S3236: In the case of failed Training, obtain the DDR channel status information.

[0258] S3237, S3240 and S3241: In the case that the DDR channel status information is 0xF0 and not 0x0F, modify the DDR channel status information to 0x0F. The modified DDR channel status information 0x0F indicates that all channels of Mc0 are enabled and all channels of Mc1 are disabled. Store the modified DDR channel status information in the CMOS.

[0259] S3239: Trigger a cold start, then return to execute S31 and S32 to re - execute DDR Training.

[0260] Specifically, after the cold start, perform a PC security check and EFI pre - initialization. When performing EFI pre - initialization, perform CPU initialization, chip initialization, and memory initialization. When performing memory initialization, re - execute DDR Training, that is, the third DDR initialization.

[0261] The third DDR Training:

[0262] S3231 and S3232: Obtain DDR parameters and perform DDR parameter initialization.

[0263] Among them, the DDR parameters include the latest DDR channel status information. This DDR channel status information is used to indicate that all channels corresponding to Mc0 are in the startup state and all channels corresponding to Mc1 are in the disabled state.

[0264] During DDR initialization, the parameter acquisition module is responsible for reading the DDR channel status information saved in the CMOS. Then, the parameter initialization module is responsible for passing the DDR channel status information to the DDR Training module to trigger the start of the third DDR Training.

[0265] S3233 and S3234: Execute DDR Training and judge the Training result.

[0266] During the third DDR Training, all channels corresponding to Mc0 are in the enabled state, and all channels corresponding to Mc1 are in the disabled state. In this case, all channels corresponding to Mc0 are initialized.

[0267] In the case of successful Training, the subsequent stage of the PC boot process is entered.

[0268] In the case of failed Training, the electronic device fails to boot.

[0269] As described above, when performing memory initialization and DDR Training anomalies, the DDR channel status information can be modified and DDR Training can be retried to attempt a normal boot of the PC.

[0270] In some embodiments, the electronic device can use different numbers or symbols to represent the DDR channel status information. Exemplarily, referring to Table 3, 0x00 can represent all channels of controller Mc0 and controller Mc1 being fully open, 0xF0 can represent all channels of controller Mc1 being disabled, and 0x0F can represent all channels of controller Mc0 being disabled.

[0271] In some embodiments, the electronic device can use the 0x4E position in the CMOS to save the DDR channel status information.

[0272] It should be noted that in actual implementation, other positions in the CMOS can also be used to save the DDR channel status information, and other forms can also be used to represent the DDR channel status information, which can be specifically determined according to actual usage requirements, and the embodiments of the present application are not limited.

[0273] In the embodiments of the present application, the CMOS is a storage chip on the PC motherboard that supports reading and writing. The present application solution uses an address bit (0x4E) of the CMOS to save the DDR channel status information. Taking 8 channels of 2 controllers as an example, referring to Table 3, a bit value of 1 indicates that the channel is in the disabled state; a bit value of 0 indicates that the channel is in the enabled state.

[0274] Table 3

[0275] Bit position 7 6 5 4 3 2 1 0 Value 1 or 0 1 or 0 1 or 0 1 or 0 1 or 0 1 or 0 1 or 0 1 or 0 Define Mc1Ch3 Mc1Ch2 Mc1Ch1 Mc1Ch0 Mc0Ch3 Mc0Ch2 Mc0Ch1 Mc0Ch0

[0276] Assume that all channels of Mc1 are in the disabled state and all channels of Mc0 are in the enabled state. Then the final binary value at the 0x4E position is 11110000, which is converted to hexadecimal as 0xF0.

[0277] Assume that all channels of Mc1 are enabled and all channels of Mc0 are disabled. Then the final binary value at the 0x4E position is 00001111, which is converted to hexadecimal as 0x0F.

[0278] Assume that all channels of Mc1 are enabled and all channels of Mc0 are enabled. Then the final binary value at the 0x4E position is 00000000, which is converted to hexadecimal as 0x00.

[0279] Table 4

[0280]

[0281] Referring to Table 4, at the 0x4E position in the CMOS, 0x00 is initially stored by default, indicating that all channels of the controllers Mc0 and Mc1 are fully open. After disabling all channels of the controller Mc0, the channel status information at the 0x4E position in the CMOS is updated from 0x00 to 0x0F. After disabling all channels of the controller Mc1, the channel status information at the 0x4E position in the CMOS is updated from 0x0F to 0xF0.

[0282] In the first embodiment of the present application, the electronic device can accumulate the number of DDR Training failures. Referring to Table 4, if the result of DDR Training is a failure, the number of failures is saved at the 0x4F position in the CMOS. Each time there is a failure, 1 is added to the number of failures. The electronic device can judge the DDR damage frequency or severity based on the accumulated number of failures.

[0283] Figure 9 It not only shows the logical functions of the first embodiment on the BIOS side but also shows the upper-layer processing of the first embodiment of the present application on the Windows side. In the embodiment of the present application, the upper-layer application can be a computer manager. The computer manager reads the value at the 0x4E position in the CMOS. If the value at the 0x4E position is not 0x00, the computer manager determines that some channels of the DDR have been disabled. In this case, the computer manager performs a pop-up window process to remind the user through the pop-up window that the DDR is damaged and needs to send the DDR for repair or back up the data.

[0284] Here will Figure 9 The PC boot process shown Figure 3 be compared and described with the

[0285] In Figure 3During the PC startup process shown, after the Training results of all channels (e.g., 8 channels) are passed or successful, the system will enter the next stage to execute the subsequent startup process. If the Training result of any one of the 8 channels is failed, the system will be stuck at this stage, that is, the system will have an exception and the startup process will end. On the Windows side, it is manifested as a black screen and the system fails to boot.

[0286] During Figure 9 During the PC startup process shown, when DDR Training fails during BIOS boot after the electronic device is started, the electronic device can disable all DDR channels corresponding to one controller at a time. After restarting, DDR Training is performed based on the non-disabled channels. In the case of a failed Training, the disabled channels are restored and enabled, and the DDR channels corresponding to another controller are disabled, and then the device is cold restarted and DDR Training is performed on the non-disabled channels; this process is iteratively executed for each controller, avoiding the damaged channels during DDR Training, completing DDR initialization, booting the electronic device normally, and prompting the user that a DDR failure has occurred. Through this solution, not only can the electronic device be booted normally when DDR Training fails, but also it can find out which channels in the DDR may be damaged and prompt the user to send it for repair in time or perform data backup, thereby improving the user experience.

[0287] The above has described the logical functions of the first embodiment of the present application from the BIOS side and the upper-layer processing of the first embodiment of the present application from the Windows side. Next, in combination with Figure 10 the interaction timing diagram of each module of the PC in the method for handling abnormal device startup provided by the embodiment of the present application is described.

[0288] As Figure 10 shown, each module of the PC involved in the interaction timing diagram includes a power management module, a parameter acquisition module, a DDR Training module, a channel status setting module, and a computer manager. In addition, each module of the PC also includes a CMOS for storing DDR channel status information. For the sake of convenience of description, here an example is given where the PC includes two controllers Mc0 and Mc1, and each controller corresponds to multiple DDR channels.

[0289] S401. In response to the user's operation to trigger the PC startup, the power management module starts the PC startup process.

[0290] As described above, the PC boot process includes security verification, pre - EFI initialization, driver execution environment, selecting a boot device, loading the operating system, running the operating system, and system failure repair. After completing the security verification, the PC performs pre - EFI initialization.

[0291] S402. The power management module instructs the parameter acquisition module to perform pre - EFI initialization.

[0292] Among them, pre - EFI initialization includes: CPU initialization, chip initialization, memory initialization, and motherboard initialization, etc.

[0293] After completing CPU initialization and chip initialization, the PC performs memory initialization.

[0294] S403. The parameter acquisition module obtains DDR channel status information from the CMOS and obtains other relevant information for memory initialization, where the DDR channel status information by default indicates that the channels of all controllers are available.

[0295] Exemplarily, at the 0x4E position in the CMOS, 0x00 is initially stored by default, indicating that all channels of controllers Mc0 and Mc1 are fully open.

[0296] S404. The parameter acquisition module sends the DDR channel status information and other relevant information for memory initialization to the DDR Training module.

[0297] S405. The DDR Training module performs DDR Training on all channels of controllers Mc0 and Mc1 based on the DDR channel status information and other relevant information.

[0298] S406. The DDR Training module determines whether the DDR Training is successful.

[0299] S407. When the DDR Training module determines that the DDR Training is successful (i.e., the DDR Training passes), the PC boot process continues.

[0300] Among them, if the DDR Training is successful, it means that the memory initialization has been completed and the motherboard initialization can be continued.

[0301] It should be noted that in the embodiments of the present application, when the PC includes multiple controllers and each controller correspondingly controls multiple DDR channels, if the DDR Training fails, it may be caused by the damage of the DDR channels corresponding to one of the controllers, or it may be caused by the damage of the DDR channels corresponding to both controllers. Accordingly, in the present application, the DDR channels corresponding to one controller are disabled once, then cold restarted and the DDR Training is performed on the non-disabled channels. In the case of training failure, the disabled channels are restored and enabled, the DDR channels corresponding to another controller are disabled, then cold restarted and the DDR Training is performed on the non-disabled channels; this process is traversed and executed for each controller, avoiding the damaged channels during DDR Training, completing DDR initialization, and guiding the electronic device to boot up normally.

[0302] The following describes the process of traversing each controller among multiple controllers and performing memory initialization retry.

[0303] S408. When the DDR Training module determines that the DDR Training fails, the DDR Training module accumulates the failure count (Fail_Count), for example, Fail_Count = 1.

[0304] S409. When the DDR Training module determines that the DDR Training fails, the DDR Training module determines whether the DDR channel status information is 0x0F.

[0305] It should be noted that the present application does not limit the execution order of S408 and S409 described above.

[0306] S410. When the DDR channel status information is not 0x0F, the channel status setting module updates the DDR channel status information to 0x0F, where 0x0F indicates that all channels corresponding to the controller Mc0 are in the disabled state.

[0307] It should be noted that when the DDR channel status information is 0x0F, all channels corresponding to Mc0 are in the disabled state, and all channels corresponding to Mc1 are in the enabled state.

[0308] Exemplarily, the channel status information at the 0x4E position in the CMOS is updated to 0x0F, indicating that all channels of the controller Mc0 are disabled. That is to say, during the next DDR Training, the channels of other controllers except the controller Mc0 will be trained, while avoiding all channels of the controller Mc0, in an attempt to make the DDR Training successful after a cold start, and then the PC boots up normally.

[0309] S411. The channel status setting module updates the number of failures stored in the CMOS.

[0310] For example, the number of failures can be stored at the 0x4F position in the CMOS.

[0311] S412. The channel status setting module instructs the power management module to perform a cold restart.

[0312] S413. The power management module performs a cold restart.

[0313] S414. The power management module instructs the parameter acquisition module to perform pre-EFI initialization.

[0314] S415. The parameter acquisition module obtains the DDR channel status information from the CMOS and obtains other relevant information for memory initialization, where the DDR channel status information indicates that the channels of the controller Mc0 are disabled.

[0315] Exemplarily, 0x0F is stored at the 0x4E position in the CMOS, indicating that all channels of the controller Mc0 are disabled.

[0316] S416. The parameter acquisition module sends the DDR channel status information and other relevant information for memory initialization to the DDR Training module.

[0317] S417. The DDR Training module performs DDR Training on all channels of the controller Mc1 based on the DDR channel status information and other relevant information for memory initialization.

[0318] Since all channels of the controller Mc0 are disabled, during this DDR Training, the channels of the controller Mc1 will be trained to avoid all channels of the controller Mc0 during a cold start for DDR Training. If the DDR Training is successful, then the subsequent PC boot process continues. If the DDR Training fails, then all channels of the controller Mc0 are restored to the enabled state, and all channels of the controller Mc1 are disabled and DDR Training is performed while avoiding all channels of the controller Mc1 during a cold start.

[0319] The S418, DDR Training module determines whether the DDR Training is successful.

[0320] Among them, in the case where the DDR Training is successful, the PC startup process continues (see S407).

[0321] S419. After the PC is powered on, the computer manager displays the information: at least one DDR channel corresponding to the controller Mc0 is damaged.

[0322] The computer manager reads the value at the 0x4E position of the CMOS through the Get CMOS() method. The computer manager can view the value at the 0x4E position to determine whether the DDR is damaged.

[0323] In some embodiments, if the value at the 0x4E position is not 0x00 (0x00 is used to indicate that all channels corresponding to M controllers are enabled), the computer manager determines that some channels of the DDR have been disabled. In this case, the computer manager performs a pop-up window process, reminding the user through the pop-up window that the DDR is damaged and that the DDR needs to be sent for repair or data backup.

[0324] S420. In the case where the DDR Training fails, the DDR Training module accumulates the number of failures (Fail_Count), for example, Fail_Count = 2.

[0325] S421. In the case where the DDR Training fails, the DDR Training module determines whether the DDR channel status information is 0xF0.

[0326] It should be noted that the present application does not limit the execution order of the above S420 and S421.

[0327] S422. In the case where the DDR channel status information is not 0xF0, the channel status setting module updates the DDR channel status information to 0xF0, and 0xF0 indicates that all channels corresponding to Mc1 are in the disabled state.

[0328] It should be noted that when the DDR channel status information is 0xF0, all channels corresponding to Mc1 are in the disabled state, and all channels corresponding to Mc0 are in the enabled state.

[0329] Exemplarily, the channel status information at the 0x4E position in the CMOS is updated to 0xF0, indicating that all channels of the controller Mc1 are disabled. That is to say, during the next DDR Training, the channels of other controllers except the controller Mc1 will be subjected to DDR Training to attempt to avoid all channels of the controller Mc1 during DDR Training after a cold start.

[0330] S423. The channel status setting module updates the number of failure times stored in the CMOS.

[0331] S424. The channel status setting module instructs the power management module to perform a cold restart.

[0332] S425. The power management module performs a cold restart.

[0333] S426. The power management module instructs the parameter acquisition module to perform pre-EFI initialization.

[0334] S427. The parameter acquisition module obtains the DDR channel status information from the CMOS and obtains other relevant information for memory initialization, where the DDR channel status information indicates that the channels of the controller Mc1 are disabled.

[0335] Exemplarily, 0xF0 is stored at the 0x4E position in the CMOS, indicating that all channels of the controller Mc1 are disabled.

[0336] S428. The parameter acquisition module sends the DDR channel status information and other relevant information for memory initialization to the DDR Training module.

[0337] S429. The DDR Training module performs DDR Training on all channels of the controller Mc0 based on the DDR channel status information and other relevant information for memory initialization.

[0338] S430. The DDR Training module determines whether the DDR Training is successful.

[0339] Among them, in the case of successful DDR Training, the PC boot process continues (see S407).

[0340] S431. After the PC is powered on, the computer manager displays the information: At least one DDR channel corresponding to the controller Mc1 is damaged.

[0341] In some embodiments, if the value at the 0x4E position is not 0x00, the computer manager determines that some channels of the DDR have been disabled. In this case, the computer manager performs a pop-up window process to remind the user through the pop-up window that the DDR is damaged and that the DDR needs to be sent for repair or the data needs to be backed up.

[0342] In other embodiments, if the value at the 0x4E position is 0xF0, the computer manager determines that all channels of the controller Mc1 have been disabled. In this case, the computer manager performs a pop-up window process to remind the user through the pop-up window that at least one DDR channel corresponding to the controller Mc1 is damaged and that the DDR needs to be sent for repair or the data needs to be backed up.

[0343] S432. When DDR Training fails, the computer manager determines that at least one DDR channel of each of the controllers Mc1 and Mc0 is damaged.

[0344] In the first embodiment described above, it is illustrated that one DDR channel corresponding to one controller is disabled each time, then a cold restart is performed, and then DDR Training is performed on the non-disabled channels. By this method, an attempt is made to succeed in Training, the memory initialization is completed, and then the subsequent steps in the PC boot process are continued.

[0345] Second Embodiment

[0346] In the second embodiment of the present application, in the case where the PC includes multiple controllers and each controller controls multiple DDR channels, if DDR Training fails, it may be due to a damage to a certain DDR channel corresponding to one of the controllers that causes the DDR Training to fail. Accordingly, in the present application, one DDR channel is disabled each time, then a cold restart is performed, and then DDR Training is performed on the non-disabled channels. When Training fails, the disabled channel is restored and enabled, another DDR channel is disabled, and then a cold restart is performed and DDR Training is performed on the non-disabled channels; this process is executed for each channel in this way, avoiding the damaged channels during DDR Training, completing the DDR initialization, and guiding the electronic device to boot up normally.

[0347] It should be noted that the method for handling abnormal device startup provided in the second embodiment of the present application is applied to an electronic device. The electronic device includes a DDR and at least one controller. The DDR is divided into multiple channels, and each controller is used to control one or more channels of the DDR, and different controllers control different channels.

[0348] The following introduces the method for handling abnormal device startup provided in the embodiments of the present application in combination with specific embodiments.

[0349] In the second embodiment of the present application, when the electronic device detects that DDR Training fails, the electronic device can disable one channel of one controller at a time, and perform DDR Training on the non-disabled channels after a cold restart.

[0350] Assume that the electronic device includes a first controller Mc0 and a second controller Mc1, and each controller controls 4 DDR channels.

[0351] Table 5

[0352] Serial number Disable one channel at a time 1 Disable channel Ch0 of the first controller Mc0, i.e., Mc0Ch0 2 Disable channel Ch1 of the first controller Mc0, i.e., Mc0Ch1 3 Disable channel Ch2 of the first controller Mc0, i.e., Mc0Ch2 4 Disable channel Ch3 of the first controller Mc0, i.e., Mc0Ch3 5 Disable channel Ch0 of the second controller Mc1, i.e., Mc1Ch0 6 Disable channel Ch1 of the second controller Mc1, i.e., Mc1Ch1 7 Disable channel Ch2 of the second controller Mc1, i.e., Mc1Ch2 8 Disable channel Ch3 of the second controller Mc1, i.e., Mc1Ch3

[0353] Combined with Table 5, referring to Figure 11 in (a) and (b), when the electronic device detects that DDR Training fails, the electronic device first disables Mc0Ch0, and performs DDR Training on the non-disabled channels after a cold restart; if the Training fails, then disable Mc0Ch1 and resume enabling Mc0Ch0, and continue to perform DDR Training on the non-disabled channels after a cold restart; in this way, disable one channel at a time, and perform DDR Training on the non-disabled channels after a cold restart, and try multiple times in this way.

[0354] It should be noted that, compared with the first embodiment where the granularity of each disable is 1 controller, the granularity of each disable in the second embodiment is 1 channel, that is, the granularity of a single disable becomes smaller. Since the total number of restarts in the second embodiment becomes more, the boot time will be sacrificed. The advantage of the second embodiment is that the available storage capacity can be increased.

[0355] For example, assume that a 16G DDR PC product has one damaged channel. In order for the PC to boot normally, the method provided by the first embodiment of the present application can be used to disable 4 channels at a time, and perform at most two cold restarts. Since the DDR storage capacity disabled each time is 8G, the DDR storage capacity after restart is 8G. If the method provided by the second embodiment of the present application is used, then disable 1 channel at a time, and there will be at most 8 cold restarts. The DDR storage capacity disabled each time is 2G. Correspondingly, the DDR storage capacity after the first successful cold restart is 14G, and the DDR storage capacity after the second successful cold restart is 12G, and so on.

[0356] The implementation process of the method provided by the second embodiment of the present application will be briefly described below with reference to the accompanying drawings.

[0357] Figure 12 is a schematic flowchart of a method for processing abnormal device startup provided by the second embodiment of the present application. Referring to Figure 12 shown, the method includes the following steps S501 - S516.

[0358] In the embodiment of the present application, the electronic device can disable one channel each time and perform DDR Training after a cold restart. For example, the electronic device first disables one channel and performs DDR Training on the non-disabled channels after a cold restart; if the Training fails, then the disabled channel is restored and enabled, while another channel is disabled, and DDR Training is continued on the non-disabled channels after a cold restart; this way is tried multiple times.

[0359] S501. After the electronic device is started, it enters the first stage of BIOS boot-up and detects an abnormal DDR Training.

[0360] S502 - S503. The electronic device sets the i-th channel corresponding to the first controller to the disabled state. The electronic device performs a cold restart and performs Training on the channels other than the disabled channel. The initial value of i is 1.

[0361] S504. The electronic device determines whether the Training is successful.

[0362] S505 - S506. In the case where the Training is successful (corresponding to "yes" in S504), the electronic device enters the second stage of BIOS boot-up so that the electronic device can be normally powered on. The electronic device prompts through the computer management application that a certain channel corresponding to the first controller has a fault.

[0363] Among them, the first stage of BIOS boot-up includes CPU initialization, chip initialization, and memory initialization, where the memory initialization includes DDR parameter initialization and Training on the channels of DDR;

[0364] The second stage of the BIOS boot-up includes motherboard initialization, driver execution environment, selection of a boot device, and loading and running of the operating system.

[0365] S507 - S508. In the case where the Training fails (corresponding to "no" in S504), the electronic device determines whether i is greater than 4, that is, whether all channels of the first controller have been traversed. In the case where i is less than or equal to 4, the electronic device sets i = i + 1 and continues to traverse another channel of the first controller.

[0366] The above describes the process of traversing all channels of the first controller. The process of traversing all channels of the second controller will be described below.

[0367] S509 - S510. When i is greater than 4, the electronic device restores the channels corresponding to the first controller to the enabled state, and sets the j-th channel corresponding to the second controller to the disabled state. The electronic device performs a cold restart and conducts Training on all channels corresponding to the first controller. The initial value of j is 1.

[0368] S511. The electronic device determines whether the Training is successful.

[0369] S512 - S513. When the Training is successful (corresponding to "yes" in S511), the electronic device enters the second stage of BIOS boot to enable the electronic device to boot normally. The electronic device uses the computer management application to prompt that a channel corresponding to the second controller has a fault.

[0370] S514 - S515. When the Training fails (corresponding to "no" in S511), the electronic device determines whether j is greater than 4, that is, whether all channels of the second controller have been traversed. When j is less than or equal to 4 (corresponding to "no" in S514), the electronic device sets j = j + 1 and continues to traverse another channel of the second controller.

[0371] S517. When j is greater than 4 (corresponding to "yes" in S514), the electronic device fails to boot and determines that all DDR channels have faults.

[0372] It can be understood that after the electronic device detects that the DDR channels may be damaged, the electronic device can display the DDR channel damage information through logs, pop - up windows, etc., and prompt the user to send the DDR for repair in time or perform data backup, thereby improving the user experience.

[0373] Through the solution of this application, when a DDR Training exception occurs during BIOS boot after the electronic device is started, the electronic device can disable one channel at a time and perform DDR Training based on the non - disabled channels after a cold start. Specifically, the electronic device first disables one channel, and performs DDR Training on the non - disabled channels after a cold restart; if the Training fails, then the disabled channel is restored to the enabled state, another channel is disabled, and DDR Training is performed on the non - disabled channels after a cold restart; retry in this way multiple times; when the Training is successful, the electronic device is booted normally, and the user can be prompted that the DDR has a fault after booting.

[0374] It should be noted that in the above second embodiment, through Figure 12The DDR Training exception handling solution in the case where the electronic device includes two controllers is described. It can be understood that in actual implementation, the electronic device may also include four or more controllers, or each controller may control fewer or more channels. For the DDR Training exception handling solution in this case, reference can be made to the above DDR Training exception handling solution, which will not be elaborated here.

[0375] Next, refer to Figure 13 , and from the BIOS side, the logical function of the device startup exception handling method provided in the second embodiment of the present application will be described.

[0376] At the beginning of the DDR initialization phase, the parameter acquisition module is responsible for reading the DDR channel status information saved in the CMOS and determining the DDR channels to be trained based on the read DDR channel status information. Exemplarily, as described above, the present application uses the 0x4E position in the CMOS to save the DDR channel status information.

[0377] In some embodiments, the electronic device may use different numbers or symbols to represent the DDR channel status information. Exemplarily, as shown in Table 6 below, 0x00 means that all channels of controller Mc0 and controller Mc1 are open, 0x01 means that channel Ch0 of controller Mc0 is disabled, 0x02 means that channel Ch1 of controller Mc0 is disabled, and so on. It should be noted that in actual implementation, other methods may also be used to represent the DDR channel status information, which can be specifically determined according to actual usage requirements, and the embodiments of the present application do not make limitations.

[0378] Table 6

[0379]

[0380]

[0381] Referring to Table 6, at the 0x4E position in the CMOS, 0x00 is initially stored by default, indicating that all channels of controllers Mc0 and Mc1 are open. When the channel status information at the 0x4E position in the CMOS is updated to 0x01, it means that channel Ch0 of controller Mc0 is in the disabled state. When the channel status information at the 0x4E position in the CMOS is updated to 0x02, it means that channel Ch1 of controller Mc0 is in the disabled state; and so on. When the channel status information at the 0x4E position in the CMOS is updated to 0x05, it means that channel Ch0 of controller Mc1 is in the disabled state; when the channel status information at the 0x4E position in the CMOS is updated to 0x06, it means that channel Ch1 of controller Mc1 is in the disabled state; and so on.

[0382] In the second embodiment of the present application, the electronic device can accumulate the number of DDR Training failures. Referring to Table 6, if the result of DDR Training is a failure, the number of failures (denoted as Fail_Count) is saved at the 0x4F position of the CMOS. Each time there is a failure, the number of failures is incremented by 1, i.e., Fail_Count = Fail_Count + 1.

[0383] The parameter initialization module is responsible for passing the current DDR channel status information to the DDR Training mechanism to trigger the start of DDR Training.

[0384] The above has described the logical functions of the second embodiment of the present application from the BIOS side. Now, the upper-layer processing of the second embodiment of the present application will be described from the Windows side. The upper-layer application can be a computer manager. The computer manager reads the value at the 0x4E position of the CMOS. If the value at the 0x4E position is not 0x00, the computer manager determines that some channels of the DDR have been disabled. In this case, the computer manager performs a pop-up window process, reminding the user through the pop-up window that the DDR is damaged and needs to be sent for repair or data backup.

[0385] Here, the Figure 13 shown PC boot process is compared with the Figure 3 shown PC boot process.

[0386] In Figure 3 the shown PC boot process, it is necessary for the Training results of all channels (such as 8 channels) to be passed or successful before entering the next stage to execute the subsequent boot process. If the Training result of any one of the 8 channels is a failure, then the system will get stuck at this stage, that is, the system will have an abnormality and the boot process will end. On the Windows side, it appears as a black screen and the computer cannot boot.

[0387] In Figure 13During the PC startup process shown, when DDR Training fails during BIOS boot after the electronic device starts up, the electronic device can disable one DDR channel at a time and perform DDR Training on the non-disabled channels after restarting. Specifically, the electronic device first disables one channel and performs DDR Training on the non-disabled channels after a cold restart; if the Training fails, then the disabled channel is restored and enabled, another channel is disabled, and DDR Training is performed on the non-disabled channels after a cold restart; retry multiple times in this way; when the Training is successful, boot the electronic device to start up normally, and the user can be prompted that the DDR has failed after startup. Through this solution, not only can the electronic device be booted up normally when DDR Training fails, but also it can find out which channels in the DDR may be damaged and prompt the user to send it for repair in time or perform data backup, thus improving the user experience.

[0388] Third Embodiment

[0389] The third embodiment needs to traverse all combinations of channel states. For example, taking two controllers with four channels each as an example, all 8-channel state combinations need to be traversed. One or more channels are disabled each time, and DDR Training is performed on the non-disabled channels after a cold start until DDR Training is successful, thereby booting the electronic device to start up normally. Among them, the state of each channel is the enabled state (represented by 0) or the disabled state (represented by 1).

[0390] Table 7

[0391] Bit position 7 6 5 4 3 2 1 0 Value 1 or 0 1 or 0 1 or 0 1 or 0 1 or 0 1 or 0 1 or 0 1 or 0 Define Mc1Ch3 Mc1Ch2 Mc1Ch1 Mc1Ch0 Mc0Ch3 Mc0Ch2 Mc0Ch1 Mc0Ch0

[0392] See Table 7 and Figure 14 , all 8-channel state combinations can include 00000000 to 11111111, a total of 2*2*2*2*2*2*2*2 = 256 state combinations. The electronic device traverses all combinations of channel states, a total of 256 times.

[0393] 00000000, control all 8 channels to be in the enabled state.

[0394] 00000001, control Mc0Ch0 among all 8 channels to be in the disabled state, and the other seven channels are all in the enabled state.

[0395] 00000010, control Mc0Ch1 among all 8 channels to be in the disabled state, and the other seven channels are all in the enabled state.

[0396] 00000011, control two channels, namely Mc0Ch0 and Mc0Ch1, among all 8 channels to be in the disabled state, and the other six channels to be in the enabled state.

[0397] 00000100, control Mc0Ch2 among all 8 channels to be in the disabled state, and the other seven channels to be in the non-enabled state.

[0398] 00000101, control two channels, namely Mc0Ch2 and Mc0Ch0, among all 8 channels to be in the disabled state, and the other six channels to be in the non-enabled state.

[0399] 00000110, control two channels, namely Mc0Ch2 and Mc0Ch1, among all 8 channels to be in the disabled state, and the other six channels to be in the non-enabled state.

[0400] 00000111, control three channels, namely Mc0Ch2, Mc0Ch1, and Mc0Ch0, among all 8 channels to be in the disabled state, and the other five channels to be in the non-enabled state.

[0401] And so on, for 11111111, control all 8 channels to be in the disabled state. It should be noted that when all 8 channels are in the disabled state, Training cannot be performed, so the total number of traversal times is at most 255 times.

[0402] For the specific solution of the third embodiment, reference can be made to the first embodiment and the second embodiment. The difference is that: when retrying, all combined states of 8 channels will be traversed, and the maximum number of retry times is 255 times. Compared with the first embodiment and the second embodiment, since the third embodiment has more retry times, the startup time is relatively longer.

[0403] Through the third embodiment, the success rate of fixing the startup problem caused by channel damage is higher. For example, if each of the two controllers has 1 channel damaged, the probability of this situation occurring is relatively small. If the first embodiment and the second embodiment are used to retry the repair, then it cannot be repaired.

[0404] Next, the implementation process of the method provided in the third embodiment of the present application will be briefly described with reference to the accompanying drawings.

[0405] Figure 15 is a schematic flowchart of a method for handling abnormal startup of a device provided in the third embodiment of the present application. Refer to Figure 15 As shown, the method includes the following steps S601 - S609. Here, it is still described by taking DDR with 8 channels as an example.

[0406] S601. After the electronic device is started, it enters the first stage of BIOS boot to start up, and DDR Training exception is detected.

[0407] S602 - S603. The electronic device determines K channels according to the value of 8 bits, and sets these K channels to the disabled state. The electronic device performs a cold restart and conducts Training on the non - disabled channels among the 8 channels. The initial value of i is 1. 1 ≤ K ≤ 8.

[0408] Among them, the value range of the 8 - bit number starts from 00000001 and polls up to 11111111.

[0409] Among them, according to the value of the 8 - bit number, 1 channel can be determined, or 2 channels can be determined, or 3 channels can be determined, or 4 channels can be determined, or 5 channels can be determined, or 6 channels can be determined, or 7 channels can be determined, or 8 channels can be determined.

[0410] S604. The electronic device determines whether the Training is successful.

[0411] S605 - S606. In the case where the Training is successful (corresponding to "yes" in S604), the electronic device enters the second stage of BIOS - guided startup to enable the electronic device to boot normally. The electronic device uses the computer management application to prompt that a certain channel corresponding to the first controller has failed.

[0412] Among them, the first stage of BIOS - guided startup includes CPU initialization, chip initialization, and memory initialization. Memory initialization includes DDR parameter initialization and Training on the DDR channels. The second stage of BIOS - guided startup includes motherboard initialization, driver execution environment, selection of the boot device, and loading and running the operating system.

[0413] S607 - S608. In the case where the Training fails (corresponding to "no" in S604), the electronic device determines whether the value of the 8 - bit number is less than 11111111. In the case where the value of the 8 - bit number is less than 11111111, the state combinations of all channels have not been traversed, and the electronic device increments the value of the 8 - bit number and continues to traverse the state combinations of each channel.

[0414] S609. In the case where the value of the 8 - bit number is equal to 11111111 (corresponding to "yes" in S614), that is, all state combinations of the channels have been traversed, the electronic device fails to boot.

[0415] It can be understood that after the electronic device detects that the DDR channel may be damaged, the electronic device can display the DDR channel damage information through logs, pop - up windows, etc., and prompt the user to send the DDR for repair in time or perform data backup, thereby improving the user experience.

[0416] Through the solution of this application, when a DDR Training exception occurs during BIOS boot after the electronic device is started, the electronic device can traverse all channel status combinations, disable one or more channels each time, perform DDR Training based on the non-disabled channels after a cold start, and execute in this traversing manner to avoid damaged channels during DDR Training, complete DDR initialization, and boot the electronic device to start up normally. Through this solution, not only can the electronic device be booted up normally by disabling a part of the DDR channels and then attempting DDR Training after restarting when a DDR Training exception occurs, but also it can find out which channels in the DDR may be damaged and prompt the user to send it for repair in time or perform data backup, thereby improving the user experience.

[0417] It should be noted that in the above third embodiment, through Figure 15 a DDR Training exception handling solution in the case where the electronic device includes 8 DDR channels is described. It can be understood that in actual implementation, the electronic device may also include fewer or more DDR channels. For the DDR Training exception handling solution in this case, reference can be made to the above DDR Training exception handling solution, which will not be elaborated here.

[0418] In the embodiment of this application, the appropriate DDR status control method can be selected based on the startup memory required by the operating system to handle DDR Training exceptions.

[0419] In other words, for operating systems with different startup memory requirements, the enabling status of the DDR channels can be controlled through the corresponding DDR status control method.

[0420] The following is an example. Suppose the electronic device includes 8 DDR channels, and each DDR channel provides 2G of memory.

[0421] Exemplarily, for an operating system that requires a relatively small startup memory (for example, requires at least 1G of startup memory), the number of DDR channels disabled by the electronic device each time is less than or equal to 7, so as to ensure that at least 1 DDR channel is in the startup state, thereby ensuring that DDR can provide at least 1G of memory for the operating system to complete startup.

[0422] Exemplarily again, for an operating system that requires a relatively large startup memory (for example, requires at least 6G of startup memory), the number of DDR channels disabled by the electronic device each time is less than or equal to 5, so as to ensure that at least 3 DDR channels are in the startup state, thereby ensuring that DDR can provide at least 6G of memory for the operating system to complete startup.

[0423] In this case, during the process of the electronic device traversing all the state combinations of the channels, the cases where 6 or more channels are disabled are not included, that is, the cases of traversing the disabling of 6 or more channels are excluded. For example, 00111111, 11001111, 11110011, 11111100, 11111110, 11111111 will not be traversed. Here, 0 represents the enabled state and 1 represents the disabled state. It can be understood that the cases of excluded traversal are exemplarily listed here and do not represent all cases.

[0424] It should also be noted that, for the sake of easy understanding, the above embodiments of the present application take the computer manager, CMOS, 0xF0, 0x0F, 0x4E, etc. as examples for exemplary illustration. In actual implementation, the embodiments of the present application are not limited thereto. For example, other tools can be used to replace the manager to obtain the DDR channel status information; the module for storing the DDR channel status information is not limited to CMOS; 0xF0, 0x0F, 0x4E, etc. are custom values and can be customized according to actual usage requirements.

[0425] Each of the embodiments described in this article can be an independent solution or can be combined according to the internal logic, and these solutions all fall within the protection scope of the present application.

[0426] The above mainly describes the solution provided by the embodiments of the present application from the perspective of method steps. It can be understood that, in order to implement the above functions, the electronic device implementing the method includes the corresponding hardware structure and / or software module for executing each function. Those skilled in the art should be able to realize that, in combination with the units and algorithm steps of each example described in the embodiments disclosed in this article, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a certain function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraint conditions of the technical solution. Professional technicians can use different methods to implement the described function for each specific application, but such implementation should not be considered to exceed the protection scope of the present application.

[0427] The embodiments of the present application can divide the electronic device into functional modules according to the above method examples. For example, each functional module can be divided corresponding to each function, or two or more functions can be integrated into one processing module. The above integrated module can be implemented in the form of hardware or in the form of a software functional module. It should be noted that the division of modules in the embodiments of the present application is illustrative, only a logical function division, and there can be other feasible division methods in actual implementation.

[0428] The present application further provides a chip, which is coupled to a memory and is configured to read and execute a computer program or instructions stored in the memory to execute the methods in the above embodiments.

[0429] The present application further provides an electronic device, which includes a chip configured to read and execute a computer program or instructions stored in a memory, such that the methods in the embodiments are executed.

[0430] This embodiment further provides a computer-readable storage medium storing computer instructions, which, when running on an electronic device, cause the electronic device to execute the above related method steps to implement the method for processing abnormal device startup in the above embodiments.

[0431] This embodiment further provides a computer program product, where the computer-readable storage medium stores program code, which, when running on a computer, causes the computer to execute the above related steps to implement the method for processing abnormal device startup in the above embodiments.

[0432] In addition, an embodiment of the present application further provides a device, which may specifically be a chip, a component, or a module. The device may include a processor and a memory connected to each other. The memory is configured to store computer execution instructions. When the device runs, the processor may execute the computer execution instructions stored in the memory, so that the chip executes the method for processing abnormal device startup in the above method embodiments.

[0433] Among them, the electronic device, computer-readable storage medium, computer program product, or chip provided in this embodiment are all configured to execute the corresponding methods provided above. Therefore, the beneficial effects that can be achieved may refer to the beneficial effects in the corresponding methods provided above, which will not be elaborated here.

[0434] Terms such as "first" and "second" in the description and claims of this application are used to distinguish different objects, rather than to describe a specific order of objects. In the description of the embodiments of the present application, unless otherwise specified, the meaning of "a plurality" refers to two or more. For example, a plurality of processing units refers to two or more processing units, and a plurality of elements refers to two or more elements.

[0435] It should be noted that in the embodiments of the present application, "greater than" may be replaced by "greater than or equal to", "less than or equal to" may be replaced by "less than", or "greater than or equal to" may be replaced by "greater than", and "less than" may be replaced by "less than or equal to".

[0436] As used herein, the term "and / or" describes the relationship between associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, both A and B exist simultaneously, and B exists alone. As used herein, the symbol " / " indicates that the associated objects are in an "or" relationship. For example, A / B means A or B.

[0437] As described above, the above are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims described.

Claims

1. A method for handling abnormal startup of a device, characterized in that, including: detecting first fault information, where the first fault information indicates that the initialization of the memory of the electronic device fails; reading channel status information of the memory, where the channel status information is used to indicate the channel status of each channel in the memory, and the channel status is an enabled state or a disabled state; modifying the channel status information according to the recognition result of the channel status information; triggering a restart; reading the modified channel status information and initializing the channels in the enabled state in the memory.

2. The method according to claim 1, wherein The modifying the channel status information according to the recognition result of the channel status information includes: recognizing that the channel status information is a first value; modifying the first value to a second value; wherein the second value and the first value respectively represent the channel status of different channels of the memory, and the channel status is an enabled state or a disabled state.

3. The method according to claim 2, wherein the first value indicates that all channels in the memory are in the enabled state or some channels are in the disabled state; the second value indicates that a first channel set in the memory is in the disabled state and a second channel set is in the enabled state, and the second channel set is the other channels in the memory except the first channel set.

4. The method according to claim 3, wherein The electronic device includes M controllers, and each controller correspondingly controls multiple channels of the memory; the first channel set is the channels corresponding to the first controller; the second channel set is the channels corresponding to M-1 controllers except the first controller; wherein the first controller is any one of the M controllers.

5. The method according to claim 4, wherein The range of the number of restarts x is 1≤x≤M.

6. The method according to claim 3, characterized in that The electronic device includes N channels; the first channel set is the first channel; the second channel set is N-1 channels in the N channels except the first channel; wherein the first channel is any one of the N channels.

7. The method according to claim 6, wherein The range of the number of restarts x is 1≤x≤N.

8. The method according to claim 2 or 3, characterized in that, The memory includes N channels, the channel status information is an N-bit binary value, and the N-bit binary values 0 and 1 respectively represent the enabled state or the disabled state of the N channels; Wherein, the first value and the second value are respectively 2 N different N-bit binary numerical values among N-bit binary numerical values.

9. The method according to claim 8, wherein The range of the number of times x of the restart is 1 ≤ x ≤ 2 N -1.

10. The method according to claim 8 or 9, characterized in that, The modifying the channel status information of the memory includes: modifying the channel status information according to the startup memory requirement of the operating system of the electronic device, so that the number of channels in the enabled state is greater than or equal to a preset number threshold.

11. The method according to any one of claims 1 to 10, characterized in that, The memory is a double data rate synchronous dynamic random access memory DDR, and the memory initialization failure is a DDR Training failure.

12. The method according to any one of claims 1 to 11, characterized in that, The detecting the first fault information includes: performing memory initialization based on the basic input / output system BIOS boot process; detecting the first fault information during the memory initialization process.

13. The method according to any one of claims 1 to 12, characterized in that, After the initialization is performed, the method further includes: when the memory initialization is successful, the electronic device boots up.

14. The method according to claim 13, wherein After the electronic device boots up, the method further includes: reading the channel status information of the memory; When the channel status information indicates that some channels of the memory are in a disabled state, the electronic device displays a damage prompt message for prompting that there are damaged channels in the memory.

15. The method according to claim 14, wherein The damage prompt message is determined according to the channel status information of the memory.

16. A method for processing abnormal startup of a device, characterized in that, Applied to an electronic device, the electronic device includes a first memory, a complementary metal-oxide-semiconductor memory (CMOS), a first controller, and a second controller, and the first controller and the second controller respectively control different channels of the first memory; the method includes: Detecting first fault information, where the first fault information indicates that the initialization of the first memory fails. When the first fault information is detected, writing a first value to a first register address in the CMOS. When the first value is written, triggering the electronic device to restart. During the restart process of the electronic device, initializing the channels corresponding to the second controller and not initializing the channels corresponding to the first controller. When the initialization of the channels corresponding to the second controller is successful, after the initialization of the channels corresponding to the second controller is successful, the electronic device powers on.

17. The method according to claim 16, wherein The first value indicates that the channels corresponding to the first controller are in a disabled state.

18. The method according to claim 16 or 17, characterized in that After the initialization of the channels corresponding to the second controller is successful and the electronic device powers on, the method further includes: The electronic device displays a damage prompt message for prompting that there are damaged channels in the channels corresponding to the first controller.

19. The method according to any one of claims 16 to 18, characterized in that The method further includes: During the initialization of the channels corresponding to the second controller, detecting the first fault information. When the first fault information is detected, writing a second value to the first register address in the CMOS. When the second value is written, triggering the electronic device to restart. During the restart process of the electronic device, initializing the channels corresponding to the first controller and not initializing the channels corresponding to the second controller. When the initialization of the channels corresponding to the first controller is successful, after the initialization of the channels corresponding to the first controller is successful, the electronic device powers on.

20. The method according to claim 19, characterized in that, The second value indicates that the channels corresponding to the second controller are in a disabled state.

21. The method according to claim 19 or 20, characterized in that, After the initialization of the channels corresponding to the first controller is successful and the electronic device powers on, the method further includes: The electronic device displays a damage prompt message for prompting that there are damaged channels in the channels corresponding to the second controller.

22. The method according to any one of claims 16 to 21, characterized in that, The first memory is a double data rate synchronous dynamic random access memory (DDR), and the initialization failure is a DDR Training failure.

23. An electronic device, characterized in that, It includes a processor, a memory, and a computer program stored on the memory. The processor is configured to execute the computer program to enable the electronic device to implement the method described in any one of claims 1 to 15, or the method described in any one of claims 16 to 22.

24. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program which, when running on an electronic device, causes the electronic device to execute the method described in any one of claims 1 to 15, or the method described in any one of claims 16 to 22.

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