Display compensation circuit, display compensation method and display device

Abstract

The invention provides a display compensation circuit, a display compensation method and a display device, relates to the technical field of display, and aims to improve the display quality. The display compensation circuit comprises an equalizer circuit and a source driving circuit. The equalizer circuit comprises a plurality of voltage division sub-circuits which are connected in parallel, at least one voltage division sub-circuit comprises a plurality of resistors which are connected in series, the equalizer circuit further comprises a plurality of control output ends, and at least one control output end is connected between two adjacent resistors of one voltage division sub-circuit. The source electrode driving circuit comprises a plurality of control input ends, and one control input end is electrically connected with one control output end. Wherein the resistor of at least one voltage division sub-circuit is a thermistor, and the equalizer circuit is configured to detect the temperature change by using the thermistor and adjust the output signals of the plurality of control output ends according to the temperature change. The source driving circuit is configured to receive the data signal and the output signal and compensate the data signal according to the output signal.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and in particular, to a display compensation circuit, a display compensation method, and a display device. Background Art

[0002] With the improvement of the refresh rate specifications of large-size products, the differential signal transmission rate from the Timing Controller (TCON) to the Driver circuit is getting higher and higher. The distance between the TCON IC and the Driver IC is relatively long, and the attenuation of the distal signal is relatively large. The higher the signal transmission rate, the more serious the attenuation.

[0003] Due to the difference in signal attenuation between high-temperature conditions and normal-temperature conditions, the display quality is reduced. Summary of the Invention

[0004] The present application provides a display compensation circuit, a display compensation method, and a display device, aiming to improve the display quality.

[0005] To achieve the above object, the embodiments of the present application provide the following technical solutions:

[0006] On the one hand, a display compensation circuit is provided. The display compensation circuit includes an equalizer circuit and a source driver circuit. The equalizer circuit includes a plurality of voltage-dividing sub-circuits connected in parallel. At least one voltage-dividing sub-circuit includes a plurality of resistors connected in series. The equalizer circuit further includes a plurality of control output terminals, and at least one control output terminal is connected between two adjacent resistors of a voltage-dividing sub-circuit. The source driver circuit includes a plurality of control input terminals, and one control input terminal is electrically connected to one control output terminal. Among them, at least one resistor of the voltage-dividing sub-circuit is a thermistor. The equalizer circuit is configured to detect the change in temperature using the thermistor and adjust the output signals of the plurality of control output terminals according to the change in temperature. The source driver circuit is configured to receive a data signal and an output signal, and compensate the data signal according to the output signal.

[0007] The display compensation circuit provided by this application includes an equalizer circuit and a source driver circuit. The equalizer circuit includes a plurality of voltage-dividing sub-circuits connected in parallel and a plurality of control input terminals. At least one voltage-dividing sub-circuit includes a plurality of thermistors connected in series. A control output terminal is electrically connected to the voltage-dividing sub-circuit. As the temperature changes, the impedances of the plurality of thermistors also change, so that different control signals are output from the control output terminal. The source driver circuit includes a plurality of control input terminals. One control input terminal is electrically connected to one control output terminal. After the control output terminal connected to the voltage-dividing sub-circuit including the thermistor outputs a control signal, the signal is received by the control input terminal. The source driver circuit compensates the data signal received by the source driver circuit through this signal, thereby improving the quality of the signal received by the source driver circuit and further improving the display quality.

[0008] In some embodiments, among the plurality of voltage-dividing sub-circuits, at least one voltage-dividing sub-circuit includes a positive temperature coefficient thermistor and a negative temperature coefficient thermistor connected in series.

[0009] In some embodiments, the plurality of voltage-dividing sub-circuits connected in parallel are electrically connected to a first voltage terminal and a second voltage terminal. The plurality of voltage-dividing sub-circuits include a first voltage-dividing sub-circuit. The first voltage-dividing sub-circuit includes a first resistor and a second resistor connected in series. The first resistor is a negative temperature coefficient thermistor, and the second resistor is a positive temperature coefficient thermistor. The plurality of control output terminals include a first control output terminal, and the first control output terminal is connected between the first resistor and the second resistor.

[0010] In some embodiments, the plurality of voltage-dividing sub-circuits further include a second voltage-dividing sub-circuit and a third voltage-dividing sub-circuit. The second voltage-dividing sub-circuit includes a third resistor, and the third voltage-dividing sub-circuit includes a fourth resistor. The plurality of control input terminals further include a second control output terminal and a third control output terminal. The second control output terminal is electrically connected to the first voltage terminal through the third resistor, and the third control output terminal is electrically connected to the second voltage terminal through the fourth resistor.

[0011] In some embodiments, the plurality of voltage-dividing sub-circuits connected in parallel are electrically connected to a first voltage terminal and a second voltage terminal. The plurality of voltage-dividing sub-circuits include a first voltage-dividing sub-circuit. The first voltage-dividing sub-circuit includes a first resistor, a second resistor, and a third resistor connected in series. The first resistor and the second resistor are both negative temperature coefficient thermistors, and the third resistor is a positive temperature coefficient thermistor. The equalizer circuit further includes a logic gate circuit. One input terminal of the logic gate circuit is connected between the first resistor and the second resistor, and the other input terminal is connected between the second resistor and the third resistor. One of the plurality of control output terminals is electrically connected to the output terminal of the logic gate circuit.

[0012] In some embodiments, the logic gate circuit includes an AND gate circuit. The plurality of control output terminals include a first control output terminal, and the first control output terminal is electrically connected to the output terminal of the AND gate circuit.

[0013] In some embodiments, the logic gate circuit includes an exclusive - OR gate circuit, and the plurality of control output terminals include a second control output terminal, and the second control output terminal is electrically connected to the output terminal of the exclusive - OR gate circuit.

[0014] In some embodiments, the plurality of voltage - dividing sub - circuits further include a second voltage - dividing sub - circuit, and the second voltage - dividing sub - circuit includes a fourth resistor. The equalizer circuit includes a plurality of logic gate circuits, and the plurality of logic gate circuits include an AND gate circuit and an exclusive - OR gate circuit. The plurality of control input terminals include a first control output terminal, a second control output terminal, and a third control output terminal. The first control output terminal is electrically connected to the output terminal of the AND gate circuit, the second control output terminal is electrically connected to the output terminal of the exclusive - OR gate circuit, and the third control output terminal is electrically connected to the first voltage terminal through the fourth resistor.

[0015] On the other hand, a display compensation method is provided. The display compensation method includes using a thermistor to detect temperature changes, switching the gear of the equalizer circuit according to the temperature changes, and compensating the data signal from the timing controller according to the gear of the equalizer circuit.

[0016] The compensation method provided in this application uses the impedance change of the thermistor to detect temperature changes. When a temperature change is detected, the equalizer circuit switches to a matching gear to compensate the data signal from the timing controller, thereby improving the quality of the signal received by the source driver circuit, preventing abnormal display caused by signal processing errors, and thus improving the display quality.

[0017] In yet another aspect, a display device is provided. The display device includes the display compensation circuit in the above - mentioned embodiments and a timing controller electrically connected to the display compensation circuit.

[0018] The above - mentioned display device has the same structure and beneficial technical effects as the display module provided in some of the above - mentioned embodiments, and will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] To more clearly illustrate the technical solutions in this application, the following will briefly introduce the drawings required in some embodiments of this application. Obviously, the drawings in the following description are only the drawings of some embodiments of this application, and those of ordinary skill in the art can also obtain other drawings based on these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and do not represent the actual size of the products or the actual process of the methods involved in the embodiments of this application.

[0020] Figure 1 It is a structural diagram of the display device provided in the embodiments of this application;

[0021] Figure 2A circuit diagram of a display compensation circuit provided by an embodiment of the present application;

[0022] Figure 3 A circuit diagram of another display compensation circuit provided by an embodiment of the present application. Specific embodiments

[0023] Next, in conjunction with the accompanying drawings, the technical solutions in some embodiments of the present application will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present application.

[0024] Unless the context requires otherwise, throughout the specification and claims, the term "comprising" is interpreted as being open and inclusive, that is, "including, but not limited to".

[0025] Hereinafter, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present application, unless otherwise stated, the meaning of "a plurality" is two or more.

[0026] When describing some embodiments, the expression "connected" and its derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connected" may be a fixed connection, a detachable connection, or an integral body; it may be directly connected or indirectly connected through an intermediate medium. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components have direct physical contact or electrical contact with each other.

[0027] In addition, the use of "based on" means open and inclusive, because a process, step, calculation, or other action "based on" one or more of the stated conditions or values may, in practice, be based on additional conditions or values beyond those stated.

[0028] It should be understood that when a layer or element is referred to as being on another layer or substrate, it may be that the layer or element is directly on the other layer or substrate, or there may be an intermediate layer between the layer or element and the other layer or substrate.

[0029] Exemplary embodiments are described with reference to cross-sectional views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of regions are enlarged for clarity. Thus, variations in the shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Accordingly, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but include shape deviations resulting from, for example, manufacturing. For example, an etched region shown as rectangular will generally have curved features. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to depict the actual shape of the regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0030] An embodiment of the present application provides a display device 100. Figure 1 It is a structural diagram of the display device provided by the embodiment of the present application.

[0031] The display device 100 includes a display module 200 and a plurality of printed circuit boards (PCBs) disposed on one side of the display module 200. Exemplarily, the plurality of PCBs include three circuit boards (xPCBs) 400 and one main circuit board (CPCB) 500. The xPCBs 400 and the display module 200 are electrically connected through a chip on flexible printed circuit (COF) 300, and the xPCBs 400 and the CPCB 500 are electrically connected.

[0032] A plurality of integrated circuit (IC) chips, such as a source driver circuit (Driver IC) 2, are disposed on the COF 300. An equalizer (EQ) circuit 1 is disposed on each xPCB 400, and the equalizer circuit 1 and the source driver circuit 2 form a display compensation circuit 10. A timing controller (TCON) 600 is disposed on the main circuit board (CPCB) 500, and the timing controller 600 is electrically connected to the display compensation circuit 10. A differential signal is transmitted to the source driver circuit 2 through the timing controller 600, so that the source driver circuit 2 transmits a data signal (data) to the display module 200, thereby controlling the image display of the display panel of the display module 200.

[0033] The above display device can be any device that displays images whether in motion (e.g., video) or stationary (e.g., still images), and whether text or otherwise. More specifically, it is contemplated that the embodiments can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rear view cameras in vehicles), electronic photos, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0034] Figure 2 The circuit diagram of a display compensation circuit provided by an embodiment of the present application.

[0035] See Figure 1 and Figure 2 An embodiment of the present application further provides a display compensation circuit 10. The display compensation circuit 10 can perform signal compensation for two temperature levels, namely normal temperature and high temperature. The display compensation circuit 10 includes an equalizer circuit 1 and a source driver circuit 2. The equalizer circuit 1 includes a plurality of voltage dividing sub-circuits connected in parallel. Exemplarily, the equalizer circuit 1 includes a first voltage dividing sub-circuit 11, a second voltage dividing sub-circuit 12, and a third voltage dividing sub-circuit 13. Exemplarily, the plurality of voltage dividing sub-circuits connected in parallel are electrically connected to a first voltage terminal 31 and a second voltage terminal 32. The first voltage terminal 31 is electrically connected to the TCON 600, and the voltage value of the first voltage terminal 31 is 1.8V. The second voltage terminal 32 is a ground terminal (Ground, GND).

[0036] At least one voltage dividing sub-circuit includes a plurality of resistors connected in series. In the present application, the first voltage dividing sub-circuit 11 including a first resistor R3 and a second resistor R4 connected in series is taken as an example for illustration.

[0037] The equalizer circuit 1 further includes a plurality of control output terminals. Exemplarily, the equalizer circuit 1 includes a first control output terminal EQ1, a second control output terminal EQ2, and a third control output terminal EQ0. At least one control output terminal is connected between two adjacent resistors of a voltage dividing sub-circuit, that is, the first control output terminal EQ1 is connected between the adjacent first resistor R3 and second resistor R4 of the first voltage dividing sub-circuit 11.

[0038] Continue to see Figure 2, the source driver circuit 2 includes multiple control input terminals. Exemplarily, the source driver circuit 2 includes a first control input terminal 21, a second control input terminal 22, and a third control input terminal 23. One control input terminal is electrically connected to one control output terminal. It can be understood that the first control output terminal EQ1 is electrically connected to the first control input terminal 21, the second control output terminal EQ2 is electrically connected to the second control input terminal 22, and the third control output terminal EQ0 is electrically connected to the third control input terminal 23.

[0039] Among them, referring to Figure 2 , the resistance of at least one voltage-dividing sub-circuit is a thermistor, that is, the first resistor R3 and the second resistor R4 are thermistors. The equalizer circuit 1 uses the thermistor to detect the temperature change and adjusts the output signals of multiple control output terminals according to the temperature change. It can be understood that the impedance of the first resistor R3 and the second resistor R4 changes with the temperature. When the temperature reaches the preset threshold, due to different voltage divisions of the series-connected first resistor R3 and second resistor R4, the level of the IO port of the first control output terminal EQ1 is converted (from high to low or from low to high), so that the first control output terminal EQ1 outputs different control signals to achieve the gear switching of the first control output terminal EQ1 (from "1" to "0", or from "0" to "1").

[0040] Referring to Figure 1 and Figure 2 , one end of the source driver circuit 2 connected to the timing controller 600 receives a data signal, and one end of the source driver circuit 2 connected to the equalizer circuit 1 (i.e., the control input terminal) receives an output signal. Moreover, the source driver circuit 2 compensates the data signal according to the received output signal. It can be understood that the first control input terminal 21 receives the output signal from the first control output terminal EQ1, so that the source driver circuit 2 compensates the data signal according to this output signal.

[0041] The display compensation circuit 10 provided by the present application includes an equalizer circuit 1 and a source driver circuit 2. The equalizer circuit 1 includes multiple parallel voltage-dividing sub-circuits and multiple control input terminals. At least one voltage-dividing sub-circuit includes multiple series-connected thermistors. One control output terminal is electrically connected to the voltage-dividing sub-circuit. As the temperature changes, the impedance of the multiple thermistors also changes, so that the control output terminal outputs different control signals. The source driver circuit 2 includes multiple control input terminals. One control input terminal is electrically connected to one control output terminal. After the control output terminal connected to the voltage-dividing sub-circuit including the thermistor outputs a control signal, the control input terminal receives this signal. The source driver circuit 2 compensates the data signal received by the source driver circuit 2 through this signal, thereby improving the quality of the signal received by the source driver circuit 2 and further improving the display quality.

[0042] In some embodiments, refer to Figure 2 , among multiple voltage-dividing sub-circuits, at least one voltage-dividing sub-circuit includes a positive temperature coefficient thermistor and a negative temperature coefficient thermistor connected in series. Exemplarily, in the first voltage-dividing sub-circuit 11, the first resistor R3 is a negative temperature coefficient thermistor (the impedance is lower at higher temperatures), and the second resistor R4 is a positive temperature coefficient thermistor (the impedance is higher at higher temperatures). As the temperature changes, there is a significant difference in the impedance between the first resistor R3 and the second resistor R4, making it easier for the level at the first control output terminal EQ1 to reach a preset threshold, thereby increasing the sensitivity of the equalizer circuit 1 to temperature changes.

[0043] In some embodiments, refer to Figure 2 , the second voltage-dividing sub-circuit 12 includes a third resistor R1, and the third voltage-dividing sub-circuit 13 includes a fourth resistor R6. The second control output terminal EQ2 is electrically connected to the first voltage terminal 31 through the third resistor R1, and the third control output terminal EQ0 is electrically connected to the second voltage terminal 32 through the fourth resistor R6. The third resistor R1 and the fourth resistor R6 are conventional resistors, and their impedance remains unchanged when the temperature changes, that is, the positions of the second control output terminal EQ2 and the third control output terminal EQ0 remain unchanged, and signal compensation can be achieved only by changing the position of the first control output terminal EQ1.

[0044] An embodiment of the present application further provides a display compensation method. Refer to Figure 1 and Figure 2 , the display compensation method includes using thermistors (the first resistor R3 and the second resistor R4) to detect temperature changes, switching the position of the equalizer circuit 1 according to the temperature changes, and compensating the data signal from the timing controller 600 according to the position of the equalizer circuit 1. It can be understood that when an environmental change is detected, the equalizer circuit 1 switches to a matching position to compensate the data signal from the timing controller 600, thereby improving the quality of the signal received by the source driver circuit 2 and preventing abnormal display caused by signal processing errors, thereby improving the display quality.

[0045] Exemplarily, refer to Figure 2 , the display compensation circuit 10 provided by the present application can distinguish between two positions of normal temperature and high temperature, which are controlled by 3 IO ports, namely the second control output terminal EQ2, the first control output terminal EQ1, and the third control output terminal EQ0. For example, at normal temperature, the control output terminal outputs the "100" position, and at high temperature, the control output terminal outputs the "110" position. That is, when changing from the normal temperature state to the high temperature state, only the second control output terminal EQ2 outputs "1", and only the third control output terminal EQ0 outputs "0", and the levels of the two do not need to be switched. The output of the first control output terminal EQ1 needs to be switched from "0" to "1".

[0046] Figure 2 Among them, the third resistor R1 located in the second voltage dividing sub-circuit 12 is set as a conventional resistor, there is an open circuit at R2, and the second control output terminal EQ2 is electrically connected to the first voltage terminal 31 through the third resistor R1. The fourth resistor R6 located in the third voltage dividing sub-circuit 13 is set as a conventional resistor, there is an open circuit at R5, and the third control output terminal EQ0 is electrically connected to the second voltage terminal 32 through the fourth resistor R6. The first resistor R3 is set as a negative temperature coefficient thermistor (the impedance is lower as the temperature is higher), and the second resistor R4 is set as a positive temperature coefficient thermistor (the impedance is higher as the temperature is higher).

[0047] Under normal temperature conditions, the impedance of the second resistor R4 is much smaller than that of the first resistor R3, and the first control output terminal EQ1 outputs "0"; under high temperature conditions, the impedance of the second resistor R4 is much larger than that of the first resistor R3, and the first control output terminal EQ1 outputs "1". The change in the gear of the first control output terminal EQ1 also changes the signal received by the first control input terminal 21 of the source driver circuit 2, so that the source driver circuit 2 compensates the data signal from the timing controller 600 according to the output signal, thereby realizing the compensation of the signal by the display compensation circuit 10 under temperature change conditions.

[0048] Figure 3 It is the circuit diagram of another display compensation circuit provided by the embodiment of the present application.

[0049] The embodiment of the present application also provides another display compensation circuit, which can perform signal compensation for three temperature levels of normal temperature, medium temperature and high temperature. Refer to Figure 3 , this display compensation circuit 10 includes an equalizer circuit 1 and a source driver circuit 2. The equalizer circuit 1 includes a plurality of parallel voltage dividing sub-circuits. Exemplarily, the equalizer circuit 1 includes a first voltage dividing sub-circuit 11, a second voltage dividing sub-circuit 12, a third voltage dividing sub-circuit 13 and a fourth voltage dividing sub-circuit 14. Exemplarily, the plurality of parallel voltage dividing sub-circuits are electrically connected to the first voltage terminal 31 and the second voltage terminal 32. The first voltage terminal 31 is electrically connected to the TCON 600, the voltage value of the first voltage terminal 31 is 1.8V, and the second voltage terminal 32 is a ground terminal (GND).

[0050] At least one voltage dividing sub-circuit includes a plurality of resistors connected in series. In the present application, the first voltage dividing sub-circuit 11 including the first resistor R1, the second resistor R2 and the third resistor R3 connected in series is taken as an example for illustration.

[0051] The equalizer circuit 1 further includes a plurality of control output terminals. Exemplarily, the equalizer circuit 1 includes a first control output terminal EQ1, a second control output terminal EQ0, and a third control output terminal EQ3. At least one control output terminal is connected between two adjacent resistors of a voltage dividing sub-circuit. It can be understood that in the embodiments of the present application, the first control output terminal EQ1 is connected between the adjacent first resistor R1 and second resistor R2 of the first voltage dividing sub-circuit 11, and between the second resistor R2 and the third resistor R3, and the second control output terminal EQ0 is connected between the adjacent first resistor R1 and second resistor R2 of the first voltage dividing sub-circuit 11, and between the second resistor R2 and the third resistor R3.

[0052] Continuing to refer to Figure 2 , the source driver circuit 2 includes a plurality of control input terminals. Exemplarily, the source driver circuit 2 includes a first control input terminal 21, a second control input terminal 22, and a third control input terminal 23. One control input terminal is electrically connected to one control output terminal. It can be understood that the first control output terminal EQ1 is electrically connected to the first control input terminal 21, the second control output terminal EQ0 is electrically connected to the second control input terminal 22, and the third control output terminal EQ2 is electrically connected to the third control input terminal 23.

[0053] Among them, referring to Figure 3 , the resistors of at least one voltage dividing sub-circuit are thermistors. Exemplarily, the first resistor R1, the second resistor R2, and the third resistor R3 are all thermistors. The equalizer circuit 1 uses the thermistors to detect the change in temperature and adjusts the output signals of the plurality of control output terminals according to the change in temperature. It can be understood that the impedances of the first resistor R1, the second resistor R2, and the third resistor R3 change with the change in temperature. When the temperature reaches the preset threshold, due to the different voltage divisions of the series-connected first resistor R1, second resistor R2, and third resistor R3, the levels of the I / O ports of the first control output terminal EQ1 and the second control output terminal EQ0 are converted (from high to low or from low to high), so that the first control output terminal EQ1 and the second control output terminal EQ0 output different control signals to realize the gear shift of the first control output terminal EQ1 and the second control output terminal EQ0 (from "1" to "0", or from "0" to "1").

[0054] Refer to Figure 1 and Figure 3, one end of the source driver circuit 2 connected to the timing controller 600 receives a data signal, and one end of the source driver circuit 2 connected to the equalizer circuit 1 (i.e., the control input terminal) receives an output signal. Moreover, the source driver circuit 2 compensates the data signal according to the received output signal. It can be understood that the first control input terminal 21 receives the output signal from the first control output terminal EQ1, and the second control input terminal 22 receives the output signal from the second control output terminal EQ0, so that the source driver circuit 2 compensates the data signal according to the output signal.

[0055] The display compensation circuit 10 provided in this application includes an equalizer circuit 1 and a source driver circuit 2. The equalizer circuit 1 includes a plurality of voltage-dividing sub-circuits connected in parallel and a plurality of control input terminals. At least one voltage-dividing sub-circuit includes a plurality of thermistors connected in series. A control output terminal is electrically connected to the voltage-dividing sub-circuit. As the temperature changes, the impedance of the plurality of thermistors also changes, so that the control output terminal outputs different control signals. The source driver circuit 2 includes a plurality of control input terminals. One control input terminal is electrically connected to one control output terminal. After the control output terminal connected to the voltage-dividing sub-circuit including the thermistor outputs a control signal, the control input terminal receives the signal. The source driver circuit 2 compensates the data signal received by the source driver circuit 2 through this signal, thereby improving the quality of the signal received by the source driver circuit 2, and further improving the display quality.

[0056] In some embodiments, refer to Figure 3 , both the first resistor R1 and the second resistor R2 are negative temperature coefficient thermistors, and the third resistor R3 is a positive temperature coefficient thermistor. In the first voltage-dividing sub-circuit 11, the voltage value U at point a a is greater than the voltage value U at point b b .

[0057] Continue to refer to Figure 3 , the equalizer circuit 1 further includes a logic gate circuit. Exemplarily, the equalizer circuit 1 includes a first logic gate circuit U1, a second logic gate circuit U2, and a third logic gate circuit U3. One input terminal of the logic gate circuit is connected between the first resistor R1 and the second resistor R2 (point a), and the other input terminal is connected between the second resistor R2 and the third resistor R3 (point b). It can be understood that the voltage value at the input terminals of the first logic gate circuit U1, the second logic gate circuit U2, and the third logic gate circuit U3 is equal to U a , and the voltage value at the other input terminal of the three is equal to U b .

[0058] One of the multiple control output terminals is electrically connected to the output terminal of the logic gate circuit. It can be understood that the first control output terminal EQ1 is electrically connected to the output terminal of the second logic gate circuit U2, and the second control output terminal EQ0 is electrically connected to the output terminal of the third logic gate circuit U3. When the temperature changes, the voltage values at U a and U b change. By setting appropriate voltage thresholds for the second logic gate circuit U2 and the third logic gate circuit U3, the output of the logic gate circuit ("0" or "1") can be controlled, thereby controlling the gear of the control output terminal.

[0059] Exemplarily, at room temperature, the impedances of the first resistor R1 and the second resistor R2 are much greater than the impedance of the third resistor R3, U a ≈U b >U c . By setting an appropriate voltage threshold, for example, the voltage threshold is greater than U a , so that U a and U b are both low levels. At medium temperature, the impedances of the first resistor R1, the second resistor R2, and the third resistor R3 are close, U a >U b >U c . By setting an appropriate voltage threshold, for example, the voltage threshold is between U a and U b , so that U a is a high level and U b is a low level. At high temperature, the impedances of the first resistor R1 and the second resistor R2 are much less than the impedance of the third resistor R3, U a ≈U b >U c . By setting an appropriate voltage threshold, for example, the voltage threshold is between U b and U c , so that U a and U b are both high levels.

[0060] In some embodiments, referring to Figure 3 , the logic gate circuit includes an AND gate circuit. Exemplarily, the second logic gate circuit U2 is an AND gate circuit. At U a and U bWhen both are at high level, the second logic gate circuit U2 outputs "1", and in other cases, the second logic gate circuit U2 outputs "0". The first control output terminal EQ1 is electrically connected to the output terminal of the second logic gate circuit (AND gate circuit) U2. When the second logic gate circuit U2 outputs "1", the first control output terminal EQ1 is in the on gear. By setting an AND gate circuit with a suitable voltage threshold, the change of the gear of the first control output terminal EQ1 at different temperatures is realized.

[0061] In some embodiments, refer to Figure 3 , the logic gate circuit includes an exclusive-OR gate circuit. Exemplarily, the third logic gate circuit U3 is an exclusive-OR gate circuit. When U a and U b are both at high level or both at low level, the third logic gate circuit U3 outputs "0", and in other cases, the third logic gate circuit U3 outputs "1". The second control output terminal EQ2 is electrically connected to the output terminal of the third logic gate circuit (exclusive-OR gate circuit) U3. When the third logic gate circuit U3 outputs "1", the second control output terminal EQ2 is in the on gear. By setting an exclusive-OR gate circuit with a suitable voltage threshold, the change of the gear of the second control output terminal EQ2 at different temperatures is realized.

[0062] In some embodiments, refer to Figure 3 , the second voltage dividing sub-circuit 12 includes a fourth resistor R4. The equalizer circuit 1 includes a plurality of logic gate circuits. The plurality of logic gate circuits include an AND gate circuit and an exclusive-OR gate circuit. Exemplarily, the first logic gate circuit U1 is open-circuited, the second logic gate circuit U2 is an AND gate circuit, and the third logic gate circuit U3 is an exclusive-OR gate circuit. The first control output terminal EQ1 is electrically connected to the output terminal of the second logic gate circuit (AND gate circuit) U2, the second control output terminal EQ0 is electrically connected to the output terminal of the third logic gate circuit (exclusive-OR gate circuit) U3, and the third control output terminal EQ2 is electrically connected to the first voltage terminal through the fourth resistor R4. When the temperature changes, the first logic gate circuit U1 is open-circuited, that is, the gear of the third control output terminal EQ2 remains unchanged, and the signal compensation can be realized by changing the gears of the first control output terminal EQ1 and the second control output terminal EQ0.

[0063] The embodiment of the present application also provides a display compensation method, refer to Figure 1 and Figure 3, the display compensation method includes using a thermistor (the first resistor R1, the second resistor R2, and the third resistor R3) to detect temperature changes, switching the gear of the equalizer circuit 1 according to the temperature changes, and compensating the data signal from the timing controller 600 according to the gear of the equalizer circuit 1. It can be understood that when a temperature change is detected, the equalizer circuit 1 switches to a matching gear to compensate the data signal from the timing controller 600, thereby improving the quality of the signal received by the source driver circuit 2 and preventing abnormal display caused by signal processing errors, thereby improving the display quality.

[0064] Exemplarily, refer to Figure 3 , in the display compensation circuit 10 provided in the present application, the outputs of the three thermistors connected in series in the first voltage dividing sub-circuit 21 control the logic gate circuit. The type of the logic gate circuit can be an AND gate, an OR gate, a NAND gate, a NOR gate, etc. In the embodiments of the present application, the logic gate circuit including an AND gate circuit and a NOR gate circuit is taken as an example for illustration. The display compensation circuit 10 can distinguish three gears of normal temperature, medium temperature, and high temperature. The equalizer circuit 1 has 3 IO ports, namely the second control output terminal EQ2, the first control output terminal EQ1, and the third control output terminal EQ0. The first resistor R1 and the second resistor R2 are thermistors with a negative temperature coefficient, and the third resistor R3 is a thermistor with a positive temperature coefficient.

[0065] For example, at normal temperature, the control output terminal outputs the "100" gear, at medium temperature, the control output terminal outputs the "101" gear, and at high temperature, the control output terminal outputs the "110" gear. In the case of a temperature change, only the third control output terminal EQ2 outputs "1", and its level does not need to be switched. The first logic gate circuit U1 is open, and R5 is open. The third control output terminal EQ2 is electrically connected to the first voltage terminal 31 through the fourth resistor R4.

[0066] R6 and R7 in the third voltage dividing sub-circuit 13 are open, and the second logic gate circuit U2 is an AND gate circuit. In the case of normal temperature, both U a and U b are at low level, and the second logic gate circuit U2 outputs "0", so the first control output terminal EQ1 outputs "0". When switching from normal temperature to medium temperature, U a is at high level, U b is at low level, and the second logic gate circuit U2 outputs "0", so the first control output terminal EQ1 remains unchanged and is still "0". In the case of high temperature, both U a and U b are at high level, and the second logic gate circuit U2 outputs "1", so the first control output terminal EQ1 outputs "1".

[0067] R8 and R9 in the fourth voltage-dividing sub-circuit 14 are open-circuited, and the third logic gate circuit U3 is an exclusive-OR gate circuit. At normal temperature, U a and U b are both at low level, and the third logic gate circuit U3 outputs "0", so the third control output terminal EQ0 outputs "0". At medium temperature, U a is at high level, U b is at low level, and the output of the third control output terminal EQ0 switches to "1", so the third logic gate circuit U3 outputs "1".

[0068] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application, thinking of changes or substitutions, should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claimed rights.

Claims

1. A display compensation circuit, characterized in that Comprising: An equalizer circuit including a plurality of voltage-dividing sub-circuits connected in parallel, at least one of the voltage-dividing sub-circuits including a plurality of resistors connected in series; the equalizer circuit further includes a plurality of control output terminals, and at least one of the control output terminals is connected between two adjacent resistors of a voltage-dividing sub-circuit; A source driver circuit including a plurality of control input terminals, one control input terminal being electrically connected to one control output terminal; Wherein, the resistor of at least one of the voltage-dividing sub-circuits is a thermistor, and the equalizer circuit is configured to detect a change in temperature using the thermistor and adjust the output signals of the plurality of control output terminals according to the change in temperature; The source driver circuit is configured to receive a data signal and the output signal and compensate the data signal according to the output signal.

2. The display compensation circuit according to claim 1, wherein Among the plurality of voltage-dividing sub-circuits, at least one of the voltage-dividing sub-circuits includes a positive temperature coefficient thermistor and a negative temperature coefficient thermistor connected in series.

3. The display compensation circuit according to claim 1, wherein The plurality of voltage-dividing sub-circuits connected in parallel are electrically connected to a first voltage terminal and a second voltage terminal; The plurality of voltage-dividing sub-circuits includes a first voltage-dividing sub-circuit, the first voltage-dividing sub-circuit includes a first resistor and a second resistor connected in series, the first resistor is a negative temperature coefficient thermistor, and the second resistor is a positive temperature coefficient thermistor; The plurality of control output terminals includes a first control output terminal, and the first control output terminal is connected between the first resistor and the second resistor.

4. The display compensation circuit according to claim 3, wherein The plurality of voltage-dividing sub-circuits further includes a second voltage-dividing sub-circuit and a third voltage-dividing sub-circuit, the second voltage-dividing sub-circuit includes a third resistor, and the third voltage-dividing sub-circuit includes a fourth resistor; The plurality of control input terminals further includes a second control output terminal and a third control output terminal, the second control output terminal is electrically connected to the first voltage terminal through the third resistor, and the third control output terminal is electrically connected to the second voltage terminal through the fourth resistor.

5. The display compensation circuit according to claim 1, wherein The plurality of voltage-dividing sub-circuits connected in parallel are electrically connected to a first voltage terminal and a second voltage terminal; The plurality of voltage-dividing sub-circuits includes a first voltage-dividing sub-circuit, the first voltage-dividing sub-circuit includes a first resistor, a second resistor, and a third resistor connected in series, the first resistor and the second resistor are both negative temperature coefficient thermistors, and the third resistor is a positive temperature coefficient thermistor; The equalizer circuit further includes a logic gate circuit, one input terminal of the logic gate circuit is connected between the first resistor and the second resistor, and the other input terminal is connected between the second resistor and the third resistor; one of the plurality of control output terminals is electrically connected to the output terminal of the logic gate circuit.

6. The display compensation circuit according to claim 5, wherein The logic gate circuit includes an AND gate circuit, the plurality of control output terminals includes a first control output terminal, and the first control output terminal is electrically connected to the output terminal of the AND gate circuit.

7. The display compensation circuit according to claim 5, wherein The logic gate circuit includes an XOR gate circuit, the plurality of control output terminals includes a second control output terminal, and the second control output terminal is electrically connected to the output terminal of the XOR gate circuit.

8. The display compensation circuit according to any one of claims 5 to 7, characterized in that, The plurality of voltage-dividing sub-circuits further includes a second voltage-dividing sub-circuit, and the second voltage-dividing sub-circuit includes a fourth resistor; The equalizer circuit includes a plurality of the logic gate circuits, and the plurality of the logic gate circuits include an AND gate circuit and an exclusive-OR gate circuit; The plurality of control input terminals include a first control output terminal, a second control output terminal, and a third control output terminal. The first control output terminal is electrically connected to the output terminal of the AND gate circuit, the second control output terminal is electrically connected to the output terminal of the exclusive-OR gate circuit, and the third control output terminal is electrically connected to the first voltage terminal through the fourth resistor.

9. A display compensation method, characterized in that, Comprising: Using a thermistor to detect the change in temperature and switching the gear of the equalizer circuit according to the change in temperature; Compensating the data signal from the timing controller according to the gear of the equalizer circuit.

10. A display device, characterized in that, Comprising: The display compensation circuit according to any one of claims 1 to 8; A timing controller, electrically connected to the display compensation circuit.

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