Shifting register, display panel and display device

Abstract

The invention discloses a shift register, a display panel and a display device. The shift register comprises an input module, a first control module, a second control module, a first output module and a second output module, the input module transmits an input signal to the input end of the first control module and the first end of the second control module according to a first clock signal; the first control module is used for transmitting a signal opposite to the control end logic to the first node; a signal which is logically opposite to the first node is transmitted to the second node; the second control module is used for transmitting the signal of the first end to the second node according to the first clock signal; the first output module is used for outputting a first power supply voltage according to a signal of a first node and outputting a second clock signal according to a signal of a second node; the second output module is used for outputting a second power supply voltage according to the signal of the first node and outputting a first power supply voltage according to the signal of the second node. The use performance of the shift register can be improved.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and particularly to a shift register, a display panel, and a display device. Background Art

[0002] With the development of display technologies, display panels using technologies such as OLED (Organic Light Emitting Diode) have been more and more widely applied, and correspondingly, the requirements for display panels have also become higher and higher.

[0003] In a display panel, a shift register is required to provide a scanning signal. However, the performance of the shift register in related technologies is poor, which limits the further application of the display panel. Summary of the Invention

[0004] The present invention provides a shift register, a display panel, and a display device to improve the performance of the shift register.

[0005] According to an aspect of the present invention, there is provided a shift register, characterized in that the shift register includes:

[0006] an input module, a first control module, a second control module, a first output module, and a second output module;

[0007] The input module is configured to transmit an input signal to the input end of the first control module and the first end of the second control module according to a first clock signal; the first control module is configured to transmit a signal opposite in logic to its control end to a first node; and transmit a signal opposite in logic to the first node to a second node;

[0008] The second control module is configured to transmit the signal at its first end to the second node according to the first clock signal; wherein, the second control module has a conduction voltage level opposite in logic to that of the input module;

[0009] The first output module is configured to output a first power supply voltage according to the signal of the first node, and output a second clock signal according to the signal of the second node;

[0010] The second output module is configured to output a second power supply voltage according to the signal of the first node, and output a first power supply voltage according to the signal of the second node.

[0011] Optionally, the shift register further includes a third output module, and the third output module is configured to output the first power supply voltage according to the signal of the first node, and output a third clock signal according to the signal of the second node;

[0012] Preferably, the first output module includes a first pull-up unit, a first pull-down unit, and a first coupling unit. A first end of the first pull-up unit is connected to the first power supply voltage. A control end of the first pull-up unit is electrically connected to the first node. A second end of the first pull-up unit is electrically connected to an output end of the first output module. A first end of the first pull-down unit is connected to the second clock signal. A control end of the first pull-down unit is electrically connected to the second node. A second end of the first pull-down unit is electrically connected to the output end of the first output module. A first end of the first coupling unit is electrically connected to the second end of the first pull-down unit. A second end of the first coupling unit is electrically connected to the control end of the first pull-down unit.

[0013] Preferably, the third output module includes a second pull-up unit, a second pull-down unit, and a second coupling unit. A first end of the second pull-up unit is connected to the first power supply voltage. A control end of the second pull-up unit is electrically connected to the first node. A second end of the second pull-up unit is electrically connected to an output end of the third output module. A first end of the second pull-down unit is connected to the second clock signal. A control end of the second pull-down unit is electrically connected to the second node. A second end of the second pull-down unit is electrically connected to the output end of the third output module. A first end of the second coupling unit is electrically connected to the second end of the second pull-down unit. A second end of the second coupling unit is electrically connected to the control end of the second pull-down unit.

[0014] Optionally, the first control module includes a first inverter unit and a second inverter unit. An input end of the first inverter unit is electrically connected to an input end of the first control module. An output end of the first inverter unit is electrically connected to the first node. An input end of the second inverter unit is electrically connected to the first node. An output end of the second inverter unit is electrically connected to the second node.

[0015] Preferably, the first inverter unit includes a complementary metal-oxide inverter.

[0016] Preferably, the second inverter unit includes a complementary metal-oxide inverter.

[0017] Optionally, the second output module includes:

[0018] A third pull-up unit, a third pull-down unit, a third coupling unit, and a fourth pull-down unit; a first end of the third pull-up unit is connected to the first power supply voltage, a control end of the third pull-up unit is electrically connected to the second node, and a second end of the third pull-up unit is electrically connected to an output end of the second output module; the fourth pull-down unit is configured to output the third power supply voltage to a control end of the third pull-down unit according to a potential of the first node, and output the first power supply voltage to the control end of the third pull-down unit according to a potential of the second node; a first end of the third pull-down unit is connected to the second power supply voltage, and a second end of the third pull-down unit is electrically connected to the output end of the second output module; a first end of the third coupling unit is electrically connected to the first end of the third pull-up unit, and a second end of the third coupling unit is electrically connected to the control end of the third pull-up unit;

[0019] Preferably, the fourth pull-down unit includes a voltage modulation unit, and the voltage modulation unit is configured to modulate a conductive level of the first node into the third power supply voltage and output the third power supply voltage to the control end of the third pull-down unit;

[0020] Preferably, the fourth pull-down unit includes a first sub-switch unit, a second sub-switch unit, a third sub-switch unit, and a fourth sub-switch unit; a first end of the first sub-switch unit is connected to the first power supply voltage, a second end of the first sub-switch unit is electrically connected to a first end of the second sub-switch unit, and a control end of the first sub-switch unit is electrically connected to the first node; a second end of the second sub-switch unit is connected to the third power supply voltage; a first end of the third sub-switch unit is connected to the first power supply voltage, a second end of the third sub-switch unit is electrically connected to a first end of the fourth sub-switch unit, a second end of the fourth sub-switch unit is connected to the third power supply voltage, and a control end of the third sub-switch unit is electrically connected to the second node; a control end of the second sub-switch unit is electrically connected to a second end of the third sub-switch unit, and a control end of the fourth sub-switch unit is electrically connected to a second end of the first sub-switch unit; a second end of the third sub-switch unit is electrically connected to the control end of the third pull-down unit; the transistor channel types of the first sub-switch unit and the second sub-switch unit are different, the transistor channel types of the third sub-switch unit and the fourth sub-switch unit are different, and the transistor channel types of the first sub-switch unit and the third sub-switch unit are the same.

[0021] According to another aspect of the present invention, a display panel is provided, and the display panel includes multiple rows of pixel circuits, multiple first shift registers, and multiple second shift registers; wherein, both the first shift register and the second shift register include the shift register as described above;

[0022] The pixel circuit includes a data writing module, a threshold compensation module, a driving module, and a first initialization module. The data writing module is configured to write a data voltage into the driving module. The threshold compensation module is configured to compensate the threshold voltage of the driving module. The first initialization module is configured to initialize the control terminal of the driving module. Among them, the transistor channel types of the threshold compensation module and the first initialization module are different from those of the driving module. The transistor channel type of the data writing module is the same as that of the driving module.

[0023] The second output module of the first shift register is configured to drive the first initialization module of the corresponding pixel circuit.

[0024] The second output module of the second shift register is configured to drive the threshold compensation module of the corresponding pixel circuit.

[0025] The first output module of the second shift register is configured to drive the data writing module of the corresponding pixel circuit; and / or, the first output module of the first shift register is configured to drive the data writing module of the corresponding pixel circuit.

[0026] Optionally, the display panel includes three clock lines.

[0027] The display panel includes n rows of the pixel circuits, n + 2 stages of the first shift register, and n stages of the second shift register; n is an integer greater than or equal to 1.

[0028] The first initialization module of the k-th stage of the pixel circuit is electrically connected to the second output module of the k-th stage of the first shift register.

[0029] The threshold compensation module of the k-th stage of the pixel circuit is electrically connected to the second output module of the k-th stage of the second shift register; k is an integer greater than or equal to 1.

[0030] In the same stage of the first shift register, the first clock signal is provided by the a-th clock line, and the second clock signal is provided by the b-th clock line. Among them, if a is less than or equal to 2, then b is equal to a + 1; if a is greater than 2, then b is equal to 1.

[0031] In adjacent two stages of the first shift register, the second clock signal of the previous stage of the first shift register and the first clock signal of the next stage of the first shift register are provided by the same clock line.

[0032] The first clock signal corresponding to the second shift register of the k-th stage and the first clock signal corresponding to the first shift register of the (k + 2)-th stage are provided by the same clock line; the second clock signal corresponding to the second shift register of the k-th stage and the second clock signal corresponding to the first shift register of the (k + 2)-th stage are provided by the same clock line;

[0033] Preferably, the first clock signal of the first shift register of the k-th stage is provided by the j-th clock line; j is equal to the remainder of k divided by 3 plus 1.

[0034] Optionally, the display panel includes four clock lines;

[0035] The display panel includes n rows of the pixel circuits, n + 3 stages of the first shift registers, and n stages of the second shift registers; n is an integer greater than or equal to 1;

[0036] The first initialization module of the pixel circuit of the k-th stage is electrically connected to the second output module of the first shift register of the k-th stage;

[0037] The threshold compensation module of the pixel circuit of the k-th stage is electrically connected to the second output module of the second shift register of the k-th stage; k is an integer greater than or equal to 1;

[0038] In the first shift register of the same stage, the first clock signal is provided by the a-th clock line, and the second clock signal is provided by the b-th clock line; wherein, if a is less than or equal to 2, then b is equal to a + 1; if a is greater than 2, then b is equal to 1; in the first shift registers of adjacent two stages, the second clock signal of the previous first shift register and the first clock signal of the subsequent first shift register are provided by the same clock line;

[0039] The first clock signal corresponding to the second shift register of the k-th stage and the first clock signal corresponding to the first shift register of the (k + 3)-th stage are provided by the same clock line; the second clock signal corresponding to the second shift register of the k-th stage and the second clock signal corresponding to the first shift register of the (k + 3)-th stage are provided by the same clock line;

[0040] Preferably, the first clock signal of the first shift register of the first stage is provided by the fourth clock line; the first clock signal of the first shift register of the k1-th stage is provided by the j-th clock line; j is equal to the remainder of k1 divided by 4 minus 1; k1 is greater than 1.

[0041] Optionally, the shift register further includes a third output module, configured to output the first power voltage according to the signal of the first node and output a third clock signal according to the signal of the second node;

[0042] The display panel includes six clock lines;

[0043] The display panel includes n rows of the pixel circuits, n + 3 stages of the first shift register, and n stages of the second shift register; n is an integer greater than or equal to 1;

[0044] The second output module of the k-th stage of the first shift register is electrically connected to the first initialization modules of the (2*k)-th stage and the (2*k - 1)-th stage of the pixel circuits;

[0045] The second output module of the k-th stage of the second shift register is electrically connected to the threshold compensation modules of the (2*k)-th stage and the (2*k - 1)-th stage of the pixel circuits;

[0046] Among two adjacent stages of the first shift register, for one stage of the first shift register, the first clock signal is provided by the second clock line, the second clock signal is provided by the fifth clock line, and the third clock signal is provided by the sixth clock line; for the other stage of the first shift register, the first clock signal is provided by the first clock line, the second clock signal is provided by the third clock line, and the third clock signal is provided by the fourth clock line;

[0047] The first clock signal corresponding to the k-th stage of the second shift register and the first clock signal corresponding to the (k + 3)-th stage of the first shift register are provided by the same clock line; the second clock signal corresponding to the k-th stage of the second shift register and the second clock signal corresponding to the (k + 3)-th stage of the first shift register are provided by the same clock line; the third clock signal corresponding to the k-th stage of the second shift register and the third clock signal corresponding to the (k + 3)-th stage of the first shift register are provided by the same clock line;

[0048] Preferably, the first clock signal of the first stage of the first shift register is provided by the second clock line.

[0049] Optionally, the shift register further includes a third output module, configured to output the first power voltage according to the signal of the first node and output a third clock signal according to the signal of the second node;

[0050] The display panel includes six clock lines;

[0051] The display panel includes n rows of the pixel circuits, n+2 stages of the first shift registers, and n stages of the second shift registers; n is an integer greater than or equal to 1;

[0052] The second output module of the k-th stage of the first shift register is electrically connected to the first initialization modules of the pixel circuits of the (2*k)-th stage and the (2*k-1)-th stage;

[0053] The second output module of the k-th stage of the second shift register is electrically connected to the threshold compensation modules of the pixel circuits of the (2*k)-th stage and the (2*k-1)-th stage;

[0054] Among three adjacent stages of the first shift registers, the first clock signal of the first stage of the first shift registers is provided by the j1-th clock line, where j1 is an odd number less than or equal to 5; the first clock signal of the second stage of the first shift registers is provided by the j2-th clock line; the first clock signal of the third stage of the first shift registers is provided by the j3-th clock line; wherein, if j1 is less than or equal to 3, then j2 is equal to j1 plus 2, if j1 is equal to 5, then j2 is equal to 1; if j2 is less than or equal to 3, then j3 is equal to j2 plus 2, if j2 is equal to 5, then j3 is equal to 1; among two adjacent stages of the first shift registers, the first clock signal of the subsequent stage of the first shift registers and the second clock signal of the previous stage of the first shift registers are provided by the same clock line; in the same stage of the first shift registers, the second clock signal is provided by the a-th clock line, and the third clock signal is provided by the b-th clock line, where b is equal to a plus 1;

[0055] The first clock signal corresponding to the k-th stage of the second shift register and the first clock signal corresponding to the (k+2)-th stage of the first shift register are provided by the same clock line; the second clock signal corresponding to the k-th stage of the second shift register and the second clock signal corresponding to the (k+2)-th stage of the first shift register are provided by the same clock line; the third clock signal corresponding to the k-th stage of the second shift register and the third clock signal corresponding to the (k+2)-th stage of the first shift register are provided by the same clock line;

[0056] Preferably, the first clock signal of the first stage of the first shift register is provided by the first clock line.

[0057] According to another aspect of the present invention, there is provided a display device, which includes the display panel as described above.

[0058] The technical solution of the embodiment of the present invention uses a shift register including: an input module, a first control module, a second control module, a first output module, and a second output module; the input module is used to transmit an input signal to the control end of the first control module and the first end of the second control module according to a first clock signal; the first control module is used to transmit a signal opposite to the logic of its control end to a first node; and transmit a signal opposite to the logic of the first node to a second node; the second control module is used to transmit the signal at its first end to the second node according to the first clock signal; wherein, the conduction level logic of the second control module is opposite to that of the input module; the first output module is used to output a first power supply voltage according to the signal of the first node, and output a second clock signal according to the signal of the second node; the second output module is used to output a second power supply voltage according to the signal of the first node, and output a first power supply voltage according to the signal of the second node. The first output module and the second output module can output scan signals with different conduction levels, and the conduction levels of the input module and the second control module are set to be different. The shift register can achieve the above functions with a smaller number of components, thereby greatly reducing the area occupied by the shift register, which is beneficial to reducing the border of the display panel and improving the performance of the shift register.

[0059] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. Brief Description of the Drawings

[0060] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0061] Figure 1 It is a schematic circuit diagram of a shift register provided by an embodiment of the present invention;

[0062] Figure 2 It is a schematic circuit diagram of a pixel circuit provided by an embodiment of the present invention;

[0063] Figure 3 It is a timing diagram of a pixel circuit provided by an embodiment of the present invention;

[0064] Figure 4 It is a schematic circuit diagram of another shift register provided by an embodiment of the present invention;

[0065] Figure 5Schematic diagram of another circuit structure of the shift register provided by the embodiment of the present invention;

[0066] Figure 6 Timing diagram of a shift register provided by the embodiment of the present invention;

[0067] Figure 7 Schematic diagram of a structure of a display panel provided by the embodiment of the present invention;

[0068] Figure 8 For Figure 7 Timing diagram corresponding to the first cascaded shift register;

[0069] Figure 9 Schematic diagram of another structure of a display panel provided by the embodiment of the present invention;

[0070] Figure 10 For Figure 9 Timing diagram corresponding to the first cascaded shift register;

[0071] Figure 11 Schematic diagram of another structure of a display panel provided by the embodiment of the present invention;

[0072] Figure 12 Schematic diagram of another structure of a display panel provided by the embodiment of the present invention;

[0073] Figure 13 For Figure 12 Timing diagram corresponding to the first cascaded shift register;

[0074] Figure 14 Schematic diagram of a structure of a display device provided by the embodiment of the present invention. Detailed implementation manners

[0075] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0076] It should be noted that the terms "first", "second", etc. in the specification, claims and the above drawings of the present invention are used to distinguish similar objects and do not necessarily describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0077] There are problems with the poor performance of the shift register in the related art. After a large amount of research by the inventors, it is found that the reason for this technical problem is that: in the related art, the demand for a display panel is narrow bezel and low power consumption, while there are many components in the shift register in the related art, and the occupied space is large. And it is necessary to use a variety of different types of shift registers to generate different scan signals, which will also make the number of shift registers required in the display panel relatively large, and the occupied space of the display panel will be even larger.

[0078] In view of the above technical problems, the present invention proposes the following solutions:

[0079] Figure 1 It is a schematic circuit diagram of a shift register provided for an embodiment of the present invention. Refer to Figure 1 The shift register includes an input module 11, a first control module 12, a second control module 13, a first output module 14 and a second output module 15; the input module 11 is used to transmit the input signal IN to the input end of the first control module 12 and the first end of the second control module 13 according to the first clock signal CK1; the first control module 12 is used to transmit a signal opposite to the logic of its control end to the first node QB, and transmit a signal opposite to the logic of the first node QB to the second node Q; the second control module 13 is used to transmit the signal at its first end to the second node Q according to the first clock signal CK1; wherein, the conduction voltage logic of the second control module 13 is opposite to that of the input module 11; the first output module 14 is used to output the first power supply voltage VGH according to the signal of the first node QB, and output the second clock signal CK2 according to the signal of the second node Q; the second output module 15 is used to output the second power supply voltage VGL according to the signal of the first node QB, and output the first power supply voltage VGH according to the signal of the second node Q.

[0080] Specifically, the shift register can shift the input signal IN and then output it, so as to provide a scan signal for the pixel circuit in the display panel. In some embodiments, the pixel circuit requires multiple scan signals. For example, it requires both a scan signal that conducts when the level is high and a scan signal that conducts when the level is low. Herein, the level conduction mentioned refers to that when this level is input to the corresponding module, it can make the corresponding module conduct. In addition, there needs to be a certain dependency relationship between the respective scan signals corresponding to the pixel circuit. For example, when a certain scan signal conducts, another scan signal must be turned off (controlling the corresponding module to turn off). In the related art, implementing the above functions requires a relatively complex shift register circuit, which is not conducive to narrow borders.

[0081] In this embodiment, only a small number of components are required to implement the function of simultaneously outputting two different scan signals. More specifically, the first output module 14 is used to output a scan signal that is shifted relative to the input signal, hereinafter referred to as the first output signal Pout1. The second output module 15 is used to output a scan signal that is related to the first clock signal CK1 and has a conduction level different from that of the second output signal, hereinafter referred to as the second output signal Nout. The conduction level of the first output signal Pout1 can be a low level, which can be used to drive the PMOS transistor in the pixel circuit; the conduction level of the second output signal Nout can be a high level, which can be used to drive the NMOS transistor in the pixel circuit.

[0082] The conduction levels of the input module 11 and the second control module 13 are logically opposite. That is to say, if the conduction level of the input module 11 is a low level, then the conduction level of the second control module 13 is a high level; conversely, if the conduction level of the input module 11 is a high level, then the conduction level of the second control module 13 is a low level. And since the control terminals of the input module 11 and the second control module 13 are both connected to the first clock signal CK1, that is, both control terminals are connected to the same periodically changing signal, then the input module 11 and the second control module 13 are both periodically conducting and turning off, and their conduction states are opposite. The periods of the first clock signal CK1 and the second clock signal CK2 are the same, and within the same clock period, the pulse of the second clock signal CK2 is later than the pulse of the first clock signal CK1, and the pulses of the first clock signal CK1 and the second clock signal CK2 do not overlap in time. That is to say, the second clock signal CK2 can be understood as a signal that is shifted backward in time sequence relative to the first clock signal CK1. The pulse mentioned herein is a level with a small duty cycle, such as a low level.

[0083] By configuring the conduction level of the input signal IN (for example, a low level) within the conduction level of the first clock signal CK1 corresponding to the input module 11 (i.e., a low level), the first output signal Pout1 can be shifted relative to the input signal IN by a certain amount.

[0084] When the first clock signal CK1 is at a low level and the input signal IN is at a low level, the input module 11 is turned on, enabling the low-level input signal IN to be transmitted to the input terminal of the first control module 12 and the first terminal of the second control module 13; at this time, the first control module 12 transmits a high level to the first node QB, and at this time, the first node QB is at a turn-off level; and at this time, the second output module 13 is turned off, so the second node Q becomes a low level under the control of the first node QB and the first control module 12. In summary, at this time, the output of the first output module 14 follows the second clock signal CK2.

[0085] In the next stage, the first clock signal CK1 is at a high level and the second clock signal CK2 is at a low level. At this time, the input module 11 is turned off and the second control module 13 is turned on. Then, the second control module 13 transmits the low level at its first terminal in the previous moment to the second node Q. The first output module 14 responds to the low level on the second node Q, so that the first output signal Pout1 follows the action of the second clock signal CK2, that is, a low level is output.

[0086] In the next clock cycle, when the first clock signal CK1 becomes low again, at this time the input signal IN is at a high level. Therefore, the first control module 12 will output a low level to the first node QB, and the first output signal Pout1 output by the first output module 14 becomes the first power supply voltage VGH. The second node Q is at a high level, and in the next stage, when the second control module 13 is turned on, it transmits the high level at its first terminal to the second node Q. In summary, for the shift register of this embodiment, the pulse timing of the first output signal Pout1 is the same as the pulse timing of the second clock signal CK2 within the clock cycle in which the input signal IN pulse is located, and there is only one pulse of the first output signal Pout1 within one frame time. Therefore, it can be used as a scanning signal in the pixel circuit, such as a scanning signal for driving a P-type transistor.

[0087] For the second output module 15, when the first clock signal CK1 is at a low level and the input signal IN is at a low level, the input module 11 is turned on, enabling the low-level input signal IN to be transmitted to the control terminal of the first control module 12 and the first terminal of the second control module 13; at this time, the first control module 12 transmits a high level to the first node QB, and at this time, the first node QB is at a turn-off level; and at this time, the second output module 13 is turned off, and the second node Q is controlled by the first control module 12 to become a low level. The second output module 15 outputs the first power supply voltage (high level) in response to the level of the second node Q.

[0088] In the next clock cycle, when the first clock signal CK1 becomes low again, and at this time the input signal IN is high, the first control module 12 will output a low level to the first node QB, thereby causing the second output module 15 to output the second power supply voltage (low level) in response to the level on the first node QB. In summary, for the shift register of this embodiment, the start time of the pulse of the second output signal Nout is the same as the start time of the pulse of the first clock signal CK1 within the first clock cycle, the end time of the pulse of the second output signal Nout is the same as the start time of the pulse of the first clock signal CK1 within the second clock cycle, and there is only one pulse for the first output signal Pout1 within one frame time. Therefore, it can be used as a scanning signal in a pixel circuit, such as a scanning signal for driving an N-type transistor.

[0089] The technical solution of this embodiment uses a shift register including: an input module, a first control module, a second control module, a first output module, and a second output module; the input module is used to transmit the input signal to the control end of the first control module and the first end of the second control module according to the control of the first clock signal; the first control module is used to transmit a signal opposite to the logic of its control end to the first node; and transmit a signal opposite to the logic of the first node to the second node; the second control module is used to transmit the signal at its first end to the second node according to the first clock signal; wherein, the conduction level logic of the second control module is opposite to that of the input module; the first output module is used to output the first power supply voltage according to the signal of the first node, and output the second clock signal according to the signal of the second node; the second output module is used to output the second power supply voltage according to the signal of the first node, and output the first power supply voltage according to the signal of the second node. The first output module and the second output module can output scanning signals with different conduction levels, and by setting the conduction levels of the input module and the second control module to be different, the shift register can achieve the above functions with a smaller number of components, thereby greatly reducing the area occupied by the shift register, which is beneficial to reducing the border of the display panel and improving the performance of the shift register.

[0090] In addition, multiple shift registers can be used in cooperation to drive the pixel circuit, enabling the pixel circuit to work stably, and this part will be described later.

[0091] For ease of explanation, first, a brief introduction to the pixel circuit that can be driven by the shift register of this embodiment is given.

[0092] Figure 2 It is a schematic circuit diagram of a pixel circuit provided by an embodiment of the present invention. Figure 3 It is a timing diagram of a pixel circuit provided by an embodiment of the present invention. Figure 3 And Figure 2 corresponds to. Refer to Figure 2, the pixel circuit includes: a driving transistor M1, a data writing transistor M2, a threshold compensation transistor M3, a first initialization transistor M4, a first light-emitting control transistor M5, a second light-emitting control transistor M6, a second initialization transistor M7, a third initialization transistor M8, a storage capacitor Cst, and a light-emitting element 9. Among them, the first terminal of the data writing transistor M2 is connected to a data voltage Data, the second terminal of the data writing transistor M2 is electrically connected to the first terminal of the driving transistor M1, and the control terminal of the data writing transistor M2 is connected to a second scan signal S2. The first terminal of the threshold compensation transistor M3 is electrically connected to the second terminal of the driving transistor M1, the second terminal of the threshold compensation transistor M3 is electrically connected to the control terminal of the driving transistor M1, and the control terminal of the threshold compensation transistor M3 is connected to a third scan signal S3; the first terminal of the first initialization transistor M4 is connected to a first initialization signal Vref1, the second terminal of the first initialization transistor M4 is electrically connected to the first terminal of the threshold compensation transistor M3, and the control terminal of the first initialization transistor M4 is connected to a first scan signal S1; the first terminal of the first light-emitting control transistor M5 is connected to a first power supply signal ELVDD, the second terminal of the first light-emitting control transistor M5 is electrically connected to the first terminal of the driving transistor M1, and the control terminal of the first light-emitting control transistor M5 is connected to a light-emitting control signal EM; the first terminal of the second light-emitting control transistor M6 is electrically connected to the second terminal of the driving transistor M1, the second terminal of the second light-emitting control transistor M6 is electrically connected to the first terminal of the light-emitting element 9, and the control terminal of the second light-emitting control transistor M6 is connected to the light-emitting control signal EM; the first terminal of the second initialization transistor M7 is connected to a second initialization signal Vref2, the second terminal of the second initialization transistor M7 is electrically connected to the first terminal of the light-emitting element 9, and the control terminal of the second initialization transistor M7 is connected to a fourth scan signal S4; the first terminal of the third initialization transistor M8 is connected to a third initialization signal Vref3, the second terminal of the third initialization transistor M8 is electrically connected to the second terminal of the driving transistor M1, and the control terminal of the third initialization transistor M8 is connected to the fourth scan signal S4; the second terminal of the light-emitting element 9 is connected to a second power supply signal ELVSS; the first terminal of the storage capacitor Cst is connected to the first power supply signal ELVDD, and the second terminal of the storage capacitor Cst is electrically connected to the control terminal of the driving transistor M1. Among them, the threshold compensation transistor M3 and the first initialization transistor M4 can be N-type oxide transistors to reduce leakage current and are more suitable for low-frequency display. The remaining transistors can be P-type low-temperature polycrystalline silicon transistors.

[0093] As Figure 3 shown, the working process of the pixel circuit includes a first initialization stage t11, a charging stage t12, a second initialization stage t13, and a light-emitting stage t14.

[0094] In the first initialization stage t11, the first scan signal S1 controls the first initialization transistor M4 to turn on, and the third scan signal S3 controls the threshold compensation transistor M3 to turn on. The gate of the driving transistor M1 is initialized using the first initialization signal Vref1.

[0095] In the charging stage t12, the second scan signal S2 controls the data writing transistor M2 to turn on, and the third scan signal S3 controls the threshold compensation transistor M3 to turn on. In this stage, the data voltage Data is written into the control terminal of the driving transistor M1, and the threshold compensation of the driving transistor M1 is completed in this stage.

[0096] In the second initialization stage t13, the fourth scan signal S4 controls the second initialization transistor M7 and the third initialization transistor M8 to turn on. The second initialization signal Vref2 and the third initialization signal Vref3 respectively complete the initialization of the first end of the light-emitting element 9 and the second end of the driving transistor M1.

[0097] In the light-emitting stage t14, the light-emitting control signal EM controls the first light-emitting control transistor M5 and the second light-emitting control transistor M6 to turn on. The driving transistor M1 generates a driving current, and the light-emitting element 9 emits light in response to the driving current.

[0098] From the above analysis and Figure 3 it can be seen that in the first initialization stage t11, the first scan signal S1 and the third scan signal S3 need to be at the conductive level; in the charging stage t12, the first scan signal S1 needs to be at the non-conductive level, and the second scan signal S2 and the third scan signal S3 need to be at the conductive level. If different shift registers are designed separately for the first scan signal S1 and the third scan signal S3, complex circuits and more clocks will be required. However, the shift register of this embodiment can output both the first scan signal S1 and the third scan signal S3 (which will be described in more detail in the subsequent display panel section). Therefore, the shift register structure required on the display panel is simpler and more conducive to realizing a narrow border.

[0099] Optionally, Figure 4 is a schematic circuit diagram of another shift register provided by an embodiment of the present invention. Referring to Figure 4 , the shift register further includes a third output module 16. The third output module 16 is configured to output the first power supply voltage VGH according to the signal of the first node QB and output the third clock signal CK3 according to the signal of the second node Q.

[0100] Specifically, the third clock signal CK3 has the same clock period as the first clock signal CK1, and the pulse duty cycle of the third clock signal CK3 is the same as that of the first clock signal CK1. Within the same clock period, the pulse of the third clock signal CK3 is later than the pulse of the second clock signal CK2. Or rather, the third clock signal CK3 is a clock signal with a time sequence shifted backward relative to the second clock signal CK2. The function of the third output module 16 is the same as that of the first output module 14, so it also has a similar time sequence, that is, the pulse time sequence of the output of the third output module 16 (hereinafter referred to as the third output signal Pout2) is the same as the pulse time sequence of the third clock signal CK3 within the clock period in which the input signal IN pulse is located, and there is only one pulse of the third output signal Pout2 within one frame time. Therefore, it can be used as a scanning signal in the pixel circuit, such as a scanning signal for driving a P-type transistor. And since the third output signal Pout2 is time-sequentially shifted backward relative to the first output signal Pout1, it can be used as a driving signal for different rows of pixel circuits. That is to say, the shift register of this embodiment can simultaneously provide scanning signals for driving P-type transistors for two rows of pixel circuits, thereby further reducing the number of components and further reducing the border of the display panel.

[0101] Optionally, Figure 5 is a schematic circuit diagram of another shift register provided by an embodiment of the present invention. Refer to Figure 5 . The first output module 14 includes a first pull-up unit 141, a first pull-down unit 142, and a first coupling unit 143; the first end of the first pull-up unit 141 is connected to the first power supply voltage VGH, the control end of the first pull-up unit 141 is electrically connected to the first node QB, and the second end of the first pull-up unit 141 is electrically connected to the output end of the first output module 14; the first end of the first pull-down unit 142 is connected to the second clock signal CK2, the control end of the first pull-down unit 142 is electrically connected to the second node Q, and the second end of the first pull-down unit 142 is electrically connected to the output end of the first output module 14; the first end of the first coupling unit 143 is electrically connected to the second end of the first pull-down unit 142, and the second end of the first coupling unit 143 is electrically connected to the control end of the first pull-down unit 142.

[0102] Specifically, when the first node QB is at a conductive level (low level), the first pull-up unit 141 is turned on, thereby controlling the output terminal of the first output module 14 to output the first power supply voltage VGH, that is, the first output signal Pout1 follows the first power supply voltage VGH. When the second node Q is at a conductive level (low level), the first pull-down unit 142 is turned on, thereby controlling the output terminal of the first output module 14 to output the second clock signal CK2, that is, the first output signal Pout1 follows the second clock signal CK2. The first coupling unit 143 can couple the first output signal Pout1 to the control terminal of the first pull-down unit 142, making the conduction degree of the first pull-down unit 142 deeper. In this embodiment, the functions of the first output module 14 can be realized by using three simple units, and the circuit structure is simpler.

[0103] Optionally, continue to refer to Figure 5 , the third output module 16 includes a second pull-up unit 161, a second pull-down unit 162, and a second coupling unit 163; the second pull-up unit 161 is connected to the first power supply voltage VGH, the control terminal of the second pull-up unit 161 is electrically connected to the first node QB, and the second terminal of the second pull-up unit 161 is electrically connected to the output terminal of the second output module 16; the first terminal of the second pull-down unit 162 is connected to the third clock signal CK3, the control terminal of the second pull-down unit 162 is electrically connected to the second node Q, and the second terminal of the second pull-down unit 162 is electrically connected to the output terminal of the second output module 16; the first terminal of the second coupling unit 163 is electrically connected to the second terminal of the second pull-down unit 162, and the second terminal of the second coupling unit 163 is electrically connected to the control terminal of the second pull-down unit 162.

[0104] Specifically, when the first node QB is at a conductive level (low level), the second pull-up unit 161 is turned on, thereby controlling the output terminal of the second output module 16 to output the first power supply voltage VGH, that is, the second output signal Pout2 follows the first power supply voltage VGH. When the second node Q is at a conductive level (low level), the second pull-down unit 162 is turned on, thereby controlling the output terminal of the second output module 16 to output the third clock signal CK3, that is, the second output signal Pout2 follows the third clock signal CK3. The second coupling unit 163 can couple the second output signal Pout2 to the control terminal of the second pull-down unit 162, making the conduction degree of the second pull-down unit 162 deeper. In this embodiment, the functions of the second output module 16 can be realized by using three simple units, and the circuit structure is simpler.

[0105] Optionally, continue to refer to Figure 5, the first control module 12 includes a first inverter unit 121 and a second inverter unit 122; the input end of the first inverter unit 121 is electrically connected to the input end of the first control module 12, and the output end of the first inverter unit 121 is electrically connected to the first node QB; the input end of the second inverter unit 122 is electrically connected to the first node QB, and the output end of the second inverter unit 122 is electrically connected to the second node Q.

[0106] Specifically, in this embodiment, the first inverter unit 121 and the second inverter unit 122 are adopted to implement all functions of the first control module 12, and the circuit structure is simple. Moreover, when the second control module 12 is turned on and the input module 11 is turned off, the output end of the second inverter unit 122 is electrically connected to the input end of the first inverter unit 121, and the first inverter unit 121 and the second inverter unit 122 form a latch, so that the stability of the first node QB and the second node Q can be maintained without external input, that is, the power consumption of the shift register is relatively low, and the power consumption of the display panel can be reduced.

[0107] Further, the first end of the input module 11 is connected to the input signal IN, the second end of the input module 11 is electrically connected to the input end of the first inverter unit 121 and the first end of the second control module 13, and the control end of the input module 11 is connected to the first clock signal CK1. The second end of the second control module 13 is electrically connected to the second node Q, and the control end of the second control module 13 is connected to the first clock signal CK1.

[0108] Optionally, continue to refer to Figure 5 , the second output module 15 includes a third pull-up unit 151, a third pull-down unit 152, a third coupling unit 153, and a fourth pull-down unit 154; the first end of the third pull-up unit 151 is connected to the first power supply voltage VGH, the control end of the third pull-up unit 151 is electrically connected to the second node Q, and the second end of the third pull-up unit 151 is electrically connected to the output end of the second output module 15; the fourth pull-down unit 154 is configured to output the third power supply voltage VGL2 to the control end of the third pull-down unit 152 according to the potential of the first node QB, and output the first power supply voltage VGH to the control end of the third pull-down unit 152 according to the potential of the second node Q; the first end of the third pull-down unit 152 is connected to the second power supply voltage VGH, and the second end of the third pull-down unit 152 is electrically connected to the output end of the second output module 15; the first end of the third coupling unit 153 is electrically connected to the first end of the third pull-up unit 151, and the second end of the third coupling unit 153 is electrically connected to the control end of the third pull-up unit 151.

[0109] Specifically, in this embodiment, the logic of the signal output by the fourth pull-down unit 154 to the control terminal of the third pull-down unit 152 is the same as the logic of the first node QB. That is, when the first node QB is at a low level, the signal output to the control terminal of the third pull-down unit 152 is also at a low level; when the first node QB is at a high level, the level output to the control terminal of the third pull-down unit 152 is at a high level. The third power supply voltage VGL2 cooperates with the second power supply voltage VGL to enable the third pull-down unit 152 to conduct. That is, the fourth pull-down unit in this embodiment can also be understood as a voltage modulation unit, and the voltage modulation unit can modulate the conduction level of the first node QB to the third power supply voltage and output it to the control terminal of the third pull-down unit 152.

[0110] Optionally, continuing to refer to Figure 5 , the fourth pull-down unit 154 includes a first sub-switch unit 1541, a first sub-switch unit 1542, a third sub-switch unit 1543, and a fourth sub-switch unit 1544; the first end of the first sub-switch unit 1541 is connected to the first power supply voltage, the second end of the first sub-switch unit 1541 is electrically connected to the first end of the first sub-switch unit 1542, and the control terminal of the first sub-switch unit 1541 is connected to the first node; the second end of the first sub-switch unit 1542 is connected to the third power supply voltage; the first end of the third sub-switch unit 1543 is connected to the first power supply voltage, the second end of the third sub-switch unit 1543 is electrically connected to the first end of the fourth sub-switch unit 1544, the second end of the fourth sub-switch unit 1544 is connected to the third power supply voltage, and the control terminal of the third sub-switch unit 1543 is connected to the second node; the control terminal of the first sub-switch unit 1542 is electrically connected to the second end of the third sub-switch unit 1543, and the control terminal of the fourth sub-switch unit 1544 is electrically connected to the second end of the first sub-switch unit 1541; the second end of the third sub-switch unit 1543 is connected to the control terminal of the third pull-down unit; the transistor channel types of the first sub-switch unit 1541 and the first sub-switch unit 1542 are different, the transistor channel types of the third sub-switch unit 1543 and the fourth sub-switch unit 1544 are different, and the transistor channel types of the first sub-switch unit 1541 and the third sub-switch unit 1543 are the same.

[0111] Specifically, the first sub-switching unit 1541 and the third sub-switching unit 1543 can be P-channel transistors, and the second sub-switching unit 1542 and the fourth sub-switching unit 1544 can be N-channel transistors. When the first node QB is at a low level, the second node Q is correspondingly at a high level. At this time, the first sub-switching unit 1541 is turned on, which in turn causes the fourth sub-switching unit 1544 to be turned on. The fourth pull-down unit 154 outputs the third power supply voltage VGL2 to the control terminal of the third pull-down unit 152. The third power supply voltage VGL2 is less than the second power supply voltage VGL, so that the third pull-down unit 152 is turned on. When the first node QB is at a high level, the second node Q is correspondingly at a low level. At this time, the third sub-switching unit 1543 is turned on, and the fourth pull-down unit 154 outputs the first power supply voltage VGH to the control terminal of the third pull-down unit 152; at the same time, the second sub-switching unit 1542 is turned on, so that the control terminal of the fourth sub-switching unit 1544 is connected to the third power supply voltage VGL2, ensuring that the fourth sub-switching unit 1544 is turned off. That is to say, the fourth pull-down unit 154 in this embodiment can make the signal output to the third pull-down unit 152 stable.

[0112] In addition, when the first node QB is at a high level and the second node Q is at a low level, the third pull-up unit 151 is turned on, and the second output signal Nout follows the first power supply voltage VGH. When the first node QB is at a low level and the second node Q is at a high level, the third pull-down unit 152 is turned on, and the second output signal Nout follows the second power supply voltage VGL. The third coupling unit 153 can maintain the stability of the potential of the control terminal of the third pull-up unit 151.

[0113] Optionally, continue to refer to Figure 5 , the input module 11 includes a first transistor T1, and the first transistor T1 can be a P-channel transistor. The first end of the first transistor T1 serves as the first end of the input module 11, the second end of the first transistor T1 serves as the second end of the input module 11, and the control end of the first transistor T1 serves as the control end of the input module 11.

[0114] The first inverting unit 121 can be a complementary metal oxide inverter, specifically including a second transistor T2 and a third transistor T3. The second transistor T2 is a P-channel transistor, and the third transistor T3 is an N-channel transistor; the control ends of the second transistor T2 and the third transistor T3 are electrically connected and then serve as the input end of the first inverting unit 121; the first ends of the second transistor T2 and the third transistor T3 are electrically connected and then serve as the output end of the first inverting unit 121; the second end of the second transistor T2 is connected to the first power supply voltage VGH, and the second end of the third transistor T3 is connected to the second power supply voltage VGL.

[0115] The second inverter unit 122 may be a complementary metal-oxide inverter, specifically including a fourth transistor T4 and a fifth transistor T5. The fourth transistor T4 is a P-channel transistor, and the fifth transistor T5 is an N-channel transistor. The control terminals of the fourth transistor T4 and the fifth transistor T5 are electrically connected and serve as the input terminal of the second inverter unit 122. The first terminals of the fourth transistor T4 and the fifth transistor T5 are electrically connected and serve as the output terminal of the second inverter unit 122. The second terminal of the fourth transistor T4 is connected to the first power supply voltage VGH, and the second terminal of the fifth transistor T5 is connected to the second power supply voltage VGL.

[0116] The first pull-up unit 141 includes a sixth transistor T6. The sixth transistor T6 may be a P-channel transistor. The first terminal of the sixth transistor T6 serves as the first terminal of the first pull-up unit 141, the second terminal of the sixth transistor T6 serves as the second terminal of the first pull-up unit 141, and the control terminal of the sixth transistor T6 serves as the control terminal of the first pull-up unit 141.

[0117] The first pull-down unit 142 includes a seventh transistor T7. The seventh transistor T7 may be a P-channel transistor. The first terminal of the seventh transistor T7 serves as the first terminal of the first pull-down unit 142, the second terminal of the seventh transistor T7 serves as the second terminal of the first pull-down unit 142, and the control terminal of the seventh transistor T7 serves as the control terminal of the first pull-down unit 142.

[0118] The shift register further includes an eighth transistor T8. The eighth transistor T8 is a normally open transistor, and its control terminal is connected to the second power supply voltage VGL. The second node Q is electrically connected to the control terminal of the seventh transistor T7 through the eighth transistor T8. Setting the eighth transistor T8 can reduce the leakage current.

[0119] The first coupling unit 143 includes a first capacitor C1. The first terminal of the first capacitor C1 serves as the first terminal of the first coupling unit 143, and the second terminal of the first capacitor C1 serves as the second terminal of the first coupling unit 143.

[0120] The third pull-up unit 151 includes a ninth transistor T9. The ninth transistor T9 may be a P-channel transistor. The first terminal of the ninth transistor T9 serves as the first terminal of the third pull-up unit 151, the second terminal of the ninth transistor T9 serves as the second terminal of the third pull-up unit 151, and the control terminal of the ninth transistor T9 serves as the control terminal of the third pull-up unit 151.

[0121] The third pull-down unit 152 includes a tenth transistor T10. The tenth transistor T10 may be a P-channel transistor. The first terminal of the tenth transistor T10 serves as the first terminal of the third pull-down unit 152, the second terminal of the tenth transistor T10 serves as the second terminal of the third pull-down unit 152, and the control terminal of the tenth transistor T10 serves as the control ground of the third pull-down unit 152.

[0122] The third coupling unit 153 includes a second capacitor C2. The first end of the second capacitor C2 serves as the first end of the third coupling unit 153, and the second end of the second capacitor C2 serves as the second end of the third coupling unit 153.

[0123] The second control module 13 includes an eleventh transistor T11. The eleventh transistor T11 may be a P-channel transistor. The first end of the eleventh transistor T11 serves as the first end of the second control module 13, the second end of the eleventh transistor T11 serves as the second end of the second control module 13, and the control end of the eleventh transistor T11 serves as the control end of the second control module 13.

[0124] The first sub-switching unit 1541 includes a twelfth transistor T12. The first end of the twelfth transistor T12 serves as the first end of the first sub-switching unit 1541, the second end of the twelfth transistor T12 serves as the second end of the first sub-switching unit 1541, and the control end of the twelfth transistor T12 serves as the control end of the first sub-switching unit 1541.

[0125] The second sub-switching unit 1542 includes a thirteenth transistor T13. The first end of the thirteenth transistor T13 serves as the first end of the second sub-switching unit 1542, the second end of the thirteenth transistor T13 serves as the second end of the second sub-switching unit 1542, and the control end of the thirteenth transistor T13 serves as the control end of the second sub-switching unit 1542.

[0126] The third sub-switching unit 1543 includes a fourteenth transistor T14. The first end of the fourteenth transistor T14 serves as the first end of the third sub-switching unit 1543, the second end of the fourteenth transistor T14 serves as the second end of the third sub-switching unit 1543, and the control end of the fourteenth transistor T14 serves as the control end of the third sub-switching unit 1543.

[0127] The fourth sub-switching unit 1544 includes a fifteenth transistor T15. The first end of the fifteenth transistor T15 serves as the first end of the fourth sub-switching unit 1544, the second end of the fifteenth transistor T15 serves as the second end of the fourth sub-switching unit 1544, and the control end of the fifteenth transistor T15 serves as the control end of the fourth sub-switching unit 1544.

[0128] The second pull-up unit 161 includes a sixteenth transistor T16. The sixteenth transistor T16 may be a P-channel transistor. The first end of the sixteenth transistor T16 serves as the first end of the second pull-up unit 161, the second end of the sixteenth transistor T16 serves as the second end of the second pull-up unit 161, and the control end of the sixteenth transistor T16 serves as the control end of the second pull-up unit 161.

[0129] The second pull-down unit 162 includes a seventeenth transistor T17, which may be a P-channel transistor. The first end of the seventeenth transistor T17 serves as the first end of the second pull-down unit 162, the second end of the seventeenth transistor T17 serves as the second end of the second pull-down unit 162, and the control end of the seventeenth transistor T17 serves as the control end of the second pull-down unit 162.

[0130] The second coupling unit 163 includes a third capacitor C3. The first end of the third capacitor C3 serves as the first end of the second coupling unit 163, and the second end of the third capacitor C3 serves as the second end of the second coupling unit 163.

[0131] The shift register further includes an eighteenth transistor T18, which is a normally-on transistor. Its control end is connected to the second power supply voltage VGL. The second node Q is electrically connected to the control end of the seventeenth transistor T17 through the eighteenth transistor T18. Setting the eighteenth transistor T18 can reduce the leakage current.

[0132] The working principle of the following in combination with the timing Figure 5 will be described. Figure 6 FIG. is a timing diagram of a shift register provided by an embodiment of the present invention. Figure 6 corresponding to Figure 5 Combined with Figure 5 and Figure 6 . Among them, the period of each clock signal is TT.

[0133] In the first stage t1, the input signal IN is at a low level, the first clock signal CK1 is at a low level, and the second clock signal CK2 and the third clock signal CK3 are both at a high level. At this time, the first transistor T1 is turned on and the eleventh transistor T11 is turned off. The input end of the first inverter 121 is connected to a low level. Therefore, the second transistor T2 is turned on and the third transistor T4 is turned off, and the first node QB is at a high level. Furthermore, the second node Q is at a low level, the seventh transistor T7 is turned on, the seventeenth transistor T17 is turned on, and both the first output signal Pout1 and the third output signal Pout2 are at a high level. And because the first node QB is at a high level and the second node Q is at a low level, the ninth transistor T9 is turned on and the tenth transistor T10 is turned off, making the second output signal Nout at a high level.

[0134] In the second stage t2, the input signal IN is at a high level, the second clock signal CK2 is at a low level, and the first clock signal CK1 is at a high level. At this time, the eleventh transistor T11 is turned on, and the first inverter 121 and the second inverter 122 form a latch, and the outputs of both remain unchanged. That is, the first node QB remains at a high level, and the second node Q remains at a low level. Then, since the seventh transistor T7 is turned on, the first output signal Pout1 follows the second clock signal CK2 and is at a low level at this time. The second output signal Nout remains at a high level.

[0135] Similarly, in the third stage t3, the input signal IN is at a high level, and the third clock signal CK3 is at a low level. In this stage, the third output signal Pout2 follows the third clock signal CK3 and is at a low level. The second output signal Nout remains at a high level.

[0136] In the next cycle of the clock, that is, when the low level of the first clock signal CK1 comes again, since the input signal IN is at a high level, the input terminal of the first inverter 121 is at a high level, and then the first node QB is at a low level, and the second node Q is at a high level. Therefore, the tenth transistor T10 is turned on, and the second output signal Nout is at a low level. In the subsequent cycles, since the input signal IN is always at a high level, the input terminal of the first inverter 121 remains at a high level. Then the first node QB remains at a low level, and the second node Q remains at a high level. Then both the sixth transistor T6 and the sixteenth transistor T16 are turned on, and both the first output signal Pout1 and the third output signal Pout2 remain at a high level. And the second output signal Nout remains at a low level.

[0137] Based on the same inventive concept, the present invention also provides a display panel, as Figure 7 shown. Figure 7 FIG. is a schematic structural diagram of a display panel provided by an embodiment of the present invention. The display panel includes multiple rows of pixel circuits PX, for example, including n rows of pixel circuits. The first row of pixel circuits is represented by PX(1), and the nth row of pixel circuits is represented by PX(n). The display panel also includes multiple first shift registers 2 and multiple second shift registers 3. Among them, both the first shift register 2 and the third shift register 3 include the shift register provided by any embodiment of the present invention.

[0138] The pixel circuit includes a data writing module, a driving module, a threshold compensation module, and a first initialization module. The data writing module is used to write a data voltage into the driving module, the threshold compensation module is used to compensate the threshold voltage of the driving module, and the first initialization module is used to initialize the control terminal of the driving module; wherein, the transistor channel types of the threshold compensation module and the first initialization module are different from those of the driving module; the transistor channel type of the data writing module is the same as that of the driving module; the data writing module includes the data writing transistor described above, the driving module includes the driving transistor described above, the threshold compensation module includes the threshold compensation transistor described above, and the first initialization module includes the first initialization transistor described above.

[0139] The second output module of the first shift register 2 is used to drive the first initialization module of the corresponding pixel circuit; that is, the second output signal Nout of the first shift register 2 serves as the first scan signal S1 of the corresponding pixel circuit.

[0140] The second output module of the second shift register 3 is used to drive the threshold compensation module of the corresponding pixel circuit; that is, the second output signal Nout of the second shift register 3 serves as the third scan signal S3 of the corresponding pixel circuit.

[0141] The first output module of the second shift register 3 is used to drive the data writing module of the corresponding pixel circuit; and / or, the first output module of the first shift register 2 is used to drive the data writing module of the corresponding pixel circuit.

[0142] Specifically, in this embodiment, the second output signal Nout output by the second output module of the first shift register 2 can drive the first initialization module in the pixel circuit, or it can be understood that the second output signal Nout of the first shift register 2 can be used as the first scan signal S1 of the corresponding pixel circuit. The first output signal Pout1 of the first shift register 2 can be used as the second scan signal S2 of the corresponding pixel circuit. The second output signal Nout of the second shift register 3 can be used as the third scan signal S3 of the corresponding pixel circuit, and the first output signal Pout1 of the second shift register 3 can be used as the second scan signal S2 of the corresponding pixel circuit. Through the cooperation of the first shift register 2 and the second shift register 3, the first scan signal S1, the second scan signal S2, and the third scan signal S3 corresponding to each pixel circuit can drive the pixel circuit normally. That is, in the first initialization stage, the first scan signal S1 can control the first initialization module to conduct, and the third scan signal S3 can control the threshold compensation module to conduct. In the charging stage, the second scan signal S2 can control the data writing module to conduct, the third scan signal S3 can control the threshold compensation module to conduct, and the first scan signal S1 can control the first initialization module to turn off. Its specific cooperation relationship will be described later. In this embodiment, the second scan signal S2 can be provided by at least one of the first shift register 2 and the second shift register 3. When both the first shift register 2 and the second shift register 3 provide the second scan signal S2, the voltage drop on the scan signal line corresponding to the same row of pixel circuits can be reduced, that is, the second scan signal S2 received by the same row of pixel circuits has better consistency.

[0143] The technical solution of this embodiment can use the same shift register to provide the first scan signal, the second scan signal, and the third scan signal for the pixel circuit, and the circuit structure is simple. Moreover, the space occupied by the shift register is small, which is more conducive to realizing the narrow border of the display panel.

[0144] Optionally, continue to refer to Figure 7 , the display panel includes a total of 3 clock lines, namely the first clock line SCK1, the second clock line SCK2, and the third clock line SCK3; the clock signal periods output by the first clock line SCK1, the second clock line SCK2, and the third clock line SCK3 are the same, and in the same clock cycle, the clock pulse of the second clock line SCK2 lags behind the clock pulse of the first clock line SCK1, and the clock pulse of the third clock line SCK3 lags behind the clock pulse of the second clock line SCK2; the display panel includes n rows of pixel circuits PX, n + 2 stages of the first shift register 2, and n stages of the second shift register 3; n is an integer greater than or equal to 1;

[0145] The first initialization module of the k-th stage pixel circuit is electrically connected to the second output module of the k-th stage first shift register; that is, the first scan signal S1 of the k-th stage pixel circuit PX(k) is the second output signal Nout of the k-th stage first shift register 2(k). The second output signals Nout of the last four stages of the first shift register 2 are not connected to the pixel circuit.

[0146] The threshold compensation module of the k-th stage pixel circuit is electrically connected to the second output module of the k-th stage second shift register 3, where k is an integer greater than or equal to 1. That is, the third scan signal S3 of the k-th stage pixel circuit PX(k) is the second output signal Nout of the k-th stage second shift register 3(k).

[0147] In the same stage of the first shift register 2, the first clock signal CK1 is provided by the a-th clock line, and the second clock signal CK2 is provided by the b-th clock line; where, if a is less than or equal to 2, then b is equal to a + 1, and if a is greater than 2, then b is equal to 1.

[0148] In adjacent stages of the first shift register, the second clock signal CK2 of the previous stage first shift register 2 and the first clock signal CK1 of the next stage first shift register are provided by the same clock line.

[0149] The first clock signal CK1 corresponding to the k-th stage second shift register 3 and the first clock signal corresponding to the (k + 2)-th stage first shift register are provided by the same clock line; the second clock signal corresponding to the k-th stage second shift register and the second clock signal corresponding to the (k + 2)-th stage first shift register are provided by the same clock line.

[0150] Specifically, in this embodiment, the first shift register 2 and the second shift register 3 can be located in different borders of the display panel respectively. For example, the first shift register 2 is located in the left border, and the second shift register 3 is located in the right border. The clock lines can be electrically connected to the sub-clock lines located in the left border and the sub-clock lines located in the right border respectively. For the convenience of description, in this embodiment, the sub-clock lines providing the same signal in the left and right borders are defined as the same clock line. Additionally, it should be noted that the first output signal Pout1 of the previous stage shift register is used as the input signal IN of the next stage shift register. And the input signal IN of the first stage shift register is provided by the driving chip. As Figure 8 shown, Figure 8 For Figure 7 the timing diagram corresponding to the cascaded first shift registers at the intermediate stage. The first stage first shift register 2(1) outputs the first output signal Pout(1) and the second output signal Nout(1), starting from Figure 8As can be seen, there is an overlap in the conduction levels of the second output signal Nout(3) of the third-stage first shift register and the second output signal Nout(1) of the first-stage first shift register in terms of timing. And there is no overlap in the conduction levels of the first output signal Pout1(3) of the third-stage first shift register and the second output signal Nout(1) of the first-stage first shift register in terms of timing. This can meet the driving timing requirements of the pixel circuit. Therefore, by setting the input of the k-th stage second shift register 3 to be the same as the input of the (k + 2)-th stage first shift register, that is, connecting the same clock signal and having the same input signal, various scan signals required for driving the pixel circuit can be generated.

[0151] Optionally, in some embodiments, the first clock signal CK1 of the k-th stage first shift register can be provided by the j-th clock line; j is equal to the remainder of k divided by 3 plus 1. That is to say, the first clock signal CK1 of the first-stage shift register is provided by the second clock line SCK2, the first clock signal CK1 of the second-stage first shift register is provided by the third clock line SCK3; the first clock signal CK1 of the third-stage first shift register is provided by the first clock line SCK1; the first clock signal CK1 of the fourth-stage first shift register is provided by the second clock line SCK1; the first clock signal CK1 of the fifth-stage first shift register is provided by the third clock line SCK1; the first clock signal CK1 of the sixth-stage first shift register is provided by the first clock line SCK1; and so on. The technical solution of this embodiment can make the first shift register and the second shift register generate the timing that meets the requirements of the pixel circuit by using three clock lines, with fewer signal lines required, which is more conducive to wiring.

[0152] Optionally, in some other embodiments, as Figure 9 shown, Figure 9Schematic diagram of another structure of a display panel provided by an embodiment of the present invention. In this embodiment, the display panel includes four clock lines, namely the first clock line SCK1, the second clock line SCK2, the third clock line SCK3, and the fourth clock line SCK4. The clock signal periods output by the first clock line SCK1, the second clock line SCK2, and the third clock line SCK3 are the same. And within the same clock cycle, the clock pulse of the second clock line SCK2 lags behind the clock pulse of the first clock line SCK1, and the clock pulse of the third clock line SCK3 lags behind the clock pulse of the second clock line SCK2; the clock pulse of the fourth clock line SCK4 lags behind the clock pulse of the third clock line SCK3. The display panel includes n rows of pixel circuits, n + 3 stages of first shift registers, and n stages of second shift registers; n is an integer greater than or equal to 1; the first initialization module of the k-th pixel circuit is electrically connected to the second output module of the k-th first shift register 2(k), that is, the second output signal Nout of the k-th first register 2(k) is the first scan signal S1 of the k-th pixel circuit. The threshold compensation module of the k-th pixel circuit is electrically connected to the second output module of the k-th second shift register 3(k), that is, the second output signal Nout of the k-th second shift register is the third scan signal S3 of the k-th pixel circuit. In the same stage of the first shift register, the first clock signal is provided by the a-th clock line, and the second clock signal is provided by the b-th clock line; where if a is less than or equal to 2, then b is equal to a + 1; if a is greater than 2, then b is equal to 1; in adjacent stages of the first shift register, the second clock signal of the previous stage of the first shift register and the first clock signal of the next stage of the first shift register are provided by the same clock line; the first clock signal corresponding to the k-th second shift register and the first clock signal corresponding to the k + 3-th first shift register are provided by the same clock line; the second clock signal corresponding to the k-th second shift register and the second clock signal corresponding to the k + 3-th first shift register are provided by the same clock line.

[0153] Specifically, the first output signal Pout of the previous stage shift register serves as the input signal IN of the next stage shift register. And the input signal IN of the first stage shift register is provided by a driving chip. As Figure 10 shown, Figure 10 is Figure 9 the timing diagram corresponding to the cascaded first shift registers at the intermediate level. The first stage first shift register 2(1) outputs the first output signal Pout1(1) and the second output signal Nout(1), from Figure 10As can be seen, there is an overlap in the conduction levels of the second output signal Nout(4) of the fourth-stage first shift register and the conduction level of the second output signal Nout(1) of the first-stage first shift register in terms of timing. And there is no overlap in the conduction levels of the first output signal Pout1(4) of the fourth-stage first shift register and the conduction level of the second output signal Nout(1) of the first-stage first shift register in terms of timing. This can meet the driving timing requirements of the pixel circuit. Therefore, by setting the input of the k-th stage second shift register 3 to be the same as the input of the (k + 3)-th stage first shift register, that is, the clock signals connected are the same and the input signals are also the same, various scan signals required for driving the pixel circuit can be generated.

[0154] Optionally, in some embodiments, the first clock signal of the first-stage first shift register can be provided by the fourth clock line; the first clock signal of the k1-th stage first shift register can be provided by the j-th clock line; j is equal to the remainder of k1 divided by 4 minus 1; k1 is greater than 1.

[0155] Optionally, in some other embodiments, as Figure 11 shown, Figure 11 is a schematic structural diagram of another display panel provided by an embodiment of the present invention. The shift register further includes the above-mentioned third output module. The display panel includes a total of six clock lines, namely the first clock line SCK1, the second clock line SCK2, the third clock line SCK3, the fourth clock line SCK4, the fifth clock line SCK5, and the sixth clock line SCK6. The clock signals output by the first clock line SCK1, the second clock line SCK2, and the third clock line SCK3 have the same period, and within the same clock period, the clock pulse of the second clock line SCK2 is later than the clock pulse of the first clock line SCK1, and the clock pulse of the third clock line SCK3 is later than the clock pulse of the second clock line SCK2; the clock pulse of the fourth clock line SCK4 is later than the clock pulse of the third clock line SCK3. The clock pulse width of the fifth clock line SCK5 is later than the clock pulse width of the fourth clock line SCK4. The clock pulse width of the sixth clock line SCK6 is later than the clock pulse width of the fifth clock line SCK5. The display panel includes n rows of the pixel circuits, n + 3 levels of the first shift registers, and n levels of the second shift registers; n is an integer greater than or equal to 1;

[0156] The second output module of the k-th stage first shift register is electrically connected to the first initialization modules of the (2*k)-th and (2*k - 1)-th stage pixel circuits;

[0157] The second output module of the k-th stage second shift register is electrically connected to the threshold compensation modules of the (2*k)-th and (2*k - 1)-th stage pixel circuits;

[0158] Among two adjacent levels of the first shift registers, for one level of the first shift register, the first clock signal is provided by the second clock line, the second clock signal is provided by the fifth clock line, and the third clock signal is provided by the sixth clock line; for the other level of the first shift register, the first clock signal is provided by the first clock line, the second clock signal is provided by the third clock line, and the third clock signal is provided by the fourth clock line;

[0159] The first clock signal corresponding to the k-th level of the second shift register and the first clock signal corresponding to the (k + 3)-th level of the first shift register are provided by the same clock line; the second clock signal corresponding to the k-th level of the second shift register and the second clock signal corresponding to the (k + 3)-th level of the first shift register are provided by the same clock line; the third clock signal corresponding to the k-th level of the second shift register and the third clock signal corresponding to the (k + 3)-th level of the first shift register are provided by the same clock line;

[0160] Preferably, the first clock signal of the first shift register at the first level is provided by the second clock line.

[0161] Specifically, in this embodiment, six clock lines can be used to drive the shift register with the third output module. The conduction levels of the second output signal Nout of the k-th level of the first shift register and the second output signal Nout of the (k + 3)-th level of the first shift register overlap. Moreover, the conduction levels of the first output signal Pout1 and the third output signal Pout2 of the (k + 3)-th level of the first shift register do not overlap with the conduction level of the second output signal Nout of the k-th level of the first shift register.

[0162] Optionally, Figure 12 is a schematic structural diagram of another display panel provided by the embodiment of the present invention, Figure 13 is Figure 12 the timing diagram corresponding to the cascaded first shift register, refer to Figure 12 and Figure 13 . The display panel includes n rows of the pixel circuits, n + 2 levels of the first shift registers, and n levels of the second shift registers; n is an integer greater than or equal to 1;

[0163] The second output module of the k-th level of the first shift register is electrically connected to the first initialization modules of the (2*k)-th and (2*k - 1)-th level pixel circuits;

[0164] The second output module of the k-th level of the second shift register is electrically connected to the threshold compensation modules of the (2*k)-th and (2*k - 1)-th level pixel circuits;

[0165] Among adjacent three-stage first shift registers, the first clock signal of the first-stage first shift register is provided by the j1-th clock line, where j1 is an odd number less than or equal to 5; the first clock signal of the second-stage first shift register is provided by the j2-th clock line; the first clock signal of the third-stage first shift register is provided by the j3-th clock line; wherein, if j1 is less than or equal to 3, then j2 is equal to j1 + 2, if j1 is equal to 5, then j2 is equal to 1; if j2 is less than or equal to 3, then j3 is equal to j2 + 2, if j2 is equal to 5, then j3 is equal to 1; among adjacent two-stage first shift registers, the first clock signal of the subsequent-stage first shift register and the second clock signal of the previous-stage first shift register are provided by the same clock line; in the same-stage first shift register, the second clock signal is provided by the a-th clock line, and the third clock signal is provided by the b-th clock line, where b is equal to a + 1;

[0166] The first clock signal corresponding to the k-th stage second shift register and the first clock signal corresponding to the (k + 2)-th stage first shift register are provided by the same clock line; the second clock signal corresponding to the k-th stage second shift register and the second clock signal corresponding to the (k + 2)-th stage first shift register are provided by the same clock line; the third clock signal corresponding to the k-th stage second shift register and the third clock signal corresponding to the (k + 2)-th stage first shift register are provided by the same clock line. The first clock signal of the first shift register of the first stage is provided by the first clock line.

[0167] Specifically, in this embodiment, the first output signal Pout1 of the previous-stage shift register serves as the input signal IN of the subsequent shift register. As Figure 13 shown, there is an overlap in the conduction levels of the second output signal Nout(3) of the third-stage first shift register and the second output signal Nout(1) of the first-stage first shift register in terms of timing. And there is no overlap in the conduction levels of the first output signal Pout1(3) and the second output signal Pout2(3) of the third-stage first shift register and the second output signal Nout(1) of the first-stage first shift register in terms of timing. It can meet the driving timing requirements of the pixel circuit. Therefore, by setting the input of the k-th stage second shift register 3 to be the same as the input of the (k + 2)-th stage first shift register, that is, the accessed clock signals are the same and the input signals are also the same, various scan signals required for driving the pixel circuit can be generated.

[0168] It should be noted that the shift register in this embodiment can also be implemented to drive the pixel circuit in other ways.

[0169] The present invention also provides a display device, as Figure 14 shown, Figure 14Schematic structural diagram of a display device provided by an embodiment of the present invention. The display device includes a display panel provided by any embodiment of the present invention. The display device may be a mobile phone, a tablet computer, an MP3, an MP4, a smart watch, a smart helmet, a video phone, a personal digital assistant, or other wearable devices, etc. Since the display device provided by the embodiment of the present invention includes the display panel provided by the embodiment of the present invention, it also has the same beneficial effects and will not be elaborated herein.

[0170] It should be understood that various forms of processes shown above can be used, steps can be reordered, added or deleted. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and no limitation is made herein.

[0171] The above specific embodiments do not constitute a limitation to the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub - combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A shift register, characterized in that, The shift register includes: an input module, a first control module, a second control module, a first output module, and a second output module; The input module is configured to transmit an input signal to the input terminal of the first control module and the first terminal of the second control module according to a first clock signal; the first control module is configured to transmit a signal whose logic is opposite to that of its control terminal to a first node; and transmit a signal whose logic is opposite to that of the first node to a second node; The second control module is configured to transmit the signal at its first terminal to the second node according to the first clock signal; wherein, the conduction level logic of the second control module is opposite to that of the input module; The first output module is configured to output a first power supply voltage according to the signal of the first node, and output a second clock signal according to the signal of the second node; The second output module is configured to output a second power supply voltage according to the signal of the first node, and output a first power supply voltage according to the signal of the second node.

2. The shift register according to claim 1, wherein The shift register further includes a third output module, and the third output module is configured to output the first power supply voltage according to the signal of the first node, and output a third clock signal according to the signal of the second node; Preferably, the first output module includes a first pull-up unit, a first pull-down unit, and a first coupling unit. The first end of the first pull-up unit is connected to the first power supply voltage, the control terminal of the first pull-up unit is electrically connected to the first node, and the second end of the first pull-up unit is electrically connected to the output terminal of the first output module; the first end of the first pull-down unit is connected to the second clock signal, the control terminal of the first pull-down unit is electrically connected to the second node, and the second end of the first pull-down unit is electrically connected to the output terminal of the first output module; the first end of the first coupling unit is electrically connected to the second end of the first pull-down unit, and the second end of the first coupling unit is electrically connected to the control terminal of the first pull-down unit; Preferably, the third output module includes a second pull-up unit, a second pull-down unit, and a second coupling unit; the first end of the second pull-up unit is connected to the first power supply voltage, the control terminal of the second pull-up unit is electrically connected to the first node, and the second end of the second pull-up unit is electrically connected to the output terminal of the third output module; the first end of the second pull-down unit is connected to the second clock signal, the control terminal of the second pull-down unit is electrically connected to the second node, and the second end of the second pull-down unit is electrically connected to the output terminal of the third output module; the first end of the second coupling unit is electrically connected to the second end of the second pull-down unit, and the second end of the second coupling unit is electrically connected to the control terminal of the second pull-down unit.

3. The shift register according to claim 1, wherein, The first control module includes a first inverter unit and a second inverter unit. The input terminal of the first inverter unit is electrically connected to the input terminal of the first control module, and the output terminal of the first inverter unit is electrically connected to the first node; the input terminal of the second inverter unit is electrically connected to the first node, and the output terminal of the second inverter unit is electrically connected to the second node; Preferably, the first inverter unit includes a complementary metal-oxide inverter; Preferably, the second inverter unit includes a complementary metal-oxide inverter.

4. The shift register according to claim 1, wherein The second output module includes: a third pull-up unit, a third pull-down unit, a third coupling unit, and a fourth pull-down unit; a first end of the third pull-up unit is connected to the first power supply voltage, a control end of the third pull-up unit is electrically connected to the second node, and a second end of the third pull-up unit is electrically connected to an output end of the second output module; the fourth pull-down unit is configured to output the third power supply voltage to a control end of the third pull-down unit according to a potential of the first node, and output the first power supply voltage to the control end of the third pull-down unit according to a potential of the second node; a first end of the third pull-down unit is connected to the second power supply voltage, and a second end of the third pull-down unit is electrically connected to the output end of the second output module; a first end of the third coupling unit is electrically connected to the first end of the third pull-up unit, and a second end of the third coupling unit is electrically connected to the control end of the third pull-up unit; Preferably, the fourth pull-down unit includes a voltage modulation unit, and the voltage modulation unit is configured to modulate a conduction level of the first node to the third power supply voltage and output the modulated voltage to the control end of the third pull-down unit; Preferably, the fourth pull-down unit includes a first sub-switch unit, a second sub-switch unit, a third sub-switch unit, and a fourth sub-switch unit; a first end of the first sub-switch unit is connected to the first power supply voltage, a second end of the first sub-switch unit is electrically connected to a first end of the second sub-switch unit, and a control end of the first sub-switch unit is electrically connected to the first node; a second end of the second sub-switch unit is connected to the third power supply voltage; a first end of the third sub-switch unit is connected to the first power supply voltage, a second end of the third sub-switch unit is electrically connected to a first end of the fourth sub-switch unit, a second end of the fourth sub-switch unit is connected to the third power supply voltage, and a control end of the third sub-switch unit is electrically connected to the second node; a control end of the second sub-switch unit is electrically connected to the second end of the third sub-switch unit, and a control end of the fourth sub-switch unit is electrically connected to the second end of the first sub-switch unit; the second end of the third sub-switch unit is electrically connected to the control end of the third pull-down unit; the transistor channel types of the first sub-switch unit and the second sub-switch unit are different, the transistor channel types of the third sub-switch unit and the fourth sub-switch unit are different, and the transistor channel types of the first sub-switch unit and the third sub-switch unit are the same.

5. A display panel, characterized in that, The display panel includes multiple rows of pixel circuits, multiple first shift registers, and multiple second shift registers; wherein, both the first shift register and the second shift register include the shift register according to any one of claims 1-4; The pixel circuit includes a data writing module, a threshold compensation module, a driving module, and a first initialization module. The data writing module is configured to write a data voltage into the driving module. The threshold compensation module is configured to compensate the threshold voltage of the driving module. The first initialization module is configured to initialize the control terminal of the driving module. Among them, the transistor channel types of the threshold compensation module and the first initialization module are different from those of the driving module. The transistor channel type of the data writing module is the same as that of the driving module. The second output module of the first shift register is configured to drive the first initialization module of the corresponding pixel circuit. The second output module of the second shift register is configured to drive the threshold compensation module of the corresponding pixel circuit. The first output module of the second shift register is configured to drive the data writing module of the corresponding pixel circuit; and / or, the first output module of the first shift register is configured to drive the data writing module of the corresponding pixel circuit.

6. The display panel according to claim 5, wherein The display panel includes three clock lines. The display panel includes n rows of the pixel circuits, n + 2 stages of the first shift registers, and n stages of the second shift registers; n is an integer greater than or equal to 1. The first initialization module of the k-th stage of the pixel circuit is electrically connected to the second output module of the k-th stage of the first shift register. The threshold compensation module of the k-th stage of the pixel circuit is electrically connected to the second output module of the k-th stage of the second shift register; k is an integer greater than or equal to 1. In the same stage of the first shift register, the first clock signal is provided by the a-th clock line, and the second clock signal is provided by the b-th clock line. Among them, if a is less than or equal to 2, then b is equal to a + 1; if a is greater than 2, then b is equal to 1. In adjacent stages of the first shift registers, the second clock signal of the previous stage of the first shift register and the first clock signal of the next stage of the first shift register are provided by the same clock line. The first clock signal corresponding to the k-th stage of the second shift register and the first clock signal corresponding to the (k + 2)-th stage of the first shift register are provided by the same clock line; the second clock signal corresponding to the k-th stage of the second shift register and the second clock signal corresponding to the (k + 2)-th stage of the first shift register are provided by the same clock line. Preferably, the first clock signal of the k-th stage of the first shift register is provided by the j-th clock line; j is equal to the remainder of k divided by 3 plus 1.

7. The display panel according to claim 5, characterized in that, The display panel includes four clock lines. The display panel includes n rows of the pixel circuits, n + 3 stages of the first shift registers, and n stages of the second shift registers; n is an integer greater than or equal to 1. The first initialization module of the k-th stage of the pixel circuit is electrically connected to the second output module of the k-th stage of the first shift register. The threshold compensation module of the k-th stage pixel circuit is electrically connected to the second output module of the k-th stage second shift register; k is an integer greater than or equal to 1; In the first shift register of the same stage, the first clock signal is provided by the a-th clock line, and the second clock signal is provided by the b-th clock line; wherein, if a is less than or equal to 2, then b is equal to a + 1; if a is greater than 2, then b is equal to 1; in the first shift registers of adjacent two stages, the second clock signal of the previous stage first shift register and the first clock signal of the next stage first shift register are provided by the same clock line; The first clock signal corresponding to the k-th stage second shift register and the first clock signal corresponding to the (k + 3)-th stage first shift register are provided by the same clock line; the second clock signal corresponding to the k-th stage second shift register and the second clock signal corresponding to the (k + 3)-th stage first shift register are provided by the same clock line; Preferably, the first clock signal of the first shift register of the first stage is provided by the fourth clock line; the first clock signal of the first shift register of the k1-th stage is provided by the j-th clock line; j is equal to the remainder of k1 divided by 4 minus 1; k1 is greater than 1.

8. The display panel according to claim 5, characterized in that The shift register further includes a third output module, and the third output module is configured to output the first power voltage according to the signal of the first node and output the third clock signal according to the signal of the second node; The display panel includes six clock lines; The display panel includes n rows of the pixel circuits, n + 3 stages of the first shift registers, and n stages of the second shift registers; n is an integer greater than or equal to 1; The second output module of the k-th stage first shift register is electrically connected to the first initialization modules of the (2*k)-th stage and the (2*k - 1)-th stage pixel circuits; The second output module of the k-th stage second shift register is electrically connected to the threshold compensation modules of the (2*k)-th stage and the (2*k - 1)-th stage pixel circuits; In two adjacent stages of the first shift registers, the first clock signal of one of the first shift registers is provided by the second clock line, the second clock signal is provided by the fifth clock line, and the third clock signal is provided by the sixth clock line; the first clock signal of the other first shift register is provided by the first clock line, the second clock signal is provided by the third clock line, and the third clock signal is provided by the fourth clock line; The first clock signal corresponding to the k-th stage second shift register and the first clock signal corresponding to the (k + 3)-th stage first shift register are provided by the same clock line; the second clock signal corresponding to the k-th stage second shift register and the second clock signal corresponding to the (k + 3)-th stage first shift register are provided by the same clock line; the third clock signal corresponding to the k-th stage second shift register and the third clock signal corresponding to the (k + 3)-th stage first shift register are provided by the same clock line; Preferably, the first clock signal of the first shift register of the first stage is provided by the second clock line.

9. The display panel according to claim 5, wherein, The shift register further includes a third output module, which is configured to output the first power supply voltage according to the signal of the first node and output the third clock signal according to the signal of the second node; The display panel includes six clock lines; The display panel includes n rows of the pixel circuits, n + 2 stages of the first shift registers, and n stages of the second shift registers; n is an integer greater than or equal to 1; The second output module of the k-th stage of the first shift register is electrically connected to the first initialization modules of the (2*k)-th stage and the (2*k - 1)-th stage of the pixel circuits; The second output module of the k-th stage of the second shift register is electrically connected to the threshold compensation modules of the (2*k)-th stage and the (2*k - 1)-th stage of the pixel circuits; Among three adjacent stages of the first shift registers, the first clock signal of the first stage of the first shift register is provided by the j1-th clock line, where j1 is an odd number less than or equal to 5; the first clock signal of the second stage of the first shift register is provided by the j2-th clock line; the first clock signal of the third stage of the first shift register is provided by the j3-th clock line; wherein, if j1 is less than or equal to 3, then j2 is equal to j1 + 2, if j1 is equal to 5, then j2 is equal to 1; if j2 is less than or equal to 3, then j3 is equal to j2 + 2, if j2 is equal to 5, then j3 is equal to 1; among two adjacent stages of the first shift registers, the first clock signal of the subsequent stage of the first shift register and the second clock signal of the previous stage of the first shift register are provided by the same clock line; in the first shift register of the same stage, the second clock signal is provided by the a-th clock line, and the third clock signal is provided by the b-th clock line, where b is equal to a + 1; The first clock signal corresponding to the k-th stage of the second shift register and the first clock signal corresponding to the (k + 2)-th stage of the first shift register are provided by the same clock line; the second clock signal corresponding to the k-th stage of the second shift register and the second clock signal corresponding to the (k + 2)-th stage of the first shift register are provided by the same clock line; the third clock signal corresponding to the k-th stage of the second shift register and the third clock signal corresponding to the (k + 2)-th stage of the first shift register are provided by the same clock line; Preferably, the first clock signal of the first shift register of the first stage is provided by the first clock line.

10. A display device, characterized in that, The display device includes the display panel according to any one of claims 5 - 9.

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