Gate driving circuit, driving method thereof, display substrate and display device

Abstract

The embodiment of the invention provides a gate driving circuit, a driving method thereof, a display substrate and a display device. The gate drive circuit comprises a logical operation circuit (200), and the logical operation circuit (200) comprises a second input end (INBQn), a third input end (INCQn), a display switch signal end (DSn) and a display reset signal end (AZn). Under the control of a second input signal received by a second input end (INBQn) and a third input signal received by a third input end (INCQn), in a light emitting stage, the time when a display switch signal end (DSn) outputs an effective level signal in a display switch signal is not earlier than the time when a display reset signal end (AZn) stops outputting an effective level signal in a display reset signal. According to the technical scheme, the technical problems that in the prior art, peak current is formed in a pixel driving circuit, and the pixel driving circuit is unstable in work and large in power consumption due to the peak current are solved.

Description

[0001] This application claims the priority of the PCT international applications with application numbers PCT / CN2024 / 071143, PCT / CN2024 / 071152, and PCT / CN2024 / 071147, which were filed on January 8, 2024. The content thereof shall be incorporated into this application by reference. Technical Field

[0002] Embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and particularly to a gate driving circuit, a driving method thereof, a display substrate, and a display device. Background Art

[0003] Micro Organic Light-Emitting Diode (abbreviated as Micro-OLED) is a micro display developed in recent years, and silicon-based OLED is one of them. Silicon-based OLED is a new display technology that combines semiconductor process manufacturing and OLED display technology and prepares OLED devices on a wafer substrate. Due to the advantages of both semiconductor manufacturing process and OLED display technology, silicon-based OLED not only has a high pixel density (Pixels Per Inch, abbreviated as PPI), but also has advantages such as high brightness, low power consumption, high response speed, high color gamut, and high thermal stability. Summary of the Invention

[0004] The problem to be solved by the embodiments of the present disclosure is to provide a gate driving circuit, a driving method thereof, a display substrate, and a display device to overcome the technical problems of forming a spike current in the pixel driving circuit during the light-emitting stage, unstable operation of the pixel driving circuit, and high power consumption.

[0005] In a first aspect, to solve the above technical problems, embodiments of the present disclosure provide a gate driving circuit. The gate driving circuit includes a logic operation circuit. The logic operation circuit includes a second input terminal, a third input terminal, a display switch signal terminal, and a display reset signal terminal. The second input terminal is configured to receive a second input signal, the third input terminal is configured to receive a third input signal, the display switch signal terminal is configured to output a display switch signal, and the display reset signal terminal is configured to output a display reset signal.

[0006] Under the control of the second input signal and the third input signal, during the light-emitting stage, the time when the display switch signal terminal outputs a valid level signal in the display switch signal is not earlier than the time when the display reset signal terminal stops outputting a valid level signal in the display reset signal.

[0007] In an exemplary embodiment, under the control of the second input signal, the start time of the valid level signal in the display switch signal output from the display switch signal terminal is not earlier than the falling edge of the second input signal;

[0008] The falling edge of the third input signal is not later than the falling edge of the second input signal. Under the control of the second input signal and the third input signal, the end time of the valid level signal in the display reset signal output from the display reset signal terminal is synchronized with the falling edge of the second input signal.

[0009] In an exemplary embodiment, the logic operation circuit further includes a duty ratio control terminal configured to receive a duty ratio control signal; during the light emitting stage, the gate driving circuit is configured to control the duty ratio of the valid level signal in the duty ratio control signal through the end time of the valid level signal in the duty ratio control signal; the logic operation circuit is configured to control the duration of the valid level signal in the display switch signal output from the display switch signal terminal according to the duty ratio of the valid level signal in the duty ratio control signal, and control the duration of the valid level signal in the display reset signal output from the display reset signal terminal to stop according to the duty ratio of the valid level signal in the duty ratio control signal, so as to control the light emitting duration during the light emitting stage.

[0010] In an exemplary embodiment, during the light emitting stage, under the control of the duty ratio control signal, the end time of the valid level signal in the display switch signal output from the display switch signal terminal is synchronized with the end time of the valid level signal in the duty ratio control signal received by the duty ratio control terminal; the start time of the valid level signal in the display reset signal output from the display reset signal terminal is synchronized with the end time of the valid level signal in the duty ratio control signal received by the duty ratio control terminal.

[0011] In an exemplary embodiment, the logic operation circuit further includes a second operation circuit, a write switch signal terminal, and a second reset terminal; the write switch signal terminal is electrically connected to the second operation circuit and is configured to output a write switch signal to the second operation circuit; the second reset terminal is configured to input a second reset signal to the logic operation circuit;

[0012] The second operation circuit is electrically connected to the second input terminal, the write switch signal terminal, the duty ratio control terminal, the second reset terminal, and the display switch signal terminal, and is configured to perform a logic operation according to the second input signal, the write switch signal, the second reset signal, and the duty ratio control signal to generate the display switch signal, and output the display switch signal through the display switch signal terminal.

[0013] In an exemplary embodiment, the second arithmetic circuit includes a second NAND gate, a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, a ninth inverter, a tenth inverter, a fourth NOR gate, and a latch;

[0014] The input terminal of the fifth inverter is connected to the write switch signal terminal, the output terminal of the fifth inverter is connected to the input terminal of the sixth inverter, the output terminal of the sixth inverter is connected to the input terminal of the seventh inverter, the output terminal of the seventh inverter is connected to the input terminal of the eighth inverter, the output terminal of the eighth inverter is connected to the input terminal of the ninth inverter, the output terminal of the ninth inverter is connected to the input terminal of the tenth inverter, the output terminal of the tenth inverter is connected to the enable signal terminal of the latch, the input terminal of the latch is connected to the second input terminal of the logic arithmetic circuit, the output terminal of the latch is connected to the second input terminal of the fourth NOR gate, the first input terminal of the fourth NOR gate is connected to the ratio control terminal, the output terminal of the fourth NOR gate is connected to the first input terminal of the second NAND gate, the second input terminal of the second NAND gate is connected to the second reset terminal, and the output terminal of the second NAND gate serves as the output terminal of the second arithmetic circuit and the display switch signal terminal, and is connected to the display switch control terminal in the at least one pixel driving circuit to output a display switch signal to the display switch control terminal in the at least one pixel driving circuit.

[0015] In an exemplary embodiment, the gate driving circuit further includes a first test circuit configured to test the display switch signal output by the second logic circuit; the first test circuit includes a thirteenth inverter and a fourteenth inverter;

[0016] The input terminal of the thirteenth inverter is connected to the output terminal of the second arithmetic circuit, the output terminal of the thirteenth inverter is connected to the input terminal of the fourteenth inverter, and the output terminal of the fourteenth inverter serves as the output terminal of the first test circuit.

[0017] In an exemplary embodiment, the logic arithmetic circuit further includes a third arithmetic circuit;

[0018] The third arithmetic circuit is electrically connected to the second input terminal, the third input terminal, the ratio control terminal, the second reset terminal, and the display reset signal terminal, and is configured to perform a logic operation according to the second input signal, the third input signal, the ratio control signal, and the second reset signal to generate the display reset signal, and output the display reset signal through the display reset signal terminal.

[0019] In an exemplary embodiment, the third arithmetic circuit includes a fifth NOR gate and a third NAND gate;

[0020] The first input terminal of the fifth NOR gate is connected to the third input terminal of the logic operation circuit, the second input terminal of the fifth NOR gate is connected to the second input terminal of the logic operation circuit, the third input terminal of the fifth NOR gate is connected to the ratio control terminal, the output terminal of the fifth NOR gate is connected to the first input terminal of the third NAND gate, the second input terminal of the third NAND gate is connected to the second reset terminal, and the output terminal of the third NAND gate serves as the output terminal of the third operation circuit and the display reset signal terminal, and is connected to the display reset control terminal in the at least one pixel driving circuit to output a display reset signal to the display reset control terminal in the at least one pixel driving circuit.

[0021] In an exemplary embodiment, the gate driving circuit further includes a second test circuit configured to test the display reset signal output by the third logic circuit; the second test circuit includes a fifteenth inverter and a sixteenth inverter;

[0022] The input terminal of the fifteenth inverter is connected to the output terminal of the third operation circuit, the output terminal of the fifteenth inverter is connected to the input terminal of the sixteenth inverter, and the output terminal of the sixteenth inverter serves as the output terminal of the second test circuit.

[0023] In an exemplary embodiment, the gate driving circuit further includes a level conversion circuit, the level conversion circuit includes at least two level converters, and the at least two level converters at least include a second level converter and a third level converter;

[0024] The second level converter is electrically connected to the display switch signal terminal and is configured to perform a voltage domain conversion on the display switch signal and output the converted display switch signal to the display switch control terminal;

[0025] The third level converter is electrically connected to the display reset signal terminal and is configured to perform a voltage domain conversion on the display reset signal and output the converted display reset signal to the display reset control terminal.

[0026] In an exemplary embodiment, the gate driving circuit further includes a line driving enhancement circuit, the line driving enhancement circuit includes at least two line driving enhancers, and the at least two line driving enhancers at least include a second line driving enhancer and a third line driving enhancer;

[0027] The second line driving enhancer is electrically connected to the output terminal of the second level converter and is configured to enhance the display switch signal converted by the second level converter and output the enhanced display switch signal to the display switch control terminal;

[0028] The third row driving enhancer is electrically connected to the output terminal of the third level converter, and is configured to enhance the display reset signal converted by the third level converter, and output the enhanced display reset signal to the display reset control terminal.

[0029] In an exemplary embodiment, the row driving enhancer includes a fourth NAND gate, a fifth NAND gate, a first transmission gate, a twelfth inverter, a third P-type field effect transistor, and a third N-type field effect transistor;

[0030] The first input terminal of the row driving enhancer is connected to the first input terminal of the fourth NAND gate, the enable signal terminal of the row driving enhancer is connected to the second input terminal of the fourth NAND gate, the output terminal of the fourth NAND gate is connected to the input terminal of the first transmission gate, the output terminal of the first transmission gate is connected to the gate electrode of the third P-type field effect transistor, and the first pole of the third P-type field effect transistor is connected to the first power supply line;

[0031] The second input terminal of the row driving enhancer is connected to the first input terminal of the fifth NAND gate, the enable signal terminal of the row driving enhancer is connected to the second input terminal of the fifth NAND gate, the output terminal of the fifth NAND gate is connected to the input terminal of the twelfth inverter, the output terminal of the twelfth inverter is connected to the gate electrode of the third N-type field effect transistor, and the first pole of the third N-type field effect transistor is connected to the second power supply line;

[0032] The second pole of the third P-type field effect transistor and the second pole of the third N-type field effect transistor are connected to the output terminal of the row driving enhancer; the output terminal of the second row driving enhancer is electrically connected to the display switch control terminal, and the output terminal of the third row driving enhancer is electrically connected to the display reset control terminal.

[0033] In an exemplary embodiment, when the enable signal input at the enable signal terminal is a first level signal, the state of the row driving enhancer is a high impedance state.

[0034] In an exemplary embodiment, the level converter includes an eleventh inverter, a first P-type field effect transistor, a second P-type field effect transistor, a first N-type field effect transistor, and a second N-type field effect transistor;

[0035] The input terminals of the level converter are respectively connected to the input terminal of the eleventh inverter and the gate electrode of the first P-type field effect transistor; the input terminal of the second level converter is electrically connected to the display switch signal terminal, and the input terminal of the third level converter is electrically connected to the display reset signal terminal;

[0036] The output terminal of the eleventh inverter is connected to the gate electrode of the second P-type field effect transistor. The first pole of the first P-type field effect transistor and the first pole of the second P-type field effect transistor are both connected to the first power supply line. The second pole of the first P-type field effect transistor is respectively connected to the second pole of the first N-type field effect transistor, the gate electrode of the second N-type field effect transistor, and the second output terminal of the level converter. The second pole of the second P-type field effect transistor is respectively connected to the gate electrode of the first N-type field effect transistor, the second pole of the second N-type field effect transistor, and the first output terminal of the level converter. The first pole of the first N-type field effect transistor and the first pole of the second N-type field effect transistor are both connected to the second power supply line;

[0037] The first output terminal of the second level converter is electrically connected to the first input terminal of the second row driving booster; the second output terminal of the second level converter is electrically connected to the second input terminal of the second row driving booster; the first output terminal of the third level converter is electrically connected to the first input terminal of the third row driving booster; the second output terminal of the third level converter is electrically connected to the second input terminal of the third row driving booster.

[0038] In an exemplary embodiment, the logic operation circuit is configured to generate the display switch signal according to the second input signal, and generate the display reset signal according to the display switch signal and the third input signal;

[0039] Under the control of the display switch signal and the third input signal, in the light emitting stage, the time when the display reset signal terminal stops outputting the valid level signal in the display reset signal is synchronized with the time when the display switch signal terminal outputs the valid level signal in the display switch signal.

[0040] In a second aspect, the present disclosure also provides a gate driving method, configured to drive the gate driving circuit described in any of the above embodiments. The gate driving circuit includes a logic operation circuit, and the logic operation circuit includes a display switch signal terminal, a display reset signal terminal, a second input terminal, and a third input terminal; the display switch signal terminal is configured to output a display switch signal, and the display reset signal terminal is configured to output a display reset signal; the driving method includes:

[0041] Under the control of the second input signal and the third input signal, in the light emitting stage, the time when the display switch signal terminal outputs the valid level signal in the display switch signal is not earlier than the time when the display reset signal terminal stops outputting the valid level signal in the display reset signal.

[0042] In a third aspect, the present disclosure also provides a display substrate, including a display area and a non-display area; the display area includes a plurality of sub-pixels, at least one sub-pixel includes a pixel driving circuit and at least one scanning signal line, and the scanning signal line is configured to provide a scanning signal to the connected pixel driving circuit; the non-display area includes a plurality of cascaded gate driving circuits, at least one gate driving circuit is connected to the scanning signal line in the display area, and at least one gate driving circuit includes the gate driving circuit described in any of the above embodiments.

[0043] In an exemplary embodiment, at least one sub-pixel includes a light-emitting element, and the pixel driving circuit is configured to drive the light-emitting element to emit light; in the same sub-pixel, the pixel driving circuit is electrically connected to the anode of the light-emitting element; at least one of the pixel driving circuits at least includes: a display switch control terminal and a display reset control terminal; the gate driving circuit includes a display switch signal terminal and a display reset signal terminal;

[0044] The display switch control terminal is configured to receive the display switch signal from the display switch signal terminal and control the pixel driving circuit to drive the light-emitting element to emit light according to the display switch signal; the display reset control terminal is configured to receive the display reset signal from the display reset signal terminal and control the anode of the light-emitting element to be reset according to the display reset signal;

[0045] In the light-emitting stage, the time when the display switch control terminal receives the valid level signal in the display switch signal is not earlier than the time when the display reset control terminal stops receiving the valid level signal in the display reset signal.

[0046] In a fourth aspect, the present disclosure also provides a display device, including the display substrate described in any of the above embodiments.

[0047] In the gate driving circuit, the driving method, the display substrate, and the display device provided by the present disclosure, in the light-emitting stage, the time when the display switch signal terminal in the gate driving circuit outputs the valid level signal in the display switch signal is not earlier than the time when the display reset signal terminal stops outputting the valid level signal in the display reset signal, so that a spike current can be avoided from being formed in the pixel driving circuit, enabling the pixel driving circuit to work stably and reducing the power consumption of the pixel driving circuit.

[0048] Other aspects can be understood after reading and understanding the drawings and the detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The accompanying drawings are used to provide an understanding of the technical solutions of the present disclosure, and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure, but do not constitute a limitation to the technical solutions of the present disclosure. The shape and size of each component in the accompanying drawings do not reflect the true scale, and the purpose is only to schematically illustrate the content of the present disclosure.

[0050] Figure 1 It is a schematic structural diagram of a silicon-based OLED display device;

[0051] Figure 2 It is a schematic plan view of a display area in a silicon-based OLED display device;

[0052] Figure 3 It is a schematic cross-sectional view of a display area in a silicon-based OLED display device;

[0053] Figure 4a It is an equivalent circuit diagram of a pixel driving circuit;

[0054] Figure 4b It is an equivalent circuit diagram of a pixel driving circuit;

[0055] Figure 5a It is Figure 4a A driving timing diagram of the pixel driving circuit shown;

[0056] Figure 5b It is Figure 4b A driving timing diagram of the pixel driving circuit shown;

[0057] Figure 6a It is a schematic structural diagram of a gate driving circuit according to an exemplary embodiment of the present disclosure;

[0058] Figure 6b It is a working timing diagram of a gate driving circuit according to an exemplary embodiment of the present disclosure;

[0059] Figure 6c It is a working timing diagram of a gate driving circuit according to an exemplary embodiment of the present disclosure;

[0060] Figure 6d It is a working timing diagram of a gate driving circuit according to an exemplary embodiment of the present disclosure;

[0061] Figure 6e It is a schematic structural diagram of a gate driving circuit according to an exemplary embodiment of the present disclosure;

[0062] Figure 7 It is a working principle diagram of a first operation circuit according to an exemplary embodiment of the present disclosure;

[0063] Figure 8 It is an equivalent circuit diagram of a first operation circuit according to an exemplary embodiment of the present disclosure;

[0064] Figure 9a Working schematic diagram of a second arithmetic circuit according to an exemplary embodiment of the present disclosure;

[0065] Figure 9b One provided by an exemplary embodiment of the present disclosure Figure 9a Working schematic diagram of the latch in;

[0066] Figure 9c Working timing diagram of a latch provided by an exemplary embodiment of the present disclosure;

[0067] Figure 9d Working timing diagram of a second arithmetic circuit provided by an exemplary embodiment of the present disclosure;

[0068] Figure 9e Working timing diagram of a second arithmetic circuit provided by an exemplary embodiment of the present disclosure;

[0069] Figure 10 Equivalent circuit diagram of a second arithmetic circuit according to an exemplary embodiment of the present disclosure;

[0070] Figure 11a Working schematic diagram of a third arithmetic circuit according to an exemplary embodiment of the present disclosure;

[0071] Figure 11b Working timing diagram of a third arithmetic circuit according to an exemplary embodiment of the present disclosure;

[0072] Figure 11c Working timing diagram of a third arithmetic circuit according to an exemplary embodiment of the present disclosure;

[0073] Figure 11d Working timing diagram of a third arithmetic circuit according to an exemplary embodiment of the present disclosure;

[0074] Figure 12 Equivalent circuit diagram of a third arithmetic circuit according to an exemplary embodiment of the present disclosure;

[0075] Figure 13 Working schematic diagram of a level shifter according to an exemplary embodiment of the present disclosure;

[0076] Figure 14 Working schematic diagram of a row drive enhancer according to an exemplary embodiment of the present disclosure;

[0077] Figure 15 Equivalent circuit diagram of a level shifter according to an exemplary embodiment of the present disclosure;

[0078] Figure 16 Equivalent circuit diagram of a row drive enhancer according to an exemplary embodiment of the present disclosure;

[0079] Figure 17 It is an equivalent circuit diagram of an output circuit according to an exemplary embodiment of the present disclosure;

[0080] Figure 18 It is a timing diagram of the operation of a gate driving circuit according to an exemplary embodiment of the present disclosure;

[0081] Figure 19 It is a timing diagram of the operation of a gate driving circuit according to an exemplary embodiment of the present disclosure;

[0082] Figure 20 It is a timing diagram of the operation of a gate driving circuit according to an exemplary embodiment of the present disclosure;

[0083] Figure 21 It is a working principle diagram of a first test circuit according to an exemplary embodiment of the present disclosure;

[0084] Figure 22 It is an equivalent circuit diagram of a first test circuit according to an exemplary embodiment of the present disclosure;

[0085] Figure 23 It is a working principle diagram of a second test circuit according to an exemplary embodiment of the present disclosure;

[0086] Figure 24 It is an equivalent circuit diagram of a second test circuit according to an exemplary embodiment of the present disclosure;

[0087] Figure 25 It is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0088] Figure 26 It is a schematic structural diagram of a display device according to an exemplary embodiment of the present disclosure. Detailed Embodiments

[0089] To make the objectives, technical solutions and advantages of the present disclosure clearer and more understandable, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments can be implemented in multiple different forms. It is easy for those of ordinary skill in the art to understand the fact that the methods and contents can be transformed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited only to the contents described in the following embodiments. Without conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other arbitrarily. To keep the following description of the embodiments of the present disclosure clear and concise, the detailed descriptions of some known functions and known components are omitted. The accompanying drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can refer to the general design.

[0090] The ratio of the drawings in the present disclosure can be used as a reference in the actual process, but is not limited thereto. For example, the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display device and the number of sub-pixels in each pixel are not limited to the numbers shown in the drawings. The drawings described in the present disclosure are only schematic diagrams of the structure, and one embodiment of the present disclosure is not limited to the shapes, values, etc. shown in the drawings.

[0091] The ordinal numbers such as "first", "second", "third", etc. in this specification are set to avoid confusion of components, rather than to limit the quantity.

[0092] In this specification, for convenience, terms indicating orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are used to describe the positional relationship of components with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present disclosure. The positional relationship of the components changes appropriately according to the directions describing each component. Therefore, it is not limited to the terms described in the specification and can be replaced appropriately according to the situation.

[0093] In this specification, unless otherwise clearly defined and limited, the terms "mounted", "connected", and "coupled" shall be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate member, or the internal communication of two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0094] In this specification, a transistor refers to an element that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region where the current mainly flows.

[0095] In this specification, in order to distinguish between the two poles of a transistor other than the gate electrode, one of the poles is directly described as the first pole and the other as the second pole. Among them, the first pole can be the drain electrode and the second pole can be the source electrode, or the first pole can be the source electrode and the second pole can be the drain electrode. In cases where transistors with opposite polarities are used or the direction of current changes during circuit operation, etc., the functions of the "source electrode" and "drain electrode" sometimes swap with each other. Therefore, in this specification, the "source electrode" and "drain electrode" can be swapped with each other.

[0096] In this specification, "electrically connected" includes cases where components are connected together through an element having a certain electrical effect. The "element having a certain electrical effect" is not particularly limited as long as it can transfer electrical signals between the components to be connected. Examples of the "element having a certain electrical effect" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0097] In this specification, "parallel" means a state where the angle formed by two straight lines is -10° or more and 10° or less. Therefore, it also includes a state where the angle is -5° or more and 5° or less. In addition, "perpendicular" means a state where the angle formed by two straight lines is 80° or more and 100° or less. Therefore, it also includes a state where the angle is 85° or more and 95° or less.

[0098] In this specification, "film" and "layer" can be swapped with each other. For example, sometimes "conductive layer" can be changed to "conductive film". Similarly, sometimes "insulating film" can be changed to "insulating layer".

[0099] In this specification, the "same-layer setting" adopted means a structure formed by patterning two (or more) structures through the same patterning process, and their materials can be the same or different. For example, the materials of the precursors for forming multiple structures with the same-layer setting are the same, and the finally formed materials can be the same or different.

[0100] Triangles, rectangles, trapezoids, pentagons, hexagons, etc. in this specification are not strictly defined and can be approximate triangles, rectangles, trapezoids, pentagons, hexagons, etc. There can be some small deformations caused by tolerances, and there can be chamfers, arc edges, and deformations, etc.

[0101] The "about" in this disclosure means not strictly defining the boundary and allowing values within the process and measurement error ranges.

[0102] Figure 1 It is a schematic structural diagram of a silicon-based OLED display device. As Figure 1As shown, the silicon-based OLED display device may include a display area and a non-display area. The display area may include multiple scan signal lines, multiple data signal lines, and multiple sub-pixels Pxij that form multiple pixel rows and multiple pixel columns. The multiple scan signal lines are respectively arranged in the multiple pixel rows, and the multiple data signal lines are respectively arranged in the multiple pixel columns. Each sub-pixel Pxij may at least include a pixel driving circuit and a light-emitting device. The pixel driving circuit is configured to provide the current required for light emission to the connected light-emitting device. The pixel driving circuit of each sub-pixel Pxij may be connected to the scan signal line of the corresponding pixel row and the data signal line of the corresponding pixel column. The sub-pixel Pxij may refer to the sub-pixel of the i-th pixel row and the j-th pixel column. The pixel driving circuits of the sub-pixel Pxij are respectively connected to the i-th scan signal line and the j-th data signal line. i and j may be natural numbers. The non-display area may include a display driving circuit (Display Driver Integrated Circuit, abbreviated as DDIC), a gate driving device (GateDriver, abbreviated as GD), and a data driving device (Source Driver, abbreviated as SD). The display driving circuit may at least include a timing controller (Timer Controller, abbreviated as TCON). The timing controller is configured to generate the timing signals required by the gate driving device, such as a start signal (STV) and a clock signal (CKV), etc., and send the timing signals to the gate driving device. The gate driving device is respectively connected to the multiple scan signal lines in the display area. The gate driving device is configured to provide the required timing signals (timing) to the connected pixel driving circuits to implement the function of progressive scanning of the display. The data driving device is respectively connected to the multiple data signal lines in the display area. The data driving device is configured to provide the required data signals (data) to the connected pixel driving circuits to implement the switching and control of the display screen.

[0103] In an exemplary embodiment, the silicon-based OLED display device may be a single-chip display architecture (OneChip), integrating the gate driving device, the data driving device, the clock control unit, the image processing unit, and the storage unit, etc. on the same chip. The chip of the One Chip architecture includes both digital and analog parts and belongs to a mixed-signal chip.

[0104] In another exemplary embodiment, the silicon-based OLED display device may be a two-chip display architecture (TwoChip). The gate driving device and the data driving device are integrated in the display substrate. The clock control unit, the image processing unit, the Mobile Industry Processor Interface (MIPI), and the storage unit are integrated in one chip. This chip is connected to the display substrate through the COC process by bonding.

[0105] Figure 2It is a schematic plan view of a display area in a silicon-based OLED display device. As Figure 2 shown, in a plane parallel to the display device, the display area may include a plurality of pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1 that emits light of a first color, a second sub-pixel P2 that emits light of a second color, and a third sub-pixel P3 that emits light of a third color. Each of the three sub-pixels may include a pixel driving circuit and a light-emitting device. The pixel driving circuits in the sub-pixels are respectively connected to a scan signal line and a data signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and output a corresponding current to the display light-emitting device. The light-emitting device in the sub-pixel is connected to the pixel driving circuit of the sub-pixel where it is located, and the light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel where it is located.

[0106] In an exemplary embodiment, the first sub-pixel P1 may be a red (R) sub-pixel that emits red light, the second sub-pixel P2 may be a blue (B) sub-pixel that emits blue light, and the third sub-pixel P3 may be a green (G) sub-pixel that emits green light.

[0107] In an exemplary embodiment, the shape of the sub-pixel may be any one or more of a triangle, a square, a rectangle, a rhombus, a trapezoid, a parallelogram, a pentagon, a hexagon, and other polygons. The three sub-pixels may be arranged in a horizontal side-by-side, vertical side-by-side, or pyramid shape, etc., and the present disclosure does not limit this here. In other possible embodiments, the pixel unit may include four sub-pixels, and the present disclosure does not limit this here.

[0108] Figure 3 It is a schematic cross-sectional view of a display area in a silicon-based OLED display device, showing a structure for achieving full color by using white light + color film method. As Figure 3 shown, in a direction perpendicular to the display device, the silicon-based OLED display device may include: a silicon substrate 101, a driving circuit layer 102 provided on the silicon substrate 101, a light-emitting structure layer 103 provided on a side of the driving circuit layer 102 away from the silicon substrate 101, a first encapsulation layer 104 provided on a side of the light-emitting structure layer 103 away from the silicon substrate 101, a color film structure layer 105 provided on a side of the first encapsulation layer 104 away from the silicon substrate 101, a second encapsulation layer 106 provided on a side of the color film structure layer 105 away from the silicon substrate 101, and a cover layer 107 provided on a side of the second encapsulation layer 106 away from the silicon substrate 101. In some possible implementation manners, the silicon-based OLED display device may include other film layers, and the present disclosure does not limit this here.

[0109] In an exemplary embodiment, the silicon substrate 101 may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. The driving circuit layer 102 may be fabricated on the silicon substrate 101 through a silicon semiconductor process. The driving circuit layer 102 may include a plurality of circuit units, and the circuit units may at least include pixel driving circuits. The pixel driving circuits are respectively connected to the scanning signal lines and the data signal lines. The pixel driving circuits may include a plurality of transistors and storage capacitors. Figure 3 Only one transistor is taken as an example herein. The transistor may include a gate electrode G, a first pole S, and a second pole D. The gate electrode G, the first pole S, and the second pole D may be respectively connected to corresponding connection electrodes through tungsten metal-filled vias (i.e., tungsten vias, W-via), and may be connected to other electrical structures (such as traces, etc.) through the connection electrodes.

[0110] In an exemplary embodiment, the light-emitting structure layer 103 may include a plurality of light-emitting devices. The light-emitting devices may at least include an anode, an organic light-emitting layer, and a cathode. The anode may be connected to the second pole D of the transistor through a connection electrode. The organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The cathode is connected to the second power supply line. The organic light-emitting layer emits light under the drive of the anode and the cathode. In an exemplary embodiment, the organic light-emitting layer may include a light-emitting layer (abbreviated as EML), and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, for the light-emitting devices that emit white light, the organic light-emitting layers of all sub-pixels may be a common layer connected together.

[0111] In an exemplary embodiment, the first encapsulation layer 104 and the second encapsulation layer 106 may adopt the thin film encapsulation (TFE) method, which can ensure that external water vapor cannot enter the light-emitting structure layer. The color filter structure layer 105 may at least include a red filter unit, a blue filter unit, and a green filter unit. The red filter unit is disposed in the red sub-pixel to filter the white light emitted by the light-emitting device into red light. The blue filter unit is disposed in the blue sub-pixel to filter the white light emitted by the light-emitting device into blue light. The green filter unit is disposed in the green sub-pixel to filter the white light emitted by the light-emitting device into green light. The cover plate layer 107 may be made of glass or a flexible plastic such as colorless polyimide.

[0112] Figure 4a It is an equivalent circuit diagram of a pixel driving circuit. As Figure 4aAs shown, the pixel driving circuit has a 4T2C structure and may include four transistors (a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4) and two storage capacitors (a first capacitor C1 and a second capacitor C2). The pixel driving circuit is connected to six signal lines (a first scan signal line S1, a second scan signal line S2, a third scan signal line S3, a data signal line DATA, a first power supply line VDD, and a second power supply line VSS).

[0113] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is respectively connected to the second pole of the first transistor T1, the gate electrode of the third transistor T3, and the first end of the first capacitor C1. The second node N2 is respectively connected to the second pole of the second transistor T2, the first pole of the third transistor T3, the second end of the first capacitor C1, and the first end of the second capacitor C2. The third node N3 is respectively connected to the second pole of the third transistor T3 and the second pole of the fourth transistor T4.

[0114] In an exemplary embodiment, the first transistor T1 may be referred to as a Write Switch transistor. The gate electrode of the first transistor T1 is connected to the first scan signal line S1, the first pole of the first transistor T1 is connected to the data signal line DATA, and the second pole of the first transistor T1 is connected to the first node N1.

[0115] In an exemplary embodiment, the second transistor T2 may be referred to as a Display Switch transistor. The gate electrode of the second transistor T2 is connected to the second scan signal line S2, the first pole of the second transistor T2 is connected to the first power supply line VDD, and the second pole of the second transistor T2 is connected to the second node N2.

[0116] In an exemplary embodiment, the third transistor T3 may be referred to as a Driver transistor. The gate electrode of the third transistor T3 is connected to the first node N1, the first pole of the third transistor T3 is connected to the second node N2, and the second pole of the third transistor T3 is connected to the third node N3.

[0117] In an exemplary embodiment, the fourth transistor T4 may be referred to as an Auto Zero transistor. The gate electrode of the fourth transistor T4 is connected to the third scan signal line S3, the first pole of the fourth transistor T4 is connected to the second power supply line VSS, and the second pole of the fourth transistor T4 is connected to the third node N3.

[0118] In an exemplary embodiment, a first end of a first capacitor C1 is connected to a first node N1, and a second end of the first capacitor C1 is connected to a second node N2. A first end of a second capacitor C2 is connected to the second node N2, and a second end of the second capacitor C2 is connected to a first power supply line VDD.

[0119] In an exemplary embodiment, the light-emitting device EL may be an organic light-emitting diode (OLED), including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode). The first electrode of the light-emitting device XL is connected to a third node N3, and the second electrode of the light-emitting device EL is connected to a common voltage line VCOM.

[0120] In an exemplary embodiment, the signal of the first power supply line VDD may be a continuously provided high-level signal, and the signals of the second power supply line VSS and the common voltage line VCOM may be continuously provided low-level signals.

[0121] In an exemplary embodiment, the first transistor T1 to the fourth transistor T4 may be P-type transistors (PMOS), or may be N-type transistors (NMOS). For example, the first transistor T1 to the fourth transistor T4 are all P-type transistors. Using transistors of the same type in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the yield of the product.

[0122] In an exemplary embodiment, the first transistor T1 to the fourth transistor T4 may include P-type transistors and N-type transistors. For example, the first transistor T1 to the third transistor T3 may be P-type transistors, and the fourth transistor T4 may be an N-type transistor, as Figure 4a shown. In an exemplary embodiment, the first transistor T1 to the fourth transistor T4 are all P-type transistors. For example, the first transistor T1 to the fourth transistor T4 may all be P-type transistors, as Figure 4b shown.

[0123] Figure 5a is Figure 4a a driving timing diagram of the pixel driving circuit shown. As Figure 5a shown, in an exemplary embodiment, the working process of the pixel driving circuit may include:

[0124] The first stage A1 can be called the initialization stage. The signals of the first scan signal line S1 and the second scan signal line S2 are low-level signals, and the signal of the third scan signal line S3 is a high-level signal, causing the first transistor T1, the second transistor T2, and the fourth transistor T4 to conduct. The conduction of the first transistor T1 allows the bias voltage Vofs output by the data signal line DATA to be written into the first capacitor C1, and the potential Vs of the first node N1 (i.e., the gate electrode of the third transistor T3) is Vs = Vofs. The conduction of the second transistor T2 allows the first power supply voltage ELVDD output by the first power supply line VDD to be written into the second node N2, and the potential Vg of the second node N2 (i.e., the first pole of the third transistor T3) is Vg = ELVDD. At this time, the gate-source voltage Vgs of the third transistor T3 is Vgs = ELVDD - Vofs, and the stored voltage V cs of the first capacitor C1 is V = ELVDD - Vofs, and the potential Vd of the third node N3 (i.e., the second pole of the third transistor T3) is Vd = Vg + Vth, preparing for the discharge in the next stage. Among them, ELVDD - V ofs >|Vth|, where Vth is the threshold voltage of the third transistor T3.

[0125] The second stage A2 can be called the self-discharge stage. The signal of the third scan signal line S3 is a high-level signal, and the fourth transistor T4 continues to conduct. The signal of the first scan signal line S1 changes from a low-level signal to a high-level signal, causing the first transistor T1 to disconnect first, and the first node N1 floats. Subsequently, the signal of the second scan signal line S2 changes from a low-level signal to a high-level signal, causing the second transistor T2 to disconnect. The second node N2 forms a loop through the conducting third transistor T3, the third node N3, and the conducting fourth transistor T4 and starts to discharge, and the potential of the second node N2 drops. Because the first node N1 floats, the voltage difference across the first capacitor C1 remains unchanged, so the potential of the first node N1 drops as the potential of the second node N2 drops. Due to the body effect of the third transistor T3, the gate-source voltage Vgs of the third transistor T3 remains unchanged, so the equivalent threshold voltage |V th_EF | of the third transistor T3 gradually increases as the potential of the second node N2 drops. The equivalent threshold voltage |V th_EF | of the third transistor T3 is |V| = α(ELVDD - Vs) + |Vth|, where α is the body effect coefficient. When the equivalent threshold voltage |V th_EF | of the third transistor T3 increases to the gate-source voltage Vgs of the third transistor T3, the third transistor T3 disconnects, and the second node N2 stops discharging.

[0126] The third stage A3 can be referred to as the data writing stage and the threshold compensation stage. The signal of the second scan signal line S2 is a high-level signal, and the second transistor T2 remains continuously off. The signal of the third scan signal line S3 is a high-level signal, and the fourth transistor T4 remains continuously on. The signal of the first scan signal line S1 changes from a high-level signal to a low-level signal, turning on the first transistor T1. The conduction of the first transistor T1 causes the data voltage Vdata output by the data signal line DATA to be written into the first node N1, and the potential of the first node N1 changes from Vofs to Vdata. Since the second node N2 is floating, threshold compensation can be achieved in this stage.

[0127] The fourth stage A4 can be referred to as the light-emitting stage. The signals of the second scan signal line S2 and the third scan signal line S3 are low-level signals, and the signal of the first scan signal line S1 is a high-level signal, turning on the second transistor T2 and turning off the first transistor T1 and the fourth transistor T4. The conduction of the second transistor T2 causes the power supply voltage output by the first power supply line VDD to provide a driving voltage to the first pole of the light-emitting device EL through the conducting second transistor T2 and third transistor T3, driving the light-emitting device EL to emit light.

[0128] In the light-emitting stage, the driving current of the third transistor T3 is not affected by the threshold voltage of the third transistor T3, eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring the uniform display brightness of the display product, and improving the display effect of the entire display product.

[0129] Figure 5b For Figure 4b a driving timing diagram of the pixel driving circuit shown. As Figure 5b shown, Figure 4b the working process of the pixel driving circuit in it can include the first stage A1 to the fourth stage A4, Figure 5b which Figure 5a differs from Figure 4a and Figure 5a in that the timing of the third scan signal line S3 is different. In Figure 4b and Figure 5b the fourth transistor T4 is an N-type transistor (conducts at high level and turns off at low level), and in

[0130] During the light-emitting stage, there is a situation where the second transistor T2 turns on first and the fourth transistor T4 turns off later. If the second transistor T2 turns on earlier than the fourth transistor T4 turns off, the driving current flowing through the third transistor T3 will flow through the fourth transistor T4 and the light-emitting device EL. Since the resistance of the light-emitting device EL is relatively large and part of the driving current passes through the fourth transistor T4, the driving current flowing through the light-emitting device EL is small, resulting in the light-emitting device EL not being able to emit light before the fourth transistor T4 turns off, but there is current generated, increasing the power consumption of the pixel driving circuit; the resistance of the fourth transistor T4 is relatively small in the conducting state. A spike current is formed by the driving current flowing through the fourth transistor T4 in a short period of time after the second transistor T2 turns on and before the fourth transistor T4 turns off, which is not conducive to the stable operation of the pixel driving circuit and will cause problems with the reliability of the display device. Thus, the display device has technical problems of high power consumption and unstable operation of the pixel driving circuit.

[0131] An embodiment of the present disclosure provides a gate driving circuit. The gate driving circuit includes a logic operation circuit. The logic operation circuit includes a second input terminal, a third input terminal, a display switch signal terminal, and a display reset signal terminal; the second input terminal is configured to receive a second input signal, the third input terminal is configured to receive a third input signal, the display switch signal terminal is configured to output a display switch signal, and the display reset signal terminal is configured to output a display reset signal;

[0132] Under the control of the second input signal and the third input signal, during the light-emitting stage, the time when the display switch signal terminal outputs a valid level signal in the display switch signal is not earlier than the time when the display reset signal terminal stops outputting a valid level signal in the display reset signal.

[0133] In the gate driving circuit provided by the present disclosure, during the light-emitting stage when the gate driving circuit drives at least one pixel driving circuit, the time when the display switch signal terminal outputs a valid level signal in the display switch signal is not earlier than the time when the display reset signal terminal stops outputting a valid level signal in the display reset signal, thereby avoiding the formation of spike current in the pixel driving circuit, enabling the pixel driving circuit to operate stably, and reducing the power consumption of the pixel driving circuit.

[0134] Such as Figure 6aAs shown, it is a structural diagram of a gate driving circuit provided by an embodiment of the present disclosure. The gate driving circuit may include a logic operation circuit 200. The logic operation circuit 200 may include a second input terminal IN_B_Qn, a third input terminal IN_C_Qn, a display switch signal terminal DSn, and a display reset signal terminal AZn. The second input terminal IN_B_Qn is configured to receive a second input signal, the third input terminal IN_C_Qn is configured to receive a third input signal, the display switch signal terminal OUT_DSn is configured to output a display switch signal, and the display reset signal terminal OUT_AZn is configured to output a display reset signal.

[0135] Under the control of the second input signal and the third input signal, during the light-emitting stage, the time when the display switch signal terminal OUT_DSn outputs a valid level signal in the display switch signal is not earlier than the time when the display reset signal terminal OUT_AZn stops outputting a valid level signal in the display reset signal.

[0136] In an exemplary embodiment, the gate driving circuit may be configured to drive at least one pixel driving circuit, such as Figure 6a As shown, the pixel driving circuit may include a display switch control terminal DS and a display reset control terminal IN_AZ. The display switch signal terminal OUT_DSn is electrically connected to the display switch control terminal IN_DS of at least one pixel driving circuit, and is configured to output a display switch signal to the display switch control terminal IN_DS of at least one pixel driving circuit. The display reset signal terminal OUT_AZn is electrically connected to the display reset control terminal IN_AZ of at least one pixel driving circuit, and is configured to output a display reset signal to the display reset control terminal IN_AZ of at least one pixel driving circuit.

[0137] In an exemplary embodiment, the pixel driving circuit is configured to drive the light-emitting device EL to emit light under the control of the signal output by the gate driving circuit. The light-emitting stage refers to the stage when the pixel driving circuit drives the light-emitting device EL to emit light under the control of the signal output by the gate driving circuit.

[0138] In an exemplary embodiment, the valid level signal in the display switch signal may be a low level signal, and the valid level signal in the display reset signal may be a high level signal. Combining Figure 4a and Figure 6aAs shown, in the pixel driving circuit, the display switch control terminal IN_DS can be connected to the second scanning signal line S2, and the display reset control terminal IN_AZ can be connected to the third scanning signal line S3. When the display switch signal output by the display switch signal terminal DSn is at a low level, the second transistor T2 in the pixel driving circuit is turned on. Therefore, when the second transistor T2 in the pixel driving circuit is a P-type transistor, the effective level in the display switch signal is a low-level signal; when the display reset signal output by the display reset signal terminal AZn is at a high level, the fourth transistor T4 in the pixel driving circuit is turned on. Therefore, when the fourth transistor T4 in the pixel driving circuit is an N-type transistor, the effective level signal in the display reset signal is a high level. The embodiments of the present disclosure are not limited thereto, and the effective level signals of the display switch signal and the display reset signal can be set according to the type of transistors in the pixel driving circuit and the specific working timing, and it is only necessary to ensure that the conduction time of the second transistor T2 does not precede the disconnection time of the fourth transistor T4 during the light-emitting stage. For example, in the case of the pixel driving circuit as Figure 4a shown in the pixel driving circuit, the effective level of the display reset signal is high and low levels, and in the case of the pixel driving circuit as Figure 4b shown in the pixel driving circuit, the effective level of the display reset signal is a low level.

[0139] In an exemplary embodiment, as Figure 4a and Figure 4b shown, the first transistor T1 in the pixel driving circuit can be referred to as a write switch transistor, the second transistor T2 can be referred to as a display switch transistor, the third transistor T3 can be referred to as a driving transistor, and the fourth transistor T4 can be referred to as a display reset transistor. In the pixel driving circuit, the gate electrode of the write switch transistor T1 can be electrically connected to the write switch control terminal IN_WS of the pixel driving circuit, the gate electrode of the display switch transistor T2 can be electrically connected to the display switch control terminal IN_DS of the pixel driving circuit, and the gate electrode of the display reset transistor T4 can be electrically connected to the display reset control terminal IN_AZ of the pixel driving circuit. During the light-emitting stage when the pixel driving circuit drives the light-emitting device EL, the time when the effective level signal in the display switch signal is output by the display switch signal terminal OUT_DSn does not precede the time when the effective level signal in the display reset signal stops being output by the display reset signal terminal OUT_AZn, so that during the light-emitting stage, the conduction time of the display switch transistor T2 does not precede the disconnection time of the display reset transistor T4, thereby avoiding the problem that the display reset transistor T4 forms a spike current due to the display switch transistor T2 conducting first and the display reset transistor T4 disconnecting later during the light-emitting stage. Thus, the stability of the pixel driving circuit can be improved, and the technical problem of high power consumption of the pixel driving circuit caused by the formation of spike current can be avoided.

[0140] In an exemplary embodiment, asFigure 6a and Figure 6b As shown in Figure 6b , under the control of the second input signal B_Qn, the start time of the valid level signal in the display switch signal DSn output by the display switch signal terminal OUT_DSn is not earlier than the falling edge of the second input signal B_Qn;

[0141] The falling edge of the third input signal C_Qn is not later than the falling edge of the second input signal B_Qn. Under the control of the second input signal B_Qn and the third input signal C_Qn, the end time of the valid level signal in the display reset signal AZn output by the display reset signal terminal OUT_AZn is synchronized with the falling edge of the second input signal B_Qn. That is, under the control of the second input signal B_Qn and the third input signal C_Qn, the time when the display reset signal terminal OUT_AZn stops outputting the valid level signal in the display reset signal AZn is synchronized with the falling edge of the second input signal B_Qn, so that the start time of the valid level signal in the display switch signal DSn output by the display switch signal terminal OUT_DSn is not earlier than the time when the display reset signal terminal OUT_AZn stops outputting the valid level signal in the display reset signal AZn.

[0142] In an exemplary embodiment, as Figure 6b shown, the end time of the valid level signal in the display reset signal AZn output by the display reset signal terminal OUT_AZn being synchronized with the falling edge of the second input signal B_Qn can be that the end time of the valid level signal in the display reset signal AZn output by the display reset signal terminal OUT_AZn and the time of the falling edge of the second input signal B_Qn are basically at the same time (in an actual circuit structure, the end time of the valid level signal in the display reset signal AZn may be slightly delayed compared to the falling edge of the second input signal B_Qn, but can basically be regarded as the same time). For example, the end time of the valid level signal in the display reset signal AZn output by the display reset signal terminal OUT_AZn and the time of the falling edge of the second input signal B_Qn can be basically at the same time.

[0143] In an exemplary embodiment, the start time of the valid level signal in the display switch signal DSn output by the display switch signal terminal OUT_DSn is triggered by the falling edge of the second input signal B_Qn. In an actual circuit structure, the start time of the valid level signal in the display switch signal DSn output by the display switch signal terminal OUT_DSn has a certain delay compared to the time of the falling edge of the second input signal B_Qn. As Figure 6b shown, generally, the start time of the valid level signal in the display switch signal DSn output by the display switch signal terminal OUT_DSn is not earlier than the falling edge of the second input signal B_Qn. In some circuit structures, such as Figure 6cAs shown, the start time of the valid level signal in the display switch signal DSn output by the display switch signal terminal OUT_DSn is compared with the falling edge time of the second input signal B_Qn, and the delay time is relatively small and can be basically ignored. It can be regarded that the falling edge time of the second input signal B_Qn and the start time of the valid level signal in the display switch signal DSn output by the display switch signal terminal OUT_DSn are basically at the same time. Since the end time of the valid level signal in the display reset signal AZn output by the display reset signal terminal OUT_AZn is synchronized with the falling edge of the second input signal B_Qn, the time when the display reset signal terminal OUT_AZn stops outputting the valid level signal in the display reset signal AZn is basically synchronized with the start time of the valid level signal in the display switch signal DSn output by the display switch signal terminal OUT_DSn. For example, the time when the display reset signal terminal OUT_AZn stops outputting the valid level signal in the display reset signal AZn and the start time of the valid level signal in the display switch signal DSn output by the display switch signal terminal OUT_DSn can be basically at the same time.

[0144] In an exemplary embodiment, the end time of the valid level signal in the display reset signal AZn output by the display reset signal terminal OUT_AZn can be triggered by at least one of the falling edges of the second input signal B_Qn and the third input signal C_Qn. Since the start time of the valid level signal in the display switch signal DSn output by the display switch signal terminal OUT_DSn is triggered by the falling edge of the second input signal B_Qn, and the start time of the valid level signal in the display switch signal DSn output by the display switch signal terminal OUT_DSn is not earlier than the time when the display reset signal terminal OUT_AZn stops outputting the valid level signal in the display reset signal AZn, therefore, the falling edge time of the third input signal C_Qn is not earlier than the falling edge time of the second input signal B_Qn, so that the start time of the valid level signal in the display switch signal DSn output by the display switch signal terminal OUT_DSn is not earlier than the time when the display reset signal terminal OUT_AZn stops outputting the valid level signal in the display reset signal AZn.

[0145] In an exemplary embodiment, as Figure 6a 、 Figure 6b and Figure 6dAs shown, the logic operation circuit 200 may further include a duty ratio control terminal IN_D_Qn, and the duty ratio control terminal IN_D_Qn is set to receive a duty ratio control signal D_Qn; in the light emitting stage, the gate driving circuit is set to control the duty ratio of the active level signal in the duty ratio control signal D_Qn through the end time of the active level signal in the duty ratio control signal D_Qn. In an exemplary embodiment, in the light emitting stage, the logic operation circuit 200 may be set to control the duration of the active level signal in the display switch signal DSn output by the display switch signal terminal OUT_DSn and control the duration of the active level signal in the display reset signal AZn stopped being output by the display reset signal terminal OUT_AZn under the control of the duty ratio control signal D_Qn received at the duty ratio control terminal IN_D_Qn, so as to control the light emitting duration in the light emitting stage. In an exemplary embodiment, in the light emitting stage, the logic operation circuit 200 may be set to control the duration of the active level signal in the display switch signal output by the display switch signal terminal OUT_DSn according to the duty ratio of the active level signal in the duty ratio control signal D_Qn, and control the duration of the active level signal in the display reset signal AZn stopped being output by the display reset signal terminal OUT_AZn according to the duty ratio of the active level signal in the duty ratio control signal D_Qn, so as to control the light emitting duration in the light emitting stage.

[0146] In an exemplary embodiment, in the light emitting stage, under the control of the duty ratio control signal D_Qn, the end time of the active level signal in the display switch signal DSn output by the display switch signal terminal OUT_DSn is synchronized with the end time of the active level signal in the duty ratio control signal D_Qn received at the duty ratio control terminal IN_D_Qn; the start time of the active level signal OUT_AZn in the display reset signal output by the display reset signal terminal OUT_AZn is synchronized with the end time of the active level signal in the duty ratio control signal D_Qn received at the duty ratio control terminal IN_D_Qn (that is, the duration of the active level signal OUT_AZn in the display reset signal stopped being output by the display reset signal terminal OUT_AZn is controlled by the end time of the active level signal in the duty ratio control signal D_Qn received at the duty ratio control terminal IN_D_Qn).

[0147] In an exemplary embodiment, the end time of the valid level signal in the display switch signal DSn output by the display switch signal terminal OUT_DSn is synchronized with the end time of the valid level signal in the duty ratio control signal D_Qn received by the duty ratio control terminal IN_D_Qn. Under normal circumstances, the end time of the valid level signal in the display switch signal DSn output by the display switch signal terminal OUT_DSn can be slightly delayed compared to the end time of the valid level signal in the duty ratio control signal D_Qn received by the duty ratio control terminal IN_D_Qn. The delayed time is basically negligible and can be regarded as synchronous or simultaneous. The start time of the valid level signal OUT_AZn in the display reset signal output by the display reset signal terminal OUT_AZn is synchronized with the end time of the valid level signal in the duty ratio control signal D_Qn received by the duty ratio control terminal IN_D_Qn. Under normal circumstances, the start time of the valid level signal OUT_AZn in the display reset signal output by the display reset signal terminal OUT_AZn can be slightly delayed compared to the end time of the valid level signal in the duty ratio control signal D_Qn received by the duty ratio control terminal IN_D_Qn. The delayed time is basically negligible and can be regarded as synchronous or simultaneous.

[0148] In an exemplary embodiment, during the light-emitting stage, the duration of the valid level signal in the display switch signal DSn output by the display switch signal terminal OUT_DSn and the duration of the valid level signal in the display reset signal AZn output by the display reset signal terminal OUT_AZn are controlled by the duty ratio control signal D_Qn received by the duty ratio control terminal IN_D_Qn, so that the duration of the light-emitting device EL driven by the pixel driving circuit during the light-emitting stage can be controlled.

[0149] In an exemplary embodiment, as Figures 6b to 6d shown, the valid level signal in the duty ratio control signal can be a low-level signal. This is not limited in the embodiments of the present disclosure. The valid level signal in the duty ratio control signal can be set according to the circuit structure and specific working timing in the logic operation circuit 200, as long as the light-emitting duration can be controlled by the duty ratio of the valid level signal in the duty ratio control signal during the light-emitting stage.

[0150] In an exemplary embodiment, as Figure 6c shown, the logic operation circuit 200 can be set to generate the display switch signal DSn according to the second input signal B_Qn, and generate the display reset signal AZn according to the display switch signal DSn and the third input signal C_Qn;

[0151] Under the control of the display switch signal DSn and the third input signal C_Qn, during the light-emitting stage, the time when the display reset signal terminal OUT_AZn stops outputting the valid-level signal in the display reset signal AZn is synchronized with the time when the display switch signal terminal OUT_DSn starts outputting the valid-level signal in the display switch signal DSn.

[0152] In an exemplary embodiment, the time when the display reset signal terminal OUT_AZn stops outputting the valid-level signal in the display reset signal AZn is synchronized with the time when the display switch signal terminal OUT_DSn starts outputting the valid-level signal in the display switch signal DSn, which can be understood as the time when the display reset signal terminal OUT_AZn stops outputting the valid-level signal in the display reset signal AZn and the time when the display switch signal terminal OUT_DSn starts outputting the valid-level signal in the display switch signal DSn are substantially simultaneous.

[0153] In an exemplary embodiment, as Figure 6a shown, the logic operation circuit 200 may further include a second operation circuit, a write switch signal terminal OUT_WSn, and a second reset terminal IN_LF_pulse2; the write switch signal terminal OUT_WSn is electrically connected to the second operation circuit and is configured to output a write switch signal to the second operation circuit; the second reset terminal IN_LF_pulse2 is configured to input a second reset signal to the logic operation circuit 200;

[0154] The second operation circuit is electrically connected to the second input terminal OUT_B_Qn, the write switch signal terminal OUT_WSn, the duty ratio control terminal IN_D_Qn, the second reset terminal IN_LF_pulse2, and the display switch signal terminal OUT_DSn, and is configured to perform a logic operation according to the second input signal B_Qn, the write switch signal WSn, the second reset signal LF_pulse2, and the duty ratio control signal D_Qn to generate a display switch signal DSn, and output the display switch signal DSn through the display switch signal terminal OUT_DSn.

[0155] In an exemplary embodiment, as Figure 6a shown, the pixel driving circuit may further include a write switch control terminal IN_WS, and the write switch signal terminal OUT_WSn may further be electrically connected to the write switch control terminal IN_WS in at least one pixel driving circuit, and is configured to output a write switch signal WSn to the write switch control terminal IN_WS in at least one pixel driving circuit, as Figure 4a shown, the write switch control terminal IN_WS may be electrically connected to the first scan signal line S1.

[0156] In an exemplary embodiment, as Figure 6a shown, the logic operation circuit 200 may further include a third operation circuit;

[0157] The third operation circuit is electrically connected to the second input terminal IN_B_Qn, the third input terminal IN_C_Qn, the duty ratio control terminal IN_D_Qn, the second reset terminal IN_LF_pulse2, and the display reset signal terminal OUT_AZn, and is configured to perform a logical operation according to the second input signal B_Qn, the third input signal C_Qn, the duty ratio control signal D_Qn, and the second reset signal LF_pulse2 to generate a display reset signal AZn, and output the display reset signal AZn through the display reset signal terminal OUT_AZn.

[0158] In an exemplary embodiment, as Figure 6e shown, the gate driving circuit may further include a level conversion circuit 300, and the level conversion circuit 300 includes at least two level converters, and the at least two level converters at least include a second level converter and a third level converter;

[0159] The second level converter is electrically connected to the display switch signal terminal OUT_DSn, and is configured to perform a voltage domain conversion on the display switch signal DSn, and output the converted display switch signal to the display switch control terminal IN_DS in the pixel driving circuit;

[0160] The third level converter is electrically connected to the display reset signal terminal OUT_AZn, and is configured to perform a voltage domain conversion on the display reset signal AZn, and output the converted display reset signal to the display reset control terminal IN_AZ in the pixel driving circuit.

[0161] In an exemplary embodiment, as Figure 6e shown, the gate driving circuit may further include a line driving enhancement circuit 400, and the line driving enhancement circuit 400 may include at least two line driving enhancers, and the at least two line driving enhancers at least may include a second line driving enhancer and a third line driving enhancer;

[0162] The second line driving enhancer is electrically connected to the output terminal of the second level converter, and is configured to enhance the display switch signal converted by the second level converter, and output the enhanced display switch signal to the display switch control terminal IN_DS in the pixel driving circuit;

[0163] The third line driving enhancer is electrically connected to the output terminal of the third level converter, and is configured to enhance the display reset signal converted by the third level converter, and output the enhanced display reset signal to the display reset control terminal IN_AZ in the pixel driving circuit.

[0164] In an exemplary embodiment, as Figure 6eAs shown, the level conversion circuit 300 may further include a first level converter, and the row driving enhancement circuit 400 may further include a first row driving enhancer. In an exemplary embodiment, the logic operation circuit 200 may further include a first operation circuit. The output terminal of the first logic operation circuit may be connected to the write switch signal terminal OUT_WSn and is configured to generate a write switch signal WSn. The first level converter may be electrically connected to the write switch signal terminal OUT_WSn and is configured to perform a voltage domain conversion on the write switch signal WSn, and output the converted write switch signal to the first row driving enhancer. The first row driving enhancer outputs the write switch signal converted by the first level converter to the write switch control terminal IN_WS in the pixel driving circuit.

[0165] The technical solution of the gate driving circuit of the present disclosure will be described below through exemplary embodiments.

[0166] Figure 6e FIG. is a schematic structural diagram of a gate driving circuit according to an exemplary embodiment of the present disclosure. In an exemplary embodiment, the gate driving device may be disposed in a non-display area of the display substrate, may be located on one side of the pixel rows in the display area of the display substrate, or may be respectively located on both sides of the pixel rows in the display area of the display substrate. The gate driving device may include a plurality of cascaded gate driving circuits. At least one gate driving circuit is connected to the scan signal lines in a pixel row in the display area and provides a scan signal to the connected scan signal lines. When the gate driving device is disposed on both sides of the pixel rows in the display area, the scan signal lines in the pixel row are driven by two gate driving circuits to form a bilateral driving structure, which can ensure the driving ability of a high pixel density and avoid distortion of the driving signal. As Figure 6e shown, the gate driving circuit may include a shift register circuit 100, a logic operation circuit (Logical Transition Unit) 200, a level conversion circuit (Level shifter) 300, and a row driving enhancement circuit (Line Driver) 400.

[0167] In an exemplary embodiment, the shift register circuit 100 may be a shift register circuit composed of D flip-flops. The shift register circuit 100 is connected to the display driving circuit and receives the timing signals generated by the display driving circuit. The timing signals may include a start signal STV and a clock signal CKV. The D flip-flops are configured to perform shift register operations on the received timing signals to initially generate a timing that can be shifted row by row. The logic operation circuit 200 is connected to the shift register circuit 100 and is configured to perform logic operations on the shifted signals to generate target timings of multiple different waveforms. The level conversion circuit 300 is connected to the logic operation circuit 200 and is configured to perform voltage domain conversion on the target timings. The row driving enhancement circuit 400 is connected to the level conversion circuit 300 and is configured to enhance the converted signals, enhance the output capability, and output scan signals to the display area.

[0168] In an exemplary embodiment, for the pixel driving circuit in the display area, which includes a first scan signal line S1, a second scan signal line S2, and a third scan signal line S3, the level conversion circuit 300 and the row driving enhancement circuit 400 form an output circuit. The output circuit may include 3 output sub-circuits. Each sub-output circuit may include a level converter and a row driving enhancer. One output sub-circuit is connected to the first scan signal line S1 of a pixel row in the display area and is configured to output a first scan signal to the display area. Another output sub-circuit is connected to the second scan signal line S2 of a pixel row in the display area and is configured to output a second scan signal to the display area. Yet another output sub-circuit is connected to the third scan signal line S3 of a pixel row in the display area and is configured to output a third scan signal to the display area.

[0169] In an exemplary embodiment, the first scan signal may be referred to as a Write Switch (WS) signal and is configured to control the conduction and disconnection of the first transistor T1 in the pixel driving circuit. The second scan signal may be referred to as a Display Switch (DS) signal and is configured to control the conduction and disconnection of the second transistor T2 in the pixel driving circuit. The third scan signal may be referred to as a Display Reset signal (or may be referred to as an AutoZero (AZ) signal) and is configured to control the conduction and disconnection of the fourth transistor T4 in the pixel driving circuit.

[0170] In an exemplary embodiment, since signals such as the start signal and the clock signal are output by the display driving circuit and their voltage domains are inconsistent with the voltage domain of the pixel driving circuit, through the conversion of the level converter in the level conversion circuit 300, the required voltage (0V to -2V & -5V) is introduced, which can ensure that the voltage of the output gate driving signal matches the pixel driving circuit.

[0171] In an exemplary embodiment, the start signal STV may be referred to as a frame start signal and has a period of one frame. The clock signal CKV may be referred to as a line drive clock signal and has a period of one line.

[0172] In an exemplary embodiment, the logic operation circuit 200 may at least include a first operation circuit, a second operation circuit, and a third operation circuit. The first operation circuit is configured to generate a write switch signal WS, the second operation circuit is configured to generate a display switch signal DS, and the third operation circuit is configured to generate a display reset signal (auto-zero switch signal) AZ.

[0173] Figure 7 This is a schematic diagram of the operation of a first operation circuit according to an exemplary embodiment of the present disclosure. The first operation circuit may include nine parts, which are four inverters (Inverter, abbreviated as INV X), three NOR gates (NOR Gate, abbreviated as NOR), one NAND gate (NAND gate, abbreviated as NAND), and one two-way selector (MUX2). As Figure 7 shown, the first operation circuit may include a first NAND gate 301, a first inverter 401, a second inverter 402, a third inverter 403, a fourth inverter 404, a first NOR gate 501, a second NOR gate 502, a third NOR gate 503, and a two-way selector 510.

[0174] In an exemplary embodiment, the first input terminal of the first NAND gate 301 is connected to the second input terminal IN_B_Qn of the logic operation circuit, the second input terminal of the first NAND gate 301 is connected to the third input terminal IN_C_Qn of the logic operation circuit, the output terminal of the first NAND gate 301 is connected to the input terminal of the first inverter 401, the output terminal of the first inverter 401 is connected to the first input terminal of the first NOR gate 501, the second input terminal of the first NOR gate 501 is connected to the first input terminal IN_A_Qn of the logic operation circuit, the output terminal of the first NOR gate 501 is connected to the input terminal of the second inverter 402, the output terminal of the second inverter 402 is connected to the first input terminal of the second NOR gate 502, the second input terminal of the second NOR gate 502 is connected to the clock signal terminal IN_CKV4 of the logic operation circuit, the output terminal of the second NOR gate 502 is connected to the input terminal of the fourth inverter 404, and the output terminal of the fourth inverter 404 is connected to the second input terminal of the two-way selector 510. The input terminal of the third inverter 403 is connected to the second reset terminal LF_pulse2 of the logic operation circuit, the output terminal of the third inverter 403 is connected to the second input terminal of the third NOR gate 503, the first input terminal of the third NOR gate 503 is connected to the first reset terminal IN_LF_pulse1 of the logic operation circuit, and the output terminal of the third NOR gate 503 is connected to the control terminal of the two-way selector 510. The first input terminal of the two-way selector 510 is connected to the first input terminal IN_A_Qn of the logic operation circuit, and the output terminal of the two-way selector 510 serves as the output terminal of the first operation circuit (which can serve as the write switch signal terminal OUT_WSn of the logic operation circuit) and is connected to the input terminal of a level shifter (such as the first level shifter) to output the write switch signal WSn to the level shifter.

[0175] In an exemplary embodiment, the working principle of the first operation circuit is as follows: The first NAND gate 301 and the first inverter 401 perform an AND operation on the second input signal B_Qn of the second input terminal IN_B_Qn and the third input signal C_Qn of the third input terminal IN_C_Qn. The first NOR gate 501 and the second inverter 402 perform an OR operation on the AND operation result and the first input signal A_Qn of the first input terminal IN_A_Qn. The second NOR gate 502 and the fourth inverter 404 perform an OR operation on the OR operation result and the clock signal CKV4 (which can be referred to as the fourth clock signal) of the clock signal terminal IN_CKV4 (which can be referred to as the fourth clock signal terminal), that is, F1 = B_Qn & C_Qn + A_Qn + CKV4. The third inverter 403 performs an inversion process on the second reset signal LF_pulse2 of the second reset terminal IN_LF_pulse2, and the third NOR gate 503 performs a NOR operation on the inversion process result and the first reset signal LF_pulse1 of the first reset terminal IN_LF_pulse1, that is, F2 serves as the control signal for the two-way selector 510. When F2 = 1, the output terminal of the two-way selector 510 outputs the inverted signal A_Qn_ of the first input signal A_Qn. When F2 = 0, the output terminal of the two-way selector 510 outputs F1.

[0176] Figure 8 This is the equivalent circuit diagram of a first arithmetic circuit according to an exemplary embodiment of the present disclosure. As Figure 8 shown, in the gate driving circuit of the embodiment of the present disclosure, the first arithmetic circuit of the logic arithmetic circuit may include 30 transistors. Among them, the first inverter 401, the second inverter 402, the third inverter 403, and the fourth inverter 404 each include 1 P-type transistor and 1 N-type transistor. The first NAND gate 301, the first NOR gate 501, the second NOR gate 502, and the third NOR gate 503 each include 2 P-type transistors and 2 N-type transistors. The two-way selector 510 includes 3 P-type transistors and 3 N-type transistors.

[0177] In an exemplary embodiment, the first NAND gate 301, the first inverter 401, the first NOR gate 501, the second inverter 402, the second NOR gate 502, the fourth inverter 404, the third inverter 403, the third NOR gate 503, and the two-way selector 510 may be arranged in sequence along the first direction X (the direction close to the display area).

[0178] In an exemplary embodiment, the first P-type transistor P1, the first N-type transistor N1, the second P-type transistor P2, and the second N-type transistor N2 form the first NAND gate 301. The gate electrodes of the first P-type transistor P1 and the first N-type transistor N1 are connected to each other and connected to the third input terminal IN_C_Qn of the logic arithmetic circuit. The gate electrodes of the second P-type transistor P2 and the second N-type transistor N2 are connected to each other and connected to the second input terminal IN_B_Qn of the logic arithmetic circuit. The first poles of the first P-type transistor P1 and the second P-type transistor P2 are both connected to the first power supply line VDD. The second poles of the first P-type transistor P1 and the second P-type transistor P2 are connected to each other and are respectively connected to the second pole of the second N-type transistor N2, the gate electrode of the third P-type transistor P3, and the gate electrode of the third N-type transistor N3. The first pole of the first N-type transistor N1 is connected to the ground wire GND, and the second pole of the first N-type transistor N1 is connected to the first pole of the second N-type transistor N2.

[0179] In an exemplary embodiment, a third P-type transistor P3 and a third N-type transistor N3 form a first inverter 401. The gate electrodes of the third P-type transistor P3 and the third N-type transistor N3 are connected to each other and are respectively connected to the second pole of the first P-type transistor P1, the second pole of the second P-type transistor P2, and the second pole of the second N-type transistor N2. The first pole of the third P-type transistor P3 is connected to the first power supply line VDD, the first pole of the third N-type transistor N3 is connected to the ground line GND, the second poles of the third P-type transistor P3 and the third N-type transistor N3 are connected to each other and are respectively connected to the gate electrodes of the fifth P-type transistor P5 and the fifth N-type transistor N5.

[0180] In an exemplary embodiment, a fourth P-type transistor P4, a fourth N-type transistor N4, a fifth P-type transistor P5, and a fifth N-type transistor N5 form a first NOR gate 501. The gate electrodes of the fourth P-type transistor P4 and the fourth N-type transistor N4 are connected to each other and are connected to the first input terminal IN_A_Qn of the logic operation circuit. The gate electrodes of the fifth P-type transistor P5 and the fifth N-type transistor N5 are connected to each other and are respectively connected to the second pole of the third P-type transistor P3 and the second pole of the third N-type transistor N3. The first pole of the fourth P-type transistor P4 is connected to the first power supply line VDD, the second pole of the fourth P-type transistor P4 is connected to the first pole of the fifth P-type transistor P5. The first poles of the fourth N-type transistor N4 and the fifth N-type transistor N5 are both connected to the ground line GND. The second poles of the fourth N-type transistor N4 and the fifth N-type transistor N5 are connected to each other and are respectively connected to the second pole of the fifth P-type transistor P5, the gate electrode of the sixth P-type transistor P6, and the gate electrode of the sixth N-type transistor N6.

[0181] In an exemplary embodiment, a sixth P-type transistor P6 and a sixth N-type transistor N6 form a second inverter 402. The gate electrodes of the sixth P-type transistor P6 and the sixth N-type transistor N6 are connected to each other and are respectively connected to the second pole of the fifth P-type transistor P5, the second pole of the fourth N-type transistor N4, and the second pole of the fifth N-type transistor N5. The first pole of the sixth P-type transistor P6 is connected to the first power supply line VDD, the first pole of the sixth N-type transistor N6 is connected to the ground line GND. The second poles of the sixth P-type transistor P6 and the sixth N-type transistor N6 are connected to each other and are respectively connected to the gate electrodes of the eighth P-type transistor P8 and the eighth N-type transistor N8.

[0182] In an exemplary embodiment, a seventh P-type transistor P7, a seventh N-type transistor N7, an eighth P-type transistor P8, and an eighth N-type transistor N8 form a second NOR gate 502. The gate electrodes of the seventh P-type transistor P7 and the seventh N-type transistor N7 are connected to each other and connected to the clock signal terminal IN_CKV4 of the logic operation circuit. The gate electrodes of the eighth P-type transistor P8 and the eighth N-type transistor N8 are connected to each other and are respectively connected to the second pole of the sixth P-type transistor P6 and the second pole of the sixth N-type transistor N6. The first pole of the seventh P-type transistor P7 is connected to the first power supply line VDD. The second pole of the seventh P-type transistor P7 is connected to the first pole of the eighth P-type transistor P8. The first poles of the seventh N-type transistor N7 and the eighth N-type transistor N8 are both connected to the ground wire GND. The second poles of the seventh N-type transistor N7 and the eighth N-type transistor N8 are connected to each other and are respectively connected to the second pole of the eighth P-type transistor P8, the gate electrode of the ninth P-type transistor P9, and the gate electrode of the ninth N-type transistor N9.

[0183] In an exemplary embodiment, a ninth P-type transistor P9 and a ninth N-type transistor N9 form a fourth inverter 404. The gate electrodes of the ninth P-type transistor P9 and the ninth N-type transistor N9 are connected to each other and are respectively connected to the second pole of the seventh N-type transistor N7, the second pole of the eighth N-type transistor N8, and the second pole of the eighth P-type transistor P8. The first pole of the ninth P-type transistor P9 is connected to the first power supply line VDD. The first pole of the ninth N-type transistor N9 is connected to the ground wire GND. The second poles of the ninth P-type transistor P9 and the ninth N-type transistor N9 are connected to each other and are respectively connected to the first pole of the fifteenth P-type transistor P15 and the first pole of the fifteenth N-type transistor N15.

[0184] In an exemplary embodiment, a tenth P-type transistor P10 and a tenth N-type transistor N10 form a third inverter 403. The gate electrodes of the tenth P-type transistor P10 and the tenth N-type transistor N10 are connected to each other and connected to the second reset terminal IN_LF_pulse2 of the logic operation circuit. The first pole of the tenth P-type transistor P10 is connected to the first power supply line VDD. The first pole of the tenth N-type transistor N10 is connected to the ground wire GND. The second poles of the tenth P-type transistor P10 and the tenth N-type transistor N10 are connected to each other and are respectively connected to the gate electrode of the eleventh P-type transistor P11 and the gate electrode of the eleventh N-type transistor N11.

[0185] In an exemplary embodiment, an eleventh P-type transistor P11, an eleventh N-type transistor N11, a twelfth P-type transistor P12, and a twelfth N-type transistor N12 form a third NOR gate 503. The gate electrodes of the eleventh P-type transistor P11 and the eleventh N-type transistor N11 are connected to each other and are respectively connected to the second poles of the tenth P-type transistor P10 and the tenth N-type transistor N10. The gate electrodes of the twelfth P-type transistor P12 and the twelfth N-type transistor N12 are connected to each other and are connected to the first reset terminal IN_LF_pulse1 of the logic operation circuit. The first pole of the eleventh P-type transistor P11 is connected to the first power supply line VDD, the second pole of the eleventh P-type transistor P11 is connected to the first pole of the twelfth P-type transistor P12. The first poles of the eleventh N-type transistor N11 and the twelfth N-type transistor N12 are both connected to the ground wire GND. The second poles of the eleventh N-type transistor N11 and the twelfth N-type transistor N12 are connected to each other and are respectively connected to the second pole of the twelfth P-type transistor P12, the gate electrode of the thirteenth P-type transistor P13, the gate electrode of the thirteenth N-type transistor N13, the gate electrode of the fourteenth N-type transistor N14, and the gate electrode of the fifteenth P-type transistor P15.

[0186] In an exemplary embodiment, a thirteenth P-type transistor P13, a thirteenth N-type transistor N13, a fourteenth P-type transistor P14, a fourteenth N-type transistor N14, a fifteenth P-type transistor P15, and a fifteenth N-type transistor N15 form a two-way selector 510. The gate electrodes of the thirteenth P-type transistor P13 and the thirteenth N-type transistor N13 are connected to each other and are respectively connected to the second pole of the eleventh N-type transistor N11, the second pole of the twelfth N-type transistor N12, the second pole of the twelfth P-type transistor P12, the gate electrode of the fourteenth N-type transistor N14, and the gate electrode of the fifteenth P-type transistor P15. The first pole of the thirteenth P-type transistor P13 is connected to the first power supply line VDD, and the first pole of the thirteenth N-type transistor N13 is connected to the ground line GND. The second poles of the thirteenth P-type transistor P13 and the thirteenth N-type transistor N13 are connected to each other and are respectively connected to the gate electrode of the fourteenth P-type transistor P14 and the gate electrode of the fifteenth N-type transistor N15. The first poles of the fourteenth P-type transistor P14 and the fourteenth N-type transistor N14 are connected to each other and are connected to the input terminal IN_A_Qn_ of the inverted signal of the first input signal A_Qn of the logic operation circuit. The first poles of the fifteenth P-type transistor P15 and the fifteenth N-type transistor N15 are connected to each other and are respectively connected to the second pole of the ninth P-type transistor P9 and the second pole of the ninth N-type transistor N9. The second poles of the fourteenth P-type transistor P14, the fourteenth N-type transistor N14, the fifteenth P-type transistor P15, and the fifteenth P-type transistor P15 are connected to each other and serve as the output terminal OUT_WS of the first operation circuit (i.e., Figure 7 the output terminal of the output write switch signal WSn in

[0187] Figure 9a This is a schematic diagram of the operation of a second operation circuit according to an exemplary embodiment of the present disclosure. The second operation circuit may include nine parts, which are six inverters, one NOR gate, one NAND gate, and one latch (D-Latch). As Figure 9a shown, the second operation circuit may include a second NAND gate 302, a fifth inverter 405, a sixth inverter 406, a seventh inverter 407, an eighth inverter 408, a ninth inverter 409, a tenth inverter 410, a fourth NOR gate 504, and a latch 520.

[0188] In an exemplary embodiment, the input terminal of the fifth inverter 405 is connected to the write switch signal terminal WSn of the logic operation circuit, the output terminal of the fifth inverter 405 is connected to the input terminal of the sixth inverter 406, the output terminal of the sixth inverter 406 is connected to the input terminal of the seventh inverter 407, the output terminal of the seventh inverter 407 is connected to the input terminal of the eighth inverter 408, the output terminal of the eighth inverter 408 is connected to the input terminal of the ninth inverter 409, the output terminal of the ninth inverter 409 is connected to the input terminal of the tenth inverter 410, the output terminal of the tenth inverter 410 is connected to the enable signal terminal EN of the latch 520, the input terminal of the latch 520 is connected to the second input terminal IN_B_Qn of the logic operation circuit, the output terminal of the latch 520 is connected to the second input terminal of the fourth NOR gate 504, the first input terminal of the fourth NOR gate 504 is connected to the ratio control terminal IN_D_Qn of the logic operation circuit, the output terminal of the fourth NOR gate 504 is connected to the first input terminal of the second NAND gate 302, the second input terminal of the second NAND gate 302 is connected to the second reset terminal IN_LF_pulse2 of the logic operation circuit, and the output terminal of the second NAND gate 302 serves as the output terminal OUT_DS of the second operation circuit and the display switch signal terminal OUT_DSn, and is connected to the display switch control terminal DS in at least one pixel driving circuit, and outputs a display switch signal to the display switch control terminal DS in at least one pixel driving circuit. In an exemplary embodiment, the output terminal of the second NAND gate 302 may be connected to the input terminal of another level converter (such as the second level converter), and outputs the display switch signal DSn to the level converter. After the level converter performs level conversion on the display switch signal DSn, it outputs the signal to the corresponding line driving enhancer (such as the second line driving enhancer), and after the signal is enhanced by the line driving enhancer, it outputs the signal to the display switch control terminal of the corresponding pixel driving circuit.

[0189] In an exemplary embodiment, the working principle of the second arithmetic circuit is as follows: The fifth inverter 405 to the tenth inverter 410 delay the signal of the write switch signal terminal OUT_WSn and input it to the enable signal terminal IN_EN of the latch 520 as the enable signal EN of the latch 520. The second input signal B_Qn of the second input terminal IN_B_Qn of the logic arithmetic circuit serves as the input signal of the latch 520. When the enable signal EN at the enable signal terminal IN_EN is at a low level, the output of the latch 520 remains unchanged. When the enable signal EN at the enable signal terminal IN_EN is at a high level, the output of the latch 520 changes with the second input signal B_Qn. Subsequently, the fourth nor gate 504 performs a nor operation on the duty ratio control signal at the duty ratio control terminal IN_D_Qn and the signal at the first output terminal OUT_Q of the latch 520. The second nand gate 302 performs a nand operation on the nor operation result and the second reset signal LF_pulse2 at the second reset terminal IN_LF_pulse2. Its logical expression is: Where Q is the output signal of the latch 520 (when the enable signal EN input to the enable signal terminal of the latch 520 is at a high level, Q = B_Qn; when the enable signal EN input to the enable signal terminal of the latch 520 is at a low level, the signal output at the output terminal Q remains the original output signal; under normal working conditions, the enable signal EN at the enable signal terminal of the latch is at a high level, Q = B_Qn), LF_pulse2 is the reset signal, and in the normal working state, LF_pulse2 = 1, DSn = D_Qn + Q. When global reset is required, LF_pulse2 = 0 for global reset, and the output signal DSn of the second arithmetic circuit is at a high level (i.e., DSn = 1). D_Qn is the emission duty control signal. When the emission duty is 100%, D_Qn remains at a low level, and then DSn = Q. When it is necessary to adjust the emission duty, it can be achieved by adjusting the duty cycle of D_Qn.

[0190] As Figure 9b shown, it is the working principle diagram of a latch 520 according to an exemplary embodiment of the present disclosure. The latch 520 includes 1 inverter and 4 nand gates, as Figure 9bAs shown, the latch 520 includes the twenty-first NAND gate 521, the twenty-second NAND gate 522, the twenty-third NAND gate 523, the twenty-fourth NAND gate 524, and the twenty-fifth inverter 525. The first input terminal of the twenty-first NAND gate 521 is connected to the second input terminal IN_B_Qn of the logic operation circuit. The second input terminal of the twenty-first NAND gate 521 is connected to the enable signal terminal EN. The output terminal of the twenty-first NAND gate 521 is connected to the first input terminal of the twenty-second NAND gate 522. The second input terminal of the twenty-second NAND gate 522 is connected to the second output terminal OUT_Q_ of the latch 520. The output terminal of the twenty-second NAND gate 522 serves as the first output terminal OUT_Q of the latch 520. The input terminal of the twenty-fifth inverter 525 is connected to the second input terminal B_Qn of the logic operation circuit. The output terminal of the twenty-fifth inverter 525 is connected to the first input terminal of the twenty-third NAND gate 523. The second input terminal of the twenty-third NAND gate 523 is connected to the enable signal terminal EN. The output terminal of the twenty-third NAND gate 523 is connected to the second input terminal of the twenty-fourth NAND gate 524. The first input terminal of the twenty-fourth NAND gate 524 is connected to the first output terminal OUT_Q of the latch 520. The output terminal of the twenty-fourth NAND gate 524 serves as the second output terminal OUT_Q_ of the latch 520. As Figure 9c shown, it is a working timing diagram of the latch provided by an embodiment of the present disclosure ( Figure 9c where the abscissa is time, with the unit of microsecond; the ordinate is voltage, with the unit of volt V); in Figure 9b it, the signal of the first node B1 is the NAND operation result obtained by performing a NAND operation on the second input signal B_Qn and the enable signal EN. The signal of the second node B2 is the operation result obtained by performing a NAND operation on the inverted signal of the second input signal B_Qn after passing through the inverter and the enable signal EN. The output signal Q is the operation result obtained by performing a NAND operation on the signal of the first node B1 and the signal of the second output terminal OUT_Q_. The output signal Q_ is the operation result obtained by performing a NAND operation on the signal of the second node B2 and the signal of the first output terminal OUT_Q.

[0191] As Figure 9cAs shown, in the first stage t1, the enable signal EN is a high-level signal, and the second input signal B_Qn is a low-level signal. The signal of the first node B1 obtained by performing a NAND operation on the enable signal EN and the second input signal B_Qn is a high-level signal. The signal of the second node B2 obtained by performing a NAND operation on the inverted second input signal B_Qn and the enable signal EN is a low-level signal. The signal of the second output terminal OUT_Q_ obtained by performing a NAND operation on the signal of the second node B2 and the signal of the first output terminal OUT_Q is a high-level signal. Since the signals of the first node B1 and the second output terminal OUT_Q_ are both high-level, the signal of the first output terminal OUT_Q obtained by performing a NAND operation on the signal of the first node B1 and the signal of the second output terminal OUT_Q_ is a low-level signal; in the second stage t2, the enable signal EN is a low-level signal, and the second input signal B_Qn changes from a low-level signal to a high-level signal. Since the enable signal EN is a low-level signal, both the first node B1 and the second node B2 are high-level signals. The first output terminal OUT_Q maintains the low level of the previous stage, and the second output terminal OUT_Q_ maintains the high level signal of the previous stage; in the third stage t3, both the enable signal EN and the second input signal B_Qn are high-level signals. The first node B1 obtained by performing a NAND operation on the enable signal EN and the second input signal B_Qn is a low-level signal. The first output terminal OUT_Q is a high-level signal obtained by performing a NAND operation on the signal of the first node B1 and the signal of the second output terminal OUT_Q_. The second node B2 obtained by performing a NAND operation on the inverted second input signal B_Qn and the enable signal EN is a high-level signal. The signal of the second output terminal OUT_Q_ obtained by performing a NAND operation on the signal of the second node B2 and the signal of the first output terminal OUT_Q is a low-level signal; the timing of the fourth stage t4 and the sixth stage t6 is the same as that of the second stage t2, the timing of the fifth stage t5 and the seventh stage t7 is the same as that of the third stage t3, and the timing of the eighth stage t8 and the tenth stage t10 is the same as that of the first stage t1; in the ninth stage t9 and the eleventh stage t11, the second input signal B_Qn changes from a high level to a low-level signal, and the timing of other signals is the same as that of the second stage t2.

[0192] From Figure 9b and Figure 9cIt can be seen that the latch 520 has a total of the following three states. The first state: the enable signal EN is at a high level (1), the second input signal B_Qn is at a low level signal (0), the signal of the first node B1 is at a high level, the signal of the second node B2 is at a low level, the signal of the second output terminal OUT_Q_ is at a high level signal, and the signal of the first output terminal OUT_Q is at a low level signal (referred to as the latch clear operation); the second state: the enable signal EN is at a low level (0), the second input signal B_Qn is an arbitrary signal (high level or low level), the signals of the first node B1 and the second node B2 are both at a high level, and the second output terminal OUT_Q_ and the first output terminal OUT_Q maintain their original output signals and do not change with the change of the second input signal B_Qn (referred to as the hold stage, the stage of latching a 1-bit binary number); the third state: the enable signal EN is at a high level (1), the second input signal B_Qn is at a high level signal (1), the signal of the first node B1 is at a low level, the signal of the second node B2 is at a high level, the signal of the first output terminal OUT_Q is at a high level signal (the latch set stage), and the signal of the second output terminal OUT_Q_ is at a low level signal.

[0193] Figure 9a The main function of the D latch 520 is to prevent the high level of the display switch signal DSn from covering the first low level of the write switch signal WSn (that is, the first low level of the write switch signal WSn overlaps at least partially with the high level of the display switch signal DSn). If the high level of the display switch signal DSn moves forward to cover the first low level of the write switch signal WSn, it will reduce the time of the first power supply voltage of the second node N2 in the write pixel driving circuit and the time of the bias voltage Vofs of the first node N1 in the write pixel driving circuit, resulting in incomplete initialization; if the first low level of the write switch signal WSn moves backward to cover the high level of the display switch signal DSn, it will reduce the self-discharge time of the pixel driving circuit and the threshold voltage reading will be inaccurate. The constraint condition for the normal operation of the D latch 520 is that the enable signal EN input to the enable signal terminal IN_EN of the latch 520 is at a high level (i.e., EN = 1). If the enable signal of the enable signal terminal IN_EN is not at a high level (for example, EN = 0), the latch state is uncertain, and the signal output by the first output terminal OUT_Q of the latch 520 is uncertain.

[0194] As Figure 9d shown, it is a timing diagram of a working process of a second arithmetic circuit according to an exemplary embodiment of the present disclosure. The second reset signal of the second reset terminal OUT_LF_pulse2 is at a high level signal, and the display switch signal DSn changes under the control of the signal output by the fourth NOR gate 504. As Figure 9dAs shown, the working process of the second operation circuit may include four stages: the first stage p11 to the fourth stage p14 (during the light-emitting time in the first stage p11 to the third stage p13 and the fourth stage p14, the duty ratio control signal of the duty ratio control terminal IN_D_Qn is at a low level, and the duty ratio control signal of the duty ratio control terminal IN_D_Qn is at a high or low level during the non-light-emitting time in the fourth stage p14):

[0195] First stage p11: The signal at the write switch signal terminal OUT_WSn changes from low level to high level, and the enable signal EN at the enable signal terminal IN_EN changes from high level to low level (the fifth inverter 405 to the tenth inverter 410 delay the low-level signal of the write switch signal terminal OUT_WSn by Δt1, and the falling edge of the low-level enable signal at the enable signal terminal EN arrives Δt1 later than the low-level signal of the write switch signal terminal OUT_WSn), and the second input signal at the second input terminal IN_B_Qn changes from low level to high level; since the enable signal at the enable signal terminal IN_EN changes from high level to low level, the signal at the first output terminal OUT_Q of the latch 520 remains at the low level of the previous stage (in the previous stage, the enable signal at the enable signal terminal EN was at a high level, the second input signal at the second input terminal IN_B_Qn was at a low level, and the signal at the first output terminal OUT_Q of the latch 520 was at a low level), and the duty ratio control signal (low-level signal) at the duty ratio control terminal IN_D_Qn and the signal (low-level signal) at the first output terminal OUT_Q of the latch 520 are NAND-operated by the fourth NOR gate 504 to obtain a high-level signal, and the display switch signal DSn obtained by the NAND operation of the high-level signal after the NOR operation and the second reset signal at the second reset terminal IN_LF_pulse2 by the second NAND gate 302 is at a low level signal;

[0196] Second stage p12: The signal at the write switch signal terminal OUT_WSn, the enable signal at the enable signal terminal IN_EN, and the second input signal at the second input terminal IN_B_Qn are all at high levels; since the second input signal at the second input terminal IN_B_Qn and the enable signal at the enable signal terminal EN are both at high levels, the signal at the first output terminal OUT_Q of the latch 520 is at a high level, and the duty ratio control signal (low-level signal) at the duty ratio control terminal IN_D_Qn and the signal (high-level signal) at the output terminal OUT_Q of the latch 520 are NOR-operated by the fourth NOR gate 504 to obtain a low-level signal, and the display switch signal DSn obtained by the NAND operation of the low-level signal after the NOR operation and the second reset signal at the second reset terminal IN_LF_pulse2 by the second NAND gate 302 is at a high level signal;

[0197] In the third stage p13: The signal of the write switch signal terminal OUT_WSn and the enable signal of the enable signal terminal IN_EN are both low levels, and the second input signal of the second input terminal IN_B_Qn is a high level; Since the enable signal of the enable signal terminal IN_EN is a low level, the signal at the first output terminal OUT_Q of the latch 520 remains the high level of the previous stage. The ratio control signal (low level signal) of the ratio control terminal IN_D_Qn and the signal (high level signal) at the first output terminal OUT_Q of the latch 520 are NAND-operated by the fourth NOR gate 504 to obtain a low level signal. The low level signal obtained after the NAND operation and the second reset signal of the second reset terminal IN_LF_pulse2 are NAND-operated by the second NAND gate 302 to obtain a high level display switch signal DSn;

[0198] The light emitting time in the fourth stage p14: The signal of the write switch signal terminal OUT_WSn and the enable signal of the enable signal terminal IN_EN are both high levels, and the second input signal of the second input terminal IN_B_Qn is a low level; Since the second input signal of the second input terminal IN_B_Qn is a low level and the enable signal of the enable signal terminal EN is a high level, the signal at the first output terminal OUT_Q of the latch 520 is a low level. The ratio control signal (low level signal) of the ratio control terminal IN_D_Qn and the signal (low level signal) at the output terminal OUT_Q of the latch 520 are NOR-operated by the fourth NOR gate 504 to obtain a high level signal. The high level signal obtained after the NOR operation and the second reset signal of the second reset terminal IN_LF_pulse2 are NAND-operated by the second NAND gate 302 to obtain a low level display switch signal DSn. The display switch signal DSn controls the second transistor T2 in the pixel driving circuit to conduct, and the driving current can drive the light emitting device EL to emit light. This stage is called the light emitting stage.

[0199] It can be seen that Figure 9d when the second reset signal of the second reset terminal IN_LF_pulse2 is a high level signal and the ratio control signal of the ratio control terminal IN_D_Qn is a low level signal, the falling edge of the display switch signal DSn can be controlled by the falling edge of the second input signal of the second input terminal IN_B_Qn; As Figure 9e shown, when the second reset signal of the second reset terminal IN_LF_pulse2 is a low level signal, regardless of whether the ratio control signal of the ratio control terminal IN_D_Qn is a low level signal or a high level signal, the display switch signal DSn is always a high level, thereby controlling the second transistor T2 in the pixel driving circuit to turn off. Therefore, the display switch signal DSn can be controlled to be a high level by setting the second reset signal of the second reset terminal IN_LF_pulse2 to a low level, thereby controlling the second transistor T2 in the pixel driving circuit to turn off.

[0200] As Figure 9d shown, in the light emitting stage (the fourth stage p24), when the duty ratio control signal at the duty ratio control terminal IN_D_Qn is at a high level (the non-light emitting time in the fourth stage p24), the display switch signal DSn is at a high level, and the second transistor T2 in the pixel driving circuit is turned off, so that the light emitting device EL cannot emit light. Therefore, in the light emitting stage (the fourth stage p24), the light emitting duration of the light emitting device EL can be controlled by controlling the duration of the low level of the duty ratio control signal at the duty ratio control terminal IN_D_Qn (i.e., controlling the duty ratio of the low level in the duty ratio control signal).

[0201] Figure 10 This is an equivalent circuit diagram of a second arithmetic circuit according to an exemplary embodiment of the present disclosure. As Figure 10 shown, in the gate driving circuit of the embodiment of the present disclosure, the second arithmetic circuit of the logic arithmetic circuit may include 38 transistors. Among them, the second NAND gate 302 includes 2 P-type transistors and 2 N-type transistors, and the fifth inverter 405, the sixth inverter 406, the seventh inverter 407, the eighth inverter 408, the ninth inverter 409, and the tenth inverter 410 each include 1 P-type transistor and 1 N-type transistor, the fourth NOR gate 504 includes 2 P-type transistors and 2 N-type transistors, and the latch 520 includes 9 P-type transistors and 9 N-type transistors.

[0202] In an exemplary embodiment, the fifth inverter 405, the sixth inverter 406, the seventh inverter 407, the eighth inverter 408, the ninth inverter 409, the tenth inverter 410, the latch 520, the fourth NOR gate 504, and the second NAND gate 302 may be sequentially arranged along the first direction X (the direction close to the display area in the display substrate).

[0203] In an exemplary embodiment, the twenty-first P-type transistor P21 and the twenty-first N-type transistor N21 form the fifth inverter 405. The gate electrodes of the twenty-first P-type transistor P21 and the twenty-first N-type transistor N21 are connected to each other and connected to the write switch signal terminal WSn of the logic arithmetic circuit. The first pole of the twenty-first P-type transistor P21 is connected to the first power supply line VDD, the first pole of the twenty-first N-type transistor N21 is connected to the ground wire GND, and the second poles of the twenty-first P-type transistor P21 and the twenty-first N-type transistor N21 are connected to each other and are respectively connected to the gate electrodes of the twenty-second P-type transistor P22 and the twenty-second N-type transistor N22.

[0204] In an exemplary embodiment, the twenty-second P-type transistor P22 and the twenty-second N-type transistor N22 form a sixth inverter 406. The gate electrodes of the twenty-second P-type transistor P22 and the twenty-second N-type transistor N22 are connected to each other and are respectively connected to the second pole of the twenty-first P-type transistor P21 and the second pole of the twenty-first N-type transistor N21. The first pole of the twenty-second P-type transistor P22 is connected to the first power supply line VDD, and the first pole of the twenty-second N-type transistor N22 is connected to the ground line GND. The second poles of the twenty-second P-type transistor P22 and the twenty-second N-type transistor N22 are connected to each other and are respectively connected to the gate electrodes of the twenty-third P-type transistor P23 and the twenty-third N-type transistor N23.

[0205] In an exemplary embodiment, the twenty-third P-type transistor P23 and the twenty-third N-type transistor N23 form a seventh inverter 407. The gate electrodes of the twenty-third P-type transistor P23 and the twenty-third N-type transistor N23 are connected to each other and are respectively connected to the second pole of the twenty-second P-type transistor P22 and the second pole of the twenty-second N-type transistor N22. The first pole of the twenty-third P-type transistor P23 is connected to the first power supply line VDD, and the first pole of the twenty-third N-type transistor N23 is connected to the ground line GND. The second poles of the twenty-third P-type transistor P23 and the twenty-third N-type transistor N23 are connected to each other and are respectively connected to the gate electrodes of the twenty-fourth P-type transistor P24 and the twenty-fourth N-type transistor N24.

[0206] In an exemplary embodiment, the twenty-fourth P-type transistor P24 and the twenty-fourth N-type transistor N24 form an eighth inverter 408. The gate electrodes of the twenty-fourth P-type transistor P24 and the twenty-fourth N-type transistor N24 are connected to each other and are respectively connected to the second pole of the twenty-third P-type transistor P23 and the second pole of the twenty-third N-type transistor N23. The first pole of the twenty-fourth P-type transistor P24 is connected to the first power supply line VDD, and the first pole of the twenty-fourth N-type transistor N24 is connected to the ground line GND. The second poles of the twenty-fourth P-type transistor P24 and the twenty-fourth N-type transistor N24 are connected to each other and are respectively connected to the gate electrodes of the twenty-fifth P-type transistor P25 and the twenty-fifth N-type transistor N25.

[0207] In an exemplary embodiment, the twenty-fifth P-type transistor P25 and the twenty-fifth N-type transistor N25 form a ninth inverter 409. The gate electrodes of the twenty-fifth P-type transistor P25 and the twenty-fifth N-type transistor N25 are connected to each other and are respectively connected to the second pole of the twenty-fourth P-type transistor P24 and the second pole of the twenty-fourth N-type transistor N24. The first pole of the twenty-fifth P-type transistor P25 is connected to the first power supply line VDD, and the first pole of the twenty-fifth N-type transistor N25 is connected to the ground line GND. The second poles of the twenty-fifth P-type transistor P25 and the twenty-fifth N-type transistor N25 are connected to each other and are respectively connected to the gate electrodes of the twenty-sixth P-type transistor P26 and the twenty-sixth N-type transistor N26.

[0208] In an exemplary embodiment, the twenty-sixth P-type transistor P26 and the twenty-sixth N-type transistor N26 form a tenth inverter 410. The gate electrodes of the twenty-sixth P-type transistor P26 and the twenty-sixth N-type transistor N26 are connected to each other and are respectively connected to the second pole of the twenty-fifth P-type transistor P25 and the second pole of the twenty-fifth N-type transistor N25. The first pole of the twenty-sixth P-type transistor P26 is connected to the first power supply line VDD, and the first pole of the twenty-sixth N-type transistor N26 is connected to the ground line GND. The second poles of the twenty-sixth P-type transistor P26 and the twenty-sixth N-type transistor N26 are connected to each other and are respectively connected to the gate electrodes of the twenty-ninth P-type transistor P29, the twenty-ninth N-type transistor N29, the thirty-second P-type transistor P32, and the thirty-second N-type transistor N32.

[0209] In an exemplary embodiment, the twenty-seventh P-type transistor P27 to the thirty-fifth P-type transistor P35 and the twenty-seventh N-type transistor N27 to the thirty-fifth N-type transistor N35 form a latch 520.

[0210] In an exemplary embodiment, the gate electrodes of the twenty-seventh P-type transistor P27 and the twenty-seventh N-type transistor N27 are connected to each other and are respectively connected to the second input terminal B_Qn of the logic operation circuit, the gate electrodes of the thirty-third P-type transistor P33, and the gate electrodes of the thirty-third N-type transistor N33. The first pole of the twenty-seventh P-type transistor P27 is connected to the first power supply line VDD, and the first pole of the twenty-seventh N-type transistor N27 is connected to the ground line GND. The second poles of the twenty-seventh P-type transistor P27 and the twenty-seventh N-type transistor N27 are connected to each other and are respectively connected to the gate electrodes of the twenty-eighth P-type transistor P28 and the twenty-eighth N-type transistor N28.

[0211] In an exemplary embodiment, the gate electrodes of the twenty-eighth P-type transistor P28 and the twenty-eighth N-type transistor N28 are connected to each other, and are respectively connected to the second pole of the twenty-seventh P-type transistor P27 and the second pole of the twenty-seventh N-type transistor N27. The gate electrodes of the twenty-ninth P-type transistor P29 and the twenty-ninth N-type transistor N29 are connected to each other, and are respectively connected to the second pole of the twenty-sixth P-type transistor P26, the second pole of the twenty-sixth N-type transistor N26, the gate electrode 232P of the thirty-second P-type transistor P32, and the gate electrode of the thirty-second N-type transistor N32. The first poles of the twenty-eighth P-type transistor P28 and the twenty-ninth P-type transistor P29 are both connected to the first power supply line VDD. The second poles of the twenty-eighth P-type transistor P28 and the twenty-ninth P-type transistor P29 are connected to each other, and are respectively connected to the second pole of the twenty-eighth N-type transistor N28, the gate electrode of the thirtieth P-type transistor P30, and the gate electrode of the thirtieth N-type transistor N30. The first pole of the twenty-ninth N-type transistor N29 is connected to the ground wire GND, and the second pole of the twenty-ninth N-type transistor N29 is connected to the first pole of the twenty-eighth N-type transistor N28.

[0212] In an exemplary embodiment, the gate electrodes of the thirtieth P-type transistor P30 and the thirtieth N-type transistor N30 are connected to each other, and are respectively connected to the second pole of the twenty-eighth P-type transistor P28, the second pole of the twenty-eighth N-type transistor N28, and the second pole of the twenty-ninth P-type transistor P29. The gate electrodes of the thirty-first P-type transistor P31 and the thirty-first N-type transistor N31 are connected to each other, and are respectively connected to the second pole of the thirty-fourth P-type transistor P34, the second pole of the thirty-fourth N-type transistor N34, the second pole of the thirty-fifth P-type transistor P35, the gate electrode of the thirty-sixth P-type transistor P36, and the gate electrode of the thirty-sixth N-type transistor N36. The first poles of the thirtieth P-type transistor P30 and the thirty-first P-type transistor P31 are both connected to the first power supply line VDD. The second poles of the thirtieth P-type transistor P30 and the thirty-first P-type transistor P31 are connected to each other, and are respectively connected to the second pole of the thirty-first N-type transistor N31, the gate electrode of the thirty-fifth P-type transistor P35, and the gate electrode of the thirty-fifth N-type transistor N35. The first pole of the thirtieth N-type transistor N30 is connected to the ground wire GND, and the second pole of the thirtieth N-type transistor N30 is connected to the first pole of the thirty-first N-type transistor N30.

[0213] In an exemplary embodiment, the gate electrodes of the thirty-second P-type transistor P32 and the thirty-second N-type transistor N32 are connected to each other and are respectively connected to the second pole of the twenty-sixth P-type transistor P26, the second pole of the twenty-sixth N-type transistor N26, the gate electrode of the twenty-ninth P-type transistor P29, and the gate electrode of the twenty-ninth N-type transistor N29. The gate electrodes of the thirty-third P-type transistor P33 and the thirty-third N-type transistor N33 are connected to each other and are respectively connected to the second input terminal IN_B_Qn of the logic operation circuit, the gate electrode of the twenty-seventh P-type transistor P27, and the gate electrode of the twenty-seventh N-type transistor N27. The first poles of the thirty-second P-type transistor P32 and the thirty-third P-type transistor P33 are both connected to the first power supply line VDD. The second poles of the thirty-second P-type transistor P32 and the thirty-third P-type transistor P33 are connected to each other and are respectively connected to the second pole of the thirty-third N-type transistor N33, the gate electrode of the thirty-fourth P-type transistor P34, and the gate electrode of the thirty-fourth N-type transistor N34. The first pole of the thirty-second N-type transistor N32 is connected to the ground wire GND, and the second pole of the thirty-second N-type transistor N32 is connected to the first pole of the thirty-third N-type transistor N33.

[0214] In an exemplary embodiment, the gate electrodes of the thirty-fourth P-type transistor P34 and the thirty-fourth N-type transistor N34 are connected to each other and are respectively connected to the second pole of the thirty-second P-type transistor P32, the second pole of the thirty-third P-type transistor P33, and the second pole of the thirty-third N-type transistor N33. The gate electrodes of the thirty-fifth P-type transistor P35 and the thirty-fifth N-type transistor N35 are connected to each other and are respectively connected to the second pole of the thirtieth P-type transistor P30, the second pole of the thirty-first P-type transistor P31, and the second pole of the thirty-first N-type transistor N31. The first poles of the thirty-fourth P-type transistor P34 and the thirty-fifth P-type transistor P35 are both connected to the first power supply line VDD. The second poles of the thirty-fourth P-type transistor P34 and the thirty-fifth P-type transistor P35 are connected to each other and are respectively connected to the second pole of the thirty-fourth N-type transistor N34, the gate electrode of the thirty-first P-type transistor P31, the gate electrode of the thirty-first N-type transistor N31, the gate electrode of the thirty-sixth P-type transistor P36, and the gate electrode of the thirty-sixth N-type transistor N36. The first pole of the thirty-fifth N-type transistor N35 is connected to the ground wire GND, and the second pole of the thirty-fifth N-type transistor N35 is connected to the first pole of the thirty-fourth N-type transistor N34.

[0215] In an exemplary embodiment, the thirty-sixth P-type transistor P36, the thirty-sixth N-type transistor N36, the thirty-seventh P-type transistor P37, and the thirty-seventh N-type transistor N37 form a fourth NOR gate 504. The gate electrodes of the thirty-sixth P-type transistor P36 and the thirty-sixth N-type transistor N36 are connected to each other, and are respectively connected to the second pole of the thirty-fourth P-type transistor P34, the second pole of the thirty-fourth N-type transistor N34, the second pole of the thirty-fifth P-type transistor P35, the gate electrode of the thirty-first P-type transistor P31, and the gate electrode of the thirty-first N-type transistor N31. The gate electrodes of the thirty-seventh P-type transistor P37 and the thirty-seventh N-type transistor N37 are connected to each other and are connected to the duty control terminal IN_D_Qn of the logic operation circuit. The first pole of the thirty-sixth P-type transistor P36 is connected to the first power supply line VDD, the second pole of the thirty-sixth P-type transistor P36 is connected to the first pole of the thirty-seventh P-type transistor P37, the first poles of the thirty-sixth N-type transistor N36 and the thirty-seventh N-type transistor N37 are both connected to the ground wire GND, the second poles of the thirty-sixth N-type transistor N36 and the thirty-seventh N-type transistor N37 are connected to each other, and are respectively connected to the second pole of the thirty-seventh P-type transistor P37, the gate electrode of the thirty-ninth P-type transistor P39, and the gate electrode of the thirty-ninth N-type transistor N39.

[0216] In an exemplary embodiment, the thirty-eighth P-type transistor P38, the thirty-eighth N-type transistor N38, the thirty-ninth P-type transistor P39, and the thirty-ninth N-type transistor N39 form a second NAND gate 302. The gate electrodes of the thirty-eighth P-type transistor P38 and the thirty-eighth N-type transistor N38 are connected to each other and are connected to the second reset terminal IN_LF_pulse2 of the logic operation circuit. The gate electrodes of the thirty-ninth P-type transistor P39 and the thirty-ninth N-type transistor N39 are connected to each other and are respectively connected to the second pole of the thirty-sixth N-type transistor N36, the second pole of the thirty-seventh P-type transistor P37, and the second pole of the thirty-seventh N-type transistor N37. The first poles of the thirty-eighth P-type transistor P38 and the thirty-ninth P-type transistor P39 are both connected to the first power supply line VDD, the first pole of the thirty-ninth N-type transistor N39 is connected to the ground wire GND, the second pole of the thirty-ninth N-type transistor N39 is connected to the first pole of the thirty-eighth N-type transistor N38, and the second poles of the thirty-eighth P-type transistor P38, the thirty-eighth N-type transistor N38, and the thirty-ninth P-type transistor P39 are connected to each other and serve as the output terminal OUT_DS of the second operation circuit (i.e., the output terminal for outputting the display switch signal DSn in FIG. 9, which can be used as the display switch signal terminal OUT_DSn of the logic operation circuit).

[0217] Figure 11aThis is the working principle diagram of a third arithmetic circuit according to an exemplary embodiment of the present disclosure. The third arithmetic circuit may include two parts, and the two parts are respectively a NOR gate and a NAND gate. As shown in FIG. 9, the third arithmetic circuit may include a fifth NOR gate 505 and a third NAND gate 303.

[0218] In an exemplary embodiment, the first input terminal of the fifth NOR gate 505 is connected to the third input terminal IN_C_Qn of the logic arithmetic circuit, the second input terminal of the fifth NOR gate 505 is connected to the second input terminal IN_B_Qn of the logic arithmetic circuit, the third input terminal of the fifth NOR gate 505 is connected to the ratio control terminal IN_D_Qn of the logic arithmetic circuit, the output terminal of the fifth NOR gate 505 is connected to the first input terminal of the third NAND gate 303, the second input terminal of the third NAND gate 303 is connected to the second reset terminal IN_LF_pulse2 of the logic arithmetic circuit, and the output terminal of the third NAND gate 303 serves as the output terminal OUT_AZ of the third arithmetic circuit and as the display reset signal terminal OUT_AZn of the logic arithmetic circuit, and is connected to the display reset control terminal AZ in at least one pixel driving circuit, and outputs a display reset signal to the display reset control terminal AZ in at least one pixel driving circuit. In an exemplary embodiment, the output terminal of the third NAND gate 303 may be connected to the input terminal of another level converter (such as a third level converter), and outputs a display reset signal to the level converter. After the level converter performs a voltage domain conversion on the display reset signal, it outputs the signal to the corresponding row driving enhancer (such as a third row driving enhancer), and the row driving enhancer enhances the converted signal and then outputs it to the display reset control terminal AZ in the corresponding pixel driving circuit.

[0219] In an exemplary embodiment, the working principle of the third arithmetic circuit is as follows: The fifth NOR gate 505 performs a NOR operation on the third input signal C_Qn of the third input terminal IN_C_Qn, the second input signal B_Qn of the second input terminal IN_B_Qn, and the ratio control signal D_Qn of the ratio control terminal IN_D_Qn. The third NAND gate 303 performs a NAND operation on the NOR operation result and the second reset signal of the second reset terminal IN_LF_pulse2. Its logical expression is: Among them, LF_pulse2 is the initialization signal, which remains high (i.e., LF_pulse2 = 1) under normal working conditions, then AZn = B_Qn + C_Qn + D_Qn. When LF_pulse2 is low (i.e., LF_pulse2 = 0), then AZn = 1, and AZn outputs a high level (i.e., AZn = 1). When the light-emitting time ratio is 100%, D_Qn remains low, then AZn = B_Qn + C_Qn. When it is necessary to adjust the light-emitting time ratio, it can be achieved by adjusting the duty cycle of D_Qn. That is, the duty cycle control signal of the duty cycle control terminal IN_D_Qn can affect both the write switch signal DSn and the display reset signal AZn at the same time. The write switch signal DSn and the display reset signal AZn can be controlled simultaneously through the duty cycle control signal of the duty cycle control terminal IN_D_Qn, so as to adjust and control the light-emitting time ratio in the light-emitting stage.

[0220] As Figure 11b shown, it is a timing diagram of the working process of the third arithmetic circuit provided by an exemplary embodiment of the present disclosure. When the second reset signal LF_pulse2 at the second reset terminal IN_LF_pulse2 is a high-level signal, as Figure 11b shown, the working process of the third arithmetic circuit may include four stages from the first stage p21 to the fourth stage p44 (during the light-emitting time in the first stage p21 to the third stage p23 and the fourth stage p24, the duty cycle control signal D_Qn of the duty cycle control terminal IN_D_Qn is a low-level signal, and during the non-light-emitting time in the fourth stage p24, the duty cycle control signal of the duty cycle control terminal IN_D_Qn is a high-level signal):

[0221] First stage p21: The second input signal B_Qn at the second input terminal IN_B_Qn is low level, and the third input signal C_Qn at the third input terminal IN_C_Qn is high level; since the third input signal at the third input terminal IN_C_Qn is high level, the second input signal at the second input terminal IN_B_Qn, the third input signal at the third input terminal IN_C_Qn, and the duty cycle control signal of the duty cycle control terminal IN_D_Qn are subjected to a NOR operation by the fifth NOR gate 505 to obtain a low-level signal. The display reset signal AZn obtained by the NOR operation of the low-level signal and the second reset signal at the second reset terminal IN_LF_pulse2 through the third NAND gate 303 is high level;

[0222] Second stage p22: The second input signal of the second input terminal IN_B_Qn and the third input signal of the third input terminal IN_C_Qn are both high levels; Since the second input signal of the second input terminal IN_B_Qn and the third input signal of the third input terminal IN_C_Qn are both high levels, the second input signal of the second input terminal IN_B_Qn, the third input signal of the third input terminal IN_C_Qn, and the duty ratio control signal of the duty ratio control terminal IN_D_Qn are subjected to a NOR operation by the fifth NOR gate 505 to obtain a low-level signal, and the low-level signal obtained through the NOR operation and the second reset signal of the second reset terminal IN_LF_pulse2 are subjected to a NAND operation by the third NAND gate 303 to obtain a high-level display reset signal AZn;

[0223] Third stage p23: The second input signal of the second input terminal IN_B_Qn is high level and the third input signal of the third input terminal IN_C_Qn is low level; Since the second input signal of the second input terminal IN_B_Qn is high level, the second input signal of the second input terminal B_Qn, the third input signal of the third input terminal C_Qn, and the duty ratio control signal of the duty ratio control terminal IN_D_Qn are subjected to a NOR operation by the fifth NOR gate 505 to obtain a low-level signal, and the low-level signal obtained through the NOR operation and the second reset signal of the second reset terminal IN_LF_pulse2 are subjected to a NAND operation by the third NAND gate 303 to obtain a high-level display reset signal AZn;

[0224] Emission time in the fourth stage p24: The second input signal of the second input terminal IN_B_Qn and the third input signal of the third input terminal IN_C_Qn are both low levels; Since the second input signal of the second input terminal IN_B_Qn, the third input signal of the third input terminal IN_C_Qn, and the duty ratio control signal of the duty ratio control terminal IN_D_Qn are all low levels, the second input signal of the second input terminal IN_B_Qn, the third input signal of the third input terminal IN_C_Qn, and the duty ratio control signal of the duty ratio control terminal IN_D_Qn are subjected to a NOR operation by the fifth NOR gate 505 to obtain a high-level signal, and the high-level signal obtained through the NOR operation and the second reset signal of the second reset terminal IN_LF_pulse2 are subjected to a NAND operation by the third NAND gate 303 to obtain a low-level display reset signal AZn. The low-level display reset signal AZn can control the fourth transistor T4 in the pixel driving circuit to turn off, so that the driving current can control the light-emitting device EL to emit light. This stage is called the light-emitting stage.

[0225] In an exemplary embodiment, such as Figure 11bAs shown, when the duty control signal at the duty control terminal IN_D_Qn is a high-level signal (the non-light-emitting time in the fourth stage p24), the second input signal at the second input terminal IN_B_Qn, the third input signal at the third input terminal IN_C_Qn, and the duty control signal at the duty control terminal IN_D_Qn are subjected to a NOR operation by the fifth NOR gate 505 to obtain a low-level signal. The low-level signal obtained through the NOR operation and the second reset signal at the second reset terminal IN_LF_pulse2 are subjected to a NAND operation by the third NAND gate 303 to obtain a high-level display reset signal AZn, which controls the fourth transistor T4 in the pixel driving circuit to conduct, thereby driving a current to flow through the fourth transistor T4 in the pixel driving circuit, causing the light-emitting device EL not to emit light. As Figure 11b and Figure 11c shown, in the light-emitting stage (the fourth stage p24), the duration of light emission can be controlled by controlling the duration of the low level of the duty control signal at the duty control terminal IN_D_Qn (i.e., controlling the duty ratio of the low level in the duty control signal at the duty control terminal IN_D_Qn). In Figure 11c the working timing shown, the duty ratio of the low level in the duty control signal at the duty control terminal IN_D_Qn is 100% (the light-emitting time ratio in the light-emitting stage is 100%). Figure 11b In the working timing in

[0226] In an exemplary embodiment, as Figure 11d shown, when the second reset signal at the second reset terminal IN_LF_pulse2 is a low level, the display reset signal AZn is a high level, and the fourth transistor T4 in the pixel driving circuit is turned off. Therefore, by controlling the second reset signal at the second reset terminal IN_LF_pulse2 to be a low level, the display reset signal AZn can be made a high level, thereby controlling the fourth transistor T4 in the pixel driving circuit to be turned off.

[0227] In an exemplary embodiment, in Figure 9a the second arithmetic circuit shown, the logical expression of the display switch signal DSn output from the display switch signal terminal OUT_DSn is:[[]] In the case of normal operation, the enable signal EN at the enable signal terminal EN of the latch 520 is a high level, Q = B_Qn, LF_pulse2 = 1. That is, in the case of normal operation, the logical expression of the display switch signal DSn output from the display switch signal terminal OUT_DSn is: DSn = D_Qn + B_Qn. In Figure 11a the third arithmetic circuit shown, the logical expression of the display reset signal AZn is:[[]] When LF_pulse2 = 1 under normal working conditions, the logical expression of the display reset signal AZn is: AZn = B_Qn + C_Qn + D_Qn. Thus, it can be seen that under normal working conditions, the display switch signal DSn can be controlled by the duty ratio control signal D_Qn and the second input signal B_Qn, and the display reset signal AZn can be controlled by the duty ratio control signal D_Qn, the second input signal B_Qn, and the third input signal C_Qn. The working principle diagram for generating the display switch signal DSn can be as Figure 9a shown, and the working principle diagram for generating the display reset signal AZn can be as Figure 11a shown. However, the embodiments of the present disclosure are not limited thereto. For example, from the logical expression, under normal working conditions, the display reset signal AZn can be triggered by the display switch signal DSn, i.e., AZn = DSn + C_Qn, which means the display reset signal AZn can be controlled by the display switch signal DSn and the third input signal C_Qn, that is, the display reset signal AZn can be generated through the display switch signal DSn and the third input signal C_Qn. The working timing diagram of the gate drive circuit is as Figure 6c shown. During the light-emitting stage, the time when the display reset signal terminal OUT_AZn stops outputting the valid level signal in the display reset signal AZn (i.e., the falling edge of the display reset signal) is basically synchronized with the time when the display switch signal terminal OUT_DSn starts outputting the valid level signal in the display switch signal DSn (the falling edge of the display switch signal DSn).

[0228] Under normal working conditions, the display switch signal DSn is controlled by the duty ratio control signal D_Qn and the second input signal B_Qn (DSn = D_Qn + B_Qn), and the display reset signal AZn is controlled by the duty ratio control signal D_Qn, the second input signal B_Qn, and the third input signal C_Qn (AZn = B_Qn + C_Qn + D_Qn). The working timing diagram of the gate drive circuit can be as Figure 6bAs shown, under the control of the second input signal B_Qn, the start time of the valid level signal in the display switch signal DSn output by the display switch signal terminal OUT_DSn is not earlier than the falling edge of the second input signal B_Qn; the falling edge of the third input signal C_Qn is not later than the falling edge of the second input signal B_Qn. Under the control of the second input signal B_Qn and the third input signal C_Qn, the end time of the valid level signal in the display reset signal AZn output by the display reset signal terminal OUT_AZn is substantially synchronized with the falling edge of the second input signal B_Qn. That is, under the control of the second input signal B_Qn and the third input signal C_Qn, the time when the display reset signal terminal OUT_AZn stops outputting the valid level signal in the display reset signal AZn is substantially synchronized with the falling edge of the second input signal B_Qn, so that the start time of the valid level signal in the display switch signal DSn output by the display switch signal terminal OUT_DSn is not earlier than the time when the display reset signal terminal OUT_AZn stops outputting the valid level signal in the display reset signal AZn.

[0229] Figure 12 The figure is an equivalent circuit diagram of a third arithmetic circuit according to an exemplary embodiment of the present disclosure. As Figure 12 shown, the third arithmetic circuit of the logic arithmetic circuit of the gate driving circuit in the display substrate according to the embodiment of the present disclosure may include 10 transistors. Among them, the fifth NOR gate 505 includes 3 P-type transistors and 3 N-type transistors, and the third NAND gate 303 includes 2 P-type transistors and 2 N-type transistors.

[0230] In an exemplary embodiment, the fifth NOR gate 505 and the third NAND gate 303 may be arranged in sequence along the first direction X (the direction close to the display area).

[0231] In an exemplary embodiment, a forty-first P-type transistor P41, a forty-first N-type transistor N41, a forty-second P-type transistor P42, a forty-second N-type transistor N42, a forty-third P-type transistor P43, and a forty-third N-type transistor N43 form a fifth NOR gate 505. The gate electrodes of the forty-first P-type transistor P41 and the forty-first N-type transistor N41 are connected to each other and are connected to the duty ratio control terminal IN_D_Qn of the logic operation circuit. The gate electrodes of the forty-second P-type transistor P42 and the forty-second N-type transistor N42 are connected to each other and are connected to the second input terminal IN_B_Qn of the logic operation circuit. The gate electrodes of the forty-third P-type transistor P43 and the forty-third N-type transistor N43 are connected to each other and are connected to the third input terminal IN_C_Qn of the logic operation circuit. The first pole of the forty-first P-type transistor P41 is connected to the first power supply line VDD. The second pole of the forty-first P-type transistor P41 is connected to the first pole of the forty-second P-type transistor P42. The second pole of the forty-second P-type transistor P42 is connected to the first pole of the forty-third P-type transistor P43. The first poles of the forty-first N-type transistor N41, the forty-second N-type transistor N42, and the forty-third N-type transistor N43 are all connected to the ground wire GND. The second poles of the forty-first N-type transistor N41, the forty-second N-type transistor N42, and the forty-third N-type transistor N43 are connected to each other and are respectively connected to the second pole of the forty-third P-type transistor P43, the gate electrode of the forty-fifth P-type transistor P45, and the gate electrode of the forty-fifth N-type transistor N45.

[0232] In an exemplary embodiment, the forty-fourth P-type transistor P44, the forty-fourth N-type transistor N44, the forty-fifth P-type transistor P45, and the forty-fifth N-type transistor N45 form a third NAND gate 303. The gate electrodes of the forty-fourth P-type transistor P44 and the forty-fourth N-type transistor N44 are connected to each other and connected to the second reset terminal IN_LF_pulse2 of the logic operation circuit. The gate electrodes of the forty-fifth P-type transistor P45 and the forty-fifth N-type transistor N45 are connected to each other and are respectively connected to the second pole of the forty-first N-type transistor N41, the second pole of the forty-second N-type transistor N42, the second pole of the forty-third N-type transistor N43, and the second pole of the forty-third P-type transistor P43. The first poles of the forty-fourth P-type transistor P44 and the forty-fifth P-type transistor P45 are both connected to the first power supply line VDD. The first pole of the forty-fourth N-type transistor N44 is connected to the ground wire GND. The second pole of the forty-fourth N-type transistor N44 is connected to the first pole of the forty-fifth N-type transistor N45. The second poles of the forty-fourth P-type transistor P44, the forty-fifth P-type transistor P45, and the forty-fifth N-type transistor N45 are connected to each other and serve as the output terminal OUT_AZ of the third operation circuit (i.e., the output terminal for outputting the display reset signal AZn in FIG. 11, which can be used as the display reset signal terminal OUT_AZn of the logic operation circuit).

[0233] Figure 13 This is the working principle diagram of a level shifter according to an exemplary embodiment of the present disclosure. As Figure 13 shown, the level shifter may include an eleventh inverter 411, a first P-type field effect transistor 501P, a second P-type field effect transistor 502P, a first N-type field effect transistor 501N, and a second N-type field effect transistor 502N.

[0234] In an exemplary embodiment, the input terminal IN_shifter of the level shifter is respectively connected to the input terminal of the eleventh inverter 411 and the gate electrode of the first P-type field effect transistor 501P (wherein, the input terminal of the second level shifter is electrically connected to the display switch signal terminal DSn in the logic operation circuit, and the input terminal of the third level shifter is electrically connected to the display reset signal terminal AZ in the path operation circuit). The output terminal of the eleventh inverter 411 is connected to the gate electrode of the second P-type field effect transistor 502P. The first poles of the first P-type field effect transistor 501P and the second P-type field effect transistor 502P are both connected to the first power supply line VDD. The second pole of the first P-type field effect transistor 501P is respectively connected to the second pole of the first N-type field effect transistor 501N, the gate electrode of the second N-type field effect transistor 502N, and the second output terminal OUT_B_shifter of the level shifter. The second pole of the second P-type field effect transistor 502P is respectively connected to the gate electrode of the first N-type field effect transistor 501N, the second pole of the second N-type field effect transistor 502N, and the first output terminal OUT_shifter of the level shifter. The first poles of the first N-type field effect transistor 501N and the second N-type field effect transistor 502N are both connected to the second power supply line VSS. Among them, the first output terminal of the second level shifter is electrically connected to the first input terminal of the second row driving booster; the second output terminal of the second level shifter is electrically connected to the second input terminal of the second row driving booster; the first output terminal of the third level shifter is electrically connected to the first input terminal of the third row driving booster; the second output terminal of the third level shifter is electrically connected to the second input terminal of the third row driving booster.

[0235] In an exemplary embodiment, the working principle of the level shifter is as follows: when the input signal of the input terminal IN_shifter of the level shifter is at a low level, the first P-type field effect transistor 501P is turned on, the second P-type field effect transistor 502P is turned off, the output signal of the second output terminal OUT_B_shifter of the level shifter is the signal of the first power supply line VDD, the second N-type field effect transistor 502N is turned on, the output signal of the first output terminal OUT_shifter of the level shifter is the signal of the second power supply line VSS, and the first N-type field effect transistor 501N is turned off. When the input signal of the input terminal IN_shifter of the level shifter is at a high level, the first P-type field effect transistor 501P is turned off, the second P-type field effect transistor 502P is turned on, the output signal of the first output terminal OUT_shifter of the level shifter is the signal of the first power supply line VDD, the first N-type field effect transistor 501N is turned on, the output signal of the second output terminal OUT_B_shifter of the level shifter is the signal of the second power supply line VSS, and the second N-type field effect transistor 502N is turned off.

[0236] Figure 14This is the working principle diagram of a line driver enhancer according to an exemplary embodiment of the present disclosure. As Figure 14 shown, the line driver enhancer may include a fourth NAND gate 304, a fifth NAND gate 305, a first transmission gate 201, a twelfth inverter 412, a third P-type field effect transistor 503P, and a third N-type field effect transistor 503N. The third P-type field effect transistor 503P and the third N-type field effect transistor 503N have a relatively large width-to-length ratio to achieve an improvement in driving ability. The line driver enhancer can enhance the driving ability of a signal, and the signal enhanced by the line driver enhancer can enhance the load-bearing ability and can be applied to a pixel driving circuit for driving an entire line.

[0237] In an exemplary embodiment, the first input terminal IN_driver of the line driver enhancer is connected to the first input terminal of the fourth NAND gate 304, the enable signal terminal EN of the line driver enhancer is connected to the second input terminal of the fourth NAND gate 304, the output terminal of the fourth NAND gate 304 is connected to the input terminal of the first transmission gate 201, the output terminal of the first transmission gate 201 is connected to the gate electrode of the third P-type field effect transistor 503P, and the first pole of the third P-type field effect transistor 503P is connected to the first power supply line VDD. The second input terminal IN_B_driver of the line driver enhancer is connected to the first input terminal of the fifth NAND gate 305, the enable signal terminal EN of the line driver enhancer is connected to the second input terminal of the fifth NAND gate 305, the output terminal of the fifth NAND gate 305 is connected to the input terminal of the twelfth inverter 412, the output terminal of the twelfth inverter 412 is connected to the gate electrode of the third N-type field effect transistor 503N, and the first pole of the third N-type field effect transistor 503N is connected to the second power supply line VSS. The second poles of the third P-type field effect transistor 503P and the third N-type field effect transistor 503N are connected to the output terminal OUT_driver of the line driver enhancer. The high-level active enable terminals of the first transmission gate 201 and the twelfth inverter 412 are connected to the first power supply line VDD, and the low-level active enable terminals are connected to the second power supply line VSS. The high-level active enable terminals of the fourth NAND gate 304 and the fifth NAND gate 305 are connected to the first power supply line VDD, and the low-level active enable terminals are connected to the ground wire GND. In an exemplary embodiment, the output terminal of the second line driver enhancer is electrically connected to the display switch control terminal DS in the corresponding pixel driving circuit, and the output terminal of the third line driver enhancer is electrically connected to the display reset control terminal AZ in the corresponding pixel driving circuit.

[0238] In an exemplary embodiment, when the enable signal input to the enable signal terminal EN of the row driving booster is a first-level signal, the state of the row driving booster is a high-impedance state, which can meet the requirement that on the basis of the gate driving circuit being a bilateral drive (i.e., the gate driving circuit is located on both sides of the display area of the display substrate), the enable signal input to the enable signal terminal of the row driving booster on one side of the display area is set to the first level, so that the modified row driving booster is in a high-impedance state, and unilateral driving of the gate driving circuit can be achieved. That is, when gate driving circuits are provided on both sides of the display area, unilateral driving (the row driving booster on one side of the display area is in a high-impedance state) or bilateral driving (the row driving boosters on both sides of the display area are not in a high-impedance state) of the gate driving circuit can be achieved through the high-impedance state of the row driving booster.

[0239] In an exemplary embodiment, among the enable signals input to the enable signal terminal EN of the row driving booster, the first level can be a low level, that is, the enable signal is a low level. The embodiments of the present disclosure are not limited thereto, and can be set according to the circuit structure of the row driving booster, as long as the row driving booster is in a high-impedance state when the enable signal is at the first level.

[0240] In an exemplary embodiment, the working principle of the row driving booster is as follows:

[0241] When the enable signal at the enable signal terminal EN is 0, the fourth NAND gate 304 and the fifth NAND gate 305 output 1 (high level). The output of the fourth NAND gate 304 outputs 1 (high level) after passing through the first transmission gate 201, the third P-type field effect transistor 503P is turned off, the output of the fifth NAND gate 305 outputs 0 (low level) after passing through the twelfth inverter 412, the third N-type field effect transistor 503N is turned off, and the entire circuit state is a high-impedance state.

[0242] When the enable signal at the enable signal terminal EN is 1, the circuit output is determined by the input signals of the first input terminal IN_driver and the second input terminal IN_B_driver of the row driving booster. The input signals of the first input terminal IN_driver and the second input terminal IN_B_driver of the row driving booster are opposite-direction signals. Opposite-direction signals mean that when the input signal of the first input terminal IN_driver is a high-level signal 1, the input signal of the second input terminal IN_B_driver is a low-level signal 0; when the input signal of the first input terminal IN_driver is a low-level signal 0, the input signal of the second input terminal IN_B_driver is a high-level signal 1.

[0243] When the input signal of the first input terminal IN_driver of the line driving booster is 1 and the input signal of the second input terminal IN_B_driver is 0, the fourth NAND gate 304 outputs 0. The output of the fourth NAND gate 304 passes through the first transmission gate 201 and then outputs 0, and the third P-type field effect transistor 503P conducts. The fifth NAND gate 305 outputs 1. The output of the fifth NAND gate 305 passes through the twelfth inverter 412 and then outputs 0, and the third N-type field effect transistor 503N is turned off. The output signal of the output terminal OUT_driver of the line driving booster is the signal (high level) of the first power supply line VDD.

[0244] When the input signal of the first input terminal IN_driver of the line driving booster is 0 and the input signal of the second input terminal IN_B_driver is 1, the fourth NAND gate 304 outputs 1. The output of the fourth NAND gate 304 passes through the first transmission gate 201 and then outputs 1, and the third P-type field effect transistor 503P is turned off. The fifth NAND gate 305 outputs 0. The output of the fifth NAND gate 305 passes through the twelfth inverter 412 and then outputs 1, and the third N-type field effect transistor 503N conducts. The output signal of the output terminal OUT_driver of the line driving booster is the signal (low level) of the second power supply line VSS.

[0245] In an exemplary embodiment, when the enable signal at the enable signal terminal EN is 0, the circuit outputs a high impedance state. When the enable signal at the enable signal terminal EN is 1, the circuit output does not change the logic relationship of the high and low input and output. The enable signal at the enable signal terminal EN is a high configuration control signal. In principle, the line driving booster is a buffer with a large aspect ratio, so it has a large output current and high driving ability. At the same time, the line driving booster has a small output impedance and strong driving ability.

[0246] In an exemplary embodiment, the input terminal IN_shifter of the level shifter can be connected to the output terminal of the logic operation circuit 200. The first output terminal OUT_shifter of the level shifter can be connected to the first input terminal IN_driver of the line driving booster. The second output terminal OUT_B_shifter of the level shifter can be connected to the second input terminal IN_B_driver of the line driving booster. The output terminal OUT_driver of the line driving booster can be connected to the scan signal line of the display area.

[0247] Figure 15 This is an equivalent circuit diagram of a level shifter according to an exemplary embodiment of the present disclosure. As Figure 15As shown, the level shifter of the gate driving circuit in the substrate in the embodiments of the present disclosure may include 16 transistors. Among them, the eleventh inverter 411 includes 1 P-type transistor and 1 N-type transistor, the first P-type field effect transistor 501P includes 6 P-type transistors, the second P-type field effect transistor 502P includes 6 P-type transistors, the first N-type field effect transistor 501N includes 1 N-type transistor, and the second N-type field effect transistor 502N includes 1 N-type transistor.

[0248] In an exemplary embodiment, the fifty-first P-type transistor P1 and the fifty-first N-type transistor N1 form the eleventh inverter 411. The gate electrodes of the fifty-first P-type transistor P1 and the fifty-first N-type transistor N1 are both connected to the converter input terminal IN_shifter. The first pole of the fifty-first P-type transistor P1 is connected to the first power supply line VDD, the first pole of the fifty-first N-type transistor N1 is connected to the ground line GND, the second pole of the fifty-first P-type transistor P1 is connected to the second pole of the fifty-first N-type transistor N1, and is connected to the gate electrodes of 6 P-type transistors in the second P-type field effect transistor 502P.

[0249] In an exemplary embodiment, the parallel-connected fifty-second P-type transistor P52, fifty-third P-type transistor P53, fifty-fourth P-type transistor P54, fifty-fifth P-type transistor P55, fifty-sixth P-type transistor P56, and fifty-seventh P-type transistor P57 form the first P-type field effect transistor 501P. The gate electrodes of the fifty-second P-type transistor P52 to the fifty-seventh P-type transistor P57 are all connected to the converter input terminal IN_shifter. The first poles of the fifty-second P-type transistor P52 to the fifty-seventh P-type transistor P57 are all connected to the first power supply line VDD. The second poles of the fifty-second P-type transistor P52 to the fifty-seventh P-type transistor P57 are respectively connected to the gate electrode of the fifty-third N-type transistor N53, the second pole of the fifty-second N-type transistor N52, and the converter second output terminal OUT_B_shifter.

[0250] In an exemplary embodiment, the fifty-eighth P-type transistor P58, the fifty-ninth P-type transistor P59, the sixtieth P-type transistor P60, the sixty-first P-type transistor P61, the sixty-second P-type transistor P62, and the sixty-third P-type transistor P63 connected in parallel form the second P-type field effect transistor 502P. The gate electrodes of the fifty-eighth P-type transistor P58 to the sixty-third P-type transistor P63 are all connected to the second pole of the fifty-first P-type transistor P51 and the second pole of the fifty-first N-type transistor N51. The first poles of the fifty-eighth P-type transistor P58 to the sixty-third P-type transistor P63 are all connected to the first power supply line VDD. The second poles of the fifty-eighth P-type transistor P58 to the sixty-third P-type transistor P63 are respectively connected to the gate electrode of the fifty-second N-type transistor N52, the second pole of the fifty-third N-type transistor N53, and the first output terminal OUT_shifter of the converter.

[0251] In an exemplary embodiment, the fifty-second N-type transistor N52 serves as the first N-type field effect transistor 501N. The gate electrode of the fifty-second N-type transistor N52 is respectively connected to the first output terminal OUT_shifter of the converter and the second poles of the fifty-eighth P-type transistor P58 to the sixty-third P-type transistor P63. The first pole of the fifty-second N-type transistor N52 is connected to the second power supply line VSS. The second pole of the fifty-second N-type transistor N52 is respectively connected to the second output terminal OUT_B_shifter of the converter and the second poles of the fifty-second P-type transistor P52 to the fifty-seventh P-type transistor P57.

[0252] In an exemplary embodiment, the fifty-third N-type transistor N53 serves as the second N-type field effect transistor 502N. The gate electrode of the fifty-third N-type transistor N53 is respectively connected to the second output terminal OUT_B_shifter of the converter and the second poles of the fifty-second P-type transistor P52 to the fifty-seventh P-type transistor P57. The first pole of the fifty-third N-type transistor N53 is connected to the second power supply line VSS. The second pole of the fifty-third N-type transistor N53 is respectively connected to the first output terminal OUT_shifter of the converter and the second poles of the fifty-eighth P-type transistor P58 to the sixty-third P-type transistor P63.

[0253] Figure 16 This is an equivalent circuit diagram of a line driving booster according to an exemplary embodiment of the present disclosure. As Figure 16As shown, the row driver enhancer of the gate driving circuit in the substrate in the embodiments of the present disclosure may include 20 transistors. Among them, the fourth NAND gate 304 includes 2 P-type transistors and 2 N-type transistors, the fifth NAND gate 305 includes 2 P-type transistors and 2 N-type transistors, the first transmission gate 201 includes 1 P-type transistor and 1 N-type transistor, the twelfth inverter 412 includes 1 P-type transistor and 1 N-type transistor, the third P-type field effect transistor 503P includes 4 P-type transistors, and the third N-type field effect transistor 503N includes 4 N-type transistors.

[0254] In an exemplary embodiment, the fourth NAND gate 304, the first transmission gate 201, the fifth NAND gate 305, and the twelfth inverter 412 may be sequentially arranged along the first direction X (the direction close to the display area), the third P-type field effect transistor 503P and the third N-type field effect transistor 503N may be arranged on one side of the twelfth inverter 412 in the first direction X, and the third N-type field effect transistor 503N may be arranged on one side of the third P-type field effect transistor 503P in the second direction Y.

[0255] In an exemplary embodiment, the seventy-first P-type transistor P71, the seventy-second P-type transistor P72, the seventy-first N-type transistor N71, and the seventy-second N-type transistor N72 form the fourth NAND gate 304. The gate electrodes of the seventy-first P-type transistor P71 and the seventy-first N-type transistor N71 are connected to each other and connected to the first input terminal IN_driver of the enhancer. The gate electrodes of the seventy-second P-type transistor P72 and the seventy-second N-type transistor N72 are connected to each other and connected to the enable signal terminal EN. The first poles of the seventy-first P-type transistor P71 and the seventy-second P-type transistor P72 are both connected to the first power supply line VDD. The first pole of the seventy-second N-type transistor N72 is connected to the second power supply line VSS. The second pole of the seventy-second N-type transistor N72 is connected to the first pole of the seventy-first N-type transistor N71. The second poles of the seventy-first P-type transistor P71 and the seventy-second P-type transistor P72 are connected to each other and respectively connected to the second pole of the seventy-first N-type transistor N71, the first pole of the seventy-third P-type transistor P73, and the first pole of the seventy-third N-type transistor N73.

[0256] In an exemplary embodiment, a seventy-third P-type transistor P73 and a seventy-third N-type transistor N73 form a first transmission gate 201. The gate electrode of the seventy-third P-type transistor P73 is connected to a second power supply line VSS, the gate electrode of the seventy-third N-type transistor N73 is connected to a first power supply line VDD, the first poles of the seventy-third P-type transistor P73 and the seventy-third N-type transistor N73 are connected to each other and are respectively connected to the second pole of a seventy-first P-type transistor P71, the second pole of a seventy-first N-type transistor N71, and the second pole of a seventy-second P-type transistor P72, the second poles of the seventy-third P-type transistor P73 and the seventy-third N-type transistor N73 are connected to each other and are respectively connected to the gate electrodes of a seventy-seventh P-type transistor P77 to an eightieth P-type transistor P80.

[0257] In an exemplary embodiment, a seventy-fourth P-type transistor P74, a seventy-fifth P-type transistor P75, a seventy-fourth N-type transistor N74, and a seventy-fifth N-type transistor N75 form a fifth NAND gate 305. The gate electrodes of the seventy-fourth P-type transistor P74 and the seventy-fourth N-type transistor N74 are connected to each other and are connected to an enhancer second input terminal IN_B_driver, the gate electrodes of the seventy-fifth P-type transistor P75 and the seventy-fifth N-type transistor N75 are connected to each other and are connected to an enable signal terminal EN, the first poles of the seventy-fourth P-type transistor P74 and the seventy-fifth P-type transistor P75 are both connected to a first power supply line VDD, the first pole of the seventy-fifth N-type transistor N75 is connected to a second power supply line VSS, the second pole of the seventy-fifth N-type transistor N75 is connected to the first pole of the seventy-fourth N-type transistor N74, the second poles of the seventy-fourth P-type transistor P74 and the seventy-fifth P-type transistor P75 are connected to each other and are respectively connected to the second pole of the seventy-fourth N-type transistor N74, the gate electrode of a seventy-sixth P-type transistor P76, and the gate electrode of a seventy-sixth N-type transistor N76.

[0258] In an exemplary embodiment, a seventy-sixth P-type transistor P76 and a seventy-sixth N-type transistor N76 form a twelfth inverter 412. The gate electrodes of the seventy-sixth P-type transistor P76 and the seventy-sixth N-type transistor N76 are connected to each other and are respectively connected to the second pole of the seventy-fourth P-type transistor P74, the second pole of the seventy-fourth N-type transistor N74, and the second pole of the seventy-fifth P-type transistor P75, the first pole of the seventy-sixth P-type transistor P76 is connected to a first power supply line VDD, the first pole of the seventy-sixth N-type transistor N76 is connected to a second power supply line VSS, the second pole of the seventy-sixth P-type transistor P76 is connected to the second pole of the seventy-sixth N-type transistor N27 and is respectively connected to the gate electrodes of a seventy-seventh N-type transistor N77 to an eightieth N-type transistor N80.

[0259] In an exemplary embodiment, the parallel-connected seventy-seventh P-type transistor P77, seventy-eighth P-type transistor P78, seventy-ninth P-type transistor P79, and eightieth P-type transistor P80 form a third P-type field-effect transistor 503P. The gate electrodes of the seventy-seventh P-type transistor P77 to the eightieth P-type transistor P80 are connected to each other and are respectively connected to the second pole of the seventy-third P-type transistor P73 and the second pole of the seventy-third N-type transistor N73. The first poles of the seventy-seventh P-type transistor P77 to the eightieth P-type transistor P80 are all connected to the first power supply line VDD, and the second poles of the seventy-seventh P-type transistor P77 to the eightieth P-type transistor P80 are all connected to the enhancer output terminal OUT_driver.

[0260] In an exemplary embodiment, the parallel-connected seventy-seventh N-type transistor N77, seventy-eighth N-type transistor N78, seventy-ninth N-type transistor N79, and eightieth N-type transistor N80 form a third N-type field-effect transistor 503N. The gate electrodes of the seventy-seventh N-type transistor N77 to the eightieth N-type transistor N80 are connected to each other and are respectively connected to the second pole of the seventy-sixth P-type transistor P76 and the second pole of the seventy-sixth N-type transistor N76. The first poles of the seventy-seventh N-type transistor N77 to the eightieth N-type transistor N80 are all connected to the second power supply line VSS, and the second poles of the seventy-seventh N-type transistor N77 to the eightieth N-type transistor N80 are all connected to the enhancer output terminal OUT_driver.

[0261] Figure 17 This is an equivalent circuit diagram of an output circuit (including a level converter and a line drive enhancer) according to an exemplary embodiment of the present disclosure. As Figure 15 、 Figure 16 and Figure 17 shown, the output circuit includes Figure 15 the level converter shown in Figure 16 and the line drive enhancer shown in

[0262] In an exemplary embodiment, as Figure 18As shown, it is a timing diagram of a working process of the gate drive circuit according to an exemplary embodiment of the present disclosure. When the second reset signal LF_pulse2 at the second reset terminal IN_LF_pulse2 is a high-level signal, the working process of the gate drive circuit may include four stages, namely the first stage p31 to the fourth stage p34 (during the light-emitting time in the first stage p31 to the third stage p33 and the fourth stage p34, the duty ratio control signal D_Qn at the duty ratio control terminal IN_D_Qn is a low-level signal, and during the non-light-emitting time in the fourth stage p34, the duty ratio control signal D_Qn at the duty ratio control terminal IN_D_Qn is a high-level signal):

[0263] The first stage p31: The enable signal EN of the enable signal terminal IN_EN changes from high level to low level (the fifth inverter 405 to the tenth inverter 410 delay the low-level signal of the write switch signal terminal OUT_WSn by Δt1, and the falling edge of the low level of the enable signal terminal IN_EN arrives Δt1 later than the low-level signal of the write switch signal terminal OUT_WSn). The second input signal B_Qn of the second input terminal IN_B_Qn changes from low level to high level, and the third input signal C_Qn of the third input terminal IN_C_Qn is at high level. In the second arithmetic circuit, since the enable signal EN of the enable signal terminal IN_EN changes from high level to low level, the signal at the first output terminal OUT_Q of the latch 520 remains at the low level of the previous stage (in the previous stage, the enable signal EN of the enable signal terminal IN_EN was at high level, the second input signal B_Qn of the second input terminal IN_B_Qn was at low level, and the signal at the output terminal OUT_Q of the latch 520 was at low level). The ratio control signal (low-level signal) of the ratio control terminal IN_D_Qn and the signal (low-level signal) at the first output terminal OUT_Q of the latch 520 perform NOR operation through the fourth NOR gate 504 to obtain a high-level signal. The high-level signal obtained after the NOR operation and the second reset signal of the second reset terminal IN_LF_pulse2 perform NAND operation through the second NAND gate 302 to obtain the display switch signal DSn as a low-level signal. In the third arithmetic circuit, since the third input signal of the third input terminal IN_C_Qn is at high level, the second input signal of the second input terminal IN_B_Qn, the third input signal of the third input terminal IN_C_Qn, and the ratio control signal of the ratio control terminal IN_D_Qn perform NOR operation through the fifth NOR gate 505 to obtain a low-level signal. The low-level signal obtained after the NOR operation and the second reset signal of the second reset terminal IN_LF_pulse2 perform NAND operation through the third NAND gate 303 to obtain the display reset signal AZn as a high-level signal. In this stage, the display switch signal DSn is at low level (equivalent to providing a low-level signal to the second scan signal line S2), and the display reset signal AZn is at high level (equivalent to providing a high-level signal to the third scan signal line S3). Therefore, the first stage p31 of the gate drive circuit is equivalent to the gate drive circuit providing signals to the first stage A1 (initialization stage) of the pixel drive circuit).

[0264] In the second stage p32: the signal of the write switch signal terminal OUT_WSn, the enable signal of the enable signal terminal IN_EN, the second input signal of the second input terminal IN_B_Qn, and the third input signal of the third input terminal IN_C_Qn are all at high level; in the second arithmetic circuit, since the second input signal of the second input terminal IN_B_Qn and the enable signal of the enable signal terminal IN_EN are both at high level, the signal of the first output terminal OUT_Q of the latch 520 is at high level. The ratio control signal (low level signal) of the ratio control terminal IN_D_Qn and the signal (high level signal) of the first output terminal OUT_Q of the latch 520 are NAND-operated by the fourth NOR gate 504 to obtain a low level signal. The low level signal obtained after the NOR operation and the second reset signal of the second reset terminal IN_LF_pulse2 are NAND-operated by the second NAND gate 302 to obtain the display switch signal DSn as a high level signal; in the third arithmetic circuit, since the second input signal of the second input terminal IN_B_Qn and the third input signal of the third input terminal IN_C_Qn are at high level, the second input signal of the second input terminal IN_B_Qn, the third input signal of the third input terminal IN_C_Qn, and the ratio control signal of the ratio control terminal IN_D_Qn are NOR-operated by the fifth NOR gate 505 to obtain a low level signal. The low level signal obtained after the NOR operation and the second reset signal of the second reset terminal IN_LF_pulse2 are NAND-operated by the third NAND gate 303 to obtain the display reset signal AZn as a high level; in this stage, the display switch signal DSn is at high level (equivalent to the signal provided to the second scan signal line S2 being at high level), and the display reset signal AZn is at high level (equivalent to the signal provided to the third scan signal line S3 being at high level signal). The second transistor T2 in the pixel driving circuit is turned off and the fourth transistor T4 is turned on. Therefore, the second stage p32 of the gate driving circuit is equivalent to the gate driving circuit providing a signal to the second stage A2 (self-discharge stage) of the pixel driving circuit.

[0265] The signals of the write switch signal terminal OUT_WSn, the enable signal of the enable signal terminal IN_EN, and the third input signal of the third input terminal IN_C_Qn are all low levels, and the second input signal of the second input terminal IN_B_Qn is a high level; in the second arithmetic circuit, since the enable signal of the enable signal terminal IN_EN is a low level, the signal of the first output terminal OUT_Q of the latch 520 remains the high level of the previous stage. The ratio control signal (low level signal) of the ratio control terminal IN_D_Qn and the signal (high level signal) of the first output terminal OUT_Q of the latch 520 are NAND-operated by the fourth NOR gate 504 to obtain a low level signal. The low level signal obtained after the NOR operation and the second reset signal of the second reset terminal IN_LF_pulse2 are NAND-operated by the second NAND gate 302 to obtain the display switch signal DSn as a high level signal; in the third arithmetic circuit, since the second input signal of the second input terminal IN_B_Qn is a high level, the second input signal of the second input terminal IN_B_Qn, the third input signal of the third input terminal IN_C_Qn, and the ratio control signal of the ratio control terminal IN_D_Qn are NOR-operated by the fifth NOR gate 505 to obtain a low level signal. The low level signal obtained after the NOR operation and the second reset signal of the second reset terminal IN_LF_pulse2 are NAND-operated by the third NAND gate 303 to obtain the display reset signal AZn as a high level; in this stage, the display switch signal DSn is a high level (equivalent to the signal provided to the second scan signal line S2 being a high level), and the display reset signal AZn is a high level (equivalent to the signal provided to the third scan signal line S3 being a high level signal). Therefore, the third stage p33 of the gate driving circuit is equivalent to the gate driving circuit providing signals to the third stage A3 (data writing stage and threshold compensation stage) of the pixel driving circuit.

[0266] Emission time of the fourth stage p34: The signal written to the output switch signal terminal OUT_WSn and the enable signal of the enable signal terminal IN_EN are both at high level, and the second input signal of the second input terminal IN_B_Qn and the third input signal of the third input terminal IN_C_Qn are both at low level; in the second arithmetic circuit, since the second input signal of the second input terminal IN_B_Qn is at low level and the enable signal of the enable signal terminal IN_EN is at high level, the signal at the first output terminal OUT_Q of the latch 520 is at low level. The ratio control signal (low level signal) of the ratio control terminal IN_D_Qn and the signal (low level signal) at the first output terminal Q of the latch 520 are NAND-operated by the fourth NOR gate 504 to obtain a high level signal. The high level signal obtained after the NOR operation and the second reset signal of the second reset terminal IN_LF_pulse2 are NAND-operated by the second NAND gate 302 to obtain a display switch signal DSn at low level. The display switch signal DSn controls the second transistor T2 in the pixel driving circuit to conduct, and the driving current can drive the light-emitting device EL to emit light; in the third arithmetic circuit, since the second input signal of the second input terminal IN_B_Qn, the third input signal of the third input terminal IN_C_Qn, and the ratio control signal of the ratio control terminal IN_D_Qn are all at low level, the second input signal of the second input terminal IN_B_Qn, the third input signal of the third input terminal IN_C_Qn, and the ratio control signal of the ratio control terminal IN_D_Qn are NOR-operated by the fifth NOR gate 505 to obtain a high level signal. The high level signal obtained after the NOR operation and the second reset signal of the second reset terminal IN_LF_pulse2 are NAND-operated by the third NAND gate 303 to obtain a display reset signal AZn at low level. The low level of the display reset signal AZn can control the fourth transistor T4 in the pixel driving circuit to turn off, so that the driving current can control the light-emitting device EL to emit light. In this stage, the display switch signal DSn is at low level (equivalent to the signal provided to the second scan signal line S2 being at low level, which can control the second transistor T2 to conduct), and the display reset signal AZn is at low level (equivalent to the signal provided to the third scan signal line S3 being at low level, which can control the fourth transistor T4 to turn off). Therefore, the third stage p33 of the gate driving circuit is equivalent to the gate driving circuit providing a signal to the fourth stage A4 (emission stage) of the pixel driving circuit.

[0267] Such as Figure 18As shown, during the non-light-emitting time of the fourth stage p34 (light-emitting stage), when the duty ratio control signal at the duty ratio control terminal IN_D_Qn is at a high level: in the second arithmetic circuit, the duty ratio control signal at the duty ratio control terminal IN_D_Qn and the signal at the output terminal OUT_Q of the latch 520 are subjected to a NOR operation through the fourth NOR gate 504 to obtain a low-level signal. The low-level signal obtained from the NOR operation and the second reset terminal IN_LF_pulse2 are subjected to a NAND operation through the second NAND gate 302, and the display switch signal DSn obtained is at a high level, causing the second transistor T2 in the pixel driving circuit to turn off; in the third arithmetic circuit, the second input signal at the second input terminal IN_B_Qn, the third input signal at the third input terminal IN_C_Qn, and the duty ratio control signal at the duty ratio control terminal IN_D_Qn are subjected to a NOR operation through the fifth NOR gate 505 to obtain a low-level signal. The low-level signal obtained from the NOR operation and the second reset terminal IN_LF_pulse2 are subjected to a NAND operation through the third NAND gate 303, and the display reset signal AZn obtained is at a high level, causing the fourth transistor T4 in the pixel driving circuit to turn on; since the fourth transistor T4 in the pixel driving circuit is on and the second transistor T2 is off, the light-emitting device EL does not emit light. It can be seen from this that during the light-emitting stage (the fourth stage p34), the light-emitting time can be controlled by controlling the duration of the low-level of the duty ratio control signal at the duty ratio control terminal IN_D_Qn (i.e., the duty ratio of the low-level of the duty ratio control signal at the duty ratio control terminal IN_D_Qn). For example, as Figure 19 shown, during the entire light-emitting stage of the fourth stage p34, the duty ratio control signal at the duty ratio control terminal IN_D_Qn is set to a low level, and the light-emitting time ratio of the light-emitting stage can be achieved to be 100%; Figure 18 shown, during the non-light-emitting time period of the fourth stage p34, the duty ratio control signal at the duty ratio control terminal IN_D_Qn is set to a high level, and the light-emitting time ratio is controlled to be less than 100% (i.e., during the light-emitting stage, the low-level ratio of the duty ratio control signal at the duty ratio control terminal IN_D_Qn is less than 100%, thereby controlling the light-emitting time ratio of the light-emitting stage to be less than 100%).

[0268] In an exemplary embodiment, as Figure 18 and Figure 19As shown, the falling edge of the display switch signal DSn and the falling edge of the display reset signal AZn are both controlled by the falling edge of the second input signal of the second input terminal IN_B_Qn. Therefore, during the light-emitting stage, the falling edge of the display switch signal DSn does not occur earlier than the falling edge of the display reset signal AZn, such that during the light-emitting stage, the conduction time of the second transistor T2 in the pixel driving circuit does not occur earlier than the disconnection time of the fourth transistor T4, thereby avoiding the formation of a spike current in the driving current flowing through the fourth transistor T4 for a short period of time after the second transistor T2 conducts and before the fourth transistor T4 disconnects. Therefore, it is possible to avoid problems with the reliability of the display device due to the spike current of the fourth transistor T4, enabling the pixel driving circuit to operate stably and reducing power consumption. In an exemplary embodiment, by comparing Figure 9a and Figure 11a it is not difficult to find that the path of the second input signal of the second input terminal IN_B_Qn in the second arithmetic circuit has one more latch 520 than in the third arithmetic circuit. In the case where the falling edges of both the display switch signal DSn and the display reset signal AZn are controlled by the falling edge of the second input signal of the second input terminal IN_B_Qn, during the light-emitting stage, the falling edge of the display switch signal DSn is later than the falling edge of the display reset signal AZn (refer to Figure 18 and Figure 19 ). Therefore, during the light-emitting stage, the conduction time of the second transistor T2 in the pixel driving circuit will be later than the disconnection time of the fourth transistor T4, further avoiding the problem of the fourth transistor T4 forming a spike current.

[0269] In an exemplary embodiment, as Figure 20 shown, when the second reset signal of the second reset terminal IN_LF_pulse2 is a low-level signal, regardless of whether the duty ratio control signal of the duty ratio control terminal IN_D_Qn is a low-level signal or a high-level signal, the display switch signal DSn and the display reset signal AZn are always high-level signals. Therefore, the display switch signal DSn and the display reset signal AZn can be controlled to be high-level by setting the second reset signal of the second reset terminal IN_LF_pulse2 to a low level, thereby controlling the second transistor T2 in the pixel driving circuit to disconnect and the fourth transistor T4 to conduct. Therefore, the second reset signal of the second reset terminal IN_LF_pulse2 can be referred to as a global reset signal, that is, setting the second reset signal of the second reset terminal IN_LF_pulse2 to a low level can cause the light-emitting device EL not to emit light.

[0270] In an exemplary embodiment, as Figure 21 shown, the gate driving circuit may further include a first test circuit, and the first test circuit may be configured to test the display switch signal output by the second logic circuit. The working principle diagram of the first test circuit is as Figure 21As shown, the first test circuit may include two inverters. The input end of the first test circuit is electrically connected to the output end OUT_DS of the second arithmetic circuit (i.e., the display switch signal end OUT_DSn of the logic arithmetic circuit). As Figure 21 shown, the first test circuit may include a thirteenth inverter 413 and a fourteenth inverter 414. The input end of the thirteenth inverter 413 is connected to the output end OUT_DS of the second arithmetic circuit. The output end of the thirteenth inverter 413 is connected to the input end of the fourteenth inverter 414. The output end of the fourteenth inverter 414 may serve as the output end Test_DS of the first test circuit (i.e., the test end of the display switch signal DSn of the gate drive circuit).

[0271] In an exemplary embodiment, as Figure 22 shown, it is the equivalent circuit diagram of the first test circuit. As Figure 22 shown, the first test circuit may include four transistors; among them, both the thirteenth inverter 413 and the fourteenth inverter 414 include one P-type transistor and one N-type transistor.

[0272] In an exemplary embodiment, an eighty-first P-type transistor P81 and an eighty-first N-type transistor N81 form the thirteenth inverter 413. The gate electrodes of the eighty-first P-type transistor P81 and the eighty-first N-type transistor N81 are connected to each other and connected to the display switch signal end OUT_DSn of the logic arithmetic circuit (the output end OUT_DS of the second arithmetic circuit). The first pole of the eighty-first P-type transistor P81 is connected to the first power supply line VDD. The first pole of the eighty-first N-type transistor N81 is connected to the ground wire GND. The second poles of the eighty-first P-type transistor P81 and the eighty-first N-type transistor N81 are connected to each other and are respectively connected to the gate electrodes of an eighty-second P-type transistor P82 and an eighty-second N-type transistor N82.

[0273] In an exemplary embodiment, an eighty-second P-type transistor P82 and an eighty-second N-type transistor N82 form the fourteenth inverter 414. The gate electrodes of the eighty-second P-type transistor P82 and the eighty-second N-type transistor N82 are connected to each other and connected to the second poles of the eighty-first P-type transistor P81 and the eighty-first N-type transistor N81. The first pole of the eighty-second P-type transistor P82 is connected to the first power supply line VDD. The first pole of the eighty-second N-type transistor N82 is connected to the ground wire GND. The second poles of the eighty-second P-type transistor P82 and the eighty-second N-type transistor N82 are connected to each other and connected to the output end Test_DS of the first test circuit (i.e., the test end Test_DS of the display switch signal of the gate drive circuit).

[0274] In an exemplary embodiment, the first test circuit can detect whether the display switch signal DSn output from the output terminal OUT_DS of the second arithmetic circuit is consistent with the target timing. If the display switch signal DSn detected at the output terminal Test_DS of the first test circuit is inconsistent with the target timing, it indicates that the display switch signal DSn has already been abnormal before entering the level shifter 300 and the line driver 400. Therefore, it can be inferred that the abnormal operation of the second arithmetic circuit causes the display switch signal DSn to be inconsistent with the target timing. If the display switch signal DSn detected at the output terminal Test_DS of the first test circuit is consistent with the target timing, it indicates that the display switch signal DSn becomes abnormal after entering the level shifter 300 and the line driver 400. Therefore, it can be inferred that the second arithmetic circuit operates normally. Therefore, the display switch signal DSn output by the second arithmetic circuit can be tested at the output terminal Test_DS of the first test circuit, so as to test whether the second arithmetic circuit operates normally. In an exemplary embodiment, the output terminal Test_DS of the first test circuit can be led out through a pad around the display area. During the test, the signal input terminal of the oscilloscope can be electrically connected to the pad of the output terminal Test_DS of the first test circuit, and the waveform output from the output terminal Test_DS of the first test circuit can be obtained through the oscilloscope. By comparing whether the waveform output from the output terminal Test_DS of the first test circuit is consistent with the waveform of the target timing, if they are consistent, it means that the second arithmetic circuit operates normally; if they are inconsistent, it means that the second arithmetic circuit operates abnormally.

[0275] In an exemplary embodiment, as Figure 23 shown, the gate drive circuit may further include a second test circuit, and the second test circuit may be configured to test the display reset signal output by the third logic circuit. The working principle diagram of the second test circuit is as Figure 23 shown. The second test circuit may include 2 inverters, and the input terminal of the second test circuit is electrically connected to the output terminal OUT_AZ of the third arithmetic circuit (i.e., the display reset signal terminal OUT_AZn of the logic arithmetic circuit). As Figure 23 shown, the second test circuit may include a fifteenth inverter 415 and a sixteenth inverter 416. The input terminal of the fifteenth inverter 415 is connected to the output terminal OUT_AZ of the third arithmetic circuit, the output terminal of the fifteenth inverter 415 is connected to the input terminal of the sixteenth inverter 416, and the output terminal of the sixteenth inverter 416 may be used as the output terminal Test_AZ of the second test circuit (i.e., the test terminal of the display reset signal AZn of the gate drive circuit).

[0276] In an exemplary embodiment, as Figure 24 shown, it is an equivalent circuit diagram of the second test circuit. As Figure 24 shown, the second test circuit may include four transistors; among them, the fifteenth inverter 415 and the sixteenth inverter 416 each include 1 P-type transistor and 1 N-type transistor.

[0277] In an exemplary embodiment, the eighty-third P-type transistor P83 and the eighty-third N-type transistor N83 form the fifteenth inverter 415. The gate electrodes of the eighty-third P-type transistor P83 and the eighty-third N-type transistor N83 are connected to each other and are connected to the display reset signal terminal OUT_AZn (the output terminal OUT_AZ of the third operation circuit) of the logic operation circuit. The first pole of the eighty-third P-type transistor P83 is connected to the first power supply line VDD, the first pole of the eighty-third N-type transistor N83 is connected to the ground line GND, the second poles of the eighty-third P-type transistor P83 and the eighty-third N-type transistor N83 are connected to each other and are respectively connected to the gate electrodes of the eighty-fourth P-type transistor P84 and the eighty-fourth N-type transistor N84.

[0278] In an exemplary embodiment, the eighty-fourth P-type transistor P84 and the eighty-fourth N-type transistor N84 form the sixteenth inverter 416. The gate electrodes of the eighty-fourth P-type transistor P84 and the eighty-fourth N-type transistor N84 are connected to each other and are connected to the second poles of the eighty-third P-type transistor P83 and the eighty-third N-type transistor N83. The first pole of the eighty-fourth P-type transistor P84 is connected to the first power supply line VDD, the first pole of the eighty-fourth N-type transistor N84 is connected to the ground line GND, the second poles of the eighty-fourth P-type transistor P84 and the eighty-fourth N-type transistor N84 are connected to each other and are connected to the output terminal Test_AZ of the second test circuit (i.e., the test terminal Test_AZ of the display reset signal of the gate drive circuit).

[0279] In an exemplary embodiment, the second test circuit can detect whether the display reset signal AZn output from the output terminal OUT_AZ of the third arithmetic circuit is consistent with the target timing. If the display reset signal AZn detected at the output terminal Test_AZ of the second test circuit is inconsistent with the target timing, it indicates that the display reset signal AZn has already been abnormal before entering the level shifter 300 and the line driver 400. Therefore, it can be inferred that the abnormal operation of the third arithmetic circuit causes the display reset signal AZn to be inconsistent with the target timing. If the display reset signal AZn detected at the output terminal Test_AZ of the second test circuit is consistent with the target timing, it indicates that the display reset signal AZn becomes abnormal after entering the level shifter 300 and the line driver 400. Therefore, it can be inferred that the third arithmetic circuit operates normally. Thus, the display reset signal AZn output by the third arithmetic circuit can be tested at the output terminal Test_AZ of the second test circuit, so as to test whether the third arithmetic circuit operates normally. In an exemplary embodiment, the output terminal Test_AZ of the second test circuit can be led out through a pad around the display area. During the test, the signal input terminal of the oscilloscope can be electrically connected to the pad of the output terminal Test_AZ of the second test circuit, and the waveform output from the output terminal Test_AZ of the second test circuit can be obtained through the oscilloscope. By comparing whether the waveform output from the output terminal Test_AZ of the second test circuit is consistent with the waveform of the target timing, if they are consistent, it indicates that the third arithmetic circuit operates normally; if they are inconsistent, it indicates that the third arithmetic circuit operates abnormally.

[0280] The exemplary embodiment of the present disclosure further provides a driving method for a gate driving circuit, which is configured to drive the gate driving circuit described in any of the above embodiments. The gate driving circuit includes a logic arithmetic circuit, and the logic arithmetic circuit includes a display switch signal terminal, a display reset signal terminal, a second input terminal, and a third input terminal. The display switch signal terminal is configured to output a display switch signal, and the display reset signal terminal is configured to output a display reset signal. The driving method includes:

[0281] Under the control of the second input signal and the third input signal, during the light emitting stage, the time when the display switch signal terminal outputs the valid level signal in the display switch signal is not earlier than the time when the display reset signal terminal stops outputting the valid level signal in the display reset signal.

[0282] The driving method of the gate driving circuit provided by the present disclosure, during the light emitting stage when the gate driving circuit drives at least one pixel driving circuit, the time when the display switch signal terminal outputs the valid level signal in the display switch signal is not earlier than the time when the display reset signal terminal stops outputting the valid level signal in the display reset signal, thereby avoiding the formation of spike current in the pixel driving circuit, enabling the pixel driving circuit to work stably, and reducing the power consumption of the pixel driving circuit.

[0283] In an exemplary embodiment, the display switch signal terminal is configured to output a display switch signal to the display switch control terminal of the at least one pixel driving circuit, and the display reset signal terminal is configured to output a display reset signal to the display reset control terminal of the at least one pixel driving circuit.

[0284] In an exemplary embodiment, the valid level signal in the display switch signal may be a low level signal, and the valid level signal in the display reset signal may be a high level signal. Combining Figure 4a and Figure 6a As shown, the display switch control terminal DS in the pixel driving circuit may be connected to the second scan signal line S2, and the display reset control terminal AZ may be connected to the third scan signal line S3. When the display switch signal output by the display switch signal terminal DSn is at a low level, the second transistor T2 in the pixel driving circuit is turned on. Therefore, when the second transistor T2 in the pixel driving circuit is a P-type transistor, the valid level in the display switch signal is a low level signal; when the display reset signal output by the display reset signal terminal AZn is at a high level, the fourth transistor T4 in the pixel driving circuit is turned on. Therefore, when the fourth transistor T4 in the pixel driving circuit is an N-type transistor, the valid level signal in the display reset signal is a high level signal. The embodiments of the present disclosure are not limited thereto. The valid level signals of the display switch signal and the display reset signal can be set according to the type of transistors in the pixel driving circuit and the specific working timing, and it is only necessary to ensure that the turn-on time of the second transistor T2 is not earlier than the turn-off time of the fourth transistor T4 during the light emitting stage. For example, in the case of the pixel driving circuit as Figure 4a shown, the valid level in the display reset signal is high and low levels, and in the case of the pixel driving circuit as Figure 4b shown, the valid level in the display reset signal is a low level.

[0285] The exemplary embodiment of the present disclosure also provides a display substrate, such as Figure 25As shown, the display substrate may include a display area and a non-display area; the display area includes a plurality of sub-pixels, and at least one sub-pixel includes a pixel driving circuit and at least one scanning signal line, and the scanning signal line is configured to provide a scanning signal to the connected pixel driving circuit; the non-display area includes a plurality of cascaded gate driving circuits, at least one gate driving circuit is connected to the scanning signal line in the display area, and at least one gate driving circuit may include the gate driving circuit described in any of the above embodiments.

[0286] In an exemplary embodiment, at least one sub-pixel includes a light-emitting element, and the pixel driving circuit is configured to drive the light-emitting element to emit light; in the same sub-pixel, the pixel driving circuit is electrically connected to the anode of the light-emitting element; at least one of the pixel driving circuits at least includes: a display switch control terminal and a display reset control terminal; the gate driving circuit includes a display switch signal terminal and a display reset signal terminal;

[0287] The display switch control terminal is configured to receive the display switch signal from the display switch signal terminal and control the pixel driving circuit to drive the light-emitting element to emit light according to the display switch signal; the display reset control terminal is configured to receive the display reset signal from the display reset signal terminal and control the anode of the light-emitting element to be reset according to the display reset signal;

[0288] In the light-emitting stage, the time when the display switch control terminal receives the valid level signal in the display switch signal is not earlier than the time when the display reset control terminal stops receiving the valid level signal in the display reset signal.

[0289] In an exemplary embodiment, as Figure 4a and Figure 4bAs shown, the first transistor T1 in the pixel driving circuit can be referred to as a write switch transistor, the second transistor T2 can be referred to as a display switch transistor, the third transistor T3 can be referred to as a driving transistor, and the fourth transistor T4 can be referred to as a display reset transistor. In the pixel driving circuit, the gate electrode of the write switch transistor T1 can be electrically connected to the write switch control terminal WS of the pixel driving circuit, the gate electrode of the display switch transistor T2 can be electrically connected to the display switch control terminal DS of the pixel driving circuit, and the gate electrode of the display reset transistor T4 can be electrically connected to the display reset control terminal AZ of the pixel driving circuit. During the light-emitting stage when the pixel driving circuit drives the light-emitting device EL, the time when the display switch signal terminal DSn outputs the valid level signal in the display switch signal is not earlier than the time when the display reset signal terminal AZn stops outputting the valid level signal in the display reset signal, so that during the light-emitting stage, the conduction time of the display switch transistor T2 is not earlier than the disconnection time of the display reset transistor T4, thereby avoiding the problem that the display reset transistor T4 forms a spike current due to the display switch transistor T2 conducting first and the display reset transistor T4 disconnecting later during the light-emitting stage. Thus, the stability of the pixel driving circuit can be improved, and the technical problem of high power consumption of the pixel driving circuit caused by the formation of spike current can be avoided. For the display substrate provided by the present disclosure, during the light-emitting stage, the time when the display switch control terminal receives the valid level signal in the display switch signal is not earlier than the time when the display reset control terminal stops receiving the valid level signal in the display reset signal, so that spike current can be avoided from being formed in the pixel driving circuit, enabling the pixel driving circuit to operate stably and reducing the power consumption of the pixel driving circuit.

[0290] In an exemplary embodiment, for the display substrate provided by the present disclosure, through the reasonable layout of the first arithmetic circuit, the second arithmetic circuit, and the third arithmetic circuit in the logic arithmetic circuit, the target timing required by the pixel driving circuit can be generated using standard signals, and a display panel with a pixel density of 4K and above can be driven, which can be applied to a silicon-based OLED display device with a pixel density of 4K and above.

[0291] The exemplary embodiment of the present disclosure also provides a display device, as Figure 26 shown, which may include the aforementioned display substrate. The display device of the present disclosure can be used in virtual reality (VR) devices, or augmented reality (AR) devices, extended reality (XR) devices, mixed reality (MR) devices, sights and rangefinders, computers, mobile phones, wearable devices, etc.

[0292] The gate driving circuit, driving method, display substrate, and display device provided by the present disclosure are such that, in the light emitting stage, the time when the display switching signal terminal in the gate driving circuit outputs the valid level signal in the display switching signal is not earlier than the time when the display reset signal terminal stops outputting the valid level signal in the display reset signal, thereby avoiding the formation of spike current in the pixel driving circuit, enabling the pixel driving circuit to operate stably, and reducing the power consumption of the pixel driving circuit.

[0293] Although the embodiments disclosed in the present disclosure are as above, the content described is only an embodiment adopted for the convenience of understanding the present disclosure and is not intended to limit the present disclosure. Any person skilled in the art within the scope of the present disclosure can make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in the present disclosure. However, the scope of patent protection of this application shall still be subject to the scope defined by the appended claims.

Claims

1. A gate driving circuit, characterized in that, It includes a logic operation circuit, and the logic operation circuit includes a second input terminal, a third input terminal, a display switch signal terminal, and a display reset signal terminal; the second input terminal is configured to receive a second input signal, the third input terminal is configured to receive a third input signal, the display switch signal terminal is configured to output a display switch signal, and the display reset signal terminal is configured to output a display reset signal; Under the control of the second input signal and the third input signal, during the light-emitting stage, the time when the display switch signal terminal outputs a valid level signal in the display switch signal is not earlier than the time when the display reset signal terminal stops outputting a valid level signal in the display reset signal.

2. The gate driving circuit according to claim 1, wherein Under the control of the second input signal, the start time of the valid level signal in the display switch signal output by the display switch signal terminal is not earlier than the falling edge of the second input signal; The falling edge of the third input signal is not later than the falling edge of the second input signal. Under the control of the second input signal and the third input signal, the end time of the valid level signal in the display reset signal output by the display reset signal terminal is synchronized with the falling edge of the second input signal.

3. The gate driving circuit according to claim 1 or 2, characterized in that The logic operation circuit further includes a duty ratio control terminal, and the duty ratio control terminal is configured to receive a duty ratio control signal; During the light-emitting stage, the gate driving circuit is configured to control the duty ratio of the valid level signal in the duty ratio control signal through the end time of the valid level signal in the duty ratio control signal; the logic operation circuit is configured to control the duration of the valid level signal in the display switch signal output by the display switch signal terminal according to the duty ratio of the valid level signal in the duty ratio control signal, and control the duration of the valid level signal in the display reset signal output by the display reset signal terminal according to the duty ratio of the valid level signal in the duty ratio control signal, so as to control the light-emitting duration of the light-emitting stage.

4. The gate driving circuit according to claim 3, wherein During the light-emitting stage, under the control of the duty ratio control signal, the end time of the valid level signal in the display switch signal output by the display switch signal terminal is synchronized with the end time of the valid level signal in the duty ratio control signal received by the duty ratio control terminal; the start time of the valid level signal in the display reset signal output by the display reset signal terminal is synchronized with the end time of the valid level signal in the duty ratio control signal received by the duty ratio control terminal.

5. The gate driving circuit according to claim 3, wherein The logic operation circuit further includes a second operation circuit, a write switch signal terminal, and a second reset terminal; the write switch signal terminal is electrically connected to the second operation circuit and is configured to output a write switch signal to the second operation circuit; the second reset terminal is configured to input a second reset signal to the logic operation circuit; The second operation circuit is electrically connected to the second input terminal, the write switch signal terminal, the duty ratio control terminal, the second reset terminal, and the display switch signal terminal, and is configured to perform a logic operation according to the second input signal, the write switch signal, the second reset signal, and the duty ratio control signal to generate the display switch signal, and output the display switch signal through the display switch signal terminal.

6. The gate driving circuit according to claim 5, wherein The second arithmetic circuit includes a second NAND gate, a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, a ninth inverter, a tenth inverter, a fourth NOR gate, and a latch; The input end of the fifth inverter is connected to the write switch signal end, the output end of the fifth inverter is connected to the input end of the sixth inverter, the output end of the sixth inverter is connected to the input end of the seventh inverter, the output end of the seventh inverter is connected to the input end of the eighth inverter, the output end of the eighth inverter is connected to the input end of the ninth inverter, the output end of the ninth inverter is connected to the input end of the tenth inverter, the output end of the tenth inverter is connected to the enable signal end of the latch, the input end of the latch is connected to the second input end of the logic arithmetic circuit, the output end of the latch is connected to the second input end of the fourth NOR gate, the first input end of the fourth NOR gate is connected to the ratio control end, the output end of the fourth NOR gate is connected to the first input end of the second NAND gate, the second input end of the second NAND gate is connected to the second reset end, and the output end of the second NAND gate serves as the output end of the second arithmetic circuit and the display switch signal end, and is connected to the display switch control end in the at least one pixel driving circuit to output a display switch signal to the display switch control end in the at least one pixel driving circuit.

7. The gate driving circuit according to claim 5, wherein The gate driving circuit further includes a first test circuit configured to test the display switch signal output by the second logic circuit; the first test circuit includes a thirteenth inverter and a fourteenth inverter; The input end of the thirteenth inverter is connected to the output end of the second arithmetic circuit, the output end of the thirteenth inverter is connected to the input end of the fourteenth inverter, and the output end of the fourteenth inverter serves as the output end of the first test circuit.

8. The gate driving circuit according to claim 5, wherein The logic arithmetic circuit further includes a third arithmetic circuit; The third arithmetic circuit is electrically connected to the second input end, the third input end, the ratio control end, the second reset end, and the display reset signal end, and is configured to perform a logic operation according to the second input signal, the third input signal, the ratio control signal, and the second reset signal to generate the display reset signal, and output the display reset signal through the display reset signal end.

9. The gate driving circuit according to claim 8, wherein The third arithmetic circuit includes a fifth NOR gate and a third NAND gate; The first input terminal of the fifth NOR gate is connected to the third input terminal of the logic operation circuit, the second input terminal of the fifth NOR gate is connected to the second input terminal of the logic operation circuit, the third input terminal of the fifth NOR gate is connected to the ratio control terminal, the output terminal of the fifth NOR gate is connected to the first input terminal of the third NAND gate, the second input terminal of the third NAND gate is connected to the second reset terminal, and the output terminal of the third NAND gate serves as the output terminal of the third operation circuit and the display reset signal terminal, and is connected to the display reset control terminal in the at least one pixel driving circuit to output a display reset signal to the display reset control terminal in the at least one pixel driving circuit.

10. The gate driving circuit according to claim 8, wherein The gate driving circuit further includes a second test circuit configured to test the display reset signal output by the third logic circuit; the second test circuit includes a fifteenth inverter and a sixteenth inverter; The input terminal of the fifteenth inverter is connected to the output terminal of the third operation circuit, the output terminal of the fifteenth inverter is connected to the input terminal of the sixteenth inverter, and the output terminal of the sixteenth inverter serves as the output terminal of the second test circuit.

11. The gate driving circuit according to any one of claims 1 to 4, characterized in that, The gate driving circuit further includes a level conversion circuit, and the level conversion circuit includes at least two level converters, and the at least two level converters at least include a second level converter and a third level converter; The second level converter is electrically connected to the display switch signal terminal and is configured to perform a voltage domain conversion on the display switch signal and output the converted display switch signal to the display switch control terminal; The third level converter is electrically connected to the display reset signal terminal and is configured to perform a voltage domain conversion on the display reset signal and output the converted display reset signal to the display reset control terminal.

12. The gate driving circuit according to claim 11, wherein The gate driving circuit further includes a line driving enhancement circuit, and the line driving enhancement circuit includes at least two line driving enhancers, and the at least two line driving enhancers at least include a second line driving enhancer and a third line driving enhancer; The second line driving enhancer is electrically connected to the output terminal of the second level converter and is configured to enhance the display switch signal converted by the second level converter and output the enhanced display switch signal to the display switch control terminal; The third line driving enhancer is electrically connected to the output terminal of the third level converter and is configured to enhance the display reset signal converted by the third level converter and output the enhanced display reset signal to the display reset control terminal.

13. The gate driving circuit according to claim 12, wherein, The line driving enhancer includes a fourth NAND gate, a fifth NAND gate, a first transmission gate, a twelfth inverter, a third P-type field effect transistor, and a third N-type field effect transistor; The first input terminal of the row driving enhancer is connected to the first input terminal of the fourth NAND gate, the enable signal terminal of the row driving enhancer is connected to the second input terminal of the fourth NAND gate, the output terminal of the fourth NAND gate is connected to the input terminal of the first transmission gate, the output terminal of the first transmission gate is connected to the gate electrode of the third P-type field effect transistor, and the first pole of the third P-type field effect transistor is connected to the first power supply line; The second input terminal of the row driving enhancer is connected to the first input terminal of the fifth NAND gate, the enable signal terminal of the row driving enhancer is connected to the second input terminal of the fifth NAND gate, the output terminal of the fifth NAND gate is connected to the input terminal of the twelfth inverter, the output terminal of the twelfth inverter is connected to the gate electrode of the third N-type field effect transistor, and the first pole of the third N-type field effect transistor is connected to the second power supply line; The second pole of the third P-type field effect transistor and the second pole of the third N-type field effect transistor are connected to the output terminal of the row driving enhancer; the output terminal of the second row driving enhancer is electrically connected to the display switch control terminal, and the output terminal of the third row driving enhancer is electrically connected to the display reset control terminal.

14. The gate driving circuit according to claim 13, wherein When the enable signal input at the enable signal terminal is a first level signal, the state of the row driving enhancer is a high impedance state.

15. The gate driving circuit according to claim 13, wherein The level shifter includes an eleventh inverter, a first P-type field effect transistor, a second P-type field effect transistor, a first N-type field effect transistor, and a second N-type field effect transistor; The input terminals of the level shifter are respectively connected to the input terminal of the eleventh inverter and the gate electrode of the first P-type field effect transistor; the input terminal of the second level shifter is electrically connected to the display switch signal terminal, and the input terminal of the third level shifter is electrically connected to the display reset signal terminal; The output terminal of the eleventh inverter is connected to the gate electrode of the second P-type field effect transistor. The first poles of the first P-type field effect transistor and the second P-type field effect transistor are both connected to the first power supply line. The second pole of the first P-type field effect transistor is respectively connected to the second pole of the first N-type field effect transistor, the gate electrode of the second N-type field effect transistor, and the second output terminal of the level shifter. The second pole of the second P-type field effect transistor is respectively connected to the gate electrode of the first N-type field effect transistor, the second pole of the second N-type field effect transistor, and the first output terminal of the level shifter. The first poles of the first N-type field effect transistor and the second N-type field effect transistor are both connected to the second power supply line; The first output terminal of the second level shifter is electrically connected to the first input terminal of the second row driving enhancer; The second output terminal of the second level shifter is electrically connected to the second input terminal of the second row driving enhancer; The first output terminal of the third level shifter is electrically connected to the first input terminal of the third row driving enhancer; The second output terminal of the third level shifter is electrically connected to the second input terminal of the third row driving enhancer.

16. The gate driving circuit according to claim 1, wherein The logic operation circuit is configured to generate the display switch signal according to the second input signal, and generate the display reset signal according to the display switch signal and the third input signal; Under the control of the display switch signal and the third input signal, during the light-emitting stage, the time when the display reset signal terminal stops outputting the valid level signal in the display reset signal is synchronized with the time when the display switch signal terminal outputs the valid level signal in the display switch signal.

17. A driving method for a gate driving circuit, characterized in that It is configured to drive the gate driving circuit according to any one of claims 1 to 16. The gate driving circuit includes a logic operation circuit, and the logic operation circuit includes a display switch signal terminal, a display reset signal terminal, a second input terminal, and a third input terminal; the display switch signal terminal is configured to output a display switch signal, and the display reset signal terminal is configured to output a display reset signal; the driving method includes: Under the control of the second input signal and the third input signal, during the light-emitting stage, the time when the display switch signal terminal outputs the valid level signal in the display switch signal is not earlier than the time when the display reset signal terminal stops outputting the valid level signal in the display reset signal.

18. A display substrate, characterized in that, It includes a display area and a non-display area; the display area includes a plurality of sub-pixels, and at least one sub-pixel includes a pixel driving circuit and at least one scanning signal line, and the scanning signal line is configured to provide a scanning signal to the connected pixel driving circuit; the non-display area includes a plurality of cascaded gate driving circuits, at least one gate driving circuit is connected to the scanning signal line in the display area, and at least one gate driving circuit includes the gate driving circuit according to any one of claims 1 to 16.

19. The display substrate according to claim 18, wherein, At least one sub-pixel includes a light-emitting element, and the pixel driving circuit is configured to drive the light-emitting element to emit light; In the same sub-pixel, the pixel driving circuit is electrically connected to the anode of the light-emitting element; At least one of the pixel driving circuits at least includes: a display switch control terminal, a display reset control terminal; the gate driving circuit includes a display switch signal terminal and a display reset signal terminal; The display switch control terminal is configured to receive the display switch signal of the display switch signal terminal, and control the pixel driving circuit to drive the light-emitting element to emit light according to the display switch signal; the display reset control terminal is configured to receive the display reset signal of the display reset signal terminal, and control the anode reset of the light-emitting element according to the display reset signal; During the light-emitting stage, the time when the display switch control terminal receives the valid level signal in the display switch signal is not earlier than the time when the display reset control terminal stops receiving the valid level signal in the display reset signal.

20. A display device, characterized in that, It includes the display substrate according to any one of claims 18 to 19.

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