A parallel bit error rate detection method, device, medium and product

Abstract

The application provides a parallel bit error rate detection method, device, medium and product, and belongs to the technical field of communication. The method comprises the following steps: detecting the bit error rate of parallel signals of each channel to obtain a channel bit error rate; and collecting the channel bit error rates of all channels to obtain a total bit error rate. For each channel, the channel bit error rate is obtained by the following steps: dividing the parallel signals of the channel into a plurality of first data segments according to a preset length; comparing the first data segments with corresponding second data segments in a lookup table to obtain comparison results of the first data segments; and calculating the channel bit error rate according to the comparison results of all the first data segments in the channel. The application independently and in parallel counts the bit error rates in multiple channels, collects the bit error rates of each channel through a bus, and performs data segmentation and comparison on each channel to obtain the channel bit error rate. The double parallel processing mechanism improves the bit error rate detection efficiency and can monitor the bit error rates of hundreds or thousands of parallel signals in real time.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of communication, and particularly relates to a parallel bit error rate detection method and device, a medium and a product. BACKGROUND

[0002] Currently, most traditional bit error rate detection methods directly detect serial data, and these methods are effective in low-speed or low-concurrency scenarios. However, with the increase of data transmission rate and the increasing demand for parallel detection, in high-speed communication systems, especially when multi-channel parallel transmission is involved, the traditional bit error detection method is difficult to cope with the rapid change of signal rate and high-concurrency data flow, resulting in poor bit error rate statistical efficiency. SUMMARY

[0003] The present application provides a parallel bit error rate detection method, device, medium and product, aiming at solving the technical problem that the traditional bit error detection method is difficult to cope with the rapid change of signal rate and high-concurrency data flow, resulting in poor bit error rate statistical efficiency.

[0004] In a first aspect, the present application provides a parallel bit error rate detection method, comprising:

[0005] detecting the bit error rate of the parallel signal of each channel to obtain a channel bit error rate; wherein the parallel signal of each channel is obtained when the serial input signal is converted from serial to parallel;

[0006] summarizing the channel bit error rates of all channels to obtain a total bit error rate;

[0007] wherein for each channel, obtaining the channel bit error rate specifically comprises:

[0008] dividing the parallel signal of the channel into a plurality of first data segments according to a preset length;

[0009] comparing the first data segment with the corresponding second data segment in the lookup table to obtain a comparison result of the first data segment;

[0010] calculating the channel bit error rate according to the comparison results of all first data segments in the channel.

[0011] As an embodiment, the bit error rate detection method further comprises:

[0012] in the case that the signal flow in the channel is not in a stable state, adaptively adjusting the bit error rate detection parameter of the channel according to the feedback data of the signal flow in the channel in the transmission process.

[0013] As an embodiment, the bit error rate detection parameter comprises bit error rate detection sensitivity, detection window size and error count threshold.

[0014] As an embodiment, the adjustment of the error rate detection sensitivity includes adjustment of an error detection threshold, which includes an amplitude decision threshold and a delay decision threshold.

[0015] As an embodiment, the adjustment of the amplitude decision threshold specifically includes:

[0016] calculating a real-time noise variance of the signal stream in the channel;

[0017] adjusting the amplitude decision threshold of the channel according to the real-time noise variance.

[0018] As an embodiment, the adjustment of the delay decision threshold specifically includes:

[0019] calculating a real-time jitter variance of the signal stream in the channel;

[0020] adjusting the delay decision threshold of the channel according to the real-time jitter variance.

[0021] As an embodiment, the judgment of whether the signal stream in the channel is in a stable state specifically includes:

[0022] calculating a real-time noise mean and a real-time jitter mean of the signal stream in the channel respectively;

[0023] calculating a first ratio between the real-time noise mean and a historical noise mean;

[0024] calculating a second ratio between the real-time jitter mean and a historical jitter mean;

[0025] if the first ratio is greater than a first ratio threshold and / or the second ratio is greater than a second ratio threshold, it is determined that the signal stream is not in the stable state.

[0026] As an embodiment, the adjustment of the error rate detection sensitivity specifically includes:

[0027] detecting signal strengths of the signal streams in each channel and signal strength errors between each two channels;

[0028] if a maximum value of the signal strength errors is greater than an error threshold, scanning amplitude noises of high-speed counters in each channel, drawing an amplitude-error rate bathtub curve, and determining an optimal value of the amplitude noises as the amplitude decision threshold according to the amplitude-error rate bathtub curve;

[0029] scanning local clock delays based on the amplitude decision threshold, drawing a delay-error rate bathtub curve, and determining an optimal value of timing jitter as the delay decision threshold according to the delay-error rate bathtub curve.

[0030] As an embodiment, the self-adaptive adjustment of the error rate detection parameters of the channel according to the feedback data specifically includes:

[0031] characteristic data of the signal flow of the detection channel, the characteristic data including error code number, code rate, code content, jitter condition, noise condition and error code rate;

[0032] inputting the characteristic data into a user data model to obtain error code rate detection parameters matched with the characteristic data;

[0033] The user data model is trained based on a data set, and the data set includes characteristic data of each channel and adjustment strategies of error code rate detection parameters corresponding to the characteristic data.

[0034] As an embodiment, training the user data model includes:

[0035] For each data stream rate, fitting multiple fitting curves based on all characteristic data with the data stream rate in the data set to obtain corresponding fitting functions, the independent variable of the fitting function being the characteristic data and the dependent variable being the delay value;

[0036] For each fitting function, selecting multiple groups of first characteristic data with the data stream rate from the data set, inputting the multiple groups of first characteristic data into the fitting function respectively to obtain delay values corresponding to each group of first characteristic data, and then setting hardware parameters of the communication system respectively according to the delay values to obtain first error code rate errors corresponding to each delay value in the running process of the communication system;

[0037] calculating a second error code rate error of the fitting function based on all first error code rate errors of the fitting function;

[0038] taking the fitting function with the minimum second error code rate error as the fitting function corresponding to the data stream rate in the user data model;

[0039] selecting second characteristic data with the data stream rate from the data set, obtaining error code rate detection parameters and clock synchronization parameters corresponding to the second characteristic data by using the fitting function, and combining the second characteristic data, the corresponding error code rate detection parameters and the clock synchronization parameters into a template data and storing the template data in a database of the user data model.

[0040] As an embodiment, the error code rate detection method further includes:

[0041] obtaining a real-time clock phase of the serial input signal;

[0042] adjusting the local clock phase to the real-time clock phase.

[0043] In a second aspect, the application further provides a parallel error code rate detection device, including a summary module and multiple channel detection modules;

[0044] Each channel detection module is configured to detect the bit error rate of the parallel signal of the corresponding channel, and obtain a channel bit error rate; wherein the parallel signal of each channel is obtained when the serial input signal is converted from serial to parallel;

[0045] The aggregation module is configured to aggregate the channel bit error rates of all channels, and obtain a total bit error rate.

[0046] As an embodiment, the bit error rate detection device further comprises an adaptive adjustment module, which is configured to, in the case that the signal flow in the channel is not in a stable state, adaptively adjust the bit error rate detection parameter of the channel according to the feedback data of the signal flow in the channel in the transmission process.

[0047] In a third aspect, the present application further provides a non-transitory computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement any of the parallel bit error rate detection methods.

[0048] In a fourth aspect, the present application further provides a computer program product, which comprises a computer program, and the computer program is executed by a processor to implement any of the parallel bit error rate detection methods. BRIEF DESCRIPTION OF DRAWINGS

[0049] In order to more clearly illustrate the technical solutions of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings described below are some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0050] Figure 1 is one of the flowcharts of the parallel bit error rate detection method provided by the present application;

[0051] Figure 2 is another flowchart of the parallel bit error rate detection method provided by the present application;

[0052] Figure 3 is a flowchart for judging whether the signal flow is in a stable state provided by the present application;

[0053] Figure 4 is one of the flowcharts for adjusting the bit error rate detection sensitivity provided by the present application;

[0054] Figure 5 is a flowchart for adaptively adjusting the bit error rate detection parameter of the channel according to the feedback data provided by the present application;

[0055] Figure 6This is a flowchart of the dynamic synchronization of clocks provided by this application;

[0056] Figure 7 It is a structural diagram of the communication system provided by this application;

[0057] Figure 8 This is one of the structural diagrams of the parallel bit error rate detection device provided by this application;

[0058] Figure 9 This is one of the structural diagrams of the adaptive adjustment module provided in this application. DETAILED DESCRIPTION

[0059] To make the objectives, technical solutions, and advantages of this application more clear, the technical solutions of this application will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0060] It should be noted that, in the description of the present invention, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0061] The terms "first," "second," and so forth, used herein are used to distinguish similar objects, not to describe a specific order or precedence. It should be understood that such terms are interchangeable where appropriate, allowing embodiments of the present invention to be implemented in an order other than that illustrated or described herein. Furthermore, the terms "first," "second," and so forth generally distinguish objects of a single type, and do not limit the number of objects. For example, the first object may be one or more. Furthermore, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates an "or" relationship between the connected objects.

[0062] The following combination Figures 1 to 9 The present invention describes the parallel bit error rate detection method, device, medium and product provided by the present application.

[0063] It should be noted that the parallel bit error rate detection method provided in the embodiments of the present application is implemented based on the parallel bit error rate detection device, and the parallel bit error rate detection method adopts a parallel processing mechanism, can process the bit error rate detection in multiple channels in parallel, and simultaneously processes thousands of data streams in real time, so as to ensure a high bit error rate statistical efficiency under the ultra-high concurrency of a high-speed communication system.

[0064] The parallel bit error rate detection method is described by taking the parallel bit error rate detection device as an execution subject.

[0065] Figure 1 Fig. 1 is one of flowcharts of the parallel bit error rate detection method provided in the embodiments of the present application. Figure 2 Fig. 2 is another flowchart of the parallel bit error rate detection method provided in the embodiments of the present application.

[0066] As shown in Fig. 1, the parallel bit error rate detection method provided in the embodiments of the present application includes the following steps. Figure 1

[0067] S110: detecting the bit error rate of the parallel signal of each channel to obtain a channel bit error rate. The parallel signal of each channel is obtained when the serial input signal is converted from serial to parallel.

[0068] It should be noted that the bit error rate detection of each channel is independent of each other.

[0069] S120: aggregating the channel bit error rates of all channels to obtain a total bit error rate.

[0070] Please refer to Fig. 1, in the embodiments of the present application, first, the serial input signal is converted from serial to parallel to obtain multiple parallel signals, thereby forming multiple parallel channels. Subsequently, the bit error rate in each channel is independently and in parallel counted as a channel bit error rate. Finally, the channel bit error rates of all channels are aggregated to obtain a total bit error rate. Figure 2

[0071] In one possible embodiment, the total bit error rate can be calculated by calculating the average value or weighted sum of all channel bit error rates.

[0072] Specifically, in the embodiments of the present application, the parallel bit error rate detection device detects the bit error rate of the parallel signal of each channel to obtain a channel bit error rate, and then the parallel bit error rate detection device aggregates the channel bit error rates of all channels through a data bus to obtain a total bit error rate.

[0073] As an example, the architecture of the present application can support high-speed signal transmission at a data rate of 64 Gb / s and above, and adapt to the demand for ultra-high-speed data communication.

[0074] ​​The embodiment of the application independently and in parallel processes error code data in multiple channels, realizes real-time statistics of multi-channel error code rates, and aggregates error code rates of each channel through a bus, which supports real-time monitoring of error code rates of hundreds of parallel signals without causing significant performance degradation, and improves the speed of error code rate detection.

[0075] In a possible embodiment, a pipeline architecture is adopted to realize fast transmission and calculation of data through memory caching and a data bus. The pipeline architecture is a technology that divides a complex task into multiple independent sub-tasks and allows these sub-tasks to be executed simultaneously in different stages. The core idea of this architecture is to split a large task into multiple small tasks that are executed in sequence. Different tasks can be processed simultaneously in different stages, thereby improving the overall processing speed and throughput of the system.

[0076] In step S110, the error code rate of each parallel signal of the channel is detected to obtain the channel error code rate.

[0077] In a possible embodiment, for each channel, the channel error code rate is obtained, specifically including:

[0078] S1101: The parallel signal of the channel is divided into a plurality of first data segments according to a preset length.

[0079] Specifically, each parallel signal is divided into first data segments of a preset length in sequence according to data bits.

[0080] S1102: The first data segment is compared with a corresponding second data segment in a lookup table to obtain a comparison result of the first data segment.

[0081] Each channel corresponds to a lookup table, and the length of each second data segment stored in each position of the lookup table is also a preset length. Each second data segment in the lookup table uniquely corresponds to a first data segment.

[0082] In a possible embodiment, error code data is obtained by comparing the first data segment and the second data segment, and the error code data is taken as the comparison result.

[0083] S1103: The channel error code rate is calculated according to the comparison results of all first data segments in the channel. Thus, the error code rate calculation of the input signal is realized by collecting error code data of each channel and aggregation.

[0084] Specifically, when obtaining the channel error code rate, the parallel error code rate detection device first divides the parallel signal of the channel into a plurality of first data segments according to a preset length. Then, the first data segment is compared with a corresponding second data segment in a lookup table to obtain a comparison result of the first data segment. Finally, the channel error code rate is calculated based on the comparison results of all first data segments.

[0085] The embodiment of the present application divides the parallel signals of each channel into data segments of equal length, and compares the data segments with corresponding data segments in the lookup table, to ensure that real-time comparison results can be output in each clock cycle. Subsequently, the comparison results of all data segments are counted to obtain the channel error rate, and the double parallel processing mechanism can further improve the error rate statistical efficiency.

[0086] In a high-speed communication environment, various factors such as network environment and device state are changing in real time. On this basis, a fixed error rate detection strategy cannot adapt to such changes, resulting in a decrease in the accuracy of error rate detection.

[0087] Based on the above considerations, in one possible embodiment, the error rate detection method provided by the present application further comprises:

[0088] S130: adaptively adjusting the error rate detection parameters of the channel according to the feedback data of the signal stream in the transmission process.

[0089] Specifically, after the parallel error rate detection device dynamically adjusts the error rate detection parameters of the channel, it executes steps S110 and S120 according to the adjusted error rate detection parameters.

[0090] In the embodiment of the present application, the error rate detection parameters of each channel are independently adjusted based on the feedback data of the signal stream in the transmission process, so that each channel has flexible adaptability to improve the error rate detection quality of each channel.

[0091] In one possible embodiment, in step S130, the error rate detection parameters of the channel are adaptively adjusted according to the feedback data of the signal stream in the transmission process, specifically comprising:

[0092] S1301: determining whether the signal stream is in a stable state based on the feedback data of the signal stream in the transmission process.

[0093] Specifically, the parallel error rate detection device continuously collects various feedback data of the signal stream in the transmission process in each channel, including but not limited to signal strength, noise level, timing jitter, transmission rate and other key indicators, and determines whether the signal stream is in a stable state based on these feedback data, so as to adjust the error detection parameters accordingly.

[0094] S1302: if the signal stream is not in a stable state, adaptively adjusting the error rate detection parameters of the channel according to the analysis results of the feedback data, wherein the error rate detection parameters include error rate detection sensitivity, detection window size, error count threshold and the like.

[0095] For example, on a channel with high noise, the frequency and sensitivity of the error rate detection are increased to capture smaller errors; while on a channel with good signal quality, the sensitivity is reduced to improve the detection efficiency.

[0096] In the embodiments of the present application, the stability of the signal stream is determined by the feedback data, and the error rate detection parameters are dynamically adjusted when the signal stream is unstable, so as to ensure the stable transmission of the signal stream and provide a basis for the stability and accuracy of the error rate detection. In addition, in the embodiments of the present application, the adjustment strategies of the error rate detection parameters of different channels are independent of each other, which can significantly reduce the errors caused by the difference in data rates of different channels and ensure that the error rate statistical results of each channel are accurate.

[0097] In a possible embodiment, as shown in Figure 3 In step S1301, it is determined whether the signal stream is in a stable state based on the feedback data of the signal stream in the transmission process in the channel, specifically including:

[0098] S310: The real-time noise mean and the real-time jitter mean of the signal stream in the channel are calculated respectively to understand the average state of the signal stream.

[0099] S320: The first ratio between the real-time noise mean and the historical noise mean is calculated. The smaller the first ratio, the more stable the noise of the signal stream.

[0100] S330: The second ratio between the real-time jitter mean and the historical jitter mean is calculated. The smaller the second ratio, the more stable the jitter of the signal stream.

[0101] S340: If the first ratio is greater than the first ratio threshold and / or the second ratio is greater than the second ratio threshold, it is determined that the signal stream is not in a stable state. If the first ratio is less than or equal to the first ratio threshold and the second ratio is less than or equal to the second ratio threshold, it is determined that the signal stream is in a stable state.

[0102] When the first ratio and the second ratio are both within the corresponding ratio threshold, it is indicated that the noise and the jitter of the signal stream are both within the allowable range, and the signal stream is stable. Otherwise, the noise or the jitter of the signal stream is greater than the allowable value, and the signal stream is unstable.

[0103] The noise and the jitter affect the quality of the signal stream, and therefore, in the embodiments of the present application, the stability of the signal stream can be accurately determined by the closeness of the noise mean and the jitter mean to the historical mean.

[0104] In a possible embodiment, the adjustment of the error code rate detection sensitivity includes adjustment of an error code detection threshold, which includes an amplitude decision threshold and a delay decision threshold. The amplitude decision threshold and the delay decision threshold are set in a high-speed counter of the communication system and are thresholds for judging whether the noise amplitude and the delay exceed the allowed range. The signal within the range enclosed by the amplitude decision threshold and the delay decision threshold has stable signal strength, and the error code rate detection is accurate.

[0105] Specifically, the noise causes interference on the vertical amplitude of the signal, and the jitter of the signal stream is a short-term deviation of the edge of the signal from its ideal position in the time domain, which reflects the time delay of the signal. Therefore, the noise and the jitter have a great impact on the quality of the signal stream, and the amplitude decision threshold related to the noise and the delay decision threshold related to the jitter have a great impact on the error code rate detection sensitivity. The greater the area enclosed by the two end values of the amplitude decision threshold and the two end values of the delay decision threshold, the shorter the time required for statistical error code data, the higher the feedback efficiency of the signal stream, and the faster the final dynamic clock locking.

[0106] The embodiment of the present application adjusts the error code rate detection sensitivity by adjusting the amplitude decision threshold and the delay decision threshold, and ensures that the error code rate detection sensitivity quickly adapts to the real-time changes of the signal stream.

[0107] In a possible embodiment, the amplitude decision threshold is adjusted, specifically including:

[0108] Q1: Calculate the real-time noise variance of the signal stream in the channel.

[0109] Q2: Adjust the amplitude decision threshold of the channel according to the real-time noise variance.

[0110] The real-time noise variance is used to measure the dispersion degree of the noise feedback data of the signal stream, and is used to reflect the fluctuation degree of the signal stream caused by the noise.

[0111] In a possible embodiment, when the real-time noise variance is greater than a first variance threshold, the amplitude decision threshold is offset towards the center, so that the error code data is more easily found, and the sensitivity of the error code rate detection is improved. When the real-time noise variance is less than or equal to a second variance threshold, the amplitude decision threshold is offset towards the upper and lower sides, so that the range of the error code data becomes smaller, and the sensitivity of the error code rate detection is reduced.

[0112] The embodiment of the present application adjusts the amplitude decision threshold of the channel according to the real-time noise variance, which can quickly adjust the amplitude decision threshold by accurately grasping the influence of the noise on the fluctuation of the signal stream, so as to reduce the false positives and false negatives in the error code rate detection.

[0113] In a possible embodiment, the delay decision threshold is adjusted, specifically including:

[0114] R1: calculating real-time jitter variance of the signal stream in each channel.

[0115] R2: adjusting the delay decision threshold of each channel according to the real-time jitter variance.

[0116] The real-time jitter variance is used to measure the dispersion degree of the jitter feedback data of the signal stream, so as to reflect the fluctuation degree of the signal stream caused by the jitter.

[0117] In a possible embodiment, when the real-time jitter variance is greater than a third variance threshold, the delay decision threshold is offset to the center direction, so that the error code data is more easily found, and the sensitivity of the error rate detection is improved. When the real-time jitter variance is less than or equal to a fourth variance threshold, the delay decision threshold is offset to the left and right sides, so that the range of the error code data is reduced, and the sensitivity of the error rate detection is reduced.

[0118] According to the application, the delay decision threshold of each channel is adjusted according to the real-time jitter variance, the influence of the jitter on the fluctuation of the signal stream is accurately grasped, the delay decision threshold is quickly adjusted, and the false positives and false negatives in the error rate detection are reduced.

[0119] In another possible embodiment, as shown in FIG. 5, the adjustment of the sensitivity of the error rate detection specifically includes: Figure 4

[0120] S410: detecting the signal intensity of the signal stream in each channel and the signal intensity error between each two channels.

[0121] A high-speed counter is arranged on each parallel channel. The high-speed counter is used to measure the signal intensity and carrier frequency of the parallel signal in each channel. When the signal intensity detected by multiple high-speed counters produces a large error, it indicates that the noise level or timing jitter of the signal is large.

[0122] S420: if the maximum value of the signal intensity error is greater than an error threshold, scanning the amplitude noise of the high-speed counter on each channel, drawing an amplitude-error rate bathtub curve, and determining an optimal value of the amplitude noise as an amplitude decision threshold according to the amplitude-error rate bathtub curve.

[0123] The shape of the bathtub curve is high at both ends and low in the middle, like a bathtub, so it is called "bathtub curve". The critical points of the two high positions and the low position on the amplitude-error rate bathtub curve can be used as the optimal value of the amplitude noise, and the two critical points are used as the amplitude decision threshold.

[0124] S430: scanning the local clock delay based on the amplitude decision threshold, drawing a delay-error rate bathtub curve, and determining an optimal value of the timing jitter as a delay decision threshold according to the delay-error rate bathtub curve.

[0125] ​Similarly, the two critical points of the high and low positions on the delay-bit error rate bathtub curve can be used as the optimal value of the timing jitter, and the two critical points can be used as the delay decision threshold.

[0126] The embodiment of the present application respectively determines the amplitude decision threshold and the delay decision threshold by using the bathtub curve obtained in real time, so as to accurately and adaptively adjust the sensitivity of the bit error rate detection.

[0127] In another possible embodiment, as shown in Figure 5 The bit error rate detection parameter of the channel is adaptively adjusted according to the feedback data, and specifically includes:

[0128] S510: Detecting characteristic data of the signal stream of the channel, and the characteristic data includes the code rate, the symbol content, the jitter condition, the noise condition and the bit error rate.

[0129] S520: Inputting the characteristic data into the user data model to obtain the bit error rate detection parameter and the clock synchronization parameter matched with the characteristic data.

[0130] The user data model is trained based on a data set, and the data set includes the characteristic data (including but not limited to the number of errors, the bit error rate, the code rate, the symbol content, the noise condition and the jitter condition) of each channel and the bit error rate detection parameter and the adjustment strategy of the dynamic clock synchronization corresponding to the characteristic data. The user data model not only reflects the network environment, the device configuration and the transmission quality, but also contains the potential law and trend of the error generation, thereby providing a solid foundation for subsequent data analysis and algorithm optimization.

[0131] The embodiment of the present application accumulates the data set and the user data model, directly obtains the bit error rate detection parameter and the clock synchronization parameter matched with the characteristic data of the current signal stream through the user data model, realizes the rapid and accurate adaptive adjustment of the bit error rate detection parameter and the clock synchronization, and ensures the accuracy and stability of the bit error rate detection and the clock synchronization.

[0132] In a possible embodiment, training the user data model includes:

[0133] P1: For each data stream rate, fitting multiple fitting curves based on all characteristic data with the data stream rate in the data set, obtaining a corresponding fitting function, and the independent variable of the fitting function is the characteristic data and the dependent variable is the delay value.

[0134] In a possible embodiment, the multiple fitting curves include exponential form, linear form, logarithmic form, polynomial form and the like.

[0135] In a possible embodiment, the least square method or other regression analysis algorithm can be used to fit the curve.

[0136] P2: for each fitting function, a plurality of sets of first characteristic data having the data stream rate are selected from the data set, the plurality of sets of first characteristic data are respectively input into the fitting function, a delay value corresponding to each set of first characteristic data is obtained, and then the hardware parameters of the communication system are respectively set according to the respective delay values, and a first bit error rate error corresponding to each delay value is obtained in the running process of the communication system.

[0137] P3: a second bit error rate error of the fitting function is calculated based on all the first bit error rate errors of the fitting function.

[0138] P4: the fitting function with the minimum second bit error rate error is taken as the fitting function corresponding to the data stream rate in the user data model.

[0139] P5: second characteristic data having the data stream rate are selected from the data set, the fitting function is used to obtain bit error rate detection parameters and clock synchronization parameters corresponding to the second characteristic data, and the second characteristic data, the corresponding bit error rate detection parameters and the clock synchronization parameters are combined into a template data and stored in the database of the user data model.

[0140] Based on the above, in a possible embodiment, when the user data model is used, the current signal stream characteristic data of the channel can be input into the user data model, bit error rate detection parameters and clock synchronization parameters corresponding to the output data of the fitting function corresponding to the current data stream rate are obtained as target values of the bit error rate detection parameters and the clock synchronization parameters of the channel.

[0141] In another possible embodiment, after the current characteristic data is input into the user data model, the user data model first finds template data with the same or similar jitter and noise and the same or similar bit error rate under the condition of the same code rate and the same symbol content, at this time, the current environment and the historical environment corresponding to the data are basically consistent, and then the bit error rate detection parameters (including amplitude decision threshold, delay decision threshold, etc.) and the clock synchronization parameters corresponding to the template data are taken as the bit error rate detection parameters and the clock synchronization parameters for current adaptive adjustment, which are used to improve the adjustment efficiency of the bit error rate detection parameters.

[0142] In the embodiments of the present application, the fitting function corresponding to each data stream rate is fitted by using the data set, and the bit error rate detection parameters and the clock synchronization parameters corresponding to each set of characteristic data are obtained based on the fitting function, thereby providing a basis for subsequent rapid determination of the bit error rate detection parameters and the clock synchronization parameters corresponding to the current data stream. The mechanism optimizes the synchronization algorithm and the bit error detection process through intelligent analysis and adjustment of the model based on long-term accumulated user data, can improve the synchronization accuracy and the bit error detection capability under various devices and network conditions through "learning", and thereby ensures that the system can maintain the optimal performance in complex and changing network environments.

[0143] In another possible embodiment, as shown in Figure 6 The error rate detection method further includes dynamically synchronizing the clock, specifically including:

[0144] S610: obtaining a real-time clock phase of the serial input signal;

[0145] S620: adjusting the local clock phase to the real-time clock phase to real-time calibrate and correct the clock signal.

[0146] In a possible embodiment, the digital phase-locked loop technology is adopted to realize the real-time dynamic adjustment of the local clock, ensuring that the communication system can still maintain high-precision synchronization in the case of frequent signal changes or time delay.

[0147] As shown in Figure 7 The delay-locked loop (DLL, a kind of digital phase-locked loop technology) includes a frequency divider and a phase detector, and the output signal of the digital phase-locked loop is input into a field programmable gate array (FPGA) through a filter and an analog-to-digital converter. The frequency divider is used to divide the input signal, solving the problem that the frequency of the input signal exceeds the frequency range of the phase detector. The phase detector is used to compare the phase of the output signal of the frequency divider with the phase of the local clock. The FPGA dynamically adjusts the phase of the local clock based on the error of the two phases, so that the phase of the local clock is kept synchronized with the output signal of the frequency divider.

[0148] The embodiments of the present application intelligently adjust the synchronization clock according to the change of the real-time data stream rate, to ensure that the channels keep accurate synchronization. The synchronization mechanism can dynamically optimize the synchronization signal according to the characteristics of the signal change, eliminating the clock drift problem in the traditional static synchronization, thereby greatly improving the precision and efficiency of error detection.

[0149] Based on the above, the system of the embodiments of the present application realizes asynchronous data stream processing through dynamic clock synchronization and pipeline parallel error rate detection mechanism, ensures that synchronization is still maintained under high parallelism, avoids clock offset and data delay problems caused by multi-channel parallel, and this efficient parallel processing capability is particularly suitable for error rate detection needs of high-speed large-scale parallel data stream, and the scheme has good scalability, can support more channel parallel processing in the future, meets higher concurrent and higher-speed data stream processing needs. In addition, the dynamic adjustment mechanism of the embodiments of the present application dynamically adjusts the algorithm of the synchronous clock, the threshold of the error code statistics, and the strategy of the error code detection according to the comprehensive analysis result of the historical data and the real-time data, can flexibly cope with different signal conditions, adapt to a wide range of application scenarios, including super-high-speed communication equipment, optical fiber communication, data center equipment, etc. In particular, when the system detects that clock synchronization of a channel has a drift problem in a specific environment, it will quickly start the adaptive adjustment mechanism to finely adjust the clock calibration parameters of the channel to ensure that the accuracy of error code detection is not affected.

[0150] Figure 7 The structure diagram of a communication system based on the parallel error rate detection method is shown. As shown in Figure 7 , the communication system includes a plurality of data splitters, a serial-parallel conversion circuit and an FPGA. The serial-parallel conversion circuit converts the input signal into a plurality of parallel signals, each parallel signal corresponding to a channel. The data splitter copies the input signal intact into multiple outputs, each used to realize different signal acquisition functions. The FPGA is used to execute the parallel error rate detection method described above, calculates the corresponding error rate, frequency, etc. based on the received data, and realizes dynamic synchronization and parallel error rate detection of high-speed signals.

[0151] In Figure 7 the example shown, the serial-parallel conversion circuit converts the input signal into two parallel signals, each of which is divided into two paths by the data splitter, one of which is directly connected to the FPGA signal for collecting error code data of the channel, and the other of which collects the signal strength and carrier frequency of the channel through a high-speed counter and transmits them to the FPGA.

[0152] Based on the above, the present application also provides a parallel error rate detection device. The parallel error rate detection device can be correspondingly referred to the parallel error rate detection method described above.

[0153] In one possible embodiment, the parallel error rate detection device includes Figure 7 the FPGA in .

[0154] As an embodiment, as shown in Figure 8 , the parallel error rate detection device includes a summary module 820 and a plurality of channel detection modules 810.

[0155] Each channel detection module 810 is configured to detect the error code rate of the parallel signal of the corresponding channel, and obtain a channel error code rate. The parallel signal of each channel is obtained when the serial input signal is converted from serial to parallel.

[0156] The aggregation module 820 is configured to aggregate the channel error code rates of all channels, and obtain a total error code rate.

[0157] Embodiments of the present application independently and in parallel process error code data in multiple channels, realize real-time statistics of multi-channel error code rates, and aggregate the error code rates of each channel through a bus. This architecture supports real-time monitoring of the error code rates of hundreds of parallel signals, without causing significant performance degradation, and improves the speed of error code rate detection.

[0158] In a possible embodiment, the channel detection module 810 is specifically configured to:

[0159] divide the parallel signal of the channel into a plurality of first data segments according to a preset length;

[0160] compare the first data segment with a corresponding second data segment in the lookup table, and obtain a comparison result of the first data segment;

[0161] calculate the channel error code rate according to the comparison results of all first data segments in the channel.

[0162] Embodiments of the present application divide the parallel signal of each channel into data segments of equal length, and perform comparison in parallel, to ensure that real-time comparison results can be output in each clock cycle. Then, the comparison results of all data segments are counted to obtain the channel error code rate. The double parallel processing mechanism can further improve the error code rate statistics efficiency.

[0163] In a possible embodiment, the parallel error code rate detection device further includes an adaptive adjustment module 830, which is configured to adaptively adjust the error code rate detection parameters of the channel according to the feedback data of the signal stream in the transmission process.

[0164] In embodiments of the present application, the error code rate detection parameters of each channel are independently adjusted according to the feedback data of the signal stream in the transmission process, so that each channel has flexible adaptability, to improve the error code rate detection quality of each channel.

[0165] In a possible embodiment, as shown in Figure 9 the adaptive adjustment module 830 includes a state judgment module 8301 and a detection parameter adjustment module 8302.

[0166] The state judgment module 8301 is configured to judge whether the signal stream is in a stable state based on the feedback data of the signal stream in the transmission process.

[0167] The detection parameter adjustment module 8302 is configured to adaptively adjust the error rate detection parameter of the channel according to the analysis result of the feedback data when the signal stream is not in a stable state, and the error rate detection parameter includes error rate detection sensitivity, detection window size, and error count threshold.

[0168] In the embodiments of the present application, the stability of the signal stream is determined through the feedback data, and the error rate detection parameter is dynamically adjusted when the signal stream is unstable, so as to ensure the stable transmission of the signal stream and provide a basis for the stability and accuracy of the error rate detection. In addition, in the embodiments of the present application, the adjustment strategies of the error rate detection parameters of different channels are independent of each other, which can significantly reduce the error caused by the difference in data rate of different channels and ensure that the error rate statistical result of each channel is accurate.

[0169] In a possible embodiment, the adjustment of the error rate detection sensitivity includes the adjustment of the error detection threshold, and the error detection threshold includes an amplitude decision threshold and a delay decision threshold.

[0170] The embodiments of the present application adjust the error rate detection sensitivity by adjusting the amplitude decision threshold and the delay decision threshold, so as to ensure that the error rate detection sensitivity quickly adapts to the real-time change of the signal stream.

[0171] In a possible embodiment, the detection parameter adjustment module 8302 is specifically configured to:

[0172] calculate the real-time noise variance of the signal stream in the channel;

[0173] adjust the amplitude decision threshold of the channel according to the real-time noise variance.

[0174] The embodiments of the present application adjust the amplitude decision threshold of the channel according to the real-time noise variance, which can quickly adjust the amplitude decision threshold by accurately grasping the influence of noise on the fluctuation of the signal stream, so as to reduce the false positives and false negatives in error rate detection.

[0175] In a possible embodiment, the detection parameter adjustment module 8302 is specifically configured to:

[0176] calculate the real-time jitter variance of the signal stream in the channel;

[0177] adjust the delay decision threshold of the channel according to the real-time jitter variance.

[0178] The embodiments of the present application adjust the delay decision threshold of the channel according to the real-time jitter variance, which can quickly adjust the delay decision threshold by accurately grasping the influence of jitter on the fluctuation of the signal stream, so as to reduce the false positives and false negatives in error rate detection.

[0179] In a possible embodiment, the state judgment module 8301 is specifically configured to:

[0180] respectively calculate a real-time noise mean value and a real-time jitter mean value of the signal flow in the channel;

[0181] calculate a first ratio between the real-time noise mean value and a historical noise mean value;

[0182] calculate a second ratio between the real-time jitter mean value and a historical jitter mean value;

[0183] if the first ratio is greater than a first ratio threshold value and / or the second ratio is greater than a second ratio threshold value, determine that the signal flow is not in a stable state.

[0184] The embodiment of the application can accurately determine the stability of the signal flow by the degree of similarity between the noise mean value and the jitter mean value and the historical mean value.

[0185] In a possible embodiment, the detection parameter adjustment module 8302 is further specifically configured to:

[0186] detect the signal intensity of the signal flow in each channel and the signal intensity error between each two channels;

[0187] if the maximum value of the signal intensity error is greater than an error threshold value, scan the amplitude noise of the high-speed counter in each channel, draw an amplitude-error rate bathtub curve, and determine an optimal value of the amplitude noise as an amplitude decision threshold according to the amplitude-error rate bathtub curve;

[0188] scan the local clock delay based on the amplitude decision threshold, draw a delay-error rate bathtub curve, and determine an optimal value of the timing jitter as a delay decision threshold according to the delay-error rate bathtub curve.

[0189] The embodiment of the application respectively determines the amplitude decision threshold and the delay decision threshold by using the bathtub curve obtained in real time, so as to accurately and adaptively adjust the sensitivity of the error rate detection.

[0190] In a possible embodiment, the detection parameter adjustment module 8302 is further specifically configured to:

[0191] detect the characteristic data of the signal flow of the channel, the characteristic data including the code rate, the symbol content, the jitter condition, the noise condition, and the error rate;

[0192] input the characteristic data into a user data model to obtain an error rate detection parameter matched with the characteristic data;

[0193] The user data model is trained based on a data set, and the data set includes the characteristic data of each channel and an adjustment strategy of the error rate detection parameter corresponding to the characteristic data.

[0194] The embodiment of the application accumulates a user data set and a user data model, directly obtains a bit error rate detection parameter matched with characteristic data of a current signal stream through the user data model, and realizes fast, accurate self-adaptive adjustment of a bit error rate detection parameter and clock synchronization and bit error rate detection precision and stability.

[0195] In a possible embodiment, the parallel bit error rate detection device further comprises a training module, and the training module is configured to:

[0196] For each data stream rate, a plurality of fitting curves are fitted based on all characteristic data with the data stream rate in the data set, a corresponding fitting function is obtained, and an independent variable of the fitting function is characteristic data and a dependent variable is a delay value;

[0197] For each fitting function, a plurality of groups of first characteristic data with the data stream rate are selected from the data set, the plurality of groups of first characteristic data are respectively input into the fitting function, a delay value corresponding to each group of first characteristic data is obtained, and then hardware parameters of the communication system are respectively set according to each delay value, and a first bit error rate error corresponding to each delay value is obtained in a running process of the communication system;

[0198] A second bit error rate error of the fitting function is calculated based on all first bit error rate errors of the fitting function;

[0199] The fitting function with the minimum second bit error rate error is taken as a fitting function corresponding to the data stream rate in the user data model;

[0200] Second characteristic data with the data stream rate are selected from the data set, a bit error rate detection parameter and a clock synchronization parameter corresponding to the second characteristic data are obtained by using the fitting function, and the second characteristic data, the corresponding bit error rate detection parameter and the clock synchronization parameter are combined into a template data and stored in a database of the user data model.

[0201] In the embodiment of the application, a fitting function corresponding to each data stream rate is fitted by using a data set, and a bit error rate detection parameter and a clock synchronization parameter corresponding to each group of characteristic data are obtained based on the fitting function, thereby providing a basis for subsequently quickly determining a bit error rate detection parameter and a clock synchronization parameter corresponding to a current data stream. The mechanism optimizes a synchronization algorithm and a bit error detection process by intelligently analyzing and adjusting a model based on long-term accumulated user data, can improve synchronization precision and bit error detection capability under various devices and network conditions through "learning", and thereby ensures that the system can maintain optimal performance in a complex and changing network environment.

[0202] In a possible embodiment, the parallel bit error rate detection further comprises a dynamic clock synchronization module, and the dynamic clock synchronization module is configured to:

[0203] obtain a real-time clock phase of the serial input signal;

[0204] adjusting the local clock phase to the real-time clock phase.

[0205] Embodiments of the present application intelligently adjust the synchronization clock according to the change of the real-time data stream rate, to ensure that the various channels remain accurately synchronized. The synchronization mechanism can dynamically optimize the synchronization signal according to the characteristics of the signal change, eliminating the clock drift problem in traditional static synchronization, thereby greatly improving the accuracy and efficiency of the error code detection.

[0206] In another aspect, the present application also provides a computer program product, which comprises a computer program stored on a non-transitory computer readable storage medium, the computer program comprising program instructions, when the program instructions are executed by a computer, the computer can perform the parallel error code rate detection method provided by the above embodiments, the method comprising: detecting the error code rate of the parallel signal of each channel to obtain a channel error code rate; and aggregating the channel error code rates of all channels to obtain a total error code rate.

[0207] For each channel, the channel error code rate is obtained, specifically comprising: dividing the parallel signal of the channel into a plurality of first data segments according to a preset length; comparing the first data segment with a corresponding second data segment in a lookup table to obtain a comparison result of the first data segment; and calculating the channel error code rate according to the comparison results of all the first data segments in the channel.

[0208] In another aspect, the present application also provides a non-transitory computer readable storage medium, which stores a computer program, when the computer program is executed by a processor, the parallel error code rate detection method provided by the above embodiments is implemented, the method comprising: detecting the error code rate of the parallel signal of each channel to obtain a channel error code rate; and aggregating the channel error code rates of all channels to obtain a total error code rate.

[0209] For each channel, the channel error code rate is obtained, specifically comprising: dividing the parallel signal of the channel into a plurality of first data segments according to a preset length; comparing the first data segment with a corresponding second data segment in a lookup table to obtain a comparison result of the first data segment; and calculating the channel error code rate according to the comparison results of all the first data segments in the channel.

[0210] The device embodiments described above are only schematic, wherein the units shown as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, i.e., can be located in one place, or can be distributed on a plurality of network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the present embodiment scheme. Those skilled in the art can understand and implement without creative labor.

[0211] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be realized by means of software plus necessary universal hardware platforms, and of course can also be realized by hardware. Based on such understanding, the above technical solutions, in essence or in the part that contributes to the prior art, can be embodied in the form of a software product, which can be stored in a computer readable storage medium, such as a read-only memory (ROM) / random access memory (RAM), a magnetic disk, an optical disk, and the like, and includes a number of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute the methods described in each embodiment or some parts of the embodiments.

[0212] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be realized by means of software plus necessary universal hardware platforms, and of course can also be realized by hardware. Based on such understanding, the above technical solutions, in essence or in the part that contributes to the prior art, can be embodied in the form of a software product, which can be stored in a computer readable storage medium, such as a read-only memory (ROM) / random access memory (RAM), a magnetic disk, an optical disk, and the like, and includes a number of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute the methods described in each embodiment or some parts of the embodiments.

[0213] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for some technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A parallel bit error rate detection method, characterized in that: include: Detecting a bit error rate of a parallel signal of each channel to obtain a channel bit error rate; wherein the parallel signal of each channel is obtained when a serial input signal is converted from serial to parallel; Sum up the channel bit error rates of all channels to obtain the total bit error rate; For each channel, the channel bit error rate is obtained, specifically including: Dividing the parallel signal of the channel into a plurality of first data segments according to a preset length; Comparing the first data segment with the corresponding second data segment in the lookup table to obtain a comparison result of the first data segment; Calculating the channel bit error rate according to the comparison results of all first data segments in the channel; The bit error rate detection method further includes: When the signal flow in the channel is not in a stable state, adaptively adjusting the bit error rate detection parameters of the channel according to feedback data of the signal flow in the channel during transmission; Adaptively adjusting the bit error rate detection parameters of the channel according to the feedback data specifically includes: Detecting characteristic data of the signal stream of the channel, wherein the characteristic data includes the number of bit errors, code rate, code element content, jitter, noise and bit error rate; Inputting the characteristic data into a user data model to obtain a bit error rate detection parameter matching the characteristic data; The user data model is trained based on a data set, where the data set includes characteristic data of each channel and an adjustment strategy for a bit error rate detection parameter corresponding to the characteristic data.

2. The parallel bit error rate detection method according to claim 1, characterized in that: The bit error rate detection parameters include bit error rate detection sensitivity, detection window size, and error count threshold.

3. The parallel bit error rate detection method according to claim 2, characterized in that: Adjusting the bit error rate detection sensitivity includes adjusting the bit error detection threshold, and the bit error detection threshold includes an amplitude decision threshold and a delay decision threshold.

4. The parallel bit error rate detection method according to claim 3, characterized in that: Adjusting the amplitude decision threshold includes: Calculating the real-time noise variance of the signal stream in the channel; The amplitude decision threshold of the channel is adjusted according to the real-time noise variance.

5. The parallel bit error rate detection method according to claim 3, characterized in that: Adjusting the delay decision threshold specifically includes: Calculating the real-time jitter variance of the signal stream in the channel; The delay decision threshold of the channel is adjusted according to the real-time jitter variance.

6. The parallel bit error rate detection method according to claim 1, characterized in that: Determining whether the signal flow in the channel is in a stable state specifically includes: respectively calculating a real-time noise mean and a real-time jitter mean of the signal stream in the channel; Calculating a first ratio between the real-time noise mean and the historical noise mean; Calculating a second ratio between the real-time jitter mean and the historical jitter mean; If the first ratio is greater than a first ratio threshold and / or the second ratio is greater than a second ratio threshold, it is determined that the signal flow is not in a stable state.

7. The parallel bit error rate detection method according to claim 3, characterized in that: The adjustment of the bit error rate detection sensitivity specifically includes: Detect the signal strength of the signal flow in each channel and the signal strength error between two channels; If the maximum value of the signal strength error is greater than the error threshold, the amplitude noise of the high-speed counter on each channel is scanned, and an amplitude-bit error rate bathtub curve is drawn. The optimal amplitude noise value is determined based on the amplitude-bit error rate bathtub curve and used as the amplitude decision threshold. The local clock delay is scanned based on the amplitude decision threshold, a delay-bit error rate bathtub curve is drawn, and an optimal timing jitter value is determined according to the delay-bit error rate bathtub curve as the delay decision threshold.

8. The parallel bit error rate detection method according to claim 1, characterized in that: Training the user data model includes: For each data flow rate, fitting multiple fitting curves based on all characteristic data with the data flow rate in the data set to obtain a corresponding fitting function, where the independent variable of the fitting function is the characteristic data and the dependent variable is the delay value; For each fitting function, selecting a plurality of sets of first characteristic data having the data flow rate from the data set, inputting the plurality of sets of first characteristic data into the fitting function respectively, obtaining a delay value corresponding to each set of the first characteristic data, then setting hardware parameters of the communication system according to each delay value, and obtaining a first bit error rate error corresponding to each delay value during operation of the communication system; calculating a second bit error rate error of the fitting function based on all first bit error rate errors of the fitting function; using the fitting function with the smallest second bit error rate error as the fitting function corresponding to the data flow rate in the user data model; Select second characteristic data having the data flow rate from the data set, use the fitting function to obtain the bit error rate detection parameters and clock synchronization parameters corresponding to the second characteristic data, and combine the second characteristic data, the corresponding bit error rate detection parameters and the clock synchronization parameters into a template data, and store it in a database of the user data model.

9. The parallel bit error rate detection method according to claim 1, characterized in that: The bit error rate detection method further includes: Obtaining a real-time clock phase of the serial input signal; The local clock phase is adjusted to the real-time clock phase.

10. A parallel bit error rate detection device, characterized in that: Includes summary module and multiple channel detection modules; Each of the channel detection modules is used to detect the bit error rate of the parallel signal of the corresponding channel to obtain the channel bit error rate; wherein the parallel signal of each channel is obtained when the serial input signal is converted from serial to parallel; The summarizing module is used to summarize the channel bit error rates of all channels to obtain a total bit error rate; The bit error rate detection device further includes an adaptive adjustment module, configured to adaptively adjust the bit error rate detection parameters of the channel according to feedback data of the signal flow in the channel during transmission, when the signal flow in the channel is not in a stable state; The adaptive adjustment module includes a detection parameter adjustment module, and the detection parameter adjustment module is specifically configured to: Detecting characteristic data of the signal stream of the channel, wherein the characteristic data includes the number of bit errors, code rate, code element content, jitter, noise and bit error rate; Inputting the characteristic data into a user data model to obtain a bit error rate detection parameter matching the characteristic data; The user data model is trained based on a data set, where the data set includes characteristic data of each channel and an adjustment strategy for a bit error rate detection parameter corresponding to the characteristic data.

11. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the parallel bit error rate detection method according to any one of claims 1 to 9 is implemented.

12. A computer program product, comprising a computer program, characterized in that: When the computer program is executed by a processor, the parallel bit error rate detection method according to any one of claims 1 to 9 is implemented.

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