Method and system for realizing testability of high-speed network switching chip

Abstract

The invention relates to the technical field of switching chip design, in particular to a high-speed network switching chip testability implementation method and system, and the method comprises the steps: constructing a chip function test environment, and configuring a to-be-tested high-speed network switching chip; generating function test data according to the test instruction, wherein the function test data comprises internal logic self-test data, chip exception test data, chip state test data and chip flow test data; and performing function test and verification on the high-speed network switching chip to be tested by using the function test data based on the chip function test environment. According to the method, a loopback mode, exception handling, state monitoring, flow statistics and the like penetrate through the chip front-end design process, testability of the high-speed network switching chip is achieved, rapid function testing and problem and defect positioning of the chip are supported, laboratory work performance testing efficiency after the chip is returned can be improved, and the working efficiency of a laboratory can be improved. And the screening test efficiency of the chip on an automatic machine is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of switching chip design, and particularly to a method and system for realizing the testability of a high-speed network switching chip. Background Art

[0002] The basic structure of a high-speed network switching chip is a multi-port high-speed network switching structure, which includes a core switch mainly based on a large-capacity RAM, a controller logic mainly for protocol packet processing, and a multi-channel high-speed serial transceiver (SERializer / DESerializer, SerDes) circuit.

[0003] In existing switching chip testing methods, such as the published patent (Patent No.: CN200410030885.6), which discloses a method for testing a switching chip and related high-speed links, supporting continuous and automatic testing of the switching chip and its high-speed links, and reporting statistical information in a timely manner to meet the testing needs in actual design and production; another example is the published patent (Patent No.: CN201010159835.3), which discloses a method and testing technology for realizing the full-switching function test of a switching network chip, aiming to reduce the testing cost of the full-switching function; and yet another example is the published patent (Patent No.: CN201710508592.1) which discloses a method for testing the configuration ports and routing functions of a switching chip to be tested. In the existing publicly disclosed switching chip testing schemes, most are single or a certain type of function testing, without considering the logic in the front-end design of the chip comprehensively. Therefore, how to conduct multi-type logic function testing of the chip throughout the entire process of switching chip design to quickly locate chip problems and defects and improve the efficiency of chip back-end testing has become an urgent problem to be solved in switching chip design. Summary of the Invention

[0004] Therefore, the present invention provides a system and method for realizing the testability of a high-speed network switching chip to solve the problem of incomplete logic coverage in switching chip testing.

[0005] According to the design scheme provided by the present invention, on the one hand, a method for realizing the testability of a high-speed network switching chip is provided, including:

[0006] Construct a chip function test environment and configure the high-speed network switching chip to be tested;

[0007] Generate function test data according to test instructions, where the function test data includes internal logic self-test data, chip exception test data, chip status test data, and chip traffic test data;

[0008] Based on the chip function test environment and using the function test data, conduct function testing and verification on the high-speed network switching chip to be tested.

[0009] As a method for realizing the testability of the high-speed network switching chip of the present invention, further, functional test data is generated according to test instructions, including:

[0010] The enable register matching the functional test type is configured according to the test instruction, and functional test data corresponding to the functional test type is generated. The functional test type includes the internal logic self-test type, the chip exception test type, the chip status test type, and the chip traffic test type. Among them, the number of enable registers is consistent with the functional test type of the high-speed network switching chip to be tested.

[0011] As a method for realizing the testability of the high-speed network switching chip of the present invention, further, the high-speed network switching chip to be tested is functionally tested and verified by using the test data, including:

[0012] The logic circuit function of the high-speed network switching chip to be tested is tested and verified by using the internal logic self-test data; the exception information of the high-speed network switching chip to be tested is detected and processed by using the chip exception test data; the status of the internal components of the high-speed network switching chip to be tested is monitored by using the chip status test data. The internal components of the chip include clock, reset, configuration management, high-speed channel, controller, and core switch; the service traffic of the high-speed network switching chip to be tested is counted and statistically analyzed by using the chip traffic test data.

[0013] As a method for realizing the testability of the high-speed network switching chip of the present invention, further, the logic circuit function of the high-speed network switching chip to be tested is tested and verified by using the internal logic self-test data, including:

[0014] On the core switch of the high-speed network switching chip to be tested, the packet generation logic is used to test the chip full-load pressure. The packet generation logic is used to generate multiple types of packets with full load and configurable load; the packet detection logic is used to detect the packets at the receiving and transmitting ends of the core switch.

[0015] On the protocol controller path of the high-speed network switching chip to be tested, the loopback path of the data path is tested by using a pseudo-random binary sequence, and the pseudo-random binary sequence is of multiple modes.

[0016] As a method for realizing the testability of the high-speed network switching chip of the present invention, further, the loopback path of the data path is tested by using a pseudo-random binary sequence, including:

[0017] At the high-speed channel interface of the high-speed network switching chip to be tested, the receiving and transmitting sides of the channel are directly connected by using a coaxial cable, and the external Cable loopback test of the chip is carried out by using the pseudo-random binary sequence inside the high-speed channel SerDes. The status of the receiving and transmitting paths of the chip high-speed channel SerDes is tested and the internal error code of the SerDes is detected.

[0018] Perform a serial loopback test from the transmit side to the receive side of the physical media attachment layer of the high-speed network switch chip under test, test the transmit and receive logic of the physical media attachment layer path of the chip's high-speed channel, and eliminate abnormal attenuation at the board level of the chip package machine;

[0019] Perform a parallel loopback test on the remote pseudo-random binary sequence from the receive side to the transmit side of the physical media attachment layer of the high-speed network switch chip under test. By receiving the parallel data and loopbacking it remotely to the pseudo-random binary sequence generation and detection logic, test the analog circuit logic function of the entire physical media attachment layer of the chip;

[0020] Perform a parallel loopback test on the transmit side and receive side of the physical coding layer of the high-speed network switch chip under test. By transmitting parallel data and loopbacking it proximally to the receive side before serial-to-parallel conversion, test the digital circuit logic function of the entire physical coding layer inside the chip;

[0021] Loop back the remote pseudo-random binary sequence through the receive side of the physical media attachment layer, the receive side of the physical coding layer, the transmit side of the physical coding layer, and the receive side of the physical coding layer of the high-speed network switch chip under test to the pseudo-random binary sequence generation and detection logic, and test the digital circuit of the entire physical coding layer and the analog circuit function of the physical media attachment layer;

[0022] Use the routing method to route the data packet to the controller port of the high-speed network switch chip under test, so that the data packet passes through the receive end of the physical media attachment layer, the receive end of the physical coding layer, and the receive end of the controller and loopbacks to the controller port, and test the protocol logic function of a single switch port of the controller.

[0023] As a method for realizing the testability of the high-speed network switch chip of the present invention, further, use the chip abnormal test data to detect and process the abnormal information of the high-speed network switch chip under test, including:

[0024] Perform abnormal detection on the internal abnormal states of the high-speed network switch chip under test. The internal abnormal states include: clock abnormal state, reset abnormal state, initialization abnormal state, physical media attachment layer abnormal state, port physical layer abnormal state, physical coding layer abnormal state, controller abnormal state, routing abnormal state, configuration path abnormal state, message exchange abnormal state, and storage abnormal state;

[0025] Use the abnormal detection register and log to record the abnormal detection results and report them to the off-chip processor by priority according to the abnormal classification.

[0026] As a method for realizing the testability of the high-speed network switch chip of the present invention, further, use the chip status test data to monitor the internal component status of the high-speed network switch chip under test, and also include:

[0027] Use the status register to record the operating status of the internal components of the high-speed network switching chip to be tested, and classify the operating status of the internal components of the chip into abnormal status, state machine status, storage status, and queue status according to the status information;

[0028] Monitor the operating status of the internal components of the chip through the preset monitoring logic.

[0029] On the other hand, the present invention also provides a testability implementation system for a high-speed network switching chip, including: a switching chip configuration module, a test data generation module, and a chip function test module, where,

[0030] The switching chip configuration module is used to build a chip function test environment and configure the high-speed network switching chip to be tested;

[0031] The test data generation module is used to generate functional test data according to test instructions, and the functional test data includes internal logic self-test data, chip abnormal test data, chip status test data, and chip traffic test data;

[0032] The chip function test module is used to perform functional testing and verification on the high-speed network switching chip to be tested based on the chip function test environment and using the functional test data.

[0033] Advantages of the present invention:

[0034] Combining the characteristics of the network switching chip, the present invention covers the testing of main paths such as the switching chip controller path, PCS path, and PMA path through built-in self-test and multiple loopback paths; uses abnormal information processing such as abnormal detection, abnormal reporting, and abnormal recovery to support Debug positioning of chip abnormalities, and reports and processes abnormalities at different levels for different components; and monitors the status of each internal component of the chip, accurately records the trajectories of various types of packets, and performs bandwidth statistics, etc. The loopback mode, abnormal processing, status monitoring, traffic statistics, etc. are integrated into the front-end design process of the chip to realize the testability of the high-speed network switching chip, support the rapid functional testing of the chip and problem defect positioning, which is beneficial to improving the laboratory functional testing efficiency after the chip is returned, and improving the screening test efficiency of the chip on the automated machine platform. Description of the Drawings

[0035] Figure 1 Schematic diagram of the testability implementation process of the high-speed network switching chip in the embodiment;

[0036] Figure 2 Schematic diagram of the testability architecture of the high-speed network switching chip in the embodiment. Detailed Embodiments

[0037] To make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the accompanying drawings and technical solutions.

[0038] In view of the complexity of the functional testing of high-speed network switching chips, an embodiment of the present invention, as shown in Figure 1 provides a method for realizing the testability of a high-speed network switching chip, including:

[0039] S101. Build a chip functional test environment and configure the high-speed network switching chip to be tested;

[0040] S102. Generate functional test data according to test instructions, where the functional test data includes internal logic self-test data, chip exception test data, chip status test data, and chip traffic test data;

[0041] S103. Based on the chip functional test environment and using the functional test data, perform functional testing and verification on the high-speed network switching chip to be tested.

[0042] As shown in Figure 2 , the basic structure of a high-speed network switching chip is a multi-port high-speed network switching structure, which includes a core switch mainly based on a large-capacity RAM, a controller logic mainly for protocol packet processing, and a multi-channel high-speed serial transceiver (SERializer / DESerializer, SerDes) circuit. Combining the characteristics of the high-speed network switching chip, classify the testability content, and comprehensively consider the front-end design logic of the high-speed network switching chip through built-in self-tests such as various loopback tests, exception information processing and reporting, internal state monitoring, and traffic statistics counting. Figure 2 In, the IIC integrated circuit bus uses a multi-master and multi-slave architecture, the JTAG interface is mainly used for internal chip testing, and during the physical layer, the PHY is responsible for providing the electrical, mechanical, and optoelectronic conversions required for the physical connection for the bit transmission between link layer entities. The data is transmitted in the forward order, that is, from the MAC layer to the PCS, PMA, and PMD sub-layers in sequence, and vice versa for the receiving process. Physical coding sub-layer (physical codesubplayer PCS): Compile and decode the newly transmitted data to facilitate transmission on the physical medium and perform auto-negotiation, so that network devices can adjust both ends of the line to the highest transmission capacity, that is, both ends of the line can support the fastest speed. Physical medium attachment layer (physical medium attachmenm PMA): Generate the transmission signal of the line, receive the signal on the line, perform clock recovery, and recover the reference clock from the received data stream. The physical medium dependent sub-layer (physical mediumdependent PMD) defines the interface standards for different transmission media and provides a physical connection.

[0043] Configure the enable register that matches the functional test type according to the test instruction, and generate functional test data corresponding to the functional test type. The functional test type includes the internal logic self-test type of the chip, the chip exception test type, the chip status test type, and the chip traffic test type. Among them, the number of enable registers is consistent with the functional test type of the high-speed network switching chip to be tested.

[0044] Concentrate the self-test logic on the core switch, controller, and protocol control path, and implement the loopback test that can cover the protocol controller through multiple loopback paths of the protocol controller data path. Ensure that the chip can monitor the chip status during normal or abnormal operation by adding exception handling, internal state monitoring, and traffic statistics logic functions, and improve the test location means and test efficiency of the chip. During the test process, trigger the corresponding test by configuring the enable register; correspondingly, the corresponding test result can be obtained by reading the register value related to the test or viewing certain output signals.

[0045] Specifically, the functional test and verification of the high-speed network switching chip to be tested using the test data can be designed to include:

[0046] Use the internal logic self-test data to test and verify the logic circuit function of the high-speed network switching chip to be tested; use the chip exception test data to detect and process the exception information of the high-speed network switching chip to be tested; use the chip status test data to monitor the internal component status of the high-speed network switching chip to be tested. The internal components of the chip include clock, reset, configuration management, high-speed channel, controller, and core switch; use the chip traffic test data to count and statistics the service traffic of the high-speed network switching chip to be tested.

[0047] Among them, using the internal logic self-test data to test and verify the logic circuit function of the high-speed network switching chip to be tested can include:

[0048] On the core switch of the high-speed network switching chip to be tested, use the packet generation logic to test the chip full-load pressure. The packet generation logic is used to generate multiple types of packets with full load and configurable load; use the packet detection logic to detect the packets at the receiving and transmitting ends of the core switch.

[0049] On the protocol controller path of the high-speed network switching chip to be tested, use the pseudo-random binary sequence to test the loopback path of the data path. The pseudo-random binary sequence is in multiple modes.

[0050] The built-in self-test logic of the high-speed network switching chip mainly focuses on the core switching, controller, PCS, and PMA logics. Among them, for the core switching, an independent switching interface can be added (or multiplexed with a certain data port), and a packet generator logic is designed. This logic can generate multiple types of packets with configurable full-load loads. A similar packet detection logic is designed at the receiving end to detect the received packets and support the automatic comparison function of sending and receiving packets. In terms of the protocol controller path, pseudo-random binary sequence (PRBS) generation logic is designed in the transmit (TX) direction of PCS and PMA, which includes various PRBS patterns internally, such as PRBS-31, PRBS-23, PRBS-15, PRBS-7, etc.; correspondingly, in the receiving path, PRBS detection logic is designed in the receive (RX) direction of PCS and PMA, and various PRBS patterns are also designed internally to support the detection and comparison with the PRBS logic at the sending end. The data path of the protocol controller includes multiple types of loopback paths, combined with Figure 1 the loopback paths in

[0051] 1) External Cable loopback: As shown in ① of the loopback path in Figure 2 , during external Cable loopback, the high-speed channel interface signals directly interconnect the TX and RX of each channel through coaxial cables (or through backplanes with different attenuation characteristics), and enable the PRBS generation and detection logics inside the high-speed channel SerDes through the I2C configuration interface. The channel characteristics are checked by detecting the bit errors inside the SerDes. During the Cable loopback test, the transceiver paths of the high-speed channel SerDes can be tested for normal operation.

[0052] 2) PMA_TX2RX loopback: As shown in ② of the loopback path in Figure 2 , it is a serial loopback from the PMA transmit side to the receive side. The transmitted serial data is looped back to the receiving end proximally inside the chip, which can test and eliminate problems with packaging and board-level attenuation and test the transceiver logic of the high-speed channel PMA path.

[0053] 3) PMA_RX2TX loopback: As shown in ③ of the loopback path in Figure 2 , the PRBS data generated distally is looped back in parallel from the PMA receive side to the PMA transmit side. The received parallel data is looped back distally to the PRBS generation and detection logic at the distal end, which can test the logic function of the entire PMA analog part circuit.

[0054] 4) PCS_TX2RX loopback: As shown in Figure 2As shown by ④ in the loopback path, there is a parallel loopback from the PCS transmitting side to the receiving side. The transmitted parallel data is looped back to the receiving end proximally before serial-to-parallel conversion, and the logic functions of the entire PCS digital part can be tested within the chip.

[0055] 5) PCS_RX2TX loopback: As Figure 2 shown by ⑤ in the loopback path, the PRBS data generated distally is received by PMA, then received by PCS, then sent by PCS, and looped back distally to the PRBS generation and detection logic by PCS reception, and the logic functions of the entire PCS digital part and the PMA analog part circuits can be tested.

[0056] 6) Controller port loopback function: As Figure 2 shown by ⑥ in the loopback path, by configuring the routing mode of the switching chip, the received data packet is routed to this port. The data packet is received by the PMA receiving end, the PCS receiving end, the control receiving end, and then routed to this port through routing, and then sent out through the control sending end, the PCS sending end, and the PMA sending end, and the logic function of a single switching port protocol controller can be tested.

[0057] Among them, using the chip exception test data to detect and process the exception information of the high-speed network switching chip to be tested may include:

[0058] Performing exception detection on the internal abnormal states of the high-speed network switching chip to be tested, and the internal abnormal states include: clock abnormal state, reset abnormal state, initialization abnormal state, physical media connection layer abnormal state, port physical layer abnormal state, physical coding layer abnormal state, controller abnormal state, routing abnormal state, configuration path abnormal state, message switching abnormal state, and storage abnormal state;

[0059] Recording the exception detection results using the exception detection register and log and reporting them to the off-chip processor by priority according to the exception classification.

[0060] Each component inside the high-speed network switching chip needs to be designed with exception detection, including: clock exception, reset exception, initialization exception, PMA exception, PHY exception, PCS exception, controller exception, routing exception, configuration path exception, switching exception, storage exception, etc.

[0061] 1) Clock exception: The main manifestations of the clock exception are CorePLL abnormal unlocking and gating exception.

[0062] 2) Reset exception: The main manifestations of the reset exception are the reset locking of each component during the normal power-on process and the triggering of reset exceptions, etc.

[0063] 3) Initialization exception: The initialization exception mainly refers to the abnormal loading of the EEPROM in the IIC master mode and the timeout exception of the entire chip power-on initialization.

[0064] 4) High-speed channel anomaly: High-speed channel anomaly mainly refers to PMA anomaly and PCS anomaly. PMA anomaly mainly includes PLL VCO calibration anomaly, transmitter DCC calibration anomaly, transmitter phase calibration anomaly, multi-channel transmitter clock alignment anomaly, receiver LOS calibration anomaly, CDR VCO calibration anomaly, CTLE / DFE adaptive equalization anomaly, receiver clock phase calibration anomaly, etc. PCS anomaly mainly refers to physical layer anomalies specified by the protocol, such as decoding anomaly, descrambling anomaly, IDLE anomaly, synchronization anomaly, binding anomaly, etc.

[0065] 5) Controller anomaly: Controller anomaly mainly refers to message anomalies specified by the protocol, such as response anomaly, timeout anomaly, packet detection anomaly, etc.

[0066] 6) Routing anomaly: Routing anomaly mainly refers to protocol message routing anomaly, routing ID anomaly, etc.;

[0067] 7) Configuration path anomaly: Configuration path anomaly mainly refers to configuration path response anomaly, configuration register configuration value anomaly, configuration address anomaly, etc.

[0068] 8) Switching anomaly: Switching anomaly mainly refers to message timeout anomaly, message abnormal congestion, etc.;

[0069] 9) Storage anomaly: Storage anomaly mainly includes memory anomaly and FIFO anomaly, etc.

[0070] After the above anomalies of the chip are triggered, anomaly recording and reporting are required. For the anomaly recording of each component, it is mainly through anomaly detection register recording, anomaly scene capture and anomaly log recording. Among them, anomaly detection register recording and log recording are mainly used for anomaly type discrimination and anomaly traceability. To facilitate the software and hardware collaborative function test of anomaly handling, generally the design of the anomaly detection register needs to support the function of configuring and triggering anomaly reporting; the anomaly scene capture is mainly used for capturing the scene related to the anomaly event, such as IDLE anomaly is used to capture the abnormal code pattern, message anomaly is used to capture the necessary message header information, etc. The detection of anomalies needs to pay extra attention to the anomaly detection of the main path. Especially for the switching chip, the congestion of the switching port is the most worthy of attention anomaly. After the chip detects congestion at the switching port, it should trigger the corresponding event and design a complete hardware recovery mechanism to ensure the congestion handling in case of port anomaly.

[0071] After an exception is triggered, in addition to the hardware recording the exception, the relevant exceptions need to be reported to the off-chip processor. The exception reporting of the high-speed network switching chip needs to report exceptions with priorities according to the exception classification. There are two reporting methods: interrupt reporting and maintenance packet reporting. Interrupt reporting mainly reports fatal exceptions related to faults, and maintenance reporting can report all exceptions. The exception reporting inside the chip needs to support the reporting enable control for each exception.

[0072] Chip exception handling includes Debug handling and software handling. Debug handling is mainly used to solve the positioning and recovery of the abnormal working state of the chip, such as power-on initialization exception, reset release exception, clock exception, etc. These exceptions can be located and processed by designing the Debug path. Software handling mainly includes exceptions during the protocol data processing, such as packet error, idle sequence error, transmission congestion, etc. Software exceptions are recovered through the software handling logic, and the software operations need to be designed correspondingly for different exceptions.

[0073] Among them, using the chip status test data to monitor the status of the internal components of the high-speed network switching chip to be tested also includes:

[0074] Using the status register to record the operating status of the internal components of the high-speed network switching chip to be tested, and dividing the operating status of the internal components of the chip into abnormal status, state machine status, storage status, and queue status according to the status information;

[0075] Monitoring the operating status of the internal components of the chip through the preset monitoring logic.

[0076] The internal design of the high-speed network switching chip includes multiple components such as clocks, resets, configuration management, switching, and multiple ports and channels. A large number of status registers should be designed in each component to record the operating status of the component. For the common logic of clocks, resets, initialization, configuration management, etc. in general-purpose chips, as well as the high-speed channels, protocol processing controllers, and switching processing logics unique to switching chips, status registers are designed respectively. According to the classification of status information, as shown in Table 1, the operating status monitoring logic can be added.

[0077] Table 1 Schematic diagram of the internal status monitoring logic of the chip

[0078]

[0079] The data packet service processing characteristics of the high-speed network switching chip are very obvious. Its main traffic statistics mainly include the statistical information shown in Table 2 below according to the processing of service flows.

[0080] Table 2 Schematic diagram of the internal traffic statistics count of the chip

[0081] Statistical Information Description Number of Error Bits Number of Received Error Bits Number of Decoding Errors Number of Codewords with Received Error Decoding Number of Received Messages Number of Messages Received at the Port Number of Correct Messages Received Number of Correct Messages Received at the Port Number of Error Messages Received Number of Error Messages Received at the Port Number of Locally Maintained Packets Received Number of Locally Maintained Packets Received at the Port Number of Response ACKs Received Number of ACKs Received at the Port Number of Response NACKs Received Number of NACKs Received at the Port Number of Link Request Reset Control Characters Received Number of Link Request Reset Control Characters Received at the Port Number of Messages Discarded by the Receiver Number of Messages Discarded by the Receiver at the Port Number of Messages Routed by the Receiver Number of Messages Normally Routed by the Receiver Number of Messages Entering the Switch Number of Messages Entering the Switch Input Buffer Number of Messages Forwarded by the Switch Number of Messages Forwarded by the Switch Number of Messages Forwarded by the Switch to the Port Number of Messages Forwarded by the Switch to the Port Number of Messages Discarded by the Switch Number of Messages Discarded by the Switch Number of Messages Discarded by the Port Transmitter Number of Messages Discarded by the Port Transmitter Number of Messages Transmitted by the Port Number of Messages Transmitted by the Port Number of Messages Retransmitted by the Port Number of Messages Retransmitted by the Port Number of ACKs Transmitted by the Port Number of ACK Response Control Characters Transmitted by the Port Number of NACKs Transmitted by the Port Number of NACK Response Control Characters Transmitted by the Port Number of Retries Transmitted by the Port Number of Retry Control Characters Transmitted by the Port Number of Maintenance Packets Transmitted by the Port Number of Maintenance Packets Transmitted by the Port Number of Port-Write Packets Transmitted by the Port Number of Port-Write Packets Transmitted by the Port

[0082] The above statistical information is interrelated. When designing, it is necessary to clarify the relationship between the counts of each part in order to accurately record data packets and conduct traffic analysis and statistics.

[0083] Furthermore, based on the above method, an embodiment of the present invention further provides a testability implementation system for a high-speed network switching chip, including: a switching chip configuration module, a test data generation module, and a chip function test module, where

[0084] The switching chip configuration module is used to build a chip function test environment and configure the high-speed network switching chip to be tested;

[0085] The test data generation module is used to generate function test data according to test instructions, and the function test data includes internal logic self-test data, chip exception test data, chip status test data, and chip traffic test data;

[0086] The chip function test module is used to perform function test and verification on the high-speed network switching chip to be tested based on the chip function test environment and using the function test data.

[0087] Unless otherwise specifically stated, the relative steps, numerical expressions, and values of the components and steps set forth in these embodiments do not limit the scope of the present invention.

[0088] Each embodiment in this specification is described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other. For the system disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the description of the method part.

[0089] The units and method steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those of ordinary skill in the art can use different methods to implement the described functions for each specific application, but such implementation is not considered to exceed the scope of the present invention.

[0090] Those of ordinary skill in the art can understand that all or part of the steps in the above method can be completed by instructing relevant hardware through a program, and the program can be stored in a computer-readable storage medium, such as: read-only memory, magnetic disk or optical disc, etc. Optionally, all or part of the steps of the above embodiments can also be implemented using one or more integrated circuits. Correspondingly, each module / unit in the above embodiments can be implemented in the form of hardware or in the form of a software function module. The present invention is not limited to any specific form of combination of hardware and software.

[0091] Finally, it should be noted that: the above embodiments are only specific embodiments of the present invention, used to illustrate the technical solutions of the present invention, rather than limiting it. The protection scope of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: any person skilled in the art within the technical scope disclosed by the present invention can still modify the technical solutions recorded in the foregoing embodiments, or can easily think of changes, or perform equivalent replacements on some of the technical features; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A method for realizing the testability of a high-speed network switching chip, characterized in that, Including: Build a chip function test environment and configure the high-speed network switching chip to be tested; Generate function test data according to test instructions, where the function test data includes internal logic self-test data, chip exception test data, chip status test data, and chip traffic test data; Based on the chip function test environment and using the function test data, perform function test and verification on the high-speed network switching chip to be tested.

2. The testability implementation method of the high-speed network switching chip according to claim 1, characterized in that, Generate function test data according to test instructions, including: Configure the enable register matching the function test type according to the test instructions and generate function test data corresponding to the function test type. The function test types include chip internal logic self-test type, chip exception test type, chip status test type, and chip traffic test type. Among them, the number of enable registers is consistent with the function test types of the high-speed network switching chip to be tested.

3. The implementation method of the testability of the high-speed network switching chip according to claim 1, wherein Use the test data to perform function test and verification on the high-speed network switching chip to be tested, including: Use the internal logic self-test data to test and verify the logic circuit function of the high-speed network switching chip to be tested; use the chip exception test data to detect and process the exception information of the high-speed network switching chip to be tested; use the chip status test data to monitor the status of the internal components of the high-speed network switching chip to be tested, where the internal components of the chip include clock, reset, configuration management, high-speed channel, controller, and core switch; use the chip traffic test data to count and statistically analyze the service traffic of the high-speed network switching chip to be tested.

4. The method for realizing the testability of the high-speed network switching chip according to claim 3, wherein Use the internal logic self-test data to test and verify the logic circuit function of the high-speed network switching chip to be tested, including: On the core switch of the high-speed network switching chip to be tested, use the packet generation logic to test the chip full-load pressure, and the packet generation logic is used to generate multiple types of packets with full load and configurable load; Use the packet detection logic to detect the packets at the transceiver ends of the core switch; On the protocol controller path of the high-speed network switching chip to be tested, use the pseudo-random binary sequence to test the loopback path of the data path, and the pseudo-random binary sequence is in multiple modes.

5. The method for implementing the testability of the high-speed network switching chip according to claim 4, wherein Use the pseudo-random binary sequence to test the loopback path of the data path, including: At the high-speed channel interface of the high-speed network switching chip to be tested, directly connect the transceiver sides of the channel using a coaxial cable, and use the pseudo-random binary sequence inside the high-speed channel SerDes to perform external Cable loopback test of the chip, test the transceiver path status of the chip high-speed channel SerDes and detect the internal error code of SerDes; Perform serial loopback test from the physical medium attachment layer transmit side to the receive side of the high-speed network switching chip to be tested, test the transceiver logic of the physical medium attachment layer path of the chip high-speed channel and eliminate the abnormal attenuation of the chip package board level; Perform parallel loopback test on the far-end pseudo-random binary sequence from the receive side to the transmit side of the physical medium attachment layer of the high-speed network switching chip to be tested. By receiving the parallel data and loopbacking it to the far-end pseudo-random binary sequence generation and detection logic, test the analog circuit logic function of the entire physical medium attachment layer of the chip. Perform parallel loopback tests on the physical coding layer transmit side and receive side of the high-speed network switching chip under test. Loop back the transmitted parallel data proximally to the receive side before serial-to-parallel conversion to test the digital circuit logic function of the entire physical coding layer within the chip. Loop back the distal pseudo-random binary sequence through the receive side of the physical media attachment layer, the receive side of the physical coding layer, the transmit side of the physical coding layer, and the distal end of the receive side of the physical coding layer of the high-speed network switching chip under test to the pseudo-random binary sequence generation and detection logic to test the digital circuit of the entire physical coding layer and the analog circuit function of the physical media attachment layer. Route the data packet to the controller port of the high-speed network switching chip under test using the routing method, and loop back the data packet through the receive end of the physical media attachment layer, the receive end of the physical coding layer, and the receive end of the controller to the controller port to test the protocol logic function of a single switching port of the controller.

6. The method for realizing the testability of the high-speed network switching chip according to claim 3, wherein, Detect and process the abnormal information of the high-speed network switching chip under test using the chip abnormal test data, including: Perform abnormal detection on the internal abnormal states of the high-speed network switching chip under test. The internal abnormal states include: clock abnormal state, reset abnormal state, initialization abnormal state, physical media attachment layer abnormal state, port physical layer abnormal state, physical coding layer abnormal state, controller abnormal state, routing abnormal state, configuration path abnormal state, message switching abnormal state, and storage abnormal state. Record the abnormal detection results using the abnormal detection register and log, and report them to the off-chip processor by priority according to the abnormal classification.

7. The method for realizing the testability of the high-speed network switching chip according to claim 3, wherein Monitor the internal component states of the high-speed network switching chip under test using the chip state test data, and also include: Record the operating states of the internal components of the high-speed network switching chip under test using the status register, and classify the operating states of the internal components of the chip into abnormal states, state machine states, storage states, and queue states according to the status information. Monitor the operating states of the internal components of the chip through the preset monitoring logic.

8. A testability implementation system for a high-speed network switching chip, characterized in that Include: a switching chip configuration module, a test data generation module, and a chip function test module. Among them, The switching chip configuration module is used to build a chip function test environment and configure the high-speed network switching chip under test. The test data generation module is used to generate function test data according to the test instructions. The function test data includes internal logic self-test data, chip abnormal test data, chip state test data, and chip traffic test data. The chip function test module is used to perform function tests and verifications on the high-speed network switching chip under test based on the chip function test environment and using the function test data.

9. An electronic device, characterized in that, Include: At least one processor, and a memory coupled to the at least one processor; Wherein, the memory stores a computer program, and the computer program can be executed by the at least one processor to implement the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, A computer program is stored in the computer-readable storage medium, and when the computer program is executed, it can implement the method according to any one of claims 1 to 7.

Images