Display panel motherboard, display panel manufacturing method and display device

Abstract

This disclosure provides a display panel motherboard, a method for fabricating a display panel, and a display device. The display panel motherboard includes a substrate, at least one test terminal, and at least one test line. The substrate is divided into a panel area and a first dicable area located around the panel area. The panel area includes a second dicable area and multiple sub-panel areas, each separated by the second dicable area. At least one test terminal is located on the substrate and in the first dicable area around the panel area, exposed away from the substrate surface to allow connection to an external test signal. At least one test line is located on the substrate, extending from the second dicable area to the first dicable area. One end of the test line is connected to a corresponding sub-panel area, and the other end extends into the first dicable area and connects to the test terminal. In this display panel motherboard, the test terminal exposed on the substrate allows for monitoring of the optical parameters of the light-emitting device during the vapor deposition process.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically, to a display panel motherboard, a method for preparing a display panel, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) are organic thin-film electroluminescent devices. They have attracted significant attention and are widely used in electronic display products due to their advantages such as simple fabrication process, low cost, low power consumption, high brightness, wide viewing angle, high contrast, and the ability to achieve flexible displays. The PPI (pixel density) of a display panel can be increased by setting an isolation structure within the panel. For details on the composition and fabrication of the isolation structure (also called a partition structure or isolation structure), please refer to patents CN118251982A, 202410864269.8, PCT / CN2024 / 098407, PCT / CN2024 / 102783, PCT / CN2024 / 098217, and PCT / CN2024 / 09. The relevant explanations in 9419, PCT / CN2024 / 099072, CN117979755A, CN117998900A, CN117062489A, CN117580403A, CN116583155A, CN116669477A, ​​CN117396039A, CN116669480A, CN116600606A, and CN117500332A will not be repeated here.

[0003] However, in the current manufacturing process of display products, it is impossible to monitor the optical parameters of the product during the vapor deposition process. Summary of the Invention

[0004] The first aspect of this disclosure provides a display panel motherboard, a method for manufacturing a display panel, and a display device. The display panel motherboard includes a substrate, at least one test terminal, and at least one test line. The substrate is divided into a panel area and a first dicable area located around the panel area. The panel area includes a second dicable area and a plurality of sub-panel areas, which are separated by the second dicable area. At least one test terminal is located on the substrate and in the first dicable area around the panel area. The test terminal is exposed away from the surface of the substrate so that it can be connected to an external test signal. At least one test line is located on the substrate, extending from the second dicable area to the first dicable area. One end of the test line is connected to a corresponding sub-panel area, and the other end of the test line extends to the first dicable area and is connected to the test terminal.

[0005] In the above scheme, by connecting the test terminals exposed on the substrate to an external test signal, the optical parameters of the display panel motherboard can be monitored during the evaporation process.

[0006] In one specific embodiment of the first aspect of this disclosure, multiple test terminals and multiple test lines are provided. The sub-board area is divided into a display area and a bonding area located on at least one side of the display area. The display panel motherboard also includes multiple isolation structures and multiple light-emitting devices. The multiple isolation structures are located on the substrate and at least partially located in the display area. The isolation structures enclose and form multiple isolation openings located in the display area. At least a portion of the light-emitting devices are located in the isolation openings. The film layer of the light-emitting devices at least covers the panel area of ​​the display panel motherboard.

[0007] In the above scheme, the light-emitting device can be formed by full-area evaporation based on the isolation structure, without the need for a mask, thereby reducing the size between the light-emitting devices and achieving a higher pixel density.

[0008] In one specific embodiment of the first aspect of this disclosure, a plurality of light-emitting devices include at least a first light-emitting device and a second light-emitting device that emit light of different colors, a second light-emitting device is confined within a partial isolation opening, and the first light-emitting device and the second light-emitting device are confined within the remaining partial isolation opening, wherein the second light-emitting device is located on the side of the first light-emitting device away from the substrate, wherein at least the film layer of the light-emitting device covering the panel area is the same as the film layer corresponding to the second light-emitting device.

[0009] In one specific embodiment of the first aspect of this disclosure, the display panel motherboard further includes an initial first encapsulation layer located on the side of the isolation structure away from the substrate. The initial first encapsulation layer includes a plurality of encapsulation units and an encapsulation material film layer. The orthographic projection of the encapsulation units on the substrate covers the orthographic projection of a light-emitting device of an emitted light color on the substrate. The encapsulation material film layer covers the side of the encapsulation units away from the substrate, and the orthographic projection of the encapsulation material film layer on the substrate at least covers the panel area.

[0010] In one specific embodiment of the first aspect of this disclosure, the test terminal and the light-emitting device are located on opposite sides of the substrate, the orthographic projection of the film layer corresponding to the light-emitting device on the substrate is outside the orthographic projection of the test terminal on the substrate; and the orthographic projection of the encapsulation material film layer on the substrate is outside the orthographic projection of the portion of the test line in the first slicable area on the substrate, and the orthographic projection of the encapsulation material film layer on the substrate is outside the orthographic projection of the test terminal on the substrate.

[0011] In one specific embodiment of the first aspect of this disclosure, the test terminal and the light-emitting device are located on opposite sides of the substrate, and the orthographic projection of the film layer corresponding to the light-emitting device on the substrate covers the entire orthographic projection of the test terminal on the substrate; and the orthographic projection of the encapsulation material film layer on the substrate covers the orthographic projections of the test terminal and the test line on the substrate.

[0012] In one specific embodiment of the first aspect of this disclosure, the test line includes at least two conductive layers.

[0013] In one specific embodiment of the first aspect of this disclosure, the display panel motherboard further includes thin-film transistors, a first planarization layer, a first signal line, a second signal line, and a second planarization layer sequentially stacked on a substrate, wherein the second planarization layer is located on the side of the light-emitting device closer to the substrate. The test line includes a first sub-test line located on the substrate and a second sub-test line located on the side of the first sub-test line away from the substrate; the first sub-test line is on the same layer and made of the same material as the first signal line, and the second sub-test line is on the same layer and made of the same material as the second signal line; and / or, the test terminal is located on the same side of the substrate as the light-emitting device, the orthographic projection of the second planarization layer on the substrate is outside the orthographic projection of the test terminal on the substrate, and the test terminal includes a first layer sub-test terminal and a second layer test terminal; the first layer test terminal is on the same layer and made of the same material as the first signal line, and the second layer test terminal is on the same layer and made of the same material as the second signal line.

[0014] In one specific embodiment of the first aspect of this disclosure, the isolation structure includes a support portion and a crown portion, the support portion being located between the crown portion and the substrate, and the orthographic projection of the surface of the support portion away from the substrate onto the substrate being located within the orthographic projection of the crown portion onto the substrate.

[0015] In one specific embodiment of the first aspect of this disclosure, the isolation structure further includes a bottom located between the support and the substrate, wherein the orthographic projection of the support on the substrate is located within the orthographic projection of the bottom on the substrate.

[0016] A second aspect of this disclosure provides a method for fabricating a display panel, the method comprising: providing a substrate, the substrate being divided into a panel area and a first dicable area located around the panel area, the panel area including a second dicable area and a plurality of sub-panel areas, each sub-panel area being separated by the second dicable area; forming at least one test terminal in the first dicable area of ​​the substrate, the test terminal being exposed away from the surface of the substrate so as to be connected to an external test signal; forming at least one test line on the substrate, the test line extending from the second dicable area to the first dicable area, one end of the test line being connected to a corresponding display panel, and the other end of the test line extending to the first dicable area and connected to the test terminal; cutting off the first dicable area and the second dicable area of ​​the display panel motherboard to obtain a plurality of display panels.

[0017] In the above scheme, during the process of manufacturing the display panel using this display panel manufacturing method, the optical parameters of the light-emitting devices after the entire surface is vapor-deposited are monitored by using test terminals exposed on the substrate. This allows for timely detection of problems and improvement of product quality. In addition, the test terminals are located in the first severable area and can be removed later without affecting the structure of the display panel.

[0018] In one specific embodiment of the second aspect of this disclosure, the sub-board area is divided into a display area and a bonding area located on at least one side of the display area. The fabrication method further includes: forming a plurality of isolation structures on the vapor deposition side of the substrate before cutting the display panel mother board, at least a portion of the isolation structures being located in the display area, and the isolation structures enclosing a plurality of isolation openings located in the display area; forming a plurality of light-emitting devices, at least a portion of the light-emitting devices being located in the isolation openings; forming a plurality of light-emitting devices includes: forming a plurality of first electrodes spaced apart from each other in the display area, at least a portion of the first electrodes being located within the isolation openings; fabricating a light-emitting functional layer and a second electrode located in the isolation openings based on the isolation structures, wherein the first electrode, the light-emitting functional layer, and the second electrode stacked on each other in each isolation opening constitute a light-emitting device.

[0019] In the above scheme, the light-emitting devices after the entire surface is vapor-deposited are separated by an isolation structure, which avoids the need to use a mask to prepare each light-emitting device individually and does not require consideration of the alignment accuracy during vapor deposition. Therefore, the gap between the light-emitting devices can be designed to be smaller, which is beneficial to improving the pixel density of the prepared display panel.

[0020] In one specific embodiment of the second aspect of this disclosure, fabricating a light-emitting functional layer and a second electrode located in an isolation opening based on an isolation structure includes: depositing a light-emitting material thin film and a first conductive material thin film, the light-emitting material thin film and the first conductive material thin film covering the isolation structure and the isolation opening, wherein the portions of the light-emitting material thin film and the first conductive material thin film located in the isolation opening respectively form the light-emitting functional layer and the second electrode; depositing an encapsulation material film layer to cover the light-emitting device; testing the formed light-emitting device based on at least one test terminal exposed on the substrate; forming a first photoresist layer on the encapsulation material film layer, and performing a patterning process on the first photoresist layer to form a first photoresist pattern, the first photoresist pattern covering a portion of the isolation opening; etching the encapsulation material film layer, the light-emitting material thin film and the first conductive material thin film based on the first photoresist pattern, wherein the remaining portion of the encapsulation material film layer forms an encapsulation unit, and the light-emitting functional layer and the second electrode not covered by the encapsulation unit are etched; repeating the above process to form the light-emitting device and the encapsulation unit at the isolation opening where no light-emitting device is formed, all the encapsulation units constituting a first encapsulation layer.

[0021] In one specific embodiment of the second aspect of this disclosure, in forming at least one test terminal in a first dicable region of a substrate, the at least one test terminal is formed on the vapor deposition side of the substrate, and the test terminal and the light-emitting device are located on the same side of the substrate. In depositing a light-emitting material film and a first conductive material film, the first dicable region is shielded so that the orthographic projection of the light-emitting material film and the first conductive material film on the substrate is located outside the first dicable region, thereby exposing the test terminal. In depositing an encapsulation material film layer to cover the light-emitting device, the first dicable region is shielded so that the orthographic projection of the encapsulation material film layer on the substrate is located outside the first dicable region, thereby exposing the test terminal.

[0022] In one specific embodiment of the second aspect of this disclosure, the fabrication method further includes: before forming a plurality of light-emitting devices, sequentially forming a thin-film transistor and a first planarization layer on the vapor deposition side of a substrate, wherein the thin-film transistor is located at least in the display area and the first planarization layer covers at least the panel area; depositing a second conductive material thin film layer on the substrate on which the first planarization layer is formed; forming a second photoresist layer on the second conductive material thin film layer and performing a patterning process on the second photoresist layer to form a second photoresist pattern, wherein the second photoresist pattern covers a portion of the display area; etching the second conductive material thin film layer based on the second photoresist pattern, wherein the remaining portion of the second conductive material thin film layer in the display area forms a first signal line; depositing a third conductive material thin film layer on the substrate on which the second conductive material thin film layer is formed; forming a third photoresist layer on the third conductive material thin film layer and performing a patterning process on the third photoresist layer to form a third photoresist pattern, wherein the third photoresist pattern covers a portion of the display area; etching the third conductive material thin film layer based on the third photoresist pattern, wherein the remaining portion of the third conductive material thin film layer in the display area forms a second signal line.

[0023] In one specific embodiment of the second aspect of this disclosure, in forming a second photoresist layer on a second conductive material thin film layer, the second photoresist pattern further covers a portion of the second dicable region and a portion of the first dicable region; in etching the second conductive material thin film layer based on the second photoresist pattern, the remaining portion of the second conductive material thin film layer in the second dicable region and the first dicable region forms a first sub-test line; in forming a third photoresist layer on a third conductive material thin film layer, the third photoresist pattern further covers a portion of the second dicable region and a portion of the first dicable region; in etching the third conductive material thin film layer based on the third photoresist pattern, the remaining portion of the third conductive material thin film layer in the second dicable region and the first dicable region forms a second sub-test line, and the first sub-test line and the second sub-test line constitute a test line; and / or, the remaining portion of the second conductive material thin film layer in the first dicable region further forms a first layer sub-test terminal, and the remaining portion of the third conductive material thin film layer in the first dicable region further forms a second layer sub-test terminal, and the first layer sub-test terminal and the second layer sub-test terminal constitute a test terminal.

[0024] In one specific embodiment of the second aspect of this disclosure, in forming at least one test terminal in the first dicable region of the substrate, the at least one test terminal is formed on the non-evaporated side of the substrate, and the test terminal and the light-emitting device are located on different sides of the substrate; in depositing a light-emitting material film and a first conductive material film, the orthogonal projection of the light-emitting material film and the first conductive material film on the substrate covers the panel region and the first dicable region of the substrate; in depositing an encapsulation material film layer to cover the light-emitting device, the orthogonal projection of the encapsulation material film layer on the substrate covers the panel region and the first dicable region of the substrate.

[0025] In one specific embodiment of the second aspect of this disclosure, the fabrication method further includes: before forming a plurality of light-emitting devices, sequentially forming a thin-film transistor and a first planarization layer on a substrate by vapor deposition, wherein the thin-film transistor is at least located in the display area, and the first planarization layer covers the panel area and the first dicable area; forming vias on the substrate, wherein the vias expose a portion of the surface of the test terminal near the substrate; depositing a second conductive material thin film layer on the substrate where the first planarization layer is formed, wherein the second conductive material thin film layer fills the vias; forming a second photoresist layer on the second conductive material thin film layer, and performing a patterning process on the second photoresist layer to form a second photoresist pattern. A photoresist pattern covers a portion of the display area; a second conductive material thin film layer is etched based on the second photoresist pattern, wherein the remaining portion of the second conductive material thin film layer in the display area forms a first signal line; a third conductive material thin film layer is deposited on the substrate on which the second conductive material thin film layer is formed; a third photoresist layer is formed on the third conductive material thin film layer, and a patterning process is performed on the third photoresist layer to form a third photoresist pattern, the third photoresist pattern covering a portion of the display area; the third conductive material thin film layer is etched based on the third photoresist pattern, wherein the remaining portion of the third conductive material thin film layer in the display area forms a second signal line.

[0026] In one specific embodiment of the second aspect of this disclosure, in forming a second photoresist layer on a second conductive material thin film layer, the second photoresist pattern further covers a portion of the second dicable region and a portion of the first dicable region, and the orthographic projection of the second photoresist pattern on the substrate overlaps with the orthographic projection of the test terminal on the substrate; the second conductive material thin film layer is etched based on the second photoresist pattern, and the remaining portion of the second conductive material thin film layer in the second dicable region and the first dicable region forms a first sub-test line; in forming a third photoresist layer on a third conductive material thin film layer, the third photoresist pattern further covers a portion of the second dicable region and a portion of the first dicable region, and the orthographic projection of the third photoresist pattern on the substrate overlaps with the orthographic projection of the test terminal on the substrate; the third conductive material thin film layer is etched based on the third photoresist pattern, and the remaining portion of the third conductive material thin film layer in the second dicable region and the first dicable region forms a second sub-test line, and the first sub-test line and the second sub-test line constitute a test line.

[0027] A third aspect of this disclosure provides a display device comprising a display panel obtained by the preparation method of any one of the second aspects described above. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the planar structure of a display panel motherboard provided in one embodiment of the present disclosure.

[0029] Figure 2 for Figure 1 The diagram shows a planar structural diagram of the sub-board area of ​​the display panel motherboard under one design.

[0030] Figure 3 for Figure 2 The diagram shows a cross-sectional view of the sub-board area of ​​the display panel motherboard along M1-N1 under one design.

[0031] Figure 4 for Figure 1 The diagram shows a planar structure of the display panel motherboard under one design.

[0032] Figure 5 for Figure 4 The diagram shows a cross-sectional view of the display panel motherboard along M2-N2 in one design.

[0033] Figure 6 for Figure 1 The diagram shows a planar structure of the display panel motherboard under one design.

[0034] Figure 7 for Figure 6 The diagram shows a cross-sectional view of the display panel motherboard along the M3-N3 line in one design.

[0035] Figure 8 This is a flowchart illustrating a method for manufacturing a display panel according to an embodiment of the present disclosure.

[0036] Figure 9 A flowchart illustrating another method for manufacturing a display panel according to an embodiment of this disclosure.

[0037] Figure 10 This is a partial flowchart of a method for manufacturing a display panel according to an embodiment of the present disclosure.

[0038] Figure 11 This is a partial flowchart of a method for manufacturing a display panel according to an embodiment of the present disclosure.

[0039] Figure 12 This is a flowchart illustrating a method for manufacturing a display panel according to an embodiment of the present disclosure.

[0040] Figure 13A flowchart illustrating another method for manufacturing a display panel according to an embodiment of this disclosure.

[0041] Figure 14 This is a cross-sectional schematic diagram of a display panel design provided in an embodiment of this disclosure.

[0042] Explanation of reference numerals in the attached figures:

[0043] 10-Display panel motherboard; 100-Substrate; 101-Panel area; 101a-Second dicable area; 101b-Sub-board area; 101c-Display area; 101d-Bonding area; 102-First dicable area;

[0044] 200 - Test terminal; 200a - First test terminal; 200b - Second test terminal; 210 - First layer sub-test terminal; 220 - Second layer sub-test terminal;

[0045] 300 - Test lead; 310 - First sub-test lead; 320 - Second sub-test lead; V1 - Via;

[0046] 400 - Isolation structure; 401 - Isolation opening; 410 - Support; 420 - Crown; 430 - Bottom;

[0047] 500 - Light-emitting device; 500a - First light-emitting device; 500b - Second light-emitting device; 500c - Third light-emitting device; 510 - First electrode; 520 - Light-emitting functional layer; 530 - Second electrode;

[0048] 600 - Packaging structure; 600a - Initial first packaging layer; 610 - First packaging layer; 610a - Packaging material film layer; 611 - Packaging unit; 620 - Second packaging layer; 630 - Third packaging layer;

[0049] 700 - Connecting terminal;

[0050] TFT - Thin Film Transistor; 800a - First Planarization Layer; 800b - Second Planarization Layer; 900a - First Signal Line; 900b - Second Signal Line. Detailed Implementation

[0051] The technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this specification, and not all embodiments. Based on the embodiments in this specification, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this specification.

[0052] In this disclosure, by setting an isolation structure at the gap between the light-emitting devices, the functional film layers of adjacent light-emitting devices are separated. Thus, in the evaporation process of the functional film layers, it is only necessary to perform evaporation on the entire display panel, without the need to prepare the functional film layer of each light-emitting device separately using a mask. This process does not need to consider the alignment accuracy problem during evaporation, thereby allowing the gap between the light-emitting devices to be designed to be smaller, thereby increasing the PPI.

[0053] In traditional display panel manufacturing processes, optical parameter monitoring is performed on individual light-emitting devices. This means that in the manufacturing process of the display panel disclosed herein, the film layer formed after the entire surface is vapor-deposited needs to be etched to form independent encapsulation units, and then the optical parameters of the corresponding light-emitting devices in each encapsulation unit need to be monitored. Therefore, it is not possible to monitor the optical parameters of the entire film layer corresponding to the structure of the light-emitting devices (e.g., the light-emitting functional layer and the second electrode) during the entire surface vapor deposition process. Without timely monitoring, problems cannot be detected in a timely manner. For example, if a light-emitting device with a certain emitted light color has low luminous efficiency or large color deviation under certain signal parameters, the problem cannot be improved by adjusting the structure, material, or process parameters of the light-emitting device, which is detrimental to improving the quality of the display panel.

[0054] In view of the above, at least one embodiment of this disclosure provides a display panel motherboard, a method for manufacturing a display panel, and a display device to at least solve the above-mentioned technical problems. The display panel motherboard includes a substrate, at least one test terminal, and at least one test line. The substrate is divided into a panel area and a first dicable area located around the panel area. The panel area includes a second dicable area and a plurality of sub-panel areas, each sub-panel area being separated by the second dicable area. At least one test terminal is located on the substrate and in the first dicable area around the panel area. The test terminal is exposed away from the surface of the substrate so that it can be connected to an external test signal. At least one test line is located on the substrate, extending from the second dicable area to the first dicable area. One end of the test line is connected to the corresponding sub-panel area, and the other end of the test line extends to the first dicable area and is connected to the test terminal. Thus, by using the test terminals exposed on the substrate, optical parameters of the entire film layer (including the light-emitting functional layer of the light-emitting device and the second electrode) corresponding to a light-emitting device of a certain color emitted in the sub-board area of ​​the display panel motherboard can be monitored, i.e., optical parameter monitoring is performed during the evaporation process. Furthermore, the test terminals are located in the first slicable area of ​​the display panel motherboard, which does not affect the entire evaporation process on the panel area of ​​the display panel motherboard. This improves the quality of the display panel formed from the display panel motherboard without affecting production efficiency.

[0055] The structure of the display panel motherboard according to at least one embodiment of the present disclosure will now be described in detail with reference to the accompanying drawings. Furthermore, in these drawings, a spatial rectangular coordinate system is established with the substrate as a reference to more intuitively present the positional relationships of the relevant structures in the display panel motherboard. In this spatial rectangular coordinate system, the X-axis and Y-axis are parallel to the surface of the substrate, and the Z-axis is perpendicular to the surface of the substrate.

[0056] In one embodiment of this disclosure, such as Figure 1 As shown, the display panel motherboard 10 includes a substrate 100, at least one test terminal 200, and at least one test line 300.

[0057] The substrate 100 is divided into a panel area 101 and a first dicable area 102 located around the panel area 101. The panel area 101 includes a second dicable area 101a and multiple sub-panel areas 101b, with each sub-panel area 101b separated by the second dicable area 101a. The multiple sub-panel areas 101b correspond to multiple display panels, and multiple display panels are formed on the same display panel motherboard 10. That is, multiple display panels are processed and prepared based on the same display panel motherboard 10. This allows for better control of process parameters, reduces performance differences caused by different batches, different equipment, etc., maintains the stability of display panel performance, and improves production efficiency.

[0058] At least one test terminal 200, or multiple test terminals 200, are disposed on the substrate 100. The test terminals 200 are located in the first dicable area 102 surrounding the panel area 101. The test terminals 200 are exposed away from the surface of the substrate 100 so that they can be connected to an external test signal. The fact that the test terminals 200 are exposed away from the surface of the substrate 100 means that they will not be covered by the film layers formed during the vapor deposition process, such as the film layers corresponding to the light-emitting device 500, the first encapsulation layer 610, the second encapsulation layer 620, and the third encapsulation layer 630 mentioned later. Thus, the exposed test terminals 200 are connected to an external test signal to monitor the optical parameters of the display panel motherboard 10 during the vapor deposition process.

[0059] For example, the test terminal 200 is often configured to be connected to the input or output terminal of the sub-board area 101b (corresponding to the physical structure display panel) in the mother board 10 of the display panel. For example, the test terminal 200 is connected to the electrode of the light-emitting device 500 mentioned later on the sub-board area 101b. This makes it convenient to monitor the optical performance of the light-emitting device 500 after the test terminal 200 is connected to an external test signal.

[0060] At least one test line 300, or multiple test lines 300, are located on the substrate 100. The test line 300 extends from the second dicable region 101a to the first dicable region 102. One end of the test line 300 is connected to the corresponding sub-board region 101b, and the other end of the test line 300 extends to the first dicable region 102 and is connected to the test terminal 200. The test line 300 is used to connect the test terminal 200 to a preset position on the circuit wire corresponding to the electrode of the light-emitting device 500 in the corresponding sub-board region 101b.

[0061] This disclosure does not specifically describe the case where the display panel motherboard 10 includes a test terminal 200 and a test line 300. For example, a test line 300 can be connected to a test terminal 200 as a summary detection line to monitor the optical parameters of all the sub-board areas 101b of the display panel motherboard 10. This can be designed according to actual needs and will not be elaborated here.

[0062] In one embodiment of this disclosure, such as Figure 1 , Figure 4 and Figure 6 As shown, there are multiple test terminals 200 and multiple test leads 300. Figure 2 and Figure 3 As shown, the sub-board area 101b is divided into a display area 101c and a bonding area 101d located on at least one side of the display area 101c. The display panel motherboard 10 also includes a plurality of isolation structures 400 and a plurality of light-emitting devices 500. The plurality of isolation structures 400 are located on the substrate 100 and are at least partially located in the display area 101c. The isolation structures 400 enclose a plurality of isolation openings 401 located in the display area 101c. At least a portion of the light-emitting devices 500 are located in the isolation openings 401. The film layer of the light-emitting devices 500 at least covers the panel area 101 of the display panel motherboard 10.

[0063] In this way, multiple test lines 300 correspond to different sub-board areas 101b forming display panel connections, used to simultaneously monitor the optical parameters of different display panels, ensuring test consistency and facilitating unified evaluation and control of product quality. Furthermore, compared to testing multiple connected display panels together, this solution makes it easier to quickly locate the specific area of ​​failure when testing problems occur, aiding in timely repair or replacement and reducing production and time costs. In addition, this solution can simultaneously acquire test data from multiple display panels, facilitating parallel analysis and comparison, providing a more comprehensive understanding of the product's performance distribution, and offering richer data support for product optimization and improvement. Meanwhile, the functional film layers of adjacent light-emitting devices 500 are separated by the isolation structure 400. Thus, in the evaporation process of the functional film layers, it is only necessary to perform evaporation on the entire display panel, without the need to prepare the functional film layer of each light-emitting device 500 separately with the help of a mask. This process does not need to consider the alignment accuracy problem during evaporation, so the gap between the light-emitting devices 500 can be designed to be smaller, thereby increasing the PPI (Pixels Per Inch) of the display panel corresponding to the display panel motherboard 10.

[0064] In at least one embodiment of this disclosure, the light-emitting device 500 includes a first electrode 510, a light-emitting functional layer 520, and a second electrode 530 sequentially stacked on a substrate 100, and at least a portion of the light-emitting functional layer 520 of the light-emitting device 500 is located in a corresponding isolation opening 401.

[0065] This embodiment does not specifically limit the light-emitting functional layer 520 of the light-emitting device 500 in the display panel motherboard 10. For example, the light-emitting functional layer 520 may also include a first functional layer, a light-emitting layer, and a second functional layer, which are sequentially stacked on the first electrode 510. The first functional layer may include a hole injection layer, a hole transport layer, an electron blocking layer, etc. The second functional layer may include an electron injection layer, an electron transport layer, a hole blocking layer, etc. It should be noted that since charge carriers (holes and electrons) mainly crosstalk between adjacent light-emitting devices 500 through the first functional layer, the isolation structure 400 needs to ensure that the first functional layers of each light-emitting device 500 are electrically disconnected from each other.

[0066] In at least one embodiment of this disclosure, the film layers corresponding to the first electrode 510, the light-emitting functional layer 520, and the second electrode 530 respectively cover at least the panel area 101 of the display panel motherboard 10.

[0067] For example, such as Figure 4 and Figure 5As shown, after the film layers corresponding to the first electrode 510, the light-emitting functional layer 520, and the second electrode 530 are formed, they cover the panel area 101 of the display panel motherboard 10, but do not cover the first dicable area 102. At this time, the test terminal 200 is located on the same side as the light-emitting device 500 on the vapor deposition side of the substrate 100. The surface of the test terminal 200 away from the substrate 100 is not covered by the film layers corresponding to the first electrode 510, the light-emitting functional layer 520, and the second electrode 530, so that the surface of the test terminal 200 on the substrate 100 away from the substrate 100 is exposed to connect to the external test signal.

[0068] For example, such as Figure 6 and Figure 7 As shown, after the film layers corresponding to the first electrode 510, the light-emitting functional layer 520, and the second electrode 530 are formed, they cover the panel area 101 and the first dicable area 102 of the display panel motherboard 10. The test terminal 200 is located on the non-evaporation side of the substrate 100 and in the first dicable area 102. That is, the test terminal 200 and the light-emitting device 500 are located on different sides of the substrate 100. Therefore, although the film layers corresponding to the first electrode 510, the light-emitting functional layer 520, and the second electrode 530 cover the panel area 101 and the first dicable area 102 of the substrate 100 on the evaporation side of the substrate 100, they do not cover the test terminal 200 on the non-evaporation side of the substrate 100, thereby exposing the test terminal 200 away from the surface of the substrate 100 to connect with external test signals.

[0069] In at least one embodiment, such as Figure 3 As shown, the second electrode 530 is electrically connected to the isolation structure 400. That is, the second electrodes 530 of multiple light-emitting devices 500 are connected to each other through the isolation structure 400 to serve as a common electrode, thereby alleviating the voltage drop problem generated when driving the second electrode 530.

[0070] Based on the above embodiments, this disclosure also introduces different structural designs of the display panel motherboard 10 corresponding to different emitted light colors of the light-emitting device 500, as detailed below.

[0071] In one embodiment of this disclosure, a plurality of light-emitting devices 500 include at least a first light-emitting device 500a and a second light-emitting device 500b that emit light of different colors. The second light-emitting device 500b is confined within a partial isolation opening 401, and the first light-emitting device 500a and the second light-emitting device 500b are confined within the remaining portion of the isolation opening 401. The second light-emitting device 500b is located on the side of the first light-emitting device 500a away from the substrate 100. The film layer of at least the light-emitting device 500 covering the panel area 101 is the same as the film layer corresponding to the second light-emitting device 500b.

[0072] In at least one disclosed embodiment, a plurality of light-emitting devices 500 include a first light-emitting device 500a, a second light-emitting device 500b, and a third light-emitting device 500c that emit light of different colors. The first light-emitting device 500a and the third light-emitting device 500c are confined in a partial isolation opening 401. The third light-emitting device 500c is located on the side of the first light-emitting device 500a away from the substrate 100. The second light-emitting device 500b and the third light-emitting device 500c are confined in a partial isolation opening 401. The third light-emitting device 500c is located on the side of the second light-emitting device 500b away from the substrate 100. The remaining portion of the isolation opening 401 confines the third light-emitting device 500c. The film layer of at least the light-emitting device 500 covering the panel area 101 is the same as the film layer corresponding to the third light-emitting device 500c.

[0073] For example, such as Figure 1 , Figure 2 and Figure 3 As shown, the planar area of ​​sub-board area 101b can be divided into display area 101c and non-display area located on at least one side of display area 101c. Sub-pixels (also called sub-pixels, etc.) can be arranged in display area 101c. The physical structure of the sub-pixel can be the light-emitting device 500 in the following embodiment. Adjacent sub-pixels with different emitted light colors constitute a pixel (also called a pixel unit, large pixel, etc.). The arrangement density of the pixel in display area 101c represents the pixel density.

[0074] The light-emitting devices 500 are classified into a first light-emitting device 500a, a second light-emitting device 500b, and a third light-emitting device 500c that emit light of different colors. During the manufacturing process, the first light-emitting device 500a, the second light-emitting device 500b, and the third light-emitting device 500c are manufactured sequentially. The structure of the display panel motherboard 10 includes a substrate 100, an isolation structure 400, the first light-emitting device 500a, the second light-emitting device 500b, and the third light-emitting device 500c. The first light-emitting device 500a, the second light-emitting device 500b, and the third light-emitting device 500c each include a first electrode 510, a light-emitting functional layer 520, and a second electrode 530. An isolation structure 400 is located at least on the display area 101c on the sub-panel area 101b of the panel area 101 of the substrate 100. Multiple isolation structures 400 form isolation openings 401, which are used to limit the light-emitting functional layer 520 and the second electrode 530 corresponding to the first light-emitting device 500a, the second light-emitting device 500b, and the third light-emitting device 500c.

[0075] Specifically, the first electrodes 510 corresponding to the first light-emitting device 500a, the second light-emitting device 500b, and the third light-emitting device 500c are on the same layer. For example, the first electrodes 510 corresponding to the first light-emitting device 500a, the second light-emitting device 500b, and the third light-emitting device 500c are formed using the same process. Based on the sequential formation of the first light-emitting device 500a, the second light-emitting device 500b, and the third light-emitting device 500c, the first electrode 510, the light-emitting functional layer 520, and the second electrode 530 corresponding to the first light-emitting device 500a, as well as the light-emitting functional layer 520 and the second electrode 530 of the second light-emitting device 500b located on the side of the first light-emitting device 500a away from the substrate 100, are confined within the partial isolation opening 401. The second light-emitting device 500b has a light-emitting functional layer 520 and a second electrode 530 on the side of the third light-emitting device 500c away from the substrate 100. The remaining isolation opening 401 contains the first electrode 510, the light-emitting functional layer 520 and the second electrode 530 corresponding to the third light-emitting device 500c. At the same time, in addition to covering the sub-board area 101b, the light-emitting functional layer 520 and the second electrode 530 corresponding to the third light-emitting device 500c also cover at least the second slicable area 101a. That is, the light-emitting functional layer 520 and the second electrode 530 corresponding to the third light-emitting device 500c at least cover the panel area 101.

[0076] Thus, by using the test terminals 200 exposed on the substrate 100, the optical performance of the functional film layers, such as the light-emitting functional layer 520 and the second electrode 530, corresponding to the first light-emitting device 500a, the second light-emitting device 500b, and the third light-emitting device 500c obtained after the whole-surface vapor deposition can be monitored. This allows for the effective monitoring of the performance of the display panel motherboard 10, timely detection of problems in the whole-surface vapor deposition process, and timely resolution and optimization of the process.

[0077] In at least one embodiment of this disclosure, the first light-emitting device 500a is a red light-emitting device, the second light-emitting device 500b is a blue light-emitting device, and the third light-emitting device 500c is a green light-emitting device.

[0078] Based on the above embodiments, in at least one embodiment of this disclosure, such as Figure 3As shown, the display panel motherboard 10 also includes an initial first encapsulation layer 600a. The initial first encapsulation layer 600a is located on the side of the isolation structure 400 away from the substrate 100. The initial first encapsulation layer 600a includes a plurality of encapsulation units 611 and an encapsulation material film layer 610a. The orthographic projection of the encapsulation unit 611 on the substrate 100 covers the orthographic projection of a light-emitting device 500 of an emitted light color on the substrate 100. The encapsulation material film layer 610a covers the side of the encapsulation unit 611 away from the substrate 100, and the orthographic projection of the encapsulation material film layer 610a on the substrate 100 at least covers the panel area 101.

[0079] For example, when fabricating the first light-emitting device 500a, a first light-emitting device 500a is formed in each isolation opening 401, and an encapsulation material film layer 610a is formed to cover all isolation openings 401. Then, the second electrode 530 and the light-emitting functional layer 520 of the first light-emitting device 500a in some isolation openings 401 (used in the final product to form the second light-emitting device 500b and the third light-emitting device 500c) are removed to form an encapsulation structure 600 with an independent structure. Based on this method, the second light-emitting device 500b and the third light-emitting device 500c are then fabricated sequentially. When there is no place to remove the film layer on the partial isolation opening 401 (forming the first light-emitting device 500a and the second light-emitting device 500b), the first light-emitting device 500a and the second light-emitting device 500b are respectively associated with the encapsulation unit 611, and the third light-emitting device 500c is covered with an encapsulation material film layer 610a on the side away from the substrate 100. The encapsulation material film layer 610a is located on the side of the encapsulation unit 611 away from the substrate 100 in the area of ​​the isolation opening 401 of the third light-emitting device 500c corresponding to the first light-emitting device 500a and the second light-emitting device 500b, and covers the encapsulation unit 611.

[0080] In at least one embodiment of this disclosure, the initial first encapsulation layer 600a is an inorganic film layer. The initial first encapsulation layer 600a, using an inorganic film layer, will later form an encapsulation unit 611 for the third light-emitting device 500c. This encapsulation unit 611, together with the encapsulation unit 611 corresponding to the first light-emitting device 500a and the encapsulation unit 611 corresponding to the second light-emitting device 500b, constitutes the first encapsulation layer 610. In other words, the first encapsulation layer 610 is an inorganic film layer. Therefore, the first encapsulation layer 610 not only has excellent barrier properties, effectively blocking moisture and oxygen and improving the encapsulation effect, but also has advantages such as good chemical stability and high thermal stability, effectively improving the protection effect on the light-emitting device 500, thereby increasing the lifespan of the light-emitting device 500.

[0081] Based on different display panel manufacturing processes (see the following embodiments for details), the structure of the display panel motherboard 10 has different design schemes, as detailed below.

[0082] In one embodiment of this disclosure, such as Figure 5 As shown, the test terminal 200 and the light-emitting device 500 are located on the same side of the substrate 100. The orthographic projection of the film layer corresponding to the light-emitting device 500 on the substrate 100 is outside the orthographic projection of the test terminal 200 on the substrate 100. The orthographic projection of the encapsulation material film layer 610a on the substrate 100 is outside the orthographic projection of the portion of the test line 300 in the first slicable area 102 on the substrate 100. The orthographic projection of the encapsulation material film layer 610a on the substrate 100 is outside the orthographic projection of the test terminal 200 on the substrate 100.

[0083] For example, such as Figure 5 As shown, the display panel motherboard 10 includes a substrate 100, multiple isolation structures 400, multiple light-emitting devices 500, multiple test lines 300, and multiple test terminals 200. The test terminals 200 are located on the same side of the substrate 100 relative to the light-emitting devices 500, the isolation structures 400, and the test lines 300, that is, all of the above structures are located on the vapor deposition side of the substrate 100. At least a portion of the multiple isolation structures 400 are located within the display area 101c of the sub-board area 101b of the substrate 100. The multiple light-emitting devices 500 are classified into multiple first light-emitting devices 500a, multiple second light-emitting devices 500b, and multiple third light-emitting devices 500c that emit light of different colors. Taking the sequential fabrication of the first light-emitting devices 500a, the second light-emitting devices 500b, and the third light-emitting devices 500c as an example, it can be seen that the orthographic projection of the film layer corresponding to the third light-emitting device 500c on the substrate 100 is located outside the orthographic projection of the test terminal 200 on the substrate 100 and outside the orthographic projection of the portion of the test line 300 in the first dicable area 102 on the substrate 100.

[0084] In the display area 101c, the isolation structure 400 encloses a plurality of isolation openings 401. Within some of the isolation openings 401, the first light-emitting device 500a, the encapsulation unit 611, and the light-emitting functional layer 520 and the second electrode 530 of the third light-emitting device 500c are sequentially positioned. Within some of the isolation openings 401, the second light-emitting device 500b, the encapsulation unit 611, and the light-emitting functional layer 520 and the second electrode 530 of the third light-emitting device 500c are sequentially positioned. The remaining isolation openings 401 contain only the third light-emitting device 500c. The display panel motherboard 10 also includes an encapsulation material film layer 610a. Layer 610a covers the panel area 101 of the display panel motherboard 10. Specifically, the orthographic projection of the encapsulation material film layer 610a on the substrate 100 is outside the orthographic projection of the test terminal 200 on the substrate 100 and outside the orthographic projection of the portion of the test line 300 in the first dicable area 102 on the substrate 100. This encapsulation material film layer 610a, along with the encapsulation units 611 corresponding to the first light-emitting device 500a and the second light-emitting device 500b, constitutes the initial first encapsulation layer 600a. The portion of the encapsulation material film layer 610a corresponding to the third light-emitting device 500c will subsequently form the encapsulation unit 611 corresponding to the third light-emitting unit. Thus, by exposing the test terminal 200 to the substrate 100, during the fabrication of the light-emitting device 500, after the entire surface is vapor-deposited, the test terminal 200 is used to externally connect test signals to monitor the optical parameters of the entire functional layer formed by the light-emitting device 500, such as the light-emitting functional layer 520 and the second electrode 530.

[0085] In another embodiment of this disclosure, such as Figure 7 As shown, the test terminal 200 and the light-emitting device 500 are located on opposite sides of the substrate 100. The orthographic projection of the film layer corresponding to the light-emitting device 500 on the substrate 100 covers the entire orthographic projection of the test terminal 200 on the substrate 100. The orthographic projection of the encapsulation material film layer 610a on the substrate 100 completely covers the orthographic projections of the test terminal 200 and the test line 300 on the substrate 100.

[0086] For example, such as Figure 7As shown, the display panel motherboard 10 includes a substrate 100, multiple isolation structures 400, multiple light-emitting devices 500, multiple test lines 300, and multiple test terminals 200. The test terminals 200 are located on different sides of the substrate 100, i.e., the non-evaporation side of the substrate 100, relative to the light-emitting devices 500 and the isolation structures 400. At least a portion of the multiple isolation structures 400 are located within the display area 101c of the sub-board area 101b of the substrate 100. The multiple light-emitting devices 500 are classified into multiple first light-emitting devices 500a, multiple second light-emitting devices 500b, and multiple third light-emitting devices 500c that emit light of different colors. Taking the sequential fabrication of the first light-emitting devices 500a, the second light-emitting devices 500b, and the third light-emitting devices 500c as an example, it can be seen that the film layer corresponding to the third light-emitting device 500c covers the panel area 101 and the first slicable area 102 of the substrate 100. That is, the orthogonal projection of the film layer corresponding to the third light-emitting device 500c, such as the light-emitting functional layer 520 and the second electrode 530 on the substrate 100 completely covers the orthogonal projection of the test terminal 200 on the substrate 100 and the orthogonal projection of the test line 300 on the substrate 100.

[0087] In the display area 101c, the isolation structure 400 encloses a plurality of isolation openings 401. Within some of the isolation openings 401, the first light-emitting device 500a, the encapsulation unit 611, and the light-emitting functional layer 520 and the second electrode 530 of the third light-emitting device 500c are sequentially positioned. Within some of the isolation openings 401, the second light-emitting device 500b, the encapsulation unit 611, and the light-emitting functional layer 520 and the second electrode 530 of the third light-emitting device 500c are sequentially positioned. The remaining isolation openings 401 contain only the third light-emitting device 500c. The display panel motherboard 10 also includes an encapsulation material film layer 610a. The encapsulation material film layer 610a covers the panel area 101 and the first dicable area 102 of the display panel motherboard 10. That is, the orthographic projection of the encapsulation material film layer 610a on the substrate 100 covers the orthographic projection of the test terminal 200 and the test line 300 on the substrate 100. This encapsulation material film layer 610a, together with the encapsulation units 611 corresponding to the first light-emitting device 500a and the second light-emitting device 500b, constitutes the initial first encapsulation layer 600a. Furthermore, the portion of the encapsulation material film layer 610a corresponding to the third light-emitting device 500c will subsequently form the encapsulation unit 611 corresponding to the third light-emitting unit. In this way, the test terminal 200 is exposed on the substrate 100, enabling the monitoring of optical parameters of the entire functional layer formed by the light-emitting device 500, such as the light-emitting functional layer 520 and the second electrode 530, after the entire surface is vapor-deposited during the fabrication process of the light-emitting device 500.

[0088] It should be noted that the structure of the display panel motherboard 10 provided in this disclosure is not limited to the structures shown in the examples and illustrations above. For example, gaps may be formed between the encapsulation units 611 corresponding to adjacent light-emitting devices 500, or they may overlap. For example, the first electrode 510 corresponding to the light-emitting device 500 may not be limited to being disposed in the display area 101c, but may also be disposed in the first dicable area 102 and / or the second dicable area 101a. For example, the display panel motherboard 10 may also include a pixel defining layer disposed on the substrate 100, which is not limited to being located in the display area 101c, but may also be disposed in the first dicable area 102 and / or the second dicable area 101a. Furthermore, the test terminals 200 and test lines 300 are not limited to the structures shown in the examples above; they may be single-layer structures or multi-layer structures, not limited to double-layer structures. They may also be prepared using different conductive material layers depending on the specific structure of the display panel motherboard 10. All of the above can be designed according to actual needs, and will not be elaborated here.

[0089] In at least one embodiment of this disclosure, multiple test lines 300 are respectively connected to corresponding test terminals 200 through different vias V1.

[0090] For example, multiple test leads 300 and multiple test terminals 200 are provided. Every two test leads 300 are electrically connected to the same test terminal 200. Specifically, each test lead 300 is electrically connected to the test terminal 200 through a via V1, meaning there is a one-to-one correspondence between via V1 and test lead 300. Furthermore, the structure and fabrication method of the via V1 can be designed according to actual needs and will not be elaborated upon here.

[0091] In one embodiment of this disclosure, such as Figure 2 As shown, the display panel motherboard 10 also includes a connection terminal 700 located in the bonding area 101d, and the test lines 300 include multiple lines, one end of each of the multiple test lines 300 being electrically connected to the connection terminal 700 of the corresponding daughterboard area 101b.

[0092] This disclosure does not limit the number, structure, or arrangement of the connection terminals 700. It only provides one implementation method, namely, using the connection terminals 700 on the bonding area 101d to achieve electrical connection with the test line 300, and finally realizing signal transmission between the connection terminals 700 and the test terminals 200.

[0093] In at least one embodiment of this disclosure, such as Figure 1As shown, sub-board areas 101b are arranged in an array on panel area 101. Multiple test lines 300 extend along a first direction, such as the X direction, and are arranged along a second direction, such as the Y direction. Each row of sub-board areas 101b is arranged along the first direction, such as the X direction. At least one test line 300 is provided corresponding to each row of sub-board areas 101b. At least one test terminal 200 is arranged at intervals in the second direction, such as the Y direction. The first direction and the second direction intersect, that is, the X direction and the Y direction intersect.

[0094] In at least one embodiment of this disclosure, each row of sub-board area 101b corresponds to two test lines 300 and two test terminals 200. Every two test terminals 200 form a group. Each group of test terminals 200 includes a first test terminal 200a and a second test terminal 200b. Each group of test terminals 200 is spaced apart in the second direction, i.e., the Y direction. The first test terminal 200a and the second test terminal 200b are electrically connected to different connection terminals 700 of the corresponding sub-board area 101b through different test lines 300.

[0095] For example, the first test terminal 200a is an input terminal, and its corresponding connection terminal 700 in the sub-board area 101b is a signal input terminal. The second test terminal 200b is an output terminal, and its corresponding connection terminal 700 in the sub-board area 101b is a signal output terminal. The testing equipment inputs various test signals to the display panel motherboard 10 through the input terminals. These test signals include, but are not limited to, image data signals, control signals, and clock signals. After receiving the test signals, the display panel motherboard 10 performs corresponding operations according to the requirements of the test signals and feeds back the processed signals to the testing equipment through the output terminals. These feedback signals include, but are not limited to, performance parameters of the display panel motherboard 10 such as brightness, color, and contrast, as well as information on the presence of defects such as dead pixels and bright pixels. The testing equipment analyzes and processes these feedback signals to evaluate the performance and quality of the display panel motherboard 10 and adjusts the production process accordingly. The selection of test signals and specific test methods can be chosen according to actual needs and will not be elaborated here.

[0096] In at least one embodiment of this disclosure, the spacing between test terminals 200 within each group is smaller than the spacing between test terminals 200 within each group.

[0097] In at least one embodiment of this disclosure, the test terminal 200 is located on the same side of the first cutable area 102 surrounding the panel area 101.

[0098] In at least one embodiment of this disclosure, the first direction and the second direction are perpendicular, for example, the first direction is the X direction and the second direction is the Y direction, and the X direction and the Y direction are perpendicular.

[0099] In one embodiment of this disclosure, the test line 300 includes at least two conductive layers.

[0100] In at least one embodiment of this disclosure, such as Figure 3 As shown, the display panel motherboard 10 also includes thin-film transistors (TFTs), a first planarization layer 800a, a first signal line 900a, a second signal line 900b, and a second planarization layer 800b, which are sequentially stacked on the substrate 100. The second planarization layer 800b is located on the side of the light-emitting device 500 closer to the substrate 100. The test line 300 includes a first sub-test line 310 located on the substrate 100 and a second sub-test line 320 located on the side of the first sub-test line 310 away from the substrate 100. The first sub-test line 310 is in the same layer and made of the same material as the first signal line 900a, and the second sub-test line 320 is in the same layer and made of the same material as the second signal line 900b.

[0101] In at least one embodiment of this disclosure, such as Figure 5 As shown, the test terminal 200 and the light-emitting device 500 are located on the same side of the substrate 100. The orthographic projection of the second planarization layer 800b on the substrate 100 is outside the orthographic projection of the test terminal 200 on the substrate 100. The test terminal 200 includes a first-layer sub-test terminal 210 and a second-layer sub-test terminal 220. The first-layer sub-test terminal 210 is on the same layer and made of the same material as the first signal line 900a, and the second-layer test terminal 220 is on the same layer and made of the same material as the second signal line 900b. Thus, by configuring the test terminal 200 with a structure comprising stacked layers, not only can the impedance of the test terminal 200 be reduced, and the attenuation during test signal transmission be decreased, thereby improving test accuracy, but the strength of the test terminal 200 can also be increased, reducing the risk of breakage.

[0102] In at least one embodiment of this disclosure, the first signal line 900a and the second signal line 900b are used to transmit power signals or data signals.

[0103] In at least one embodiment of this disclosure, an insulating layer is further included, which is located between the first signal line 900a and the second signal line 900b.

[0104] In one embodiment of this disclosure, such as Figure 3 As shown, the isolation structure 400 includes a support portion 410 and a crown portion 420. The support portion 410 is located between the crown portion 420 and the substrate 100. The orthographic projection of the surface of the support portion 410 away from the substrate 100 onto the substrate 100 lies within the orthographic projection of the crown portion 420 onto the substrate 100. Thus, the width of the crown portion 420 is greater than the width of the support portion 410, thereby improving the isolation effect of the isolation structure 400.

[0105] In at least one embodiment of this disclosure, the support portion 410 is a conductive structure, and the second electrode 530 is connected to the side surface of the support portion 410. The support portion 410 is designed without considering light transmission, thus allowing for a larger design thickness (greater than the second electrode 530). That is, the sheet resistance of the support portion 410 is less than the sheet resistance of the second electrode 530. In this design, the support portion 410 can be connected to the second electrode 530 of the light-emitting device 500 to achieve a common potential, thereby reducing the voltage drop across the second electrode 530.

[0106] In at least one embodiment of this disclosure, such as Figure 5 , Figure 7 As shown, the isolation structure 400 also includes a bottom 430, which is located between the support portion 410 and the substrate 100. The orthographic projection of the support portion 410 on the substrate 100 is located within the orthographic projection of the bottom 430 on the substrate 100.

[0107] In at least one embodiment of this disclosure, the bottom 430 is a conductive structure, and the second electrode 530 is electrically connected to the portion of the bottom 430's surface away from the substrate 100 that is not covered by the support portion 410. The second electrode 530 is more easily deposited on the surface area of ​​the bottom 430 away from the substrate 100 compared to the sidewall of the support portion 410, thereby reducing the impedance at the connection between the second electrode 530 and the isolation structure 400.

[0108] In at least one embodiment of this disclosure, the orthographic projection of the bottom 430 on the substrate 100 lies within the orthographic projection of the crown 420 on the substrate 100.

[0109] It should be noted that the structure of the display panel motherboard 10 in this embodiment is not limited to the above structure. For example, the display motherboard may also include a pixel defining layer, which is located at least in the display area 101c, between the isolation structure 400 and the substrate 100. The pixel defining layer includes pixel openings corresponding to the isolation openings 401, and at least a portion of the light-emitting device 500 is located in the pixel openings. For example, the pixel defining layer may be an inorganic film layer. In the process of fabricating the light-emitting device 500 based on the isolation structure 400, the pixel defining layer does not need to be thick enough to accommodate the light-emitting device 500, which is beneficial for the thinner and lighter design of the display panel. In addition, as an inorganic film layer, the pixel defining layer can have a high bonding strength with the isolation structure 400 and the first electrode 510 to reduce the risk of the isolation structure 400 and the first electrode 510 falling off. Furthermore, the inorganic film layer has high density and good barrier effect against water and gas to encapsulate and protect the first overlapping portion of the overlapping terminal. In addition, the display panel motherboard 10 may also include other structures, which can be designed according to actual needs, and will not be described in detail here.

[0110] This disclosure also provides a method for manufacturing a display panel, the method comprising: providing a substrate, the substrate being divided into a panel area and a first dicable area located around the panel area, the panel area including a second dicable area and a plurality of sub-panel areas, each sub-panel area being separated by the second dicable area; forming at least one test terminal in the first dicable area of ​​the substrate, the test terminal being exposed away from the surface of the substrate so as to connect the test terminal to an external test signal; forming at least one test line on the substrate, the test line extending from the second dicable area to the first dicable area, one end of the test line being connected to a corresponding display panel, and the other end of the test line extending to the first dicable area and connected to the test terminal; cutting off the first dicable area and the second dicable area of ​​the display panel motherboard to obtain a plurality of display panels.

[0111] At least one embodiment of this disclosure provides a method for manufacturing the above-described display panel, the method including, for example, Figure 8 Steps S100 to S400 are shown in detail below.

[0112] S100, a substrate is provided, the substrate is divided into a panel area and a first slicable area located outside the panel area, the panel area includes a second slicable area and a plurality of sub-panel areas, each sub-panel area is separated by the second slicable area.

[0113] S200, at least one test terminal is formed in the first dicable area of ​​the substrate, and the test terminal is exposed away from the surface of the substrate so that the test terminal can be connected to an external test signal.

[0114] S300, at least one test line is formed on the substrate, the test line extends from the second slicable area to the first slicable area, one end of the test line is connected to the corresponding display panel, and the other end of the test line extends to the first slicable area and is connected to the test terminal.

[0115] S400 cuts off the first and second cutable areas of the display panel motherboard to obtain multiple display panels.

[0116] The display panel obtained by the above-described display panel manufacturing method allows for the monitoring of optical parameters during the vapor deposition process (mainly referring to the process of vapor deposition of the entire surface of the light-emitting device) using test terminals exposed on the substrate. This enables timely detection and resolution of problems, and provides data support for improving the performance of the light-emitting device, thereby enhancing the quality of the display panel.

[0117] It should be noted that the manufacturing method of the display panel provided in this disclosure is not limited to the above examples. The order in which the test terminals and test lines are formed can be designed according to actual needs, and will not be elaborated here.

[0118] In at least one embodiment of this disclosure, the sub-board area is divided into a display area and a bonding area located on at least one side of the display area. The preparation method further includes: forming a plurality of isolation structures on the vapor deposition side of the substrate before cutting the display panel mother board, at least a portion of the isolation structures being located in the display area, and the isolation structures enclosing a plurality of isolation openings located in the display area; and forming a plurality of light-emitting devices, at least a portion of the light-emitting devices being located in the isolation openings.

[0119] For example, a method for manufacturing a display panel may include, as follows: Figure 9 Steps S010 to S060 are shown in detail below.

[0120] S010, a substrate is provided, the substrate is divided into a panel area and a first dicable area located outside the panel area, the panel area includes a second dicable area and a plurality of sub-panel areas, each sub-panel area is separated by the second dicable area.

[0121] S020, at least one test terminal is formed in the first dicable area of ​​the substrate, the test terminal being exposed away from the surface of the substrate so as to connect the test terminal to an external test signal.

[0122] S030, at least one test line is formed on the substrate, the test line extends from the second slicable area to the first slicable area, one end of the test line is connected to the corresponding display panel, and the other end of the test line extends to the first slicable area and is connected to the test terminal.

[0123] S040, a plurality of isolation structures are formed on the vapor deposition side of the substrate, at least part of the isolation structures are located in the display area, and the isolation structures enclose a plurality of isolation openings located in the display area.

[0124] S050, forming a plurality of light-emitting devices, at least a portion of which are located in the isolation opening.

[0125] S060, cut off the first and second cutable areas of the display panel motherboard to obtain multiple display panels.

[0126] It should be noted that the steps between S020, S030, and S040 are not limited to the examples above. They can be completed in the same process or in different sequences. For example, steps S020 and S030, which form the test terminals and test leads, can be performed first, completing them in the same process, and then step S040, which forms the isolation structure, can be performed. Alternatively, step S030, which forms the test leads, can be performed first, followed by step S020, which forms the test terminals, and then step S040, which forms the isolation structure. These can be designed according to actual needs and will not be elaborated further here.

[0127] In at least one embodiment of this disclosure, step S050, forming a plurality of light-emitting devices, may include, as follows: Figure 10 The specific steps S050a to S050b shown are as follows.

[0128] S050a, a plurality of first electrodes spaced apart from each other are formed in the display area, at least a portion of the first electrodes being located within an isolation opening.

[0129] S050b, based on the isolation structure, a light-emitting functional layer and a second electrode are fabricated in the isolation opening. The first electrode, the light-emitting functional layer and the second electrode stacked on each other in each isolation opening constitute a light-emitting device.

[0130] In at least one embodiment of this disclosure, step S050b, which involves fabricating a light-emitting functional layer and a second electrode located within an isolation opening based on an isolation structure, may include, as follows: Figure 11 Steps S051 to S056 are shown in detail below.

[0131] S051, depositing a light-emitting material thin film and a first conductive material thin film, the light-emitting material thin film and the first conductive material thin film covering the isolation structure and the isolation opening, wherein the portions of the light-emitting material thin film and the first conductive material thin film located in the isolation opening respectively form a light-emitting functional layer and a second electrode.

[0132] S052, Deposit a film of encapsulating material to cover the light-emitting device.

[0133] S053, testing the formed light-emitting device based on at least one test terminal exposed on the substrate.

[0134] S054, a first photoresist layer is formed on the encapsulation material film layer, and a patterning process is performed on the first photoresist layer to form a first photoresist pattern, the first photoresist pattern covering a portion of the isolation opening.

[0135] S055, based on the first photoresist pattern, an encapsulation material film layer, a light-emitting material film, and a first conductive material film are etched, wherein the remaining portion of the encapsulation material film layer is formed as an encapsulation unit, and the light-emitting functional layer and the second electrode not covered by the encapsulation unit are etched.

[0136] S056, repeat the above process to form a light-emitting device and a packaging unit at the isolation opening where no light-emitting device is formed, and all the packaging units constitute the first packaging layer.

[0137] In at least one embodiment of this disclosure, in step S020, when forming at least one test terminal in the first dicable area of ​​the substrate, the at least one test terminal is formed on the vapor deposition side of the substrate, and the test terminal and the light-emitting device are located on the same side of the substrate. During the deposition of the light-emitting material film and the first conductive material film, the first dicable area is shielded so that the orthogonal projections of the light-emitting material film and the first conductive material film on the substrate are outside the first dicable area, thereby exposing the test terminal. In step S052, during the deposition of an encapsulation material film layer to cover the light-emitting device, the first dicable area is shielded so that the orthogonal projection of the encapsulation material film layer on the substrate is outside the first dicable area, thereby exposing the test terminal. For example, during the vapor deposition process, a mechanical structure in the vapor deposition apparatus, such as a shielding plate, is used to shield the first dicable area on the vapor deposition side of the substrate, thus preventing the vapor-deposited film layer from covering the test terminal.

[0138] In at least one embodiment of this disclosure, the fabrication method further includes: before forming a plurality of light-emitting devices, sequentially forming a thin-film transistor and a first planarization layer on the vapor deposition side of a substrate, wherein the thin-film transistor is located at least in the display area and the first planarization layer covers at least the panel area; depositing a second conductive material thin film layer on the substrate on which the first planarization layer is formed; forming a second photoresist layer on the second conductive material thin film layer and performing a patterning process on the second photoresist layer to form a second photoresist pattern, wherein the second photoresist pattern covers a portion of the display area; etching the second conductive material thin film layer based on the second photoresist pattern, wherein the remaining portion of the second conductive material thin film layer in the display area is formed as a first signal line; depositing a third conductive material thin film layer on the substrate on which the second conductive material thin film layer is formed; forming a third photoresist layer on the third conductive material thin film layer and performing a patterning process on the third photoresist layer to form a third photoresist pattern, wherein the third photoresist pattern covers a portion of the display area; etching the third conductive material thin film layer based on the third photoresist pattern, wherein the remaining portion of the third conductive material thin film layer in the display area is formed as a second signal line.

[0139] In at least one embodiment of this invention, in forming a second photoresist layer on a second conductive material thin film layer, the second photoresist pattern further covers a portion of the second dicable region and a portion of the first dicable region; in etching the second conductive material thin film layer based on the second photoresist pattern, the remaining portion of the second conductive material thin film layer in the second dicable region and the first dicable region forms a first sub-test line; in forming a third photoresist layer on a third conductive material thin film layer, the third photoresist pattern further covers a portion of the second dicable region and a portion of the first dicable region; in etching the third conductive material thin film layer based on the third photoresist pattern, the remaining portion of the third conductive material thin film layer in the second dicable region and the first dicable region forms a second sub-test line, and the first sub-test line and the second sub-test line constitute a test line.

[0140] In at least one embodiment of the present invention, the remaining portion of the second conductive material thin film layer in the first slicable region is further formed as a first sub-test terminal, and the remaining portion of the third conductive material thin film layer in the first slicable region is further formed as a second sub-test terminal, wherein the first sub-test terminal and the second sub-test terminal constitute a test terminal.

[0141] For example, the method for manufacturing the display panel may include, as follows: Figure 12 Steps S10 to S70 are shown.

[0142] S10, a substrate is provided, the substrate is divided into a panel area and a first dicable area located outside the panel area, the panel area includes a second dicable area and a plurality of sub-panel areas, and each sub-panel area is separated by the second dicable area.

[0143] S20, a thin film transistor and a first planarization layer are sequentially formed on the vapor deposition side of the substrate, wherein the thin film transistor is located at least in the display area and the first planarization layer covers at least the panel area.

[0144] S31, deposit a second conductive material thin film layer on a substrate on which a first planarization layer has been formed.

[0145] S32, a second photoresist layer is formed on the second conductive material thin film layer, and a patterning process is performed on the second photoresist layer to form a second photoresist pattern, the second photoresist pattern covering a portion of the display area, a portion of the second dicable area, and a portion of the first dicable area.

[0146] S33, etching a second conductive material thin film layer based on a second photoresist pattern, wherein the remaining portion of the second conductive material thin film layer in the display area forms a first signal line, the remaining portion of the second conductive material thin film layer in the first dicable area and the remaining portion of the second dicable area form a first sub-test line, and the remaining portion of the second conductive material thin film layer in the first dicable area forms a first layer sub-test terminal.

[0147] S34, deposit a third conductive material thin film layer on the substrate on which the second conductive material thin film layer is formed.

[0148] S35, a third photoresist layer is formed on the third conductive material thin film layer, and a patterning process is performed on the third photoresist layer to form a third photoresist pattern, the third photoresist pattern covering a portion of the display area, a portion of the second dicable area, and a portion of the first dicable area.

[0149] S36, etching a third conductive material thin film layer based on a third photoresist pattern, wherein the remaining portion of the third conductive material thin film layer in the display area forms a second signal line, the remaining portion of the third conductive material thin film layer in the first dicable area and the remaining portion of the second dicable area forms a second sub-test line, the remaining portion of the third conductive material thin film layer in the first dicable area forms a second layer sub-test terminal, the first sub-test line and the second sub-test line constitute a test line, and the first layer sub-test terminal and the second layer test terminal constitute a test terminal.

[0150] S40, a plurality of first electrodes spaced apart from each other are formed on the vapor deposition side of the substrate on which the test lines are formed, and the first electrodes are located at least in the display area.

[0151] S50, a plurality of isolation structures are formed on the vapor deposition side of the substrate, at least a portion of the isolation structures are located in the display area, and the isolation structures enclose a plurality of isolation openings located in the display area, wherein at least a portion of the first electrode is located within the isolation openings.

[0152] S61, deposit a light-emitting material thin film and a first conductive material thin film, the light-emitting material thin film and the first conductive material thin film cover the isolation structure and the isolation opening, wherein the portions of the light-emitting material thin film and the first conductive material thin film located in the isolation opening respectively form a light-emitting functional layer and a second electrode.

[0153] S62, depositing a film of encapsulating material to cover the light-emitting device.

[0154] S63, the formed light-emitting device is tested based on at least one test terminal exposed on the substrate.

[0155] S64, a first photoresist layer is formed on the encapsulation material film layer, and a patterning process is performed on the first photoresist layer to form a first photoresist pattern, the first photoresist pattern covering a portion of the isolation opening.

[0156] S65, based on the first photoresist pattern, an encapsulation material film layer, a light-emitting material film, and a first conductive material film are etched, wherein the remaining portion of the encapsulation material film layer is formed as an encapsulation unit, and the light-emitting functional layer and the second electrode not covered by the encapsulation unit are etched.

[0157] S66, repeat the above process to form a light-emitting device and a packaging unit at the isolation opening where no light-emitting device is formed, and all the packaging units constitute the first packaging layer.

[0158] S70, cut off the first and second cutable areas of the display panel motherboard to obtain multiple display panels.

[0159] In at least one embodiment of the present invention, before depositing a third conductive material thin film layer on a substrate on which a second conductive material thin film layer is formed, the method further includes: forming an insulating layer on the substrate on which the second conductive material thin film layer is formed, the insulating layer covering the second conductive material thin film layer.

[0160] In at least one embodiment of this invention, in step S020, at least one test terminal is formed in the first dicable region of the substrate, wherein the at least one test terminal is formed on the non-evaporated side of the substrate and the test terminal and the light-emitting device are located on different sides of the substrate, and in step S052, a light-emitting material film and a first conductive material film are deposited, wherein the orthogonal projection of the light-emitting material film and the first conductive material film on the substrate covers the panel region and the first dicable region of the substrate; in step S052, an encapsulation material film layer is deposited to cover the light-emitting device, wherein the orthogonal projection of the encapsulation material film layer on the substrate covers the panel region and the first dicable region of the substrate.

[0161] In at least one embodiment of this invention, the fabrication method further includes: before forming a plurality of light-emitting devices, sequentially forming a thin-film transistor and a first planarization layer on a substrate by vapor deposition, wherein the thin-film transistor is at least located in the display area, and the first planarization layer covers the panel area and the first dicable area; forming vias on the substrate, wherein the vias expose a portion of the surface of the test terminal near the substrate; depositing a second conductive material thin film layer on the substrate having the first planarization layer, wherein the second conductive material thin film layer fills the vias; forming a second photoresist layer on the second conductive material thin film layer, and performing a patterning process on the second photoresist layer to form a second photoresist pattern, wherein the second photoresist... The process involves: a pattern covering a portion of the display area; etching a second conductive material thin film layer based on a second photoresist pattern, wherein the remaining portion of the second conductive material thin film layer in the display area forms a first signal line; depositing a third conductive material thin film layer on a substrate on which the second conductive material thin film layer is formed; forming a third photoresist layer on the third conductive material thin film layer, and performing a patterning process on the third photoresist layer to form a third photoresist pattern, the third photoresist pattern covering a portion of the display area; etching a third conductive material thin film layer based on the third photoresist pattern, wherein the remaining portion of the third conductive material thin film layer in the display area forms a second signal line.

[0162] In at least one embodiment of this invention, in forming a second photoresist layer on a second conductive material thin film layer, the second photoresist pattern further covers a portion of the second dicable region and a portion of the first dicable region, and the orthographic projection of the second photoresist pattern on the substrate overlaps with the orthographic projection of the test terminal on the substrate; the second conductive material thin film layer is etched based on the second photoresist pattern, and the remaining portion of the second conductive material thin film layer in the second dicable region and the first dicable region forms a first sub-test line; in forming a third photoresist layer on a third conductive material thin film layer, the third photoresist pattern further covers a portion of the second dicable region and a portion of the first dicable region, and the orthographic projection of the third photoresist pattern on the substrate overlaps with the orthographic projection of the test terminal on the substrate; the third conductive material thin film layer is etched based on the third photoresist pattern, and the remaining portion of the third conductive material thin film layer in the second dicable region and the first dicable region forms a second sub-test line, and the first sub-test line and the second sub-test line constitute a test line.

[0163] For example, the method for manufacturing the display panel may include, as follows: Figure 13 Steps S10a to S70a are shown.

[0164] S10a, a substrate is provided, the substrate is divided into a panel area and a first dicable area located outside the panel area, the panel area includes a second dicable area and a plurality of sub-panel areas, each sub-panel area is separated by the second dicable area.

[0165] S20a, a test terminal is formed on the non-evaporation side of the substrate, wherein the test terminal is located in the first dicable area of ​​the substrate.

[0166] For example, the test terminal can be a single-layer structure or a multi-layer structure, which can be designed according to actual needs, and will not be elaborated here.

[0167] S31a, a thin film transistor and a first planarization layer are sequentially formed on the substrate by vapor deposition. The thin film transistor is located at least in the display area, and the first planarization layer covers the panel area and the first dicable area.

[0168] It should be noted that the vapor-deposited side and the non-vapor-deposited side of the substrate are arranged opposite each other.

[0169] S32a, a via is formed on the substrate, and the via exposes the portion of the test terminal surface near the substrate.

[0170] For example, vias are formed in the corresponding region of the first planar layer located in the first dicable region and the corresponding substrate region. The vias can be formed in steps or in one step. The specific via formation process can be designed according to actual needs, but will not be designed here.

[0171] For example, there are multiple test leads, multiple test terminals, and multiple vias. Each via corresponds to a test lead, which is used to achieve electrical connection between each test lead and test terminals on different sides.

[0172] S33a, a second conductive material thin film layer is deposited on a substrate on which a first planarization layer is formed, and the second conductive material thin film layer fills the via.

[0173] S34a, a second photoresist layer is formed on the second conductive material thin film layer, and a patterning process is performed on the second photoresist layer to form a second photoresist pattern. The second photoresist pattern covers a portion of the display area, a portion of the second dicable area, and a portion of the first dicable area. The orthographic projection of the second photoresist pattern on the substrate overlaps with the orthographic projection of the test terminal on the substrate.

[0174] S35a, etching a second conductive material thin film layer based on a second photoresist pattern, wherein the remaining portion of the second conductive material thin film layer in the display area is formed as a first signal line, and the remaining portion of the second conductive material thin film layer in the second dicable area and the first dicable area is formed as a first sub-test line.

[0175] S36a, depositing a third conductive material thin film layer on a substrate on which a second conductive material thin film layer has been formed.

[0176] S37a, a third photoresist layer is formed on the third conductive material thin film layer, and a patterning process is performed on the third photoresist layer to form a third photoresist pattern. The third photoresist pattern covers a portion of the display area, a portion of the second dicable area, and a portion of the first dicable area. The orthographic projection of the third photoresist pattern on the substrate overlaps with the orthographic projection of the test terminal on the substrate.

[0177] S38a, etching a third conductive material thin film layer based on a third photoresist pattern, wherein the remaining portion of the third conductive material thin film layer in the display area forms a second signal line, and the remaining portion of the third conductive material thin film layer in the second dicable area and the first dicable area forms a second sub-test line, and the first sub-test line and the second sub-test line constitute a test line.

[0178] S40a, a plurality of first electrodes spaced apart from each other are formed on the vapor deposition side of the substrate on which the test lines are formed, and the first electrodes are located at least in the display area.

[0179] S50a, a plurality of isolation structures are formed on the vapor deposition side of the substrate, at least a portion of the isolation structures are located in the display area, and the isolation structures enclose a plurality of isolation openings located in the display area, wherein at least a portion of the first electrode is located within the isolation openings.

[0180] S61a, depositing a light-emitting material thin film and a first conductive material thin film, the light-emitting material thin film and the first conductive material thin film covering the isolation structure and the isolation opening, wherein the portions of the light-emitting material thin film and the first conductive material thin film located in the isolation opening respectively form a light-emitting functional layer and a second electrode.

[0181] S62a, depositing a film of encapsulating material to cover the light-emitting device.

[0182] S63a, the formed light-emitting device is tested based on at least one test terminal exposed on the substrate.

[0183] S64a, a first photoresist layer is formed on the encapsulation material film layer, and a patterning process is performed on the first photoresist layer to form a first photoresist pattern, the first photoresist pattern covering a portion of the isolation opening.

[0184] S65a, based on the first photoresist pattern, an encapsulation material film, a light-emitting material film, and a first conductive material film are etched, wherein the remaining portion of the encapsulation material film is formed as an encapsulation unit, and the light-emitting functional layer and the second electrode not covered by the encapsulation unit are etched.

[0185] S66a, repeat the above process to form a light-emitting device and a packaging unit at the isolation opening where no light-emitting device is formed, and all the packaging units constitute the first packaging layer.

[0186] S70a, the first and second cutable areas of the display panel motherboard are cut off to obtain multiple display panels.

[0187] It should be noted that the method for preparing the display panel in this embodiment is not limited to the above examples. For example, the test terminal formed in step S20a on the non-evaporation side of the substrate can be formed in any step before the step of forming the light-emitting functional layer of the light-emitting device, such as before step S61a. The specific design can be made according to actual needs, and will not be elaborated here.

[0188] In at least one embodiment of the present invention, before depositing a third conductive material thin film layer on a substrate having a second conductive material thin film layer, the method further includes: forming an insulating layer on the substrate having a second conductive material thin film layer, the insulating layer covering the second conductive material thin film layer; forming a second via on the insulating layer, wherein, during the deposition of the third conductive material thin film layer on the substrate having a second conductive material thin film layer, the third conductive material thin film layer fills the second via to electrically connect the third conductive material thin film layer and the second conductive material thin film layer.

[0189] In at least one embodiment of this disclosure, after forming the test terminal and between forming the light-emitting device, the fabrication method further includes forming a second planarization layer on the substrate. In at least one embodiment of this disclosure, when both the light-emitting device and the test terminal are located on the vapor deposition side of the substrate, the orthographic projection of the second planarization layer on the substrate is outside the orthographic projection of the test terminal on the substrate.

[0190] This disclosure also provides a display device comprising a display panel obtained by any of the preparation methods described above.

[0191] It should be noted that the display panel in the present disclosure is not limited to the above structure. For example, the non-display area of ​​the display panel is not limited to the bonding area mentioned above, but may also include a bending area. The bending area bends at least part of the non-display area to the back of the display panel, so that the display panel appears as a narrow bezel or a bezel-less panel when in use.

[0192] For example, the display panel in this display device, such as Figure 14 As shown, the system includes a substrate 100, an isolation structure 400, a light-emitting device 500, a first encapsulation layer 610, a second encapsulation layer 620, and a third encapsulation layer 630. The isolation structure 400 is located on the substrate 100 and encloses a plurality of isolation openings 401 at least in the display area. The light-emitting device 500 is located on the substrate 100 and corresponds to each isolation opening 401, with at least a portion of the light-emitting device 500 located within the corresponding isolation opening 401. The first encapsulation layer 610 is located on the side of the isolation structure 400 and the light-emitting device 500 away from the substrate 100. The first encapsulation layer 610 includes a plurality of encapsulation units 611, each encapsulation unit 611 corresponding to an isolation opening 401 to cover the light-emitting device 500 limited by the corresponding isolation opening 401. The second encapsulation layer 620 and the third encapsulation layer 630 are sequentially stacked on the side of the first encapsulation layer 610 away from the substrate 100. The structures of the isolation structure 400 and the light-emitting device 500 can be referred to in the above embodiment and will not be repeated here.

[0193] For example, the orthographic projection of the third encapsulation layer 630 on the substrate 100 covers the orthographic projection of the second encapsulation layer 620 on the substrate 100.

[0194] For example, the second encapsulation layer 620 can be an organic film layer to planarize the surface of the display panel, thereby giving the encapsulation structure a planarized surface for setting other structures (such as touch structures, etc.). In addition, the organic film layer can also be used for stress relief, thereby reducing the risk of stress damage to the encapsulation structure.

[0195] For example, the third encapsulation layer 630 is an inorganic film layer, which encapsulates and protects the second encapsulation layer 620 to reduce the risk of moisture intrusion.

[0196] At least one embodiment of this disclosure provides a display device, which may include the display panel in the above embodiments or a display panel obtained by the manufacturing method in the above embodiments. For example, the display device may include a touch structure, an optical film (e.g., a microlens, a polarizer), a cover plate, or other structures disposed on the light-emitting side of the display panel.

[0197] For example, the display device can be any product or component with a display function, such as a television, digital camera, mobile phone, watch, tablet computer, laptop computer, or navigator.

[0198] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0199] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A display panel motherboard, characterized in that, include: The substrate is divided into a panel area and a first cuttable area located around the panel area. The panel area includes a second cuttable area and a plurality of sub-board areas, each of the sub-board areas being separated by the second cuttable area. Each sub-board area is divided into a display area and a bonding area located on at least one side of the display area. Multiple test terminals are located on the substrate and in the first slicable area surrounding the panel area. The test terminals are exposed away from the surface of the substrate so that they can be connected to an external test signal. Multiple test lines are located on the substrate. The test lines extend from the second dicable area to the first dicable area. One end of the test line is connected to the corresponding sub-board area, and the other end of the test line extends to the first dicable area and is connected to the test terminal. Multiple isolation structures are located on the substrate and at least partially located in the display area, the isolation structures enclosing to form multiple isolation openings in the display area; A plurality of light-emitting devices, at least a portion of which are located in the isolation opening, wherein the film layer of which at least covers the panel area of ​​the display panel motherboard; as well as An initial first encapsulation layer is located on the side of the isolation structure away from the substrate. The initial first encapsulation layer includes a plurality of encapsulation units and an encapsulation material film layer. The orthographic projection of the encapsulation unit on the substrate covers the orthographic projection of the light-emitting device of one emitted light color on the substrate. The encapsulation material film layer covers the side of the encapsulation unit away from the substrate, and the orthographic projection of the encapsulation material film layer on the substrate at least covers the panel area. The test terminal and the light-emitting device are located on opposite sides of the substrate. The orthographic projection of the film layer corresponding to the light-emitting device on the substrate covers the entire orthographic projection of the test terminal on the substrate. The orthographic projection of the encapsulation material film layer on the substrate covers the orthographic projections of the test terminal and the test line on the substrate.

2. The display panel motherboard according to claim 1, characterized in that, The plurality of light-emitting devices include at least a first light-emitting device and a second light-emitting device that emit light of different colors. A portion of the isolation opening confines the second light-emitting device, and the remaining portion of the isolation opening confines both the first light-emitting device and the second light-emitting device. The second light-emitting device is located on the side of the first light-emitting device away from the substrate. The film layer of at least the light-emitting device covering the panel area is the same as the film layer corresponding to the second light-emitting device.

3. The display panel motherboard according to claim 1, characterized in that, The test line includes at least two conductive layers.

4. The display panel motherboard according to claim 3, characterized in that, The display panel motherboard further includes thin-film transistors, a first planarization layer, a first signal line, a second signal line, and a second planarization layer sequentially stacked on the substrate. The second planarization layer is located on the side of the light-emitting device closer to the substrate. The test line includes a first sub-test line located on the substrate and a second sub-test line located on the side of the first sub-test line away from the substrate. The first sub-test line is on the same layer and made of the same material as the first signal line, and the second sub-test line is on the same layer and made of the same material as the second signal line; and / or... The test terminal and the light-emitting device are located on the same side of the substrate. The orthographic projection of the second planarization layer on the substrate is outside the orthographic projection of the test terminal on the substrate. The test terminal includes a first layer sub-test terminal and a second layer sub-test terminal. The first layer test terminal is on the same layer and made of the same material as the first signal line, and the second layer test terminal is on the same layer and made of the same material as the second signal line.

5. The display panel motherboard according to any one of claims 1 to 4, characterized in that, The isolation structure includes a support portion and a crown portion, the support portion being located between the crown portion and the substrate, and The orthographic projection of the surface of the support portion away from the substrate onto the substrate lies within the orthographic projection of the crown portion onto the substrate.

6. The display panel motherboard according to claim 5, characterized in that, The isolation structure also includes a bottom, which is located between the support and the substrate, and the orthographic projection of the support on the substrate is located within the orthographic projection of the bottom on the substrate.

7. A method for manufacturing a display panel, characterized in that, include: A substrate is provided, the substrate being divided into a panel area and a first slicable area located around the periphery of the panel area, the panel area including a second slicable area and a plurality of sub-board areas, each of the sub-board areas being separated by the second slicable area, and each sub-board area being divided into a display area and a bonding area located on at least one side of the display area; At least one test terminal is formed in the first dicable region of the substrate, the test terminal being exposed away from the surface of the substrate so as to connect the test terminal to an external test signal, wherein the test terminal is formed on the non-evaporated side of the substrate; At least one test line is formed on the substrate, the test line extends from the second slicable area to the first slicable area, one end of the test line is connected to the corresponding display panel, and the other end of the test line extends to the first slicable area and is connected to the test terminal. A plurality of first electrodes spaced apart from each other are formed in the display area; A plurality of isolation structures are formed on the vapor deposition side of the substrate, at least a portion of the isolation structures are located in the display area, and the isolation structures enclose a plurality of isolation openings located in the display area, wherein at least a portion of the first electrode is located within the isolation openings; A light-emitting material film and a first conductive material film are deposited, the light-emitting material film and the first conductive material film covering the isolation structure and the isolation opening, and the orthogonal projection of the light-emitting material film and the first conductive material film on the substrate covering the panel area and the first dicable area of ​​the substrate, wherein the portions of the light-emitting material film and the first conductive material film located in the isolation opening respectively form a light-emitting functional layer and a second electrode, and the first electrode, the light-emitting functional layer and the second electrode stacked on each other in each isolation opening constitute a light-emitting device, and the light-emitting device and the test terminal are located on different sides of the substrate; A coating material film is deposited to cover the light-emitting device, wherein the orthographic projection of the coating material film on the substrate covers the panel area and the first dicable area of ​​the substrate; The light-emitting device formed is tested based on the test terminals exposed on the substrate; A first photoresist layer is formed on the encapsulation material film, and the first photoresist layer is patterned to form a first photoresist pattern, wherein the first photoresist pattern covers a portion of the isolation opening; The encapsulation material film, the light-emitting material film, and the first conductive material film are etched based on the first photoresist pattern, wherein the remaining portion of the encapsulation material film is formed as an encapsulation unit, and the light-emitting functional layer and the second electrode not covered by the encapsulation unit are etched. The above process is repeated to form the light-emitting device and the packaging unit at the isolation opening where the light-emitting device is not formed, and all the packaging units constitute the first packaging layer; The first and second cutable areas of the display panel motherboard are cut off to obtain multiple display panels.

8. The preparation method according to claim 7, characterized in that, The preparation method further includes: Before forming the plurality of light-emitting devices, thin-film transistors and a first planarization layer are sequentially formed on the substrate by vapor deposition, wherein the thin-film transistors are at least located in the display area, and the first planarization layer covers the panel area and the first dicable area. A via is formed on the substrate, the via exposing a portion of the test terminal's surface near the substrate; A second conductive material thin film layer is deposited on the substrate on which the first planarization layer is formed, and the second conductive material thin film layer fills the via. A second photoresist layer is formed on the second conductive material thin film layer, and a patterning process is performed on the second photoresist layer to form a second photoresist pattern, wherein the second photoresist pattern covers a portion of the display area; The second conductive material thin film layer is etched based on the second photoresist pattern, wherein the remaining portion of the second conductive material thin film layer in the display area is formed as a first signal line; A third conductive material thin film layer is deposited on the substrate on which the second conductive material thin film layer is formed; A third photoresist layer is formed on the third conductive material thin film layer, and the third photoresist layer is patterned to form a third photoresist pattern, the third photoresist pattern covering a portion of the display area; The third conductive material thin film layer is etched based on the third photoresist pattern, wherein the remaining portion of the third conductive material thin film layer in the display area is formed as a second signal line.

9. The preparation method according to claim 8, characterized in that, In the process of forming a second photoresist layer on the second conductive material thin film layer, the second photoresist pattern also covers a portion of the second dicable area and a portion of the first dicable area, and the orthogonal projection of the second photoresist pattern on the substrate overlaps with the orthogonal projection of the test terminal on the substrate. The second conductive material thin film layer is etched based on the second photoresist pattern, and the second conductive material thin film layer forms a first sub-test line in the remaining portion of the second dicable region and the first dicable region. In the formation of a third photoresist layer on the third conductive material thin film layer, the third photoresist pattern also covers a portion of the second dicable area and a portion of the first dicable area, and the orthographic projection of the third photoresist pattern on the substrate overlaps with the orthographic projection of the test terminal on the substrate. The third conductive material thin film layer is etched based on the third photoresist pattern, and the remaining portion of the third conductive material thin film layer in the second dicable region and the first dicable region is formed as a second sub-test line. The first sub-test line and the second sub-test line constitute the test line.

10. A display device, characterized in that, The display panel includes one prepared by any one of claims 7 to 9.

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