Display device

Abstract

The present disclosure provides a display device including: a substrate on which a plurality of sub-pixels are disposed, each of the plurality of sub-pixels including a plurality of light emitting regions; the first planarization layer is arranged above the substrate; the first pixel electrode is arranged on the first planarization layer; a second planarization layer disposed on the first pixel electrode and including at least one opening portion exposing a portion of an upper surface of the first pixel electrode; the second pixel electrode is arranged on the second planarization layer; a bank disposed on a portion of an upper surface of the second pixel electrode and including an opening in each of the plurality of sub-pixels; a light emitting layer disposed in the opening; and a common electrode disposed on the light emitting layer, and the display device can eliminate or reduce display artifacts such as defective image presentation and improve light emitting efficiency.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2024 - 0002104, filed with the Korean Intellectual Property Office on January 5, 2024, which is incorporated herein by reference in its entirety for all purposes as if fully set forth herein. Technical field

[0003] The present disclosure relates to an electronic device, and more particularly, to a display device. Background art

[0004] Displays capable of presenting information and images on a screen are widely used in various electronic devices or systems and are becoming increasingly important as a core technology for presenting various information to users in today's society. To meet various needs, various types of displays, such as liquid crystal displays (LCDs), organic light - emitting displays (OLEDs), micro - light - emitting displays (microLEDs), mini - light - emitting displays (mini LEDs), quantum dot light - emitting displays (QLEDs), etc., have been developed and widely used.

[0005] There is a need for display devices to provide excellent display quality and luminous efficiency. In particular, with the advancement of display technology, in order to provide various functions and produce excellent performance, it is desirable for display devices to use limited power, and the luminous efficiency of display devices has become increasingly important.

[0006] The luminous efficiency of a display device can be determined by the light - emitting elements included in the display device. A display device including light - emitting elements with excellent luminous efficiency can have excellent luminous efficiency. For example, the luminous efficiency of a display device can be improved by increasing the luminous efficiency of the light - emitting elements included in the display device. However, challenges may arise in increasing the luminous efficiency of light - emitting elements. Summary of the invention

[0007] To solve this problem, one or more aspects of the present disclosure may provide a display device having a structure in which a sub - pixel includes a double - layer pixel electrode, thereby being able to improve luminous efficiency.

[0008] One or more aspects of the present disclosure may provide a display device having a structure in which a sub - pixel includes a double - layer pixel electrode, thereby being able to eliminate or reduce display artifacts such as defective image presentation.

[0009] One or more aspects of the present disclosure may provide a display device having a structure in which a sub - pixel includes a plurality of light - emitting regions that emit light of the same color, thereby being able to be driven at low power with high - brightness characteristics.

[0010] According to one or more example embodiments of the present disclosure, a display device may be provided. The display device includes: a substrate on which a plurality of sub-pixels are provided, and each of the plurality of sub-pixels includes a plurality of light-emitting regions; a first planarization layer provided above the substrate; a first pixel electrode provided on the first planarization layer; a second planarization layer provided on the first pixel electrode and including at least one opening exposing at least a part of the upper surface of the first pixel electrode; a second pixel electrode provided on the second planarization layer; a bank provided on a part of the upper surface of the second pixel electrode and including an opening in each of the plurality of sub-pixels; a light-emitting layer provided in the opening; and a common electrode provided on the light-emitting layer.

[0011] According to one or more example embodiments of the present disclosure, a display device may be provided. The display device includes: a plurality of light-emitting regions provided in one sub-pixel, the plurality of light-emitting regions including at least one first light-emitting region provided in the sub-pixel, a second light-emitting region surrounding the first light-emitting region, and a third light-emitting region surrounding the second light-emitting region; and at least one opening located in one sub-pixel and enabling the first light-emitting region and the second light-emitting region to be provided.

[0012] According to one or more aspects of the present disclosure, a display device capable of eliminating or reducing display artifacts such as defective image presentation and improving luminous efficiency may be provided.

[0013] According to one or more aspects of the present disclosure, a display device capable of generating improved luminous efficiency based on a structure in which one sub-pixel includes a double-layer pixel electrode may be provided.

[0014] According to one or more aspects of the present disclosure, a display device capable of eliminating or reducing display artifacts such as defective image presentation based on a structure in which one sub-pixel includes a double-layer pixel electrode may be provided.

[0015] According to one or more aspects of the present disclosure, a display device capable of driving at low power with high brightness characteristics based on a structure in which one sub-pixel includes a plurality of light-emitting regions emitting light of the same color may be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The present disclosure includes drawings to provide a further understanding of the present disclosure. The drawings are incorporated into and constitute a part of this application. The drawings illustrate aspects of the present disclosure and, together with the description, are used to explain the principles of the present disclosure. In the drawings:

[0017] Figure 1 An example system configuration of a display device according to an aspect of the present disclosure is shown;

[0018] Figure 2Shows an exemplary display panel according to aspects of the present disclosure;

[0019] Figure 3 Is a plan view showing an exemplary area of sub-pixels disposed in the active area of the display panel according to aspects of the present disclosure;

[0020] Figure 4 Is along Figure 3 Cross-sectional view taken along line A-B of;

[0021] Figure 5 Shows Figure 4 Cross-sectional view of the light-emitting area of;

[0022] Figures 6A to 6E Is a schematic plan view showing the structure of four sub-pixels in a display device according to aspects of the present disclosure;

[0023] Figures 7A to 7J Shows an exemplary method of manufacturing a display device according to aspects of the present disclosure; and

[0024] Figure 8 Is a cross-sectional view schematically showing an exemplary structure of a display device according to aspects of the present disclosure. Detailed Description

[0025] Reference will now be made in detail to embodiments of the present disclosure, examples of which may be illustrated in the accompanying drawings. In the following description, unless otherwise stated, the structures, embodiments, implementations, methods, and operations described herein are not limited to the specific examples set forth herein and may be varied as known in the art. Unless otherwise stated, the same reference numerals refer to the same elements throughout. The names of the various elements used in the following description are chosen only for convenience in writing the specification and may thus be different from the names used in actual products. The advantages and features of the present disclosure and the methods for realizing them will be elucidated by the exemplary embodiments described below with reference to the accompanying drawings. However, the present disclosure may be implemented in different forms and should not be construed as limited to the exemplary embodiments described herein. Instead, these exemplary embodiments are provided so that the present disclosure will be thorough and complete, and will help those skilled in the art fully understand the scope of the present disclosure. In addition, the scope of protection of the present disclosure is defined by the claims and their equivalents. In the following description, detailed descriptions of related known functions or configurations may be omitted where such descriptions may unnecessarily obscure aspects of the present disclosure. The shapes, sizes, ratios, angles, quantities, etc. shown in the accompanying drawings for describing various exemplary embodiments of the present disclosure are given only by way of example. Therefore, the present disclosure is not limited to the illustrations in the accompanying drawings. When using terms such as "comprising", "having", "including", "containing", "constituting", "consisting of", "formed by", etc., one or more other elements may be added unless a term such as "only" is used. Elements described in the singular are intended to include a plurality of elements, and vice versa, unless the context clearly dictates otherwise.

[0026] Although terms such as "first", "second", A, B, (a), (b), etc. may be used herein to describe various elements, these elements should not be construed as being limited by these terms, since they are not used to define a specific order or priority. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of the present disclosure.

[0027] When referring to a first element being "connected or coupled to", "contacting or overlapping", etc. a second element, it should be understood that the first element may not only be "directly connected or coupled to" or "directly contacting or overlapping" the second element, but also a third element may be "interposed" between the first element and the second element, or the first element and the second element may be "connected or coupled to", "contacting or overlapping", etc. each other through a fourth element. Here, the second element may be included in at least one of two or more elements that are "connected or coupled to", "contacting or overlapping", etc. each other.

[0028] When describing positional relationships, for example, when using terms such as "above", "over", "below", "on top", "underneath", "beside", "near", etc. to describe the positional relationship between two parts, unless more restrictive terms are used, such as "immediately (adjacent to)", "directly", or "proximately", one or more other parts may be located between these two parts. For example, when one element or layer is disposed "on" another element or layer, a third element or layer may be interposed therebetween. Additionally, terms such as "left", "right", "top", "bottom", "downward", "upward", "upper", "lower", etc. refer to any reference system.

[0029] Furthermore, when referring to any dimensions, relative sizes, etc., the numerical values or corresponding information of elements or features (e.g., levels, ranges, etc.) should be considered to include a tolerance or error range that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.), even if no relevant description is specified. Additionally, the term "may" fully encompasses all meanings of the term "able to".

[0030] Although terms such as "first", "second", "A", "B", "(a)", or "(b)" etc. may be used herein to describe various elements, these elements should not be construed as being limited by these terms, as they are not used to define a specific order or priority. These terms are only used to distinguish one element from another. Therefore, these related elements should not be construed as being limited by these terms, as they are not used to define a specific order or priority. Additionally, the expression of the first element, the second element "and / or" the third element should be understood as one of the first element, the second element, and the third element, or any or all combinations of the first element, the second element, and the third element. For example, A, B, and / or C may refer to only A, only B, or only C; any one or some combinations of A, B, and C; or all of A, B, and C.

[0031] For the expressions of an element or layer being "connected", "joined", or "adhered" to another element or layer, unless otherwise specified, this element or layer can not only be directly connected, joined, or adhered to another element or layer, but also be indirectly connected, joined, or adhered to another element or layer in the case where one or more intermediate elements or layers are "disposed" or "interposed" between the elements or layers. Additionally, another element may be included in one or more of two or more elements that are connected, combined, joined, or in contact with each other.

[0032] For expressions such as an element or layer being "in contact with", "overlapping", etc. with another element or layer, unless otherwise specified, this element or layer can not only be directly in contact with, overlapping, etc. with another element or layer, but also be indirectly in contact with, overlapping, etc. with another element or layer through one or more intermediate elements or layers being "disposed" or "interposed" between the elements or layers.

[0033] When describing a positional relationship, for example, when using terms such as "above", "over", "below", "on top", "underneath", "beside", "near", etc. to describe the positional relationship between two parts, unless more restrictive terms such as "immediately", "directly", or "adjacent to" are used, one or more other parts may be located between the two parts. For example, when an element or layer is disposed "on" another element or layer, a third element or layer may be interposed therebetween. In addition, terms such as "left", "right", "top", "bottom", "downward", "upward", "upper", "lower", etc. refer to any reference system.

[0034] When describing a time relationship, when the time sequence is described as, for example, "after", "subsequently", "next", or "before", discontinuous cases may be included unless more restrictive terms such as "exactly", "immediately", or "directly" are used. When interpreting an element, the element should be interpreted as including an error or tolerance range, even if no explicit description of such error or tolerance range is provided. In addition, the term "may" fully encompasses all meanings of the term "can".

[0035] The term "at least one" should be understood to include any or all combinations of one or more of the related listed items. For example, the meaning of "at least one of the first element, the second element, and the third element" encompasses the combination of all three listed elements, the combination of any two of the three elements, and each individual element, namely the first element, the second element, and the third element. The expression of the first element, the second element "and / or" the third element should be understood as one of the first element, the second element, and the third element or any or all combinations of the first element, the second element, and the third element. For example, A, B, and / or C may refer to only A, only B, or only C; any or some combinations of A, B, and C; or all of A, B, and C.

[0036] Hereinafter, various exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In addition, for ease of description, the scale of each element shown in the drawings may be different from the actual scale. Therefore, the elements shown are not limited to the specific scale shown in the drawings.

[0037] Figure 1 An exemplary system configuration of a display device 100 according to an aspect of the present disclosure is shown. In all aspects according to the present disclosure, all components of each display device are operably combined and configured.

[0038] Referring to Figure 1 , in one or more aspects, the display device 100 may include a display panel 110 and a display driving circuit as components for displaying an image.

[0039] The display driving circuit may be a circuit for driving the display panel 110, and includes a data driving circuit 120, a gate driving circuit 130, a display controller 140, and other circuit components.

[0040] The display panel 110 may include an active area DA capable of displaying an image and a non-active area NDA that does not display an image. The non-active area NDA may be an area outside the active area DA, and may also be referred to as a border area or a border. All or at least a part of the non-active area NDA may be an area visible from the front of the display device 100, or may be curved and invisible from the front of the display device 100.

[0041] The display panel 110 may include a substrate SUB and a plurality of sub-pixels SP disposed on the substrate SUB. The display panel 110 may also include various types of signal lines for driving the plurality of sub-pixels SP.

[0042] In one or more aspects, the display device 100 may be a liquid crystal display device or the like, or may be a self-luminous display device that emits light from the display panel 110 itself. In an example where the display device 100 is a self-luminous display device, each of the plurality of sub-pixels SP may include a light-emitting element.

[0043] For example, the display device 100 according to an aspect of the present disclosure may be an organic light-emitting display device that uses an organic light-emitting diode (OLED) to implement the light-emitting element ED. In another example, the display device 100 according to an aspect of the present disclosure may be an inorganic light-emitting display device that uses a light-emitting diode based on an inorganic material to implement the light-emitting element. In still another example, the display device 100 according to an aspect of the present disclosure may be a quantum dot display device that uses quantum dots (which are self-luminous semiconductor crystals) as the light-emitting element.

[0044] The structure of each sub-pixel among the plurality of sub-pixels SP may be configured or designed differently according to the type of the display device 100. In an example where the display device 100 is a self-luminous display device including self-luminous sub-pixels SP, each sub-pixel SP may include a self-luminous light-emitting element, one or more transistors, and one or more capacitors.

[0045] Various types of signal lines arranged in the display device 100 may include, for example, a plurality of data lines DL for transmitting data signals (which may be referred to as data voltages or image signals), a plurality of gate lines GL for transmitting gate signals (which may be referred to as scan signals), and the like.

[0046] The plurality of data lines DL and the plurality of gate lines GL may cross each other. Each of the plurality of data lines DL may be configured to extend in a first direction. Each of the plurality of gate lines GL may be configured to extend in a second direction.

[0047] For example, the first direction may be a column direction or a vertical direction, and the second direction may be a row direction or a horizontal direction. In another example, the first direction may be a row direction or a horizontal direction, and the second direction may be a column direction or a vertical direction.

[0048] The data driving circuit 120 may be a circuit for driving a plurality of data lines DL, and may supply data signals to the plurality of data lines DL. The gate driving circuit 130 may be a circuit for driving a plurality of gate lines GL, and may supply gate signals to the plurality of gate lines GL.

[0049] The display controller 140 may be a device for controlling the data driving circuit 120 and the gate driving circuit 130. The display controller 140 may control the driving time of the plurality of data lines DL and the driving time of the plurality of gate lines GL.

[0050] The display controller 140 may supply a data driving control signal DCS to the data driving circuit 120 to control the data driving circuit 120. The display controller 140 may supply a gate driving control signal GCS to the gate driving circuit 130 to control the gate driving circuit 130.

[0051] The display controller 140 may receive input image data from the host system 150, and supply image data Data readable by the data driving circuit 120 to the data driving circuit 120 based on the input image data.

[0052] The data driving circuit 120 may control the supply of data signals to the plurality of data lines DL according to the driving timing of the display controller 140.

[0053] The data driving circuit 120 may receive digital image data Data from the display controller 140, convert the received image data Data into analog data signals, and output the obtained analog data signals to the plurality of data lines DL.

[0054] The gate driving circuit 130 may control the supply of gate signals to the plurality of gate lines GL according to the timing of the display controller 140. The gate driving circuit 130 may receive a first gate voltage corresponding to a conductive level voltage and a second gate voltage corresponding to a cutoff level voltage, as well as various gate driving control signals GCS, generate gate signals, and supply the generated gate signals to the plurality of gate lines GL.

[0055] In one or more aspects, the data driving circuit 120 can be connected to the display panel 110 through tape automated bonding (TAB) technology, or to the conductive pads (such as bonding pads) of the display panel 110 through chip on glass (COG) technology or chip on panel (COP) technology, or to the display panel 110 through chip on film (COF) technology.

[0056] In one or more aspects, the gate driving circuit 130 can be connected to the display panel 110 through tape automated bonding (TAB) technology, or to the conductive pads (such as bonding pads) of the display panel 110 through chip on glass (COG) technology or chip on panel (COP) technology, or to the display panel 110 through chip on film (COF) technology. In one or more aspects, the gate driving circuit 130 can be disposed in the non-active area NDA of the display panel 110 through in-panel gate (GIP) technology. The gate driving circuit 130 can be disposed on the substrate SUB, or connected to the substrate SUB. In an example where the gate driving circuit 130 is implemented through GIP technology, the gate driving circuit 130 can be disposed in the non-active area NDA of the substrate SUB. In an example where the gate driving circuit 130 is implemented through chip on glass (COG) technology, chip on film (COF) technology, etc., the gate driving circuit 130 can be connected to the substrate SUB.

[0057] In one or more aspects, at least one of the data driving circuit 120 and the gate driving circuit 130 can be disposed in the active area DA of the display panel 110. For example, at least one of the data driving circuit 120 and the gate driving circuit 130 can be configured not to overlap with the sub-pixels SP, or configured to overlap with one or more or all of the sub-pixels SP, or overlap with at least one or more parts of one or more sub-pixels.

[0058] The data driving circuit 120 can be disposed on one side or edge (such as the upper or lower part) of the display panel 110, and / or electrically connected to one side or edge (such as the upper or lower part) of the display panel 110, but not limited thereto. In one or more aspects, according to the driving scheme, panel design scheme, etc., the data driving circuit 120 can be located on both sides or edges (such as the upper and lower parts) of the display panel 110, or located in at least two of the four sides or edges (such as the upper, lower, left part, and right part) of the display panel 110, and / or electrically connected to both sides or edges (such as the upper and lower parts) of the display panel 110 or at least two of the four sides or edges (such as the upper, lower, left part, and right part) of the display panel 110, but not limited thereto.

[0059] The gate driving circuit 130 may be located on one side or edge (e.g., the left portion or the right portion) of the display panel 110 and / or electrically connected to one side or edge (e.g., the left portion or the right portion) of the display panel 110, but is not limited thereto. In one or more aspects, depending on the driving scheme, panel design scheme, etc., the gate driving circuit 130 may be located on both sides or edges (e.g., the left portion and the right portion) of the display panel 110, or in at least two of the four sides or edges (e.g., the upper portion, the lower portion, the left portion, and the right portion) of the panel 110, and / or electrically connected to both sides or edges (e.g., the left portion and the right portion) of the display panel 110 or at least two of the four sides or edges (e.g., the upper portion, the lower portion, the left portion, and the right portion) of the display panel 110, but is not limited thereto.

[0060] The display controller 140 may be implemented as a component separate from the data driving circuit 120 or incorporated into the data driving circuit 120 to be implemented as an integrated circuit.

[0061] The display controller 140 may be a timing controller used in typical display technologies, or may be a controller or control device capable of performing other control functions in addition to the functions of a typical timing controller. In one or more embodiments, the display controller 140 may be a controller or control device different from the timing controller, or may be a circuit or component included in the controller or control device. The display controller 140 may be implemented using various circuits or electronic components (e.g., integrated circuits (ICs), field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), processors, etc.).

[0062] The display controller 140 may be mounted on a printed circuit board, a flexible printed circuit, etc., and electrically connected to the gate driving circuit 120 and the data driving circuit 130 through a printed circuit board, a flexible printed circuit, etc.

[0063] The display controller 140 may send signals to and receive signals from the data driving circuit 120 through one or more predefined interfaces. For example, such interfaces may include a low voltage differential signal (LVDS) interface, an embedded clock point-to-point interface (EPI), a serial peripheral interface (SPI), etc.

[0064] In some aspects, the display device 100 may be a mobile terminal, such as a smart phone, a tablet computer, etc., or a monitor, a television (TV), etc. These devices may be configured in various types, sizes, and shapes. The display device 100 according to the aspects of the present disclosure is not limited thereto and may include various types, sizes, and shapes configured to display information or images.

[0065] Figure 2Shows an example configuration of a display panel 110 according to aspects of the present disclosure.

[0066] Referring Figure 2 , the display panel 110 may include a substrate SUB on which a plurality of sub-pixels SP are disposed and an encapsulation layer ENCAP above the substrate SUB. The encapsulation layer ENCAP may also be referred to as an encapsulation substrate or an encapsulation stack.

[0067] Referring Figure 2 , in an example where the display device 100 is a self-emitting display device, each of the plurality of sub-pixels SP disposed on the substrate SUB may include a light-emitting element ED and a sub-pixel circuit SPC for driving the light-emitting element ED.

[0068] Referring Figure 2 , the sub-pixel circuit SPC may include a plurality of transistors and at least one capacitor for driving the light-emitting element ED. The sub-pixel circuit SPC may drive the light-emitting element ED by providing a driving current to the light-emitting element ED in a predetermined timing sequence. The light-emitting element ED may emit light by being driven by the driving current.

[0069] The plurality of transistors may include a driving transistor DRT for driving the light-emitting element ED and a scanning transistor SCT configured to turn on or off according to a scan signal SC.

[0070] The driving transistor DRT may provide a driving current to the light-emitting element ED.

[0071] The scanning transistor SCT may be configured to control the electrical state of a corresponding node in the sub-pixel circuit SPC or control the state or operation of the driving transistor DRT.

[0072] The at least one capacitor may include a storage capacitor Cst configured to maintain a constant voltage during a display frame or a certain period of the display frame.

[0073] To drive one or more sub-pixels SP, at least one data signal VDATA (which is an image signal) and at least one scan signal SC (which is a gate signal) may be applied to the one or more sub-pixels SP. In addition, to drive one or more sub-pixels SP, a common pixel driving voltage including a first common driving voltage VDD and a second common driving voltage VSS may be applied to the one or more sub-pixels SP.

[0074] The light-emitting element ED may include a pixel electrode PE, an intermediate layer EL, and a common electrode CE. The intermediate layer EL may be disposed between the pixel electrode PE and the common electrode CE.

[0075] For example, the pixel electrode PE can be an electrode disposed in each sub-pixel SP, and the common electrode CE can be an electrode commonly disposed in multiple sub-pixels SP. For example, the pixel electrode PE can be an anode, and the common electrode CE can be a cathode. In another example, the pixel electrode PE can be a cathode, and the common electrode CE can be an anode. Hereinafter, for the sake of convenience of explanation, an example in which the pixel electrode PE is an anode and the common electrode CE is a cathode will be discussed.

[0076] In an example where the light-emitting element ED is an organic light-emitting diode, the intermediate layer EL can include a light-emitting layer EML, a first common intermediate layer COM1 located between the pixel electrode PE and the light-emitting layer EML, and a second common intermediate layer COM2 located between the light-emitting layer EML and the common electrode CE. The layer including the first common intermediate layer COM1 and the second common intermediate layer COM2 can be referred to as the common intermediate layer EL_COM.

[0077] The light-emitting layer EML can be disposed in each sub-pixel SP, and the common intermediate layer EL_COM can be commonly disposed on all or a part of multiple sub-pixels SP.

[0078] The light-emitting layer EML can be disposed in each light-emitting region, and the common intermediate layer EL_COM can be commonly disposed on all or a part of multiple light-emitting regions and all or a part of multiple non-light-emitting regions.

[0079] For example, the first common intermediate layer COM1 can include a hole injection layer (HIL), a hole transport layer (HTL), etc. The second common intermediate layer COM2 can include an electron transport layer (ETL), an electron injection layer (EIL), etc. However, the aspects of the present disclosure are not limited thereto.

[0080] The hole injection layer can inject holes from the pixel electrode PE into the hole transport layer, the hole transport layer can transport the holes to the light-emitting layer EML, the electron injection layer can inject electrons from the common electrode CE into the electron transport layer, and the electron transport layer can transport the electrons to the light-emitting layer EML.

[0081] For example, the common electrode CE can be electrically connected to the second common driving voltage line VSSL. The second common driving voltage VSS (which is a kind of common pixel driving voltage) can be applied to the common electrode CE through the second common driving voltage line VSSL. The pixel electrode PE can be directly or (through another transistor) indirectly electrically connected to the first node N1 of the corresponding driving transistor DRT of each sub-pixel SP. Herein, the second common driving voltage VSS can also be referred to as the "base voltage", and the second common driving voltage line VSSL can also be referred to as the "low power supply voltage line", "low voltage line", or "base voltage line".

[0082] Each light-emitting element ED may be formed by an overlap of a pixel electrode PE, a light-emitting layer in an intermediate layer EL, and a common electrode CE. Each light-emitting region may be formed by a corresponding light-emitting element ED. For example, the corresponding light-emitting region of each light-emitting element ED may include an overlapping region of the pixel electrode PE, the light-emitting layer in the intermediate layer EL, and the common electrode CE.

[0083] In one or more aspects, the light-emitting element ED may be an organic light-emitting diode (OLED), an inorganic light-emitting diode (LED), a quantum dot light-emitting element, etc. For example, in an example where the light-emitting element ED is an organic light-emitting diode OLED, the intermediate layer EL of the light-emitting element ED may be a layer containing an organic material.

[0084] The driving transistor DRT may be a transistor configured to supply a driving current to the light-emitting element ED. The driving transistor DRT may be connected between a first common driving voltage line VDDL and the light-emitting element ED.

[0085] The driving transistor DRT may include a first node N1, a second node N2, and a third node N3. The first node N1 may be electrically connected to the light-emitting element ED. A data signal VDATA may be applied to the second node N2. A first common driving voltage VDD may be applied to the third node N3 through the first common driving voltage line VDDL.

[0086] In the driving transistor DRT, the second node N2 may be a gate node, the first node N1 may be a source node or a drain node, and the third node N3 may be a drain node or a source node. Hereinafter, for the sake of convenience of explanation only, an example will be discussed based on the first node, the second node, and the third node (N1, N2, and N3) of the driving transistor DRT being a source node, a gate node, and a drain node, respectively. However, the aspects of the present disclosure are not limited thereto.

[0087] Figure 2 The scan transistor SCT included in the shown sub-pixel circuit SPC may be a switching transistor that enables a data signal VDATA (which is an image signal) to be provided to the second node N2 (which is the gate node of the driving transistor DRT).

[0088] The scan transistor SCT may be turned on or off by a scan signal SC (which is a kind of gate signal) applied through a scan line SCL (which is a kind of gate line GL), and controls the electrical connection between the second node N2 of the driving transistor DRT and the data line DL. The drain or source of the scan transistor SCT may be electrically connected to the data line DL. The source or drain of the scan transistor SCT may be electrically connected to the second node N2 of the driving transistor DRT. The gate of the scan transistor SCT may be electrically connected to the scan line SCL.

[0089] The storage capacitor Cst can be electrically connected between a first node N1 and a second node N2 of the driving transistor DRT. The storage capacitor Cst can include a first capacitor electrode electrically connected to or corresponding to the first node N1 of the driving transistor DRT, and a second capacitor electrode electrically connected to or corresponding to the second node N2 of the driving transistor DRT.

[0090] The storage capacitor Cst can be an external capacitor intentionally designed to be located or disposed outside the driving transistor DRT. Thus, it is different from an internal capacitor such as a parasitic capacitor (e.g., Cgs, Cgd) that can be formed between the first node N1 and the second node N2 of the driving transistor DRT.

[0091] Each of the driving transistor DRT and the scanning transistor SCT can be an n-type transistor or a p-type transistor.

[0092] The display panel 110 can have a top-emitting structure or a bottom-emitting structure.

[0093] In an example where the display panel 110 has a top-emitting structure, at least a part of the sub-pixel circuit SPC can overlap at least a part of the light-emitting element ED in the vertical direction. In such a configuration, the area or size of the corresponding light-emitting region can be increased, and the corresponding aperture ratio can be increased.

[0094] In an example where the display panel 110 has a bottom-emitting structure, the sub-pixel circuit SPC can not overlap the light-emitting element ED in the vertical direction.

[0095] As Figure 2 shown, the sub-pixel circuit SPC can include two transistors (2T: DRT and SCT) and one capacitor (1C: Cst) (which can be referred to as a "2T1C structure"). In some implementations, it can further include one or more transistors and / or further include one or more capacitors.

[0096] For example, the sub-pixel circuit SPC can have an 8T1C structure including 8 transistors and 1 capacitor. In another example, the sub-pixel circuit SPC can have a 6T2C structure including 6 transistors and 2 capacitors. In yet another example, the sub-pixel circuit SPC can have a 7T1C structure including 7 transistors and 1 capacitor.

[0097] The type and number of gate signals provided to the sub-pixel SP, and / or the type and number of gate lines connected to the sub-pixel SP may vary according to the structure of the corresponding sub-pixel circuit SPC. In addition, the type and number of common pixel driving voltages provided to the sub-pixel SP may vary according to the structure of the corresponding sub-pixel circuit SPC.

[0098] Since the circuit elements included in each sub-pixel SP (in particular, the light-emitting element ED implemented with an organic light-emitting diode containing an organic material) are vulnerable to external moisture or oxygen, an encapsulation layer ENCAP may be provided in the display panel 110 to prevent or at least reduce the infiltration of external moisture or oxygen into such circuit elements. The encapsulation layer 200 may be provided in various shapes or configurations to prevent the light-emitting element ED from coming into contact with moisture or oxygen.

[0099] Figure 3 is a plan view showing an example region of the sub-pixel SP provided in the active region of the display panel 110 according to an aspect of the present disclosure.

[0100] Referring to Figure 3 , in one or more aspects, at least one sub-pixel among the plurality of sub-pixels SP included in the display device 100 may include a region overlapping with the bank 290 and a region overlapping with the opening OP of the bank 290.

[0101] The region overlapping with the bank 290 may include a non-light-emitting region NEA. A plurality of signal lines (201, 202, 205, 206, 207, and 208), a light-shielding portion 210, and a plurality of active layers (221, 222, and 223) may be provided in the non-light-emitting region NEA. The plurality of signal lines may include a first signal line to a sixth signal line (201, 202, 205, 206, 207, and 208), and the plurality of active layers may include a first active layer to a third active layer (221, 222, and 223). The non-light-emitting region NEA may include a circuit region.

[0102] Referring to Figure 3 , a plurality of transistors (T1, T2, and T3) and a storage capacitor Cst for driving the light-emitting element included in the sub-pixel SP may be provided in the region overlapping with the bank 290.

[0103] For example, corresponding light-emitting elements including a first electrode, an organic layer, and a second electrode may be provided in respective openings OP of the bank portion 290. In one or more aspects, color filters (281, 282) may be provided in a region overlapping with the opening OP, but the aspects of the present disclosure are not limited thereto. For example, color filters (281, 282) may be provided only in a part of the sub-pixels SP included in the display device 100, or color filters (281, 282) may not be provided in all the sub-pixels SP included in the display device 100.

[0104] Referring Figure 3 , a corresponding light-emitting region EA of each light-emitting element included in the display device 100 may be formed in a region overlapping with respective openings OP of the bank portion 290.

[0105] Referring Figure 3 , at least one opening CON may be provided in one opening OP of the bank portion 290 located in one sub-pixel SP.

[0106] At least one opening CON provided in one opening OP may be formed such that a plurality of openings CON spaced apart from each other are provided in the opening OP. For example, the plurality of openings CON may be provided spaced apart in a column direction or a row direction in the opening OP.

[0107] Referring Figure 3 , for example, the plurality of openings CON may be provided in such a pattern that one or more openings CON having a shape of an angle bracket opening to the right are spaced apart in the column direction, and one or more openings CON having a shape of an angle bracket opening to the left are spaced apart in the column direction.

[0108] Although Figure 3 is shown that the plurality of openings provided in at least one sub-pixel SP are configured in a shape of an angle bracket, however, the opening CON of the display device 100 according to the aspects of the present disclosure may be formed in various shapes.

[0109] Referring Figure 3 , the plurality of openings CON overlapping with one opening OP in at least one sub-pixel SP may overlap with the color filters (281, 282).

[0110] Figure 4 is a cross-sectional view taken along line A-B of Figure 3 . Figure 5 is a cross-sectional view showing the light-emitting region of Figure 4 .

[0111] Referring Figure 4 and Figure 5, a first planarization layer 431 may be provided. The first planarization layer 431 may include holes in a region corresponding to the contact hole CTH. The first planarization layer 431 may include an organic insulating material or an inorganic insulating material, but aspects of the present disclosure are not limited thereto.

[0112] The first pixel electrode 451 may be provided on the first planarization layer 431. The first pixel electrode 451 may be provided adjacent to the holes of the first planarization layer 341 provided in the region corresponding to the contact hole CTH.

[0113] The second planarization layer 432 may be provided on the first pixel electrode 451.

[0114] The second planarization layer 432 may include openings CON (i.e., Figure 2 at least a part of the plurality of openings CON included therein). The second planarization layer 432 may include an organic insulating material or an inorganic insulating material, but aspects of the present disclosure are not limited thereto.

[0115] Each opening CON may include a lower surface 441 where the second planarization layer 432 is removed and the first pixel electrode 451 is exposed. Each opening CON may include an inclined surface 442 extending from the lower surface 441 along the side surface of the second planarization layer 432.

[0116] The second planarization layer 432 may include an upper surface extending from the side surface or the inclined surface 442 of the second planarization layer 432.

[0117] The second pixel electrode 452 may be provided on the upper surface of the second planarization layer 432.

[0118] The second pixel electrode 452 may include two or more second pixel electrode portions (4521, 4522, 4523) separated by one or more openings CON.

[0119] The second pixel electrode 452 may be configured to extend from the second planarization layer 432 to the circuit region where the contact hole CTH is located. The second pixel electrode 452 may extend to the circuit region and be electrically connected to the thin film transistor through the contact hole CTH.

[0120] The first pixel electrode 451 and the second pixel electrode 452 may be electrically connected in a contact region CTA on the side surface of the second planarization layer 432. For example, a part 4521 of the second pixel electrode 452 and one end or edge of the first pixel electrode 451 may be electrically connected at the contact region CTA.

[0121] The first pixel electrode 451 and the second pixel electrode 452 may form a pixel electrode 250 included in one sub-pixel SP.

[0122] The pixel electrode 250 may include a transparent conductive material. The transparent conductive material may include a transparent conductive oxide (TCO). For example, the transparent conductive oxide (TCO) may include one or more of indium zinc oxide (IZO), indium tin oxide (ITO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), aluminum-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO), antimony tin oxide (ATO), fluorine-doped transparent oxide (FTO), etc. However, the material of the pixel electrode 250 according to aspects of the present disclosure is not limited thereto. For example, the pixel electrode 250 may include any material having a high light transmittance and high conductivity.

[0123] The first pixel electrode 451 and the second pixel electrode 452 may include the same transparent conductive oxide, for example. In one or more aspects, the first pixel electrode 451 and the second pixel electrode 452 may include different transparent conductive oxides.

[0124] For example, in the display device 100 according to aspects of the present disclosure, the first pixel electrode 451 may include a high refractive index electrode material, and the second pixel electrode 452 may include a low refractive index electrode material. For example, the first pixel electrode 451 may include indium zinc oxide (IZO), and the second pixel electrode 452 may include indium tin oxide (ITO).

[0125] Referring to Figure 4 and Figure 5 , the first pixel electrode 451 and the second pixel electrode 452 may be configured not to overlap each other in one or more openings CON.

[0126] Referring to Figure 4 and Figure 5 , a bank 290 may be provided on a part of the upper surface of the second pixel electrode 452. The bank 290 may have at least one opening OP in one sub-pixel.

[0127] The bank 290 may include a transparent organic material or a black organic material.

[0128] Referring to Figure 4 and Figure 5 , the opening OP of the bank 290 may overlap with the opening CON provided between the respective parts of the second pixel electrode 452.

[0129] Referring to Figure 4 and Figure 5 , the light-emitting layer 260 may be provided on the pixel electrode 250, the bank 290, and the second planarization layer 432, and the common electrode 270 may be provided on the light-emitting layer 260.

[0130] Figure 4 and Figure 5It is shown that the light-emitting layer 260 and the common electrode 270 have a single-layer structure, but aspects of the present disclosure are not limited thereto. For example, at least one of the light-emitting layer 260 and the common electrode 270 may have a multi-layer structure.

[0131] Referring to Figure 4 and Figure 5 , the light-emitting layer 260 and the common electrode 270 may be disposed on the bank portion 290 and in the opening OP of the bank portion 290.

[0132] The common electrode 270 may include a conductive material capable of reflecting light. For example, the common electrode 270 may include any one of metals such as aluminum (Al), magnesium (Mg), gold (Au), silver (Ag), copper (Cu), tungsten (W), molybdenum (Mo), chromium (Cr), tantalum (Ta), titanium (Ti), etc., or any one of one or more alloys thereof, but aspects of the present disclosure are not limited thereto.

[0133] Referring to Figure 4 and Figure 5 , the light-emitting layer 260 and the common electrode 270 may be disposed in one or more openings CON formed in the second planarization layer 432 and overlapping the opening OP of the bank portion 290. In one or more aspects, the light-emitting layer 260 and the common electrode 270 may also be disposed in one or more regions where one or more portions of the second pixel electrode 452 expose the upper surface of the second planarization layer 432 in one or more regions adjacent to one or more openings CON formed in the second planarization layer 432.

[0134] Referring to Figure 4 and Figure 5 , the light-emitting layer 260 and the common electrode 270 may be formed along the morphology of the second pixel electrode 452 and the second planarization layer 432 in the opening OP of the bank portion 290. Accordingly, the light-emitting layer 260 and the common electrode 270 may have an inclination in the opening OP of the bank portion 290.

[0135] Referring to Figure 4 and Figure 5 , a plurality of light-emitting regions (EA1, EA2, EA3) may be formed in one sub-pixel.

[0136] Referring to Figure 4 and Figure 5 , the first pixel electrode 451, the light-emitting layer 260, and the common electrode 270 may be configured to be stacked on the lower surface 441 of one or more openings CON. The first light-emitting region EA1 may be formed in a region corresponding to the lower surface 441. The first light-emitting region EA1 may be a light-emitting region through which a part of the light L1 emitted from the first pixel electrode 451, the light-emitting layer 260, and the common electrode 270 is guided to the outside of the display device 100.

[0137] Reference Figure 4 and Figure 5 , the light-emitting layer 260 and the common electrode 270 may be configured to be stacked on the inclined surface 442 of one or more openings CON. A second light-emitting region EA2 may be formed in a region corresponding to the inclined surface 442. The second light-emitting region EA2 may be a light-emitting region through which a part of the light L2 among the light emitted from the second pixel electrode 452, the light-emitting layer 260, and the common electrode 270 travels laterally and is reflected by the common electrode 270 provided on the inclined surface 442 and then guided to the outside of the display device 100.

[0138] Reference Figure 4 and Figure 5 , the second pixel electrode 452, the light-emitting layer 260, and the common electrode 270 may be configured to be stacked on the upper surface of the second planarization layer 432. A third light-emitting region EA3 may be formed on a region corresponding to the upper surface of the second planarization layer 432. The third light-emitting region EA3 may be a light-emitting region through which a part of the light L3 among the light emitted from the first pixel electrode 452, the light-emitting layer 260, and the common electrode 270 is guided to the outside of the display device 100.

[0139] Reference Figure 4 and Figure 5 , the second light-emitting region EA2 may be configured to surround the first light-emitting region EA1. The third light-emitting region EA3 may be configured to surround the second light-emitting region EA2.

[0140] According to these configurations, based on the structure in which the second planarization layer 432 has at least one opening CON and an upper surface in one sub-pixel, the light emitted from the first light-emitting region EA1 provided on the lower surface 441 of the opening CON and the third light-emitting region EA3 provided on the upper surface of the second planarization layer 342 can be guided to the outside of the display device 100. In this case, among the light emitted from the third light-emitting region EA3, a part of the light traveling laterally may be reflected by the common electrode 270 provided on the inclined surface 442 of the opening CON and then guided to the outside of the display device 100. Therefore, since the light emitted from the light-emitting layer 260 can be guided to the outside of the display device 100 through the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 without loss, the display device 100 may have the ability to improve the light-emitting efficiency.

[0141] Figures 6A to 6E is a schematic plan view showing an example of the structure of four sub-pixels in the display device 100 according to an aspect of the present disclosure.

[0142] Reference Figures 6A to 6E, in one or more aspects, in the display device 100, a plurality of openings CON may be formed in a light-emitting region (which is a region corresponding to the opening OP of the bank 290). The plurality of openings CON may be configured to be spaced apart from each other within a single sub-pixel. The plurality of openings CON may be arranged in a polygon shape. The plurality of openings CON may be spaced apart from each other in the column direction or the row direction within a single sub-pixel.

[0143] Refer to Figure 6A , the plurality of openings CON provided in one opening OP of the bank 290 may be arranged in a structure in which polygons having open corners (a shape in which no opening CON is provided at the corners of the polygon) are connected to each other.

[0144] For example, the plurality of openings CON may be arranged in a structure in which six openings CON form a single hexagon having open corners, and a plurality of hexagons each including six openings CON are provided. In this example, one hexagon may be configured to share at least one opening CON with an adjacent hexagon.

[0145] Refer to Figure 6B and Figure 6C , the plurality of openings CON may be spaced apart from each other. Refer to Figure 6B , the plurality of openings CON may be arranged such that each opening CON extends longitudinally in the column direction and the plurality of openings CON are spaced apart from each other in the row direction. Refer to Figure 6C , the plurality of openings CON may be arranged such that each opening CON extends longitudinally in the row direction and the plurality of openings CON are spaced apart from each other in the column direction.

[0146] Refer to Figure 6D and Figure 6E , the plurality of openings CON may be arranged in a predetermined pattern and spaced apart from each other. Refer to Figure 6D , the plurality of openings CON may be arranged in a pattern in which an opening CON having a right-open angle bracket shape and an opening CON having a left-open angle bracket shape are spaced apart in the column direction. Refer to Figure 6E , the plurality of openings CON may be arranged in a pattern in which an opening CON having an upward-open angle bracket shape and an opening CON having a downward-open angle bracket shape are spaced apart in the column direction.

[0147] Figures 7A to 7J An example method of manufacturing a display device (e.g., the display device 100 discussed above) according to an aspect of the present disclosure is shown.

[0148] First, as Figure 7AAs shown, a first planarization layer 431 may be formed on the lower insulating layer 721 and the upper insulating layer 722. The first planarization layer 431 may be patterned to form holes in regions corresponding to the contact holes.

[0149] Next, as Figure 7B shown, a first pixel electrode material layer 451m may be formed on the first planarization layer 431 and the upper insulating layer 722. Thereafter, a second planarization layer 432 may be coated and patterned on the first pixel electrode material layer 451m.

[0150] Next, as Figure 7C shown, a portion of the first pixel electrode material layer 451m may be etched through a wet etching (W / E) process. The wet etching process may be a process of etching the first pixel electrode material layer 451m to form the first pixel electrode 451.

[0151] Next, as Figure 7D shown, a portion of the upper insulating layer 722 may be etched through a wet etching (W / E) process. The wet etching process may be a process of etching a portion of the upper insulating layer 722 to form the contact holes.

[0152] Next, as Figure 7E shown, respective portions of the first planarization layer 431 and the second planarization layer 432 may be removed through an ashing process. The ashing process may be a process of removing portions of the first planarization layer 431 and the second planarization layer 432 such that a portion of the first pixel electrode 451 disposed between the first planarization layer 431 and the second planarization layer 432 may be exposed in the contact region.

[0153] Next, as Figure 7F shown, a second pixel electrode material layer 452m may be formed on the top surface. The second pixel electrode material layer 452m may contact an exposed portion of the first pixel electrode 451 at the contact region CTA.

[0154] Next, as Figure 7G and Figure 7H shown, a photoresist PR may be coated on a portion of the second pixel electrode material layer 452m, and a portion of the second pixel electrode material layer 452m may be etched through a wet etching process. Thereby, a second pixel electrode may be formed. The wet etching (W / E) process may be a process of removing a portion of the second pixel electrode material layer 452m to form a second pixel electrode having holes.

[0155] Subsequently, as Figure 7IAs shown, a part of the exposed hole of the second planarization layer 432 in the second pixel electrode 452 can be removed through an ashing process. After performing the ashing process, the photoresist PR can be removed. The ashing process can be a process of forming an opening by removing a part of the second planarization layer 432. Figure 7I The second pixel electrode part 4521 shown can be one part of two or more parts of the second pixel electrode 452.

[0156] Next, as Figure 7J shown, a bank 290 can be formed on the second pixel electrode part 4521. After forming the bank 290, the light-emitting layer 260 and the common electrode 270 can be formed in sequence.

[0157] Figure 8 is a cross-sectional view schematically showing an example structure of a display device 100 according to an aspect of the present disclosure.

[0158] Referring to Figure 8 , in one or more aspects, the display panel 100 can include at least one thin-film transistor and at least one light-emitting element disposed above a substrate 800.

[0159] In one or more aspects, a plurality of signal lines (811 and 814) and a light-shielding part 812 can be provided on the substrate 800. Figure 8 Each of the signal lines (811 and 814) can be Figure 3 any one of the plurality of signal lines (201 and 202) shown.

[0160] Each of the signal lines (811 and 814) can include a plurality of layers.

[0161] For example, the signal line 811 can include a first layer 811a and a second layer 811b provided on the first layer 811a, and the signal line 814 can include a fifth layer 814a and a sixth layer 814b provided on the fifth layer 814a. The light-shielding part 812 can also include a plurality of layers. For example, the light-shielding part 812 can include a third layer 812a and a fourth layer 812b provided on the third layer 812a.

[0162] The first layer 811a, the third layer 812a, and the fifth layer 814a can contain the same material, and the second layer 811b, the fourth layer 812b, and the sixth layer 814b can contain the same material.

[0163] The first insulating layer 801 and the second insulating layer 802 can be provided on the plurality of signal lines (811 and 814) and the light-shielding part 812.

[0164] A thin-film transistor and a plurality of electrodes can be provided on the second insulating layer 802.

[0165] For example, referring to Figure 8 , the first active layer 820, the second active layer 821, and the third active layer 822 can be disposed on the second insulating layer 802 in the active region of the display panel.

[0166] At least one of the first to third active layers (820, 821, 822) can include an oxide semiconductor material. The oxide semiconductor material can be a semiconductor material obtained by doping an oxide material to control conductivity and adjust the bandgap, and can be a transparent semiconductor material with a relatively wide bandgap. For example, the oxide semiconductor material can include indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium gallium oxide (IGO), indium zinc oxide (IZO), cadmium oxide (CdO), indium oxide (InO), zinc tin oxide (ZTO), zinc indium tin oxide (ZITO), indium gallium zinc tin oxide (IGZTO), etc.

[0167] A gate insulating layer 835 can be disposed on the first active layer 820 and the second active layer 821.

[0168] Each of the first to third active layers (820, 821, 822) can be in a conductive state in a region not overlapping with the gate insulating layer 835. For example, each part of the first to third active layers (820, 821, 822) that does not overlap with the gate insulating layer 835 can be a conductive part.

[0169] Referring to Figure 8 , the third active layer 822 can become conductive and serve as an electrode, and the third active layer 822 can form a storage capacitor Cst with the signal line 812 disposed below the third active layer 822.

[0170] Referring to Figure 8 , the gate insulating layer 835 can be disposed on a part of the upper surface of the first active layer 820 and a part of the upper surface of the second active layer 821.

[0171] The first active layer 820 can include an auxiliary electrode 831. The auxiliary electrode 831 can be disposed in the conductive part of the first active layer 820. The auxiliary electrode 831 can electrically connect the conductive part of the first active layer 820 to the source electrode 841 and the drain electrode 842.

[0172] In the active region, the source electrode 841, the drain electrode 842, and the gate electrode 843 can be disposed on the gate insulating layer 835. Figure 8 An example is shown where the electrode 841 is the source electrode and the electrode 842 is the drain electrode, but the aspects of the present disclosure are not limited thereto. For example, the electrode 841 can be the drain electrode and the electrode 842 can be the source electrode.

[0173] In one or more aspects, in the non-active area of the display panel 110, the source electrode 841, the drain electrode 842, and the gate electrode 843 may be disposed in the same layer and may include the same material. In one or more aspects, as Figure 8 shown, the pad electrode 845 may be disposed on the second insulating layer 802.

[0174] For example, the source electrode 841, the drain electrode 842, the gate electrode 843, and the pad electrode 845 may include multiple layers.

[0175] For example, each of the source electrode 841, the drain electrode 842, the gate electrode 843, and the pad electrode 845 may include two or more layers, but the aspects of the present disclosure are not limited thereto. For example, at least one of the source electrode 841, the drain electrode 842, the gate electrode 843, and the pad electrode 845 may be a single layer.

[0176] The first layer 841a of the source electrode 841, the first layer 842a of the drain electrode 842, the first layer 843a of the gate electrode 843, and the first layer 845a of the pad electrode 845 may include the same material, and the second layer 841b of the source electrode 841, the second layer 842b of the drain electrode 842, the second layer 843b of the gate electrode 843, and the second layer 845b of the pad electrode 845 may include the same material. However, the aspects of the present disclosure are not limited thereto. For example, the first layer 841a of the source electrode 841, the first layer 842a of the drain electrode 842, the first layer 843a of the gate electrode 843, and the first layer 845a of the pad electrode 845 may include different materials, and the second layer 841b of the source electrode 841, the second layer 842b of the drain electrode 842, the second layer 843b of the gate electrode 843, and the second layer 845b of the pad electrode 845 may include different materials.

[0177] Above the substrate 800 on which the source electrode 841, the drain electrode 842, and the gate electrode 842 are disposed in the active area, a third insulating layer 803 may be provided.

[0178] A color filter 850 may be provided on the third insulating layer 803. The color filter 850 may overlap with a plurality of light-emitting regions formed in one sub-pixel.

[0179] A first planarization layer 431 may be provided on the color filter 850.

[0180] The first planarization layer 431 may include holes for enabling electrical connection between the light-emitting element and the thin-film transistor. The holes in the first planarization layer 431 may overlap with the holes in the third insulating layer 803 to form contact holes CTH.

[0181] A first pixel electrode 451 may be provided on the first planarization layer 431.

[0182] The second planarization layer 432 may be provided on the first planarization layer 431 and the first pixel electrode 451.

[0183] The second planarization layer 432 may include at least one opening in one sub-pixel.

[0184] At least one opening may include a lower surface and an inclined surface extending from the lower surface along the side surface of the second planarization layer 432. The second planarization layer 432 may include an upper surface extending from the side surface or the inclined surface.

[0185] The first pixel electrode 451 may be exposed on the lower surface of at least one opening.

[0186] For example, referring to Figure 8 , at least one opening of the second planarization layer 432 may overlap with a part of the color filter 850. However, aspects of the present disclosure are not limited thereto. For example, at least one opening of the second planarization layer 432 may even be provided in a sub-pixel where the color filter 850 is not provided.

[0187] Referring to Figure 8 , the side surface of the second planarization layer 432 may be located at a position adjacent to the hole in the first planarization layer 431 and is arranged such that the first pixel electrode 451 cannot be covered by the side surface of the second planarization layer 432.

[0188] The second pixel electrode 452 may be provided on the second planarization layer 432. In one or more aspects, in a cross-sectional view, the second pixel electrode 452 may include a plurality of second pixel electrode portions (4521, 4522, and 4523) spaced apart from each other. In such a configuration, a corresponding one of the openings formed in the second planarization layer 432 may be located between adjacent second pixel electrode portions among the second pixel electrode portions (4521, 4522, and 4523). The second pixel electrode 452 may be configured to extend to a portion of the first planarization layer 431 provided in the circuit region as the non-light-emitting area NDA.

[0189] Referring to Figure 8 , the first pixel electrode 451 and the second pixel electrode 452 may be electrically connected at the contact area CTA on the side surface of the second planarization layer 432. For example, a part 4521 of the second pixel electrode 452 and one end or edge of the first pixel electrode 451 may be electrically connected at the contact area CTA.

[0190] Referring to Figure 8, the second pixel electrode 452 can be electrically connected to the source electrode 841 of the thin-film transistor through the contact hole CTH. For example, since a part 4521 of the second pixel electrode 452 is electrically connected to the thin-film transistor, the pixel electrode 250 including the first pixel electrode 451 and the second pixel electrode 452 can be electrically connected to the thin-film transistor.

[0191] As Figures 6A to 6E shown, at least one opening CON can be provided in one sub-pixel. The second pixel electrode 452 can have a structure in which at least one hole is formed in at least a part of the second pixel electrode 452 corresponding to the at least one opening CON. For example, at least one hole formed in the second pixel electrode 452 can correspond to at least a part of the first pixel electrode 451 where the first pixel electrode 451 is exposed.

[0192] Referring to Figure 8 , a bank 290 can be provided above the substrate 800 on which the second pixel electrode 452 is provided.

[0193] For example, the bank 290 can include at least one opening OP in one sub-pixel.

[0194] A plurality of openings can be provided in the opening OP of the bank 290. In one or more aspects, a plurality of light-emitting regions can be formed in the opening OP of the bank 290.

[0195] For example, a first light-emitting region and a second light-emitting region formed on the lower surface and the inclined surface of the opening, respectively, and a third light-emitting region formed on the upper surface of the second planarization layer 432 can be formed in the opening OP.

[0196] Referring to Figure 8 , the light-emitting layer 260 and the common electrode 270 of the light-emitting element can be sequentially provided above the substrate 800 on which the bank 290 is provided.

[0197] For example, the first pixel electrode 451, the light-emitting layer 260, and the common electrode 270 can be provided on the lower surface of the opening. The light-emitting layer 260 and the common electrode 270 can be provided on the inclined surface of the opening. The second pixel electrode 452, the light-emitting layer 260, and the common electrode 270 can be provided on the upper surface of the second planarization layer 432.

[0198] Since the common electrode 270 including the reflective electrode is provided on the inclined surface, the light emitted from the light-emitting layer 260 provided between the second pixel electrode 452 and the common electrode 270 can be reflected by the inclined surface of the common electrode 270, and then, guided to the outside of the substrate 800.

[0199] According to aspects described herein, a display device capable of eliminating or reducing display artifacts such as defective image rendering and improving luminous efficiency can be provided.

[0200] According to aspects described herein, a display device capable of generating improved luminous efficiency based on a structure in which a sub-pixel includes a double-layer pixel electrode can be provided.

[0201] According to aspects described herein, a display device capable of eliminating or reducing display artifacts such as defective image rendering based on a structure in which a sub-pixel includes a double-layer pixel electrode can be provided.

[0202] According to aspects described herein, a display device capable of driving at low power with high brightness characteristics based on a structure in which a sub-pixel includes a plurality of light-emitting regions emitting light of the same color can be provided.

[0203] The above exemplary embodiments will be briefly described below.

[0204] According to an exemplary embodiment described herein, a display device can be provided, the display device including: a substrate on which a plurality of sub-pixels are provided, each of the plurality of sub-pixels including a plurality of light-emitting regions; a first planarization layer provided above the substrate; a first pixel electrode provided on the first planarization layer; a second planarization layer provided on the first pixel electrode, the second planarization layer including at least one opening exposing at least a part of the upper surface of the first pixel electrode; a second pixel electrode provided on the second planarization layer; a bank provided on a part of the upper surface of the second pixel electrode, and the bank including an opening in each of the plurality of sub-pixels; a light-emitting layer provided in the opening; and a common electrode provided on the light-emitting layer.

[0205] In one or more aspects, at least one opening can be provided in each of the plurality of sub-pixels.

[0206] In one or more aspects, the first pixel electrode and the second pixel electrode may not overlap each other in at least one opening.

[0207] In one or more aspects, the second pixel electrode may include at least one hole provided in at least one region corresponding to at least one opening.

[0208] In one or more aspects, each of the plurality of sub-pixels may include a circuit region, and a contact region in which the first pixel electrode and the second pixel electrode are electrically connected may be provided in the circuit region.

[0209] In one or more aspects, each of the plurality of sub-pixels may include a transistor, and the second pixel electrode may be electrically connected to the transistor.

[0210] In one or more aspects, at least one opening may include a lower surface and an inclined surface extending from the lower surface along a side surface of the second planarization layer, and the second planarization layer may include an upper surface extending from the inclined surface.

[0211] In one or more aspects, the first pixel electrode, the light-emitting layer, and the common electrode may be configured to be stacked in a region corresponding to the lower surface.

[0212] In one or more aspects, the light-emitting layer and the common electrode may be configured to be stacked in a region corresponding to the inclined surface.

[0213] In one or more aspects, the second pixel electrode, the light-emitting layer, and the common electrode may be configured to be stacked in a region corresponding to the upper surface of the second planarization layer.

[0214] In one or more aspects, the common electrode may include a reflective material.

[0215] In one or more aspects, the plurality of light-emitting regions may include a first light-emitting region provided in a region corresponding to the lower surface.

[0216] In one or more aspects, the plurality of light-emitting regions may include a second light-emitting region provided in a region corresponding to the inclined surface.

[0217] In one or more aspects, the plurality of light-emitting regions may include a third light-emitting region provided in a region corresponding to the upper surface of the second planarization layer.

[0218] In one or more aspects, the second light-emitting region may be configured to surround the first light-emitting region.

[0219] In one or more aspects, the third light-emitting region may be configured to surround the second light-emitting region.

[0220] In one or more aspects, the display device may further include a color filter provided between the substrate and the first planarization layer, and at least one opening may overlap a part of the color filter.

[0221] According to an exemplary embodiment described herein, a display device may be provided, the display device including a plurality of light-emitting regions provided in one sub-pixel, the plurality of light-emitting regions including at least one first light-emitting region provided within one sub-pixel, a second light-emitting region surrounding the at least one first light-emitting region, and a third light-emitting region surrounding the second light-emitting region, and the display device including at least one opening located in one sub-pixel, the at least one opening enabling the at least one first light-emitting region and the second light-emitting region to be provided in the opening.

[0222] In one or more aspects, the openings may be spaced apart from each other within a sub-pixel and arranged in a polygon shape.

[0223] In one or more aspects, the openings may be spaced apart from each other within a sub-pixel in a column direction or a row direction.

[0224] The foregoing description is provided to enable a person skilled in the art to make, use, and practice the technical features of the present disclosure, and is provided as an example in the context of a particular application and its requirements. Various modifications, additions, and substitutions to the described embodiments will be apparent to a person skilled in the art, and the principles described herein may be applied to other embodiments and applications without departing from the scope of the present invention. The above specification and drawings merely provide examples of the technical features of the present aspect for illustrative purposes. That is, the disclosed embodiments are intended to illustrate the scope of the technical features of the present invention.

Claims

1. A display device, comprising: a substrate, on which a plurality of sub-pixels are provided, and each of the plurality of sub-pixels includes a plurality of light-emitting regions; a first planarization layer, disposed above the substrate; a first pixel electrode, disposed on the first planarization layer; a second planarization layer, disposed on the first pixel electrode, and the second planarization layer includes at least one opening exposing at least a part of the upper surface of the first pixel electrode; a second pixel electrode, disposed on the second planarization layer; a bank, disposed on a part of the upper surface of the second pixel electrode, and the bank includes an opening in each of the plurality of sub-pixels; a light-emitting layer, disposed in the opening; and a common electrode, disposed on the light-emitting layer.

2. The display device according to claim 1, wherein The at least one opening is provided in each of the plurality of sub-pixels.

3. The display device according to claim 1, wherein, The first pixel electrode and the second pixel electrode do not overlap with each other in the at least one opening.

4. The display device according to claim 1, wherein, The second pixel electrode includes at least one hole provided in at least one region corresponding to the at least one opening.

5. The display device according to claim 1, wherein, Each of the plurality of sub-pixels includes a circuit region, and a contact region is provided in the circuit region, in which the first pixel electrode and the second pixel electrode are electrically connected.

6. The display device according to claim 5, wherein, Each of the plurality of sub-pixels includes a transistor, and the second pixel electrode is electrically connected to the transistor.

7. The display device according to claim 1, wherein, The at least one opening includes a lower surface and an inclined surface extending from the lower surface along a side surface of the second planarization layer, and the second planarization layer includes an upper surface extending from the inclined surface.

8. The display device according to claim 7, wherein, The first pixel electrode, the light-emitting layer, and the common electrode are stacked in a region corresponding to the lower surface.

9. The display device according to claim 7, wherein, The light-emitting layer and the common electrode are stacked in a region corresponding to the inclined surface.

10. The display device according to claim 7, wherein, The second pixel electrode, the light-emitting layer, and the common electrode are stacked in a region corresponding to the upper surface of the second planarization layer.

11. The display device according to claim 1, wherein, The common electrode includes a reflective material.

12. The display device according to claim 7, wherein, The plurality of light-emitting regions includes a first light-emitting region provided in a region corresponding to the lower surface.

13. The display device according to claim 12, wherein, The plurality of light-emitting regions includes a second light-emitting region provided in a region corresponding to the inclined surface.

14. The display device according to claim 13, wherein, The plurality of light-emitting regions includes a third light-emitting region provided in a region corresponding to the upper surface of the second planarization layer.

15. The display device according to claim 14, wherein, The second light-emitting region surrounds the first light-emitting region.

16. The display device according to claim 15, wherein, The third light-emitting region surrounds the second light-emitting region.

17. The display device according to claim 1, further comprising a color filter disposed between the substrate and the first planarization layer, Among them, and the at least one opening overlaps with a part of the color filter.

18. A display device, comprising: a plurality of light-emitting regions, provided in a sub-pixel, and the plurality of light-emitting regions includes at least one first light-emitting region provided in the sub-pixel, a second light-emitting region surrounding the at least one first light-emitting region, and a third light-emitting region surrounding the second light-emitting region; and At least one opening is provided within the one sub-pixel such that the at least one first light-emitting region and the second light-emitting region can be provided.

19. The display device according to claim 18, wherein, Two or more openings included in the at least one opening are spaced apart from each other within the one sub-pixel and are arranged in a polygon.

20. The display device according to claim 18, wherein Two or more openings included in the at least one opening are spaced apart from each other within the one sub-pixel in a column direction or a row direction.

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