Cascade coding method, cascade decoding method and device

Abstract

The invention discloses a cascade coding method and device and a cascade decoding method and device. And the sending end obtains the second bit sequence, performs LDPC coding on the second bit sequence based on the check matrix to obtain a third bit sequence, and outputs the third bit sequence. Correspondingly, the receiving end obtains the to-be-decoded information of the third bit sequence, decodes the to-be-decoded information of the first bit sequence and the to-be-decoded information of the third bit sequence, and determines K1 first bits and K2 second bits based on a decoding result. Wherein the second bit sequence comprises a first bit sequence with the length of N1 and Kz second bits, and the first bit sequence is obtained by coding based on K1 first bits. The check matrix is determined based on the corresponding relation of the first information columns and the first base graph or the check matrix corresponds to the second base graph. According to the embodiment of the invention, the key core bits are protected through the coupled LDPC codes, and the decoding performance is effectively ensured.

Description

Concatenated encoding method, concatenated decoding method and device Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a cascade encoding method, a cascade decoding method and a device. Background Art

[0002] Low-density parity-check (LDPC) code is a channel coding scheme close to the Shannon line, which has the characteristics of good performance and low complexity. It has been identified by the 3rd Generation Partnership Project (3GPP) as the fifth generation (5G) th generation, 5G) data channel coding scheme.

[0003] For example, LDPC codes can address the problem of partial decodability, as shown below: Information bits contain a small number of critical core bits, which require more precise protection. Even if overall decoding fails, the critical core bits can still be recovered. These critical core bits represent a certain percentage of core bits and are the more important portion of the information bits.

[0004] Therefore, how to encode the key core bits in the information bits and other non-key core bits in the information bits needs to be solved urgently.

[0005] Summary of the Invention

[0006] The embodiments of the present application provide a cascade coding method, a cascade decoding method and an apparatus, which encode key core bits by coupled LDPC codes to ensure decoding performance.

[0007] In a first aspect, an embodiment of the present application provides a cascade coding method, the method comprising: obtaining a second bit sequence, the second bit sequence comprising a first bit sequence of length N1 and K2 second bits, the first bit sequence being obtained based on K1 first bit encoding, K1, K2, and N1 being all positive integers; performing low-density parity check (LDPC) encoding on the second bit sequence based on a check matrix to obtain a third bit sequence; wherein the check matrix is ​​determined based on a correspondence between a first information column and a first base graph, the first information column corresponds to the first bit sequence of length N1, and the information column in the first base graph corresponds to the K2 second bits; or, the check matrix corresponds to a second base graph, and the second information column in the second base graph corresponds to the first bit sequence of length N1; and outputting the third bit sequence.

[0008] The cascade coding method provided in the embodiment of the present application can not only effectively guarantee the performance of the key core bits (i.e., the above-mentioned K1 first bits), but also guarantee the performance of other information bits (i.e., the above-mentioned K2 second bits) as much as possible, with as little or no loss of performance of other information bits as possible.

[0009] In conjunction with the first aspect, in a possible implementation, the method further includes:

[0010] Rate matching is performed on the third bit sequence; wherein the shortened information bits are included in at least one of the following items: the first bit sequence with a length of N1 corresponding to the first information column, the K2 second bits corresponding to the information column in the second base map, and the punctured information bits are included in at least one of the following items: the first bit sequence with a length of N1 corresponding to the first information column, the K2 second bits corresponding to the information column in the second base map; or, the shortened information bits are included in at least one of the following items: the first bit sequence with a length of N1 corresponding to the second information column, the K2 second bits corresponding to other information columns in the second base map except the second information column, and the punctured information bits are included in at least one of the following items: the first bit sequence with a length of N1 corresponding to the second information column, the K2 second bits corresponding to other information columns in the second base map except the second information column.

[0011] In a second aspect, an embodiment of the present application provides a cascade decoding method, the method comprising:

[0012] Obtain information to be decoded of a third bit sequence, the information to be decoded of the third bit sequence including information to be decoded of a first bit sequence with a length of N1 and information to be decoded of K2 second bits, the first bit sequence being obtained based on K1 first bit encoding; decode the information to be decoded of the first bit sequence based on a check matrix, and perform low-density parity check (LDPC) decoding on the third bit sequence based on the check matrix; wherein the check matrix is ​​determined based on a correspondence between a first information column and a first base graph, the first information column corresponds to the first bit sequence with a length of N1, and the information column in the first base graph corresponds to the K2 second bits; or, the check matrix corresponds to a second base graph, and the second information column in the second base graph corresponds to the first bit sequence with a length of N1; determine the K1 first bits and the K2 second bits based on the decoding result.

[0013] The cascade decoding method provided in the embodiment of the present application can not only effectively guarantee the performance of the key core bits (i.e., the above-mentioned K1 first bits), but also guarantee the performance of other information bits (i.e., the above-mentioned K2 second bits) as much as possible, with as little or no loss of performance of other information bits as possible.

[0014] In combination with the second aspect, in one possible implementation, when the first bit sequence with a length of N1 fails to pass the check and the K1 first bits in the first bit sequence with a length of N1 pass the cyclic redundancy check CRC check, or when the first bit sequence with a length of N1 passes the check and the third bit sequence fails the check, determining the K1 first bits and the K2 second bits based on the decoding result includes: performing LDPC decoding on the other information to be decoded in the information to be decoded of the third bit sequence except the information to be decoded of the first bit sequence, to obtain the K2 second bits.

[0015] In combination with the first aspect or the second aspect, in a possible implementation manner, the corresponding relationship of the first information column includes a relationship between a column index in the first information column, a row index of the first information column, and a translation value.

[0016] In combination with the first aspect or the second aspect, in a possible implementation manner, the row weight of the first part of the first information column is greater than the row weight of the second part of the first information column, and the first part and the second part do not overlap.

[0017] In combination with the first aspect or the second aspect, in a possible implementation manner, the first information column includes a puncture column.

[0018] In the embodiment of the present application, if the short code corresponds to the puncturing information column of the long code, when the receiving end performs decoding, the decoding of the short code and the long code can be understood as completely independent, and the common error probability of the short code and the long code is the product of the common error probabilities of the two.

[0019] In combination with the first aspect or the second aspect, in a possible implementation manner, the third bit sequence includes encoded bits corresponding to the punctured column in the first information column.

[0020] In combination with the first aspect or the second aspect, in a possible implementation manner, the second information column is determined based on a first reliability order.

[0021] In the embodiment of the present application, the second information column is determined in order of reliability, which can effectively ensure that the error probability of key core bits is low or reduce the decoding error probability of key core bits.

[0022] In combination with the first aspect or the second aspect, in a possible implementation manner, the first reliability order is determined based on at least one of a degree distribution of an information column or a puncture column in the second base graph.

[0023] In combination with the first aspect or the second aspect, in a possible implementation, the first reliability order is a reliability order determined from multiple reliability orders based on at least one of the following: the ratio of K1 to K2, the length N2 of the third bit sequence, and the encoding code rate of the second bit sequence.

[0024] In combination with the first aspect or the second aspect, in a possible implementation manner, the second information column includes a puncture column.

[0025] In combination with the first aspect or the second aspect, in a possible implementation manner, the third bit sequence includes encoded bits corresponding to the punctured column in the second information column.

[0026] In combination with the first aspect, in a possible implementation, the method further includes: sending indication information, where the indication information is used to indicate at least one of the following: N1, K1, K2, the position of the first bit sequence in the third bit sequence, and the expansion factor of the check matrix.

[0027] In combination with the first aspect, in a possible implementation, the method further includes: sending indication information, where the indication information is used to indicate one of the following: a shortened position in the third bit sequence or a punctured position in the third bit sequence.

[0028] In combination with the second aspect, in a possible implementation, the method further includes: receiving indication information, where the indication information is used to indicate at least one of the following: N1, K1, K2, the position of the first bit sequence in the third bit sequence, and the expansion factor of the check matrix.

[0029] In combination with the second aspect, in a possible implementation, the method further includes: receiving indication information, where the indication information is used to indicate one of the following: a shortened position in the third bit sequence or a punctured position in the third bit sequence.

[0030] In a third aspect, embodiments of the present application provide a communication device for executing the method of the first aspect or any possible implementation of the first aspect. The communication device includes a unit capable of executing the method of the first aspect or any possible implementation of the first aspect. Exemplarily, the communication device may include a processing unit and a transceiver unit.

[0031] In a fourth aspect, an embodiment of the present application provides a communication device for executing the method of the second aspect or any possible implementation of the second aspect. The communication device includes a unit capable of executing the method of the second aspect or any possible implementation of the second aspect. Exemplarily, the communication device may include a processing unit and a transceiver unit.

[0032] In a fifth aspect, an embodiment of the present application provides a communication device, comprising a processor configured to execute the method described in the first aspect or any possible implementation of the first aspect. Alternatively, the processor is configured to execute a program stored in a memory, and when the program is executed, the method described in the first aspect or any possible implementation of the first aspect is executed.

[0033] In a possible implementation manner, the memory is located outside the communication device.

[0034] In a possible implementation manner, the memory is located within the communication device.

[0035] In an embodiment of the present application, the processor and the memory may also be integrated into one device, that is, the processor and the memory may also be integrated together.

[0036] In a possible implementation, the communication device further includes a transceiver, and the transceiver is configured to receive signals and / or send signals.

[0037] In a sixth aspect, an embodiment of the present application provides a communication device, comprising a processor configured to execute the method described in the second aspect or any possible implementation of the second aspect. Alternatively, the processor is configured to execute a program stored in a memory, and when the program is executed, the method described in the second aspect or any possible implementation of the second aspect is executed.

[0038] In a possible implementation manner, the memory is located outside the communication device.

[0039] In a possible implementation manner, the memory is located within the communication device.

[0040] In the embodiment of the present application, the processor and the memory may also be integrated into one device, that is, the processor and the memory may also be integrated together.

[0041] In a possible implementation, the communication device further includes a transceiver, and the transceiver is configured to receive signals and / or send signals.

[0042] In seventh aspect, an embodiment of the present application provides a communication device, which includes a logic circuit and an interface, and the logic circuit and the interface are coupled; the logic circuit is used to obtain a second bit sequence, and perform LDPC encoding on the second bit sequence based on a check matrix to obtain a third bit sequence; the interface is used to output the third bit sequence.

[0043] In a possible implementation, the logic circuit is further configured to perform rate matching on the third bit sequence.

[0044] In a possible implementation, the interface is further used to output indication information.

[0045] It is understandable that the description of the logic circuit and the interface can be referred to the first aspect and will not be described in detail here.

[0046] It can be understood that the communication device shown in the embodiment of the present application can be called a chip, or an encoder, or a device with an encoding function, etc., and the embodiment of the present application does not limit this.

[0047] In an eighth aspect, an embodiment of the present application provides a communication device, comprising a logic circuit and an interface, wherein the logic circuit is coupled to the interface; the logic circuit is used to obtain information to be decoded of a third bit sequence, decode the information to be decoded of the first bit sequence based on the check matrix of the first bit sequence, and perform LDPC decoding on the information to be decoded of the third bit sequence based on the check matrix of the third bit sequence, and determine K1 first bits and K2 second bits based on the decoding results.

[0048] In a possible implementation, the logic circuit is specifically configured to perform LDPC decoding on other information to be decoded in the information to be decoded of the third bit sequence except the information to be decoded of the first bit sequence to obtain the K2 second bits.

[0049] In a possible implementation, the interface is used to input indication information.

[0050] It is understandable that the description of the logic circuit and the interface can be referred to the second aspect and will not be described in detail here.

[0051] It can be understood that the communication device shown in the embodiment of the present application can be called a chip, or a decoder, or a device with a decoding function, etc., and the embodiment of the present application does not limit this.

[0052] In a ninth aspect, an embodiment of the present application provides a computer-readable storage medium, which is used to store a computer program. When the computer-readable storage medium is run on a computer, the method shown in the above-mentioned first aspect or any possible implementation of the first aspect is executed.

[0053] In the tenth aspect, an embodiment of the present application provides a computer-readable storage medium, which is used to store a computer program. When the computer-readable storage medium is run on a computer, the method shown in the above-mentioned second aspect or any possible implementation of the second aspect is executed.

[0054] In an eleventh aspect, an embodiment of the present application provides a computer program product, which includes a computer program, and when the computer program product is run on a computer, the method shown in the above-mentioned first aspect or any possible implementation of the first aspect is executed.

[0055] In a twelfth aspect, an embodiment of the present application provides a computer program product, which includes a computer program. When the computer program product is run on a computer, the method shown in the above-mentioned second aspect or any possible implementation of the second aspect is executed.

[0056] In a thirteenth aspect, an embodiment of the present application provides a computer program. When the computer program is run on a computer, the method shown in the above-mentioned first aspect or any possible implementation of the first aspect is executed.

[0057] In a fourteenth aspect, an embodiment of the present application provides a computer program. When the computer program runs on a computer, the method shown in the above-mentioned second aspect or any possible implementation of the second aspect is executed.

[0058] In the fifteenth aspect, an embodiment of the present application provides a communication system, which includes a transmitting end and a receiving end, wherein the transmitting end is used to execute the method shown in the above-mentioned first aspect or any possible implementation of the first aspect, and the receiving end is used to execute the method shown in the above-mentioned second aspect or any possible implementation of the second aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] FIG1 is a schematic diagram of the architecture of a communication system provided in an embodiment of the present application;

[0060] FIG2a is a schematic structural diagram of a BG1 provided in an embodiment of the present application;

[0061] FIG2 b is a schematic structural diagram of a BG2 provided in an embodiment of the present application;

[0062] FIG3 is a schematic diagram of a cascade coding scenario provided by an embodiment of the present application;

[0063] FIG4 is a flow chart of a concatenated encoding method and a concatenated decoding method provided in an embodiment of the present application;

[0064] FIG5a is a schematic diagram of a first encoding method provided in an embodiment of the present application;

[0065] FIG5 b is a schematic diagram of a second encoding method provided in an embodiment of the present application;

[0066] FIG6a is a schematic diagram of a scenario of a cascade decoding method provided in an embodiment of the present application;

[0067] FIG6 b is a schematic diagram of a hardware structure provided in an embodiment of the present application;

[0068] FIG7a is a schematic diagram of a simulation result provided by an embodiment of the present application;

[0069] FIG7 b is a schematic diagram of a simulation result provided by an embodiment of the present application;

[0070] FIG7c is a schematic diagram of a simulation result provided by an embodiment of the present application;

[0071] FIG7 d is a schematic diagram of a simulation result provided by an embodiment of the present application;

[0072] FIG8 is a schematic structural diagram of a communication device provided in an embodiment of the present application;

[0073] FIG9 is a schematic structural diagram of a communication device provided in an embodiment of the present application;

[0074] FIG10 is a schematic structural diagram of a communication device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0075] In order to make the purpose, technical solutions and advantages of this application clearer, this application will be further described below with reference to the accompanying drawings.

[0076] The terms "first" and "second" in the specification, claims, and drawings of this application are used only to distinguish different objects and are not used to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units that are inherent to the process, method, product, or device.

[0077] References to "embodiments" herein mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it refer to independent or alternative embodiments that are mutually exclusive of other embodiments. It will be understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0078] In this application, "at least one (item)" refers to one or more, "more than one" refers to two or more, "at least two (items)" refers to two or three and more than three, and "and / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. "A or B" can mean: only A exists, only B exists, and A and B exist when A and B do not conflict. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c".

[0079] The technical solutions provided in the embodiments of the present application can be applied to various communication systems, for example, the Internet of Things (IoT) system, the narrowband Internet of Things (NB-IoT) system, the long term evolution (LTE) system, the fifth generation (5G) communication system, the new radio (NR) system, and new communication systems that will emerge in the future development of communications.

[0080] The technical solutions provided in the embodiments of the present application can also be applied to non-terrestrial networks (NTN) communications (also referred to as non-terrestrial network communications), machine type communications (MTC), long term evolution-machine (LTE-M), device-to-device (D2D) networks, machine-to-machine (M2M) networks, Internet of Things (IoT) networks, industrial Internet or other networks. Among them, IoT networks can include, for example, Internet of Vehicles (IoV). Among them, the communication methods in the IoV system are collectively referred to as vehicle-to-everything (V2X, where X can represent anything). For example, the V2X can include: vehicle-to-vehicle (V2V) communication, vehicle-to-infrastructure (V2I) communication, vehicle-to-pedestrian (V2P) communication or vehicle-to-network (V2N) communication, etc. For example, in FIG1 shown below, terminal devices can communicate with each other through D2D technology, M2M technology, or V2X technology.

[0081] The technical solutions provided in the embodiments of the present application can also be applied to wireless local area network (WLAN) systems, such as Wi-Fi, etc. For example, the methods provided in the embodiments of the present application can be applied to the Institute of Electrical and Electronics Engineers (IEEE) 802.11 series protocols, such as 802.11a / b / g protocols, 802.11n protocols, 802.11ac protocols, 802.11ax protocols, 802.11be protocols or next-generation protocols, etc., which are not listed here one by one. For example, they can also be applied to wireless personal area networks (WPANs) based on ultra-wideband (UWB) technology, such as 802.15.4a protocols, 802.15.4z protocols or 802.15.4ab protocols in the IEEE 802.15 series protocols, or future generations of UWB WPAN protocols, etc., which are not listed here one by one. It is easy for those skilled in the art to understand that the various aspects involved in the embodiments of the present application can be extended to other networks that adopt various standards or protocols. For example, Bluetooth, high performance radio LAN (HIPERLAN) (a wireless standard similar to IEEE 802.11, primarily used in Europe), and wide area network (WAN) or other networks now known or developed in the future. Therefore, regardless of the coverage and wireless access protocol used, the technical solutions provided in the embodiments of the present application can be applied to any suitable wireless network.

[0082] As a possible implementation, FIG1 is a schematic diagram of the architecture of a communication system provided in an embodiment of the present application. As shown in FIG1 , the communication system may include at least one network device, and at least one terminal device, such as terminal device 1 to terminal device 4 in FIG1 . Exemplarily, terminal device 3 and terminal device 4 as shown in FIG1 may communicate directly, such as direct communication between terminal devices may be achieved through D2D technology. Exemplarily, terminal devices 1 to 4 may communicate with network devices respectively, such as terminal device 3 and terminal device 4 may communicate directly with the network device, or may communicate with the network device indirectly, such as communicating with the network device via other terminal devices (not shown in FIG1 ). It should be understood that FIG1 exemplarily shows a network device and four terminal devices, as well as communication links between the communication devices. Optionally, the communication system may include multiple network devices, and the coverage range of each network device may include other numbers of terminal devices, such as more or fewer terminal devices, which is not limited in the embodiment of the present application. The terminal devices and network devices are described in detail below.

[0083] A terminal device is a device with wireless transceiver capabilities. The terminal device can communicate with access network equipment (or access equipment) in a radio access network (RAN). A terminal device may also be referred to as user equipment (UE), access terminal, terminal, subscriber unit, user station, mobile station, remote station, remote terminal, mobile device, user terminal, user agent, or user device. In one possible implementation, the terminal device can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; it can also be deployed on water (such as a ship, etc.). In one possible implementation, the terminal device can be a handheld device with wireless communication capabilities, a vehicle-mounted device, a wearable device, a sensor, a terminal in the Internet of Things, a terminal in the Internet of Vehicles, a drone, a terminal device in any form in a 5G network or future network, etc., and the embodiments of the present application are not limited to this. It is understood that the terminal device shown in the embodiments of the present application can include not only vehicles (such as cars) in the Internet of Vehicles, but also vehicle-mounted devices or vehicle-mounted terminals in the Internet of Vehicles, etc. The embodiments of the present application do not limit the specific form of the terminal device when applied to the Internet of Vehicles. It can be understood that the terminal devices shown in the embodiments of the present application can also communicate with each other through technologies such as D2D, V2X or M2M. The embodiments of the present application do not limit the communication method between terminal devices.

[0084] A network device may be a device deployed in a wireless access network to provide wireless communication services to terminal devices. The network device may also be referred to as an access network device, access device, or RAN device. Exemplarily, the network device may be a next-generation node B (gNB), a next-generation evolved node B (ng-eNB), or a network device used in 6G communications. The network device may be any device with wireless transceiver capabilities, including but not limited to the base stations described above (including base stations deployed on satellites). The network device may also be a device with base station capabilities in 6G. Optionally, the network device may be an access node, wireless relay node, or wireless backhaul node in a Wi-Fi system. Optionally, the network device may be a wireless controller in a cloud radio access network (CRAN) scenario. Optionally, the network device may be a wearable device or an in-vehicle device. Optionally, the network device may also be a small cell, a transmission reception point (TRP) (or also referred to as a transmission point), or the like.

[0085] It is understandable that the network device may also be a base station, satellite, or the like in a future evolved public land mobile network (PLMN). The network device may also be a communication device that carries base station functions in a non-terrestrial communication system, D2D, V2X, or M2M. The embodiments of the present application do not limit the specific type of the network device. In systems with different wireless access technologies, the names of communication devices with network device functions may vary, and the embodiments of the present application do not list them one by one. Optionally, in some deployments of network devices, the network device may include a centralized unit (CU) and a distributed unit (DU). In other deployments of network devices, the CU may also be divided into a CU-control plane (CP) and a CU-user plan (UP). In yet other deployments of network devices, the network device may also be an antenna unit (RU). In yet other deployments of network devices, the network device may also be an open radio access network (ORAN) architecture. The embodiments of the present application do not limit the specific deployment method of the network device. For example, when the network device is an ORAN architecture, the network device shown in the embodiment of the present application may be an access network device in the ORAN, or a module in the access network device, etc. In the ORAN system, CU may also be referred to as open (open, O)-CU, DU may also be referred to as O-DU, CU-CP may also be referred to as O-CU-CP, CU-UP may also be referred to as O-CU-UP, and RU may also be referred to as O-RU. The deployment methods of the network devices listed here are only examples. With the evolution of standard technologies, network devices may have other deployment forms. However, any method that can implement the frequency band switching method shown in the embodiment of the present application falls within the scope of protection of the embodiment of the present application.

[0086] The network architecture and service scenarios described in the embodiments of this application are intended to more clearly illustrate the technical solutions of the embodiments of this application and do not constitute a limitation on the technical solutions provided by the embodiments of this application. Persons skilled in the art will appreciate that, with the evolution of network architecture and the emergence of new service scenarios, the technical solutions provided in the embodiments of this application are equally applicable to similar technical problems.

[0087] Generally speaking, LDPC codes can have a quasi-cyclic (QC) structure. By setting the shift value of each block, bad structures such as short cycles can be effectively improved, thereby increasing the code distance. For example, the LDPC code actually used is to expand the 1 in the base graph (BG) (or basic matrix) into a cyclic shift matrix, such as the value 1 at each node in BG1 as shown in Figure 2a, and the value 1 at each node in BG2 as shown in Figure 2b. For the block structure of BG1, please refer to block A (or called A region), block B (or called B region), block C (or called C region), block D (or called D region), and block E (or called E region) in Figure 2a. For the block structure of BG2, please refer to blocks A, B, C, D, and E in Figure 2b. The BG model of QC-LDPC code is BG = (X, Y, F), where X corresponds to the variable, Y corresponds to the check equation, and F corresponds to the edge relationship between X and Y. After the BG model undergoes QC expansion with a lifting factor (or expansion factor) of Zc, the LDPC factor graph (or derived subgraph, such as a Tanner graph) is obtained: G = (V, C, E), where V is a variable node, C is a check node, and E is the edge relationship (or connection relationship) between the variable node and the check node. The corresponding check matrix columns are N = |V| = Zc*|X|, the check matrix rows are M = |C| = Zc*|Y|, and the number of non-zero elements in the check matrix is ​​|E| = Zc*|F|. The Tanner graph can be understood as a graph representing the connection relationship between check nodes and variable nodes. As shown in Figures 2a and 2b, the connection relationship between a variable node and a check node can be determined by the values ​​of the nodes in the base graph. If a node's value is 1, it indicates that the corresponding variable node and check node have a connection relationship. If a node's value is 0, it indicates that the corresponding variable node and check node do not have a connection relationship.

[0088] Exemplarily, the local decodability problem can be solved by LDPC codes, as shown below: a small number of key core bits are stored in the information bits, and these key core bits can be protected more accurately. When the overall decoding fails, the key core bits can be recovered. The key core bits are a certain proportion of core bits, which are a more important part of the information bits relative to other non-key core bits. The key core bits can be placed in the selected information bits during encoding. For example, the key core bits can be applicable to scenarios where storage is performed by encoding. For example, when storing information (such as can be understood as key core bits), the information can be encoded. By storing the encoded information, the security of the information can be effectively guaranteed and the error correction capability of the information can be improved. For another example, the key core bits can be applicable to scenarios where signaling is carried in data control channel fusion. For example, in the scenario where data control channel fusion is performed, the control signaling can be understood as the key core bits. By protecting the key core bits, the reliability of the control signaling can be effectively improved. The scenarios to which the key core bits shown in the embodiments of the present application are applicable are not listed one by one.

[0089] It is understood that the information bits shown in the embodiments of the present application can also be referred to as information bits, etc., and the check bits can also be referred to as check bits, etc. It is understood that the non-critical core bits shown in the embodiments of the present application can also be referred to as remaining information bits or other information bits, etc., that is, information bits other than the critical core bits in the bits to be encoded.

[0090] A local protection method currently available (which can be understood as a non-concatenated coding method) can achieve local protection by optimizing the degree distribution. The main principle is that the error probability of large-degree variable nodes (which can be understood as key core bits) is lower than that of small-degree variable nodes (which can be understood as other information bits or other information bits or non-key core bits, etc.). For example, the degree of the key core bit is d m , the remaining information bits have a degree of d l , the check bit degree in the variable node is d p , check the node degree to be d c For example, d m =23,d l =3,d p =2,d c =7. For another example, d m =24,d l =4,d p =2,d c= 8. However, since LDPC decoding is a globally convergent process, the error probabilities of different information bits of LDPC codes in additive white Gaussian noise (AWGN) channels are relatively small, and it is impossible to provide a small number of key core bits with an error probability that is 1-2 orders of magnitude different from the overall error probability (e.g., 10 -1 or 10 -2 ) on the protection. That is to say, when using LPDC coding by optimizing the degree as described above, it cannot be guaranteed that the decoding performance of the key core bits is higher than that of other information bits. In addition, the method of redesigning the degree distribution has a large performance loss compared to the optimal matrix (such as the currently available basis matrix). Generally speaking, 1 order of magnitude is 10 -1 , 2 orders of magnitude is 10 -2 , 3 orders of magnitude is 10 -3 .

[0091] Another existing local protection method is to independently encode and protect key core bits and other information bits, controlling the code rate of the key core bits to be lower than the overall code rate, thereby ensuring a lower bit error rate for the key core bits. However, since key core bits account for a relatively small proportion of all information bits, the encoded code length of the key core bits is relatively short, resulting in coding losses caused by the limited length, such as poor block error rate (BLER)-signal-to-noise ratio (SNR) performance slope. At the same time, resource allocation is difficult to achieve uniformity in different channel scenarios. For example, if the code length of the encoded key core bits is short, the code rate of the key core bits will not be low enough, and the poor performance of the key core bits will not achieve a higher level of protection. If the code length of the encoded key core bits is long, the code rate of the key core bits will be too low, and the performance of other information bits will be significantly lost.

[0092] In view of this, the embodiments of the present application provide a cascade encoding method, a cascade decoding method and an apparatus, which realize the protection of key core bits by coupling LDPC codes of key core bits and other information bits. It can not only effectively guarantee the performance of key core bits, but also guarantee the performance of other information bits as much as possible, with as little loss or no loss of the performance of other information bits as possible.

[0093] Before introducing the method provided by the embodiments of the present application, the terms involved in the embodiments of the present application are described in detail below.

[0094] 1. Key core bits

[0095] The key core bits may include K1 first bits. The key core bits may be referred to as information bits of an inner code or information bits of a short code, i.e., the inner code may also be referred to as a short code. The check bits (or parity bits) generated after encoding the key core bits may be referred to as key parity bits, or parity bits of an inner code, or parity bits of a short code. In other words, the parity bits formed by encoding the information bits of an inner code (or short code) may be referred to as parity bits of an inner code (or short code).

[0096] As shown in Figure 3, the first bit sequence of length N1 can be understood as the sequence obtained by encoding K1 first bits. That is, the first bit sequence can include K1 first bits and (N1-K1) parity bits. The first bit sequence of length N1 can be represented by C1. For example, the inner code C1 can be obtained by encoding the K1 first bits based on the inner code coding matrix (or inner code check matrix).

[0097] 2. Other information bits

[0098] Other information bits may include K2 second bits. These other information bits are relative to the key core bits. For example, other information bits, information bits of the inner code, and parity bits of the inner code may constitute the information bits of the outer code, which may also be called a long code. The parity bits formed by encoding the information bits of the outer code (or long code) may be referred to as the parity bits of the outer code (or long code).

[0099] As shown in Figure 3, the second bit sequence can be understood as a sequence formed based on K2 second bits and the first bit sequence. The position of the first bit sequence within the second bit sequence can be determined based on different concatenated coding methods. The specific position of the first bit sequence within the second bit sequence can be referred to below and will not be described in detail here. It should be understood that the position of the second bit sequence within the third bit sequence shown in Figure 3 is merely an example and should not be construed as limiting the embodiments of the present application.

[0100] As shown in Figure 3, the third bit sequence of length N2 can be understood as the sequence obtained by performing LDPC encoding on the second bit sequence. If the length of the third bit sequence can be N2 (i.e., the outer code length is N2), the third bit sequence of length N2 can be represented by C2. For example, the outer code C2 can be obtained by performing LDPC encoding on the second bit sequence based on the outer code encoding matrix (or outer code check matrix).

[0101] It is understood that the first bit and the second bit shown in the embodiment of the present application are for the purpose of distinguishing different types of bits in concatenated coding. In actual applications, different information bits may not be distinguished by name. Generally speaking, the first bit is more important than the second bit, or the first bit is more important than the second bit. For example, in a scenario where data and control channels are fused, K1 first bits can correspond to control signaling, and K2 second bits can correspond to data information.

[0102] FIG4 is a flow chart of a concatenated encoding method and a concatenated decoding method provided in an embodiment of the present application. The method can be applied to a transmitting end and a receiving end, where the transmitting end can be understood as an end that transmits information (such as a third bit sequence) and the receiving end can be understood as an end that receives information. Alternatively, the transmitting end can be understood as an encoding end and the receiving end can be understood as a decoding end. For example, the transmitting end can be a network device (such as a base station) and the receiving end can be a terminal device; or, the transmitting end can be an AP and the receiving end can be an STA; or, both the transmitting end and the receiving end can be terminal devices (or STAs), etc., which are not limited in the embodiment of the present application. For the communication system applied in the embodiment of the present application, please refer to FIG1 and will not be described in detail here. It can be understood that the embodiment of the present application describes the method provided in the embodiment of the present application based on the transmitting end and the receiving end, but other devices may also exist in the process of transmitting information between the transmitting end and the receiving end, such as forwarding information between the transmitting end and the receiving end through a forwarding device. Therefore, the mutual transmission of information in the embodiment of the present application can be achieved by technical means that can be completed by those skilled in the art, and the embodiment of the present application does not limit other devices other than the transmitting end and the receiving end.

[0103] As shown in FIG4 , the method includes:

[0104] 401. A transmitting end obtains a second bit sequence, where the second bit sequence includes a first bit sequence with a length of N1 and K2 second bits. The first bit sequence is obtained by encoding the K1 first bits.

[0105] The K1 first bits can be understood as bits that need to be transmitted and contain information. Optionally, the K1 bits may include a cyclic redundancy check (CRC). Optionally, the K1 information bits may not include a CRC. In this case, the transmitting end may add a CRC (or not add a CRC) in the subsequent process of encoding the K1 first bits. Exemplarily, in the cascade decoding method shown below, if the receiving end needs to decode the long code based on whether the information bits in the short code pass the CRC, the K1 bits include a CRC, or, the K1 bits do not include a CRC but the transmitting end needs to add a CRC in the subsequent process of encoding the K1 first bits. If, in the cascade decoding method shown below, the receiving end does not need to decode the long code based on whether the information bits in the short code pass the CRC, then whether the K1 bits include a CRC, or whether a CRC is added in the subsequent process of encoding the K1 bits, is not limited in the embodiment of the present application.

[0106] As described above regarding the key core bits and other information bits, the position of the first bit sequence within the second bit sequence can be determined based on different concatenated coding methods, such as Coding Method 1 and Coding Method 2 shown below. It will be understood that Coding Method 1 and Coding Method 2 shown below are both concatenated coding methods, i.e., the inner code is encoded, and then the inner code and other information bits are encoded.

[0107] Optionally, the first bit sequence can be obtained by LDPC encoding based on the K1 first bits. For example, the check matrix when the K1 first bits are LDPC encoded can be different from the check matrix when the second bit sequence is LDPC encoded. That is to say, even if the encoding method of the inner code and the outer code are both LDPC codes, the inner code and the outer code can use different check matrices, expansion factors, shift values, etc. When the encoding method of the K1 first bits is the same as the encoding method of the second bit sequence, the receiving end can use the same set of hardware for decoding, thereby reducing the decoding complexity.

[0108] Optionally, the encoding method for the K1 first bits and the encoding method for the second bit sequence can be different, thereby ensuring flexibility in the encoding method. For example, the first bit sequence can be obtained by performing polar coding based on the K1 first bits. Generally speaking, the inner code length is short, so encoding with polar codes can effectively ensure the decoding performance of key core bits. For another example, the first bit sequence can be obtained by performing algebraic coding (such as RM code or BCH code) based on the K1 first bits, thereby improving the code distance. The encoding methods for the K1 first bits are not listed one by one.

[0109] 402. The transmitter performs LDPC encoding on the second bit sequence based on the check matrix to obtain a third bit sequence.

[0110] In addition to using the check matrix during the encoding and decoding process, at least one of the target code rate and the target code length may also be used. The following text takes the check matrix and the target code rate as examples. For example, the transmitting end can perform LDPC encoding on the second bit sequence according to the check matrix and the target code rate. Correspondingly, the receiving end can perform LDPC decoding on the information to be decoded of the third bit sequence according to the check matrix and the target code rate. The target code rate can be configured to the terminal device by the network device in a dynamic or static manner. For example, the network device can send information including the target code rate to the terminal device through radio resource control (RRC) signaling; for another example, the network device can send information including the target code rate to the terminal device through downlink control information (DCI); the network device can send information including the target code rate to the terminal device by broadcasting, etc., and the embodiments of the present application are not limited to this.

[0111] Optionally, the elements in the base matrix (or base matrix) may include 0 and 1, and the check matrix (also referred to as the encoding matrix or decoding matrix, etc.) is obtained by expanding the base matrix based on the expansion factor, the shift value, and the base matrix. For example, the elements in the check matrix may include 0 and 1. Optionally, to save storage space, the check matrix may be in the following form: "-1" in the check matrix may represent an all-zero matrix of Zc*Zc, "0" in the check matrix may represent an identity matrix of Zc*Zc, and the non-zero elements in the check matrix may represent a circulant permutation matrix (CPM) of Zc*Zc. Zc represents the expansion factor when the base graph (or base matrix) is expanded to obtain the check matrix. The base graph shown here is related to encoding mode 1 or encoding mode 2 described below. Therefore, the description of the base graph can be referred to below. For example, the base graph can be determined based on the correspondence between the first information column and the first base graph, or the base graph can be the third base graph, or the base graph can be the second base graph. Similarly, the description of the expansion factor Zc can be referred to below.

[0112] The following describes in detail the parity check matrix involved in the embodiments of the present application and the position corresponding to the first bit sequence in the parity check matrix.

[0113] Encoding method 1

[0114] The check matrix is ​​determined based on the correspondence between the first information column and the first base graph. As shown in FIG5a , the first information column corresponds to a first bit sequence of length N1, and the information column in the first base graph corresponds to K2 second bits.

[0115] The first base graph can be an existing base graph, such as the first base graph can include BG1 or BG2 or other base graphs, etc., which are not listed one by one in the embodiments of the present application. For ease of description, the following examples are taken as examples of the first base graph including BG2 or BG1, but this should not be understood as a limitation on the embodiments of the present application. As shown in Figure 5a, when the second bit sequence is LDPC encoded, the first bit sequence of length N1 corresponds to the first information column, and the K2 second bits correspond to the 10 information columns in BG2.

[0116] The first information column can be understood as an information column newly added to the first base image. This newly added information column corresponds to a first bit sequence of length N1. In other words, the transmitter can add additional information columns to the base image stored in the current standard (or, alternatively, the transmitter can add additional information columns to the base matrix stored in the current standard). These newly added information columns correspond to short codes. It is understood that the conditions for the first information column described below also apply to newly added information columns corresponding to short codes.

[0117] The first information column involved in the embodiment of the present application may meet at least one of the following conditions:

[0118] Condition 1: The corresponding relationship of the first information column includes the relationship between the column index in the first information column, the row index of the first information column, and the translation value.

[0119] The row index of the first information column can be understood as the row index of the row corresponding to the first information column. Exemplarily, the sending end can obtain the connection relationship between the variable node and the check node in the newly added information column based on the column index in the first information column, the row index of the first information column, and the translation value corresponding to the row index and the column index. Thus, the sending end can determine the check matrix based on the corresponding relationship of the first information column and the first base graph. Exemplarily, the above condition 1 can also be described as: the corresponding relationship of the first information column includes at least one of the following: a connection relationship (or edge relationship) indexed by the variable node, a connection relationship indexed by the check node, and the translation value corresponding to the variable node and the check node. Alternatively, the corresponding relationship of the first information column includes at least one of the following: a mapping relationship indexed by the column in the first information column, a mapping relationship indexed by the behavior of the first information column, and the corresponding translation value.

[0120] As an example, the correspondence of the first information column may include a connection relationship with a variable node as an index and a corresponding translation value. That is, the first base graph, as well as a verification connection relationship with a newly added information column as an index and a corresponding translation value can be stored in the sending end. Exemplarily, the verification connection relationship with a newly added information column as an index can be understood as: taking each column of the first information column as a basic index (or referred to as taking the variable node in the first information column as a basic index), and the connection relationship between the row indexes corresponding to the basic indexes. For example, taking a certain column in the first information column as a basic index, the certain column can correspond to i LS +1 column, the i LS The first column in the +1 column can correspond to the check node (or row index) associated with the column in ascending order. LS +1 Column 2 to i LS The +1 column corresponds to the shift value of the expansion factor list.

[0121] For example, Table 1 shows a schematic table using columns in the first information column as basic indexes. Table 1 is shown as an example where column index j in the first information column is 0 (e.g., the first column from left to right in the newly added information column). Row indices listed in Table 1 indicate that there is a connection relationship between the row index and column index 0. Row indices not listed in Table 1 indicate that there is no connection relationship (or no edge relationship) between the row index and column index 0. For example, the row indexes i=0, i=2, and i=3 listed in Table 1 indicate that there is a connection relationship between the variable node corresponding to j=0 and the check node corresponding to i=0 (or j=0, the value of the node corresponding to i=0 is 1), there is a connection relationship between the variable node corresponding to j=0 and the check node corresponding to i=2 (or j=0, the value of the node corresponding to i=2 is 1), there is a connection relationship between the variable node corresponding to j=0 and the check node corresponding to i=3 (or j=0, the value of the node corresponding to i=3 is 1), and there is no connection relationship between the variable node corresponding to j=0 and the check node corresponding to i=1 (or j=0, the value of the node corresponding to i=1 is 0). It can be understood that the values ​​​​of "0" and "1" shown here are relative. The embodiments of the present application are illustrated by the following values ​​​​and meanings as examples: the value of a node in the base graph corresponding to the check matrix is ​​1, which indicates that there is a connection relationship between the variable node and the check node corresponding to the node; the value of a node is 0, which indicates that there is no connection relationship between the variable node and the check node corresponding to the node.

[0122] Table 1

[0123]

[0124] It is understandable that Table 1 only exemplifies the relationship between the row indices corresponding to j = 0. In a specific implementation, the number of columns of the first information column can be multiple columns. In this case, the transmitting end also needs to store the row indices and corresponding translation values ​​corresponding to the basic index j = 1, and the row indices and corresponding translation values ​​corresponding to the basic index j = 2, etc., which are not listed here one by one. x11 to x18, x21 to x28, and x31 to x38 in Table 1 respectively represent the translation values ​​under the corresponding expansion factors. For specific values, the embodiments of this application will not list them one by one.

[0125] As another example, the correspondence of the first information column may include a connection relationship with a check node as an index and a corresponding translation value. That is, the first base graph, the connection relationship of the newly added information column with a check node as an index and the corresponding translation value may be stored in the transmitting end. Exemplarily, the connection relationship of the newly added information column with a check node as an index may be understood as: the row corresponding to the first information column is used as the basic index, and the connection relationship between the column index corresponding to the basic index. For example, a row of the first information column is used as the basic index, and the row may correspond to i LS +1 column, the i LS The first column in the +1 column can correspond to the variable node (or row index) associated with a row in ascending order. LS +1 Column 2 to i LS The +1 column corresponds to the shift value of the expansion factor list.

[0126] For example, Table 2 shows a schematic table using the rows corresponding to the first information column as basic indexes. Table 2 is shown using row index i=0 in the first information column (e.g., the first row from top to bottom in the newly added information column) as an example. Column indexes listed in Table 2 indicate a connection relationship between the column index and row index 0, while column indexes not listed in Table 2 indicate no connection relationship between the column index and row index 0. For example, the column indexes j=1, j=2, and j=4 listed in Table 2 indicate that there is no connection relationship between the check node corresponding to i=1 and the variable node corresponding to j=0 (or the value of the node corresponding to i=1 and j=0 is 0), there is a connection relationship between the check node corresponding to i=1 and the variable node corresponding to j=1 (or the value of the node corresponding to i=1 and j=1 is 1), there is a connection relationship between the check node corresponding to i=1 and the variable node corresponding to j=2 (or the value of the node corresponding to i=1 and j=2 is 1), there is no connection relationship between the check node corresponding to i=1 and the variable node corresponding to j=3 (or the value of the node corresponding to i=1 and j=3 is 0), and there is a connection relationship between the check node corresponding to i=1 and the variable node corresponding to j=4 (or the value of the node corresponding to i=1 and j=4 is 1).

[0127] Table 2

[0128]

[0129] It is understandable that Table 2 only exemplifies the relationship between the row indices corresponding to i = 0. In a specific implementation, the number of rows of the first information column can be multiple rows. In this case, the sending end also needs to store the column index and the corresponding translation value corresponding to the basic index i = 1, and the row index and the corresponding translation value corresponding to the basic index i = 2, etc., which are not listed here one by one. y11 to y18, y21 to y28, and y31 to y38 in Table 2 respectively represent the translation values ​​under the corresponding expansion factors. For specific values, the embodiments of this application will not list them one by one.

[0130] It is understood that the expansion factors supported by the newly added information columns shown in Tables 1 and 2 are the same as the expansion factors supported by the first base graph, and the translation values ​​correspond to the expansion factors. It is understood that the row index and column index of the first information column shown above are only examples. For example, the row index and column index can also be distinguished by letters, such as Index A, Index B, etc.

[0131] It should be noted that the storage requirements for the transmitting end shown above also apply to the receiving end. That is, both communicating parties can store the corresponding relationships of the first information columns and the first base graph. By increasing the stored content, i.e., the corresponding relationships of the first information columns, the communicating parties can make minimal changes to the first base graph stored by both communicating parties in the current standard. For example, based on the currently stored first base graph (or the base matrix corresponding to the first base graph), the communicating parties can additionally store the content shown in Table 1 or Table 2 (for example only).

[0132] As another example, the communicating parties may update the currently stored first base graph (or the base matrix corresponding to the first base graph). Exemplarily, the communicating parties may add new edge relationships and translation values ​​to the storage content corresponding to the first base graph, and indicate that the added content is a newly added information column. For example, the communicating parties may add the correspondence between the row index and the column index corresponding to the first information column, as well as the translation value, based on the currently stored table corresponding to the first base graph. Exemplarily, the communicating parties may determine a new base graph based on the correspondence between the first information column and the first base graph, such as a third base graph. Thus, the communicating parties may store the third base graph, or store the base matrix corresponding to the third base graph. Optionally, an indication is given for the newly added part of the third base graph relative to the first base graph. Exemplarily, a method for indicating whether an information column in the third base graph is a newly added information column may be as follows: each connection relationship in the third base graph (or each node, or a node corresponding to a row index and a column index) may correspond to a sequence, and the value of the sequence is 0, which may indicate that the connection relationship corresponding to the sequence is a newly added connection relationship. If the value of the sequence is 1, it may indicate that the connection relationship corresponding to the sequence is an existing connection relationship in the first base graph.

[0133] It can be understood that the storage method of the connection relationship of the newly added information column shown in the embodiment of the present application can be consistent with the storage method of the connection relationship of the first base graph. For example, the newly added information column and the first base graph can both be based on the QC structure, and the association between the verification equation of the newly added information column and the first base graph can be determined through the first base graph and the translation value.

[0134] Condition 2: The first information column does not change the values ​​of each node in the first base graph.

[0135] Generally speaking, the value of each node in the first base graph represents the connection relationship between the check node and the variable node corresponding to that node. In other words, the addition of the first information column to the check matrix does not affect the connection relationship between the check nodes and the variable nodes in the first base graph. Therefore, the added information column is not only suitable for concatenated coding, but also does not affect the values ​​of each node in the first base graph and is compatible with existing LDPC codes.

[0136] The check equation of the newly added information column may involve the check nodes and variable nodes of the first base graph, that is, there will be no new check equation associated only with the newly added information column.

[0137] Condition 3: The row weight of the first part of the first information column is greater than the row weight of the second part of the first information column, and the first part and the second part do not overlap.

[0138] Optionally, the first portion may be the rows of the first information column corresponding to the rows of the first block in the first base image. The first block may be block A, block B, or block C as shown in FIG2a or FIG2b. The second portion may be the rows of the first information column corresponding to the rows of the second block in the first base image. The second block may be block D or block E as shown in FIG2a or FIG2b. It is understood that the first portion may contain some rows whose weight is not greater than the row weight of the second portion, for example, the first portion may contain one or two rows (for example only) whose row weight is less than the row weight of the second portion.

[0139] For example, if expressed in terms of edge density, the above condition 3 can also be described as follows: the edge density of the factor graph of the first information column (such as the Tanner graph) regarding this part of the column (hereinafter referred to as the edge density of the first information column) is close to the edge density of the first base graph (such as less than or equal to the first edge density threshold), such as the first part of the first information column is dense, the second part of the first information column is sparse, and the overall density is small. The edge density can satisfy the following relationship: edge density = E / (M*N), where M is the number of rows, N is the number of columns, and E is the number of edges. For example, the edge density of the first base graph can be determined based on the number of rows of the first base graph, the number of columns of the first base graph, the number of edges, and the above relationship. For another example, the edge density of the first information column can be determined based on the number of rows of the first information column, the number of columns of the first information column, the number of edges, and the above relationship. The edge density of the newly added information column is close to the edge density of the first base graph, which can make high bit rate dense and low bit rate sparse. The edge density tends to decrease as the bit rate decreases, thereby ensuring the decoding threshold and making the decoding threshold better (such as lowering the decoding threshold).

[0140] Optionally, the first part may be the rows of the first information column corresponding to the rows of the second block in the first base image, and the second part may be the rows of the first information column corresponding to the rows of the first block in the first base image. Exemplarily, if expressed in terms of edge density, the above condition 3 may be described as follows: the edge density of the connecting edges of the first information column differs greatly from the edge density of the first base image (such as greater than the second edge density threshold), such as the first part of the first information column is sparse, the second part of the first information column is dense, and the overall density is large. The sparse core part makes the decoding threshold for low bit rates better, is suitable for medium and low bit rates, and has better versatility. The embodiment of the present application does not limit the specific values ​​of the first edge density threshold and the second edge density threshold, and the first edge density threshold may be less than or equal to the second edge density threshold.

[0141] Condition 4: The first information column includes a punched column.

[0142] The information column newly added on the basis of the first base image may include a puncture column. It is understandable that even if the first information column includes a puncture column, the third bit sequence still includes the encoded bits corresponding to the puncture column in the first information column. Generally speaking, when a puncture column is included in the base image, the encoded bits corresponding to the puncture column will be punctured, that is, the encoded bits do not include the information bits corresponding to the puncture column. However, in the embodiment of the present application, the encoded bits corresponding to the first bit sequence of length N1 corresponding to the first information column still include bits encoded based on the puncture column. For example, before the long code is encoded, the transmitting end can ignore the puncture operation of the puncture column, so that the third bit sequence includes the encoded bits corresponding to the puncture column. If rate matching is performed on the puncture column after the long code encoding is completed, that is, there are still puncture positions when the encoding is completed. Whether the encoded bits corresponding to the puncture column are sent needs to be determined based on the rate matching method. For long codes, the encoded bits corresponding to the punctured columns in the first information column are punctured. However, for short codes, the encoded bits corresponding to the punctured columns in the first information column are not punctured and still need to be transmitted. Positions where both the inner and outer codes are punctured (also known as common punctured bits) do not need to be transmitted; otherwise, they need to be transmitted. Therefore, when the newly added information columns are all punctured columns for long codes, the log likelihood ratio (LLR) of the short code can be omitted for decoding the long code. Recovery of the short code from the long code and decoding of the short code can be independent, and the overall decoding error probability is the product of these two error probabilities, with the short code having a lower error probability.

[0143] Optionally, the first information column may not include a puncturing column, so that the long code has more information to decode, the code length is longer, and the long code gain is guaranteed.

[0144] In a specific implementation, the above conditions 1 to 4 can be combined with each other, such as part of the newly added information column can correspond to the punctured column, and another part of the newly added information column can correspond to the non-punctured column, etc., which will not be listed here one by one. For example, the newly added information column corresponding to the short code (including the value of each node in the information column and the number of columns) can be defined by the standard, or negotiated by the communicating parties, such as the sending end sending information to the receiving end to indicate the newly added information column, and the receiving end feedbacks confirmation information based on the information, etc. The embodiment of the present application does not limit the negotiation process. For example, the standard defines the maximum number of columns K of the newly added information column max The sending end determines the number of columns K of the first information column based on at least one of the rate matching method and the resource conditions for sending information. eFor example, based on different scenarios, the number of puncturing columns in the newly added information column can be 0 or 1. For example, in a data control channel fusion scenario, when the channel quality is stable, the first information column includes a puncturing column; for another example, in a coding-based storage scenario, the first information column may not include a puncturing column. Optionally, the transmitting end may send a K e About K e For details, please refer to the description of rate matching below.

[0145] Encoding method 2

[0146] The check matrix corresponds to the second base graph, and the second information column in the second base graph corresponds to a first bit sequence of length N1. The other information columns in the second base graph except the second information column correspond to K2 second bits. The second base graph shown here can be understood as an existing base graph, such as the second base graph can include BG1 or BG2 or other base graphs, etc., which are not listed here one by one. The description of the second base graph can refer to the first base graph, but the difference between encoding method 2 and encoding method 1 is that the first bit sequence of length N1 in encoding method 2 corresponds to some information columns in the second base graph, and the other information columns in the second base graph correspond to K2 second bits. As shown in Figure 5b, the second information column in the second base graph (the information column in the rectangular box in Figure 5b) can correspond to a first bit sequence of length N1, and the other information columns in the second base graph except the rectangular box correspond to K2 second bits.

[0147] Exemplarily, the standard defines the information columns corresponding to the short code in the second base graph, or the communicating parties negotiate the information columns corresponding to the short code in the second base graph. Specific negotiation methods are not listed here. For example, the communicating parties can store the second base graph (or base matrix) and position indication information of the information columns corresponding to the short code in the second base graph (or base matrix). This position indication information can be used to indicate the position of the information columns corresponding to the short code in the second base graph. Exemplarily, the information columns corresponding to the short code can be based on a QC structure, and the position indication information can be indicated at the BG level. The information columns corresponding to the short code can be related to the expansion factor, such as being a multiple of the expansion factor. In another example, the information columns corresponding to the short code can be related to the expansion factor and the short code length. The information columns corresponding to the short code can be information columns with a column weight greater than a first threshold, such as those with a column weight greater than the first threshold containing a large number of equations with nodes and a low bit error rate. Alternatively, the information columns corresponding to the short code can be information columns with a column weight less than a second threshold but with other reliability guarantees, such as those with a column weight less than the second threshold containing a checksum equation with a small row weight, high reliability, and more robust protection (e.g., a lower error rate). During simultaneous retransmissions, the starting points of the retransmissions are different, and the probability of each variable node being retransmitted can vary, thereby providing additional protection. Specific information column positions, such as the retransmission position, determine that information in columns 9 and 10 has additional protection. Optionally, the position of the information column corresponding to the short code in the second base graph may include the column index of the information column corresponding to the short code. Optionally, the position of the information column corresponding to the short code in the second base graph may include the short code's placement starting position (e.g., column index) and the length corresponding to the placement starting position (e.g., number of columns). It is understood that the placement starting position of the short code may include one or multiple placement starting positions. If the short code's placement starting position includes multiple placement starting positions, the position of the information column corresponding to the short code in the second base graph also includes the length corresponding to each placement starting position. Exemplarily, the transmitting end determines the second information column from the information column corresponding to the short code based on at least one item in the reliability order. For another example, the transmitting end may determine the second information column from the information column corresponding to the short code based on the reliability order, the rate matching method, and the resources available for transmitting information. For further description of the second information column, please refer to conditions 5 to 7 below.

[0148] It can be understood that the second information column corresponding to the first bit sequence of length N1 is less than or equal to the number of information columns corresponding to the short code, and the remaining information columns in the second base image except the second information column all correspond to K2 second bits.

[0149] The second information column involved in the embodiment of the present application may meet at least one of the following conditions:

[0150] Condition 5: The second information sequence is determined based on the first reliability order.

[0151] Exemplarily, the first reliability order is determined based on at least one of the column weight (or degree distribution) of the information column in the second base graph or the perforation column. For example, the greater the column weight of an information column in the second base graph, the higher the reliability corresponding to that information column. That is, the column weight can be positively correlated with the reliability. Generally speaking, the reliability corresponding to the perforation column is low, but because the column weight corresponding to the perforation column is high, the reliability corresponding to the perforation column can be improved in embodiments of the present application.

[0152] Exemplarily, the first reliability order can be a reliability order determined from multiple reliability orders based on at least one of the following: the ratio of K1 to K2, the length N2 of the third bit sequence, and the encoding rate of the second bit sequence. In other words, there can be multiple information columns corresponding to the short code determined based on the reliability order. The transmitter can determine one of the multiple information columns as the second information column based on the application scenario, the long code length, and the long code rate. Exemplarily, different long code rates vary, resulting in different reliability orders. Exemplarily, different application scenarios may also vary the aforementioned ratio and long code rate, resulting in different second information columns determined based on the reliability order. As an example, in a data and control channel fusion scenario, when K1 / K2 is less than a certain threshold, the second information column can correspond to the first, second, and seventh columns of BG2. Alternatively, in a storage scenario, when K1 / K2 is less than a certain threshold, the second information column can correspond to the fourth and fifth columns of BG2, and so on.

[0153] Condition 6: The second information column includes a puncture column.

[0154] For example, the first two columns in BG1 and BG2 are both punctured columns. Therefore, when the second base image includes BG1 or BG2, at least one of the first two columns in BG1 can be included in the second information column, and at least one of the first two columns in BG2 can be included in the second information column. Even if the second information column includes a punctured column, the third bit sequence still includes the coded bits corresponding to the punctured column in the second information column. In other words, before the long code is encoded, the transmitter can ignore the puncturing operation of the punctured column, so that the third bit sequence still includes the coded bits corresponding to the punctured column in the second information column. However, whether the coded bits corresponding to the punctured column are transmitted is determined based on rate matching. If the receiver needs to use the punctured column (for example, except for the position where both the inner and outer codes are punctured, the remaining outer or inner code punctured columns are punctured columns that the receiver needs to use), the coded bits corresponding to the punctured column need to be transmitted. If the receiver does not need to use the punctured column, the coded bits corresponding to the punctured column may not be transmitted. For example, if the short code is 100 bits, of which bits 1-10 need to be punctured, the long code cannot be punctured before encoding. The long code needs to puncture some positions, such as 5-20 bits. In this case, bits 5-10 of the long code can be left unsent, bits 1-4 need to be sent, and bits 11-20 also need to be sent (the short code is required for decoding; if bits 11-20 are not sent, the short code cannot be independently decoded). The bits that need to be sent shown here can be understood as the bits required for decoding.

[0155] It can be understood that the condition 4 shown above means that the newly added information column may include a puncture column, and the condition 6 means that the information column corresponding to the short code may be a puncture column in the second base image.

[0156] Optionally, the second information column may not include a puncture column, that is, the second information column may not include a puncture column in the second base image.

[0157] Condition 7: The second information column does not include nodes with degree 1.

[0158] Since the second information column corresponds to information bits, the second information column does not include information columns with a column weight of 1. For example, the second information column does not include columns 27 to 68 in BG1. For another example, the second information column does not include columns 15 to 52 in BG2.

[0159] The above-mentioned encoding method 1 and encoding method 2 are generally described. The embodiments of the present application may involve the following situations:

[0160] Case 1: Short code C1 (N1, K1).

[0161] Case 2: Puncturing of long code C2: (N2-N1, K2+N1), short code corresponds to the puncturing information sequence of the long code. Case 2 is illustrated as an example of puncturing all the short codes in the long code.

[0162] Case 3: Code C2 is not punctured: (N2, K2+N1), the short code corresponds to the non-punctured information column of the long code.

[0163] Case 4: Code (N2-N1, K2) after shortening the newly added information sequence of long code C2. Case 4 is an example of shortening the short code after decoding it at the receiving end, i.e., decoding other information bits.

[0164] It can be understood that Case 2 and Case 3 shown above can be understood as two extreme cases. The embodiment of the present application does not list the case where the short code corresponds to a partial punctured column and a partial non-punctured column, but it should not be understood as a limitation to the embodiment of the present application.

[0165] The overall system performance is affected by the coding schemes in the four scenarios described above. Case 1 is entirely short code and does not involve coupling issues. Therefore, cases 2 and 3 are primarily effective for short codes, while case 4 is effective for long codes. For case 2, if the short code corresponds to the punctured information sequence of the long code, the decoding of the short and long codes can be considered completely independent during decoding at the receiver, and the common error probability of the short and long codes is the product of the common error probabilities of the two. If the short code corresponds to the non-punctured information sequence of the long code, the decoding of the short and long codes can be considered not independent during decoding at the receiver, but the long code has a lower code rate, which reduces the common error probability of the long and short codes to a certain extent. For coding scheme 1, the short code is placed in the newly added information sequence (the newly added information sequence can be punctured) of the long code (without changing the original base matrix). The parity check matrix of the long code can add information sequences (including punctured sequences) as needed. Therefore, when the receiving end decodes other information bits, the newly added information columns can be shortened, and the parity check matrix used can be the optimal parity check matrix (the parity check matrix corresponding to the first base graph is assumed to be optimal). For coding method 2, the short code is placed in the information column of the long code (including the punctured column), and the parity check matrix of the long code is not modified. When the receiving end decodes the short code, the long code performance in cases 2 and 3 is better.

[0166] 403. The transmitting end outputs a third bit sequence.

[0167] It is understood that after outputting the third bit sequence, the third bit sequence may further undergo rate matching, modulation, frequency conversion, and other operations to obtain a symbol sequence. The transmitting end transmits this symbol sequence. Correspondingly, the receiving end receives the sequence obtained by transmitting the symbol sequence through a wired or wireless channel. The receiving end then obtains the to-be-decoded information of the third bit sequence by performing operations corresponding to those performed by the transmitting end.

[0168] The rate matching method of the third bit sequence is described in detail below. In one possible implementation, the method shown in FIG4 further includes step 404:

[0169] 404. The transmitting end performs rate matching on the third bit sequence.

[0170] Generally speaking, rate matching methods can include at least one of puncturing and shortening. Furthermore, the shortened information bits generally correspond to the last column or columns of an information column in a parity check matrix. However, in an embodiment of the present application, the shortened information bits are included in at least one of the following: a first bit sequence of length N1 corresponding to the first information column, and K2 second bits corresponding to an information column in the second base graph. In other words, the shortened information bits are not limited to the information bits corresponding to the last information column or columns in the parity check matrix. For example, for encoding method one, the shortened information bits can be included in at least one of the following: information bits in a first bit sequence of length N1 corresponding to the first information column, and information bits in the K2 second bits corresponding to an information column in the second base graph. For example, for encoding method two, the shortened information bits are included in at least one of the following: information bits in a first bit sequence of length N1 corresponding to the second information column, and information bits in the K2 second bits corresponding to information columns other than the second information column in the second base graph. Of course, shortening is not required when the number of transmitted bits is an integer multiple of the expansion factor. That is, when the number of bits in the third bit sequence is an integer multiple of the expansion factor, the transmitting end may not need to perform a shortening operation.

[0171] For encoding method 1, the punctured information bits are included in at least one of the following: a first bit sequence of length N1 corresponding to the first information column, and K2 second bits corresponding to the information column in the second base graph. For encoding method 2, the punctured information bits are included in at least one of the following: a first bit sequence of length N1 corresponding to the second information column, and K2 second bits corresponding to information columns other than the second information column in the second base graph.

[0172] The following describes the rate matching methods for encoding mode 1 and encoding mode 2 respectively:

[0173] It's understandable that both inner and outer code rate matching are required for both coding schemes 1 and 2. The difference lies in the fact that the inner and outer code expansion factors may differ, or the number of rows or columns used in the base image may differ. In other words, the inner and outer code parity check matrices, expansion factors, and other factors may differ, resulting in different inner and outer code rate matching.

[0174] In the embodiments of the present application, the transmitting end may first determine the inner code expansion factor, parity check matrix, etc. based on the inner code rate matching method, thereby performing inner code encoding. After the inner code encoding is completed, the information bit shortening operation and / or the parity check bit puncturing operation are performed. It is understood that the parity check bit puncturing operation shown here actually needs to be punctured, and the information bit puncturing operation of the inner code can be ignored before the outer code is encoded. Because the inner code needs to ignore the information bit puncturing operation before the outer code is encoded, the inner code rate matching shown in the embodiments of the present application can be referred to as partial rate matching, etc.

[0175] Exemplarily, the inner code rate matching method can be as follows: the expansion factor Zc1 is selected according to the length K1 of the inner code information bit, such as for BG2, 10*Zc1≥K1 (only as an example). The unused positions of the information bit portion are shortened according to Zc1, and the number of check bits to be used is calculated according to the inner code rate R1, and the unused check bits are punctured. For example, for BG2, (52-10)*Zc1-the actual number of check bits = the number of punctured check bits. The inner code rate matching method shown in the embodiment of the present application is applicable to both the above-mentioned encoding method 1 and encoding method 2.

[0176] For example, for the above encoding method 1, the rate matching method of the outer code can refer to the rate matching method 1 shown below; for the above encoding method 2, the rate matching method of the outer code can refer to the rate matching method 2 shown below.

[0177] Rate matching method 1

[0178] The transmitter can select the expansion factor Zc2 according to the length K2 of the information bit (i.e., the second bit) of the outer code, and add the number K of new information columns according to Zc2 and the inner code length N1. e Such as the information bit length K2 of the outer code, the expansion factor Zc2, the inner code length N1, the number of columns K of the second information column e , the number of total information columns in the first base graph K BG1 The following relationship can be satisfied: Zc2*K BG1 ≥K2,Zc2*K BG1 +K e)≥K2+N1. For example, for BG2, Zc2*10≥K2, Zc2*10+K e )≥K2+N1. The transmitting end may also shorten the information bits that are not used in the newly added information column and the information column in the first base graph, calculate the number of check bits according to the outer code rate R2, and perform puncturing on the unused check bits. Optionally, the selection principle of Zc2 may be jointly optimized with the number of newly added information columns, such as the optimization target of the above two formulas may be to minimize the number of shortened bits of other information bits and / or key core bits. It is understandable that in this method, there may be some other information bits carried in the information column corresponding to the newly added information column, and the information bits corresponding to the newly added information column may not need to be shortened, and the part that needs to be shortened may be the information bits that are not used by the outer code. Regarding the selection principle of Zc2, the embodiments of the present application will not be listed one by one. It is understandable that in the embodiments of the present application, only the information bits corresponding to the information column in the first base graph may be shortened, or only the information bits corresponding to the newly added information column may be shortened, or both the information bits corresponding to the newly added information column and the information bits corresponding to the information column in the first base graph may be shortened.

[0179] The first rate matching method is based on the method of adding new information columns, which is a rate matching scheme for different code lengths. When the target code length (K2+N1) is not the product of an element in the expansion factor list and the information column, the method of adding new information columns can be used for rate matching, which reduces the number of shortened bits, has less impact on the degree distribution, and has more stable performance.

[0180] Rate matching method 2

[0181] The transmitter can use the inner code length N1 and the number of columns K of the second information column to calculate the n And the expansion factor Zc2 determines Zc2. If the inner code length N1, the number of columns of the second information column K n , expansion factor Zc2, the number of columns K of the total information columns in the second base graph BG2 The following relationship is satisfied: Zc2*K n ≥N1,K BG2 *Zc2≥N1+K2. Optional, K n The value of can be defined by the standard, such as K n The value of is fixed; or, K n The value of can be determined by the above expansion factor Zc2. Optionally, the transmitting end can select Zc2 based on the above formula to satisfy K BG2*Zc2≥N1+K2 is the smallest positive integer. This ensures that all inner code bits are carried in positions corresponding to the information sequence of the short code (such as those specified by the standard). Other information bits may correspond to the information sequence of the short code, or may all correspond to information sequences other than the second information sequence in the second base map. This ensures that the positions that need to be shortened do not include information bits in the short code, such as only unused information bits in the outer code.

[0182] It is understandable that, regardless of whether it is an inner code or an outer code, the shortened and punctured information columns and check columns are used in the encoding process, and the common puncturing bits may not be sent. Optionally, the transmitting end may indicate the shortening position and / or puncturing position through indication information, or the above-mentioned rate matching method is defined in the standard, thereby ensuring that both the transmitting end and the receiving end can complete rate matching based on the information bit length K1 of the inner code, the length K2 of other information bits, the inner code length N1, and the outer code length N2. It can be seen from the above-mentioned rate matching method 1 and rate matching method 2 that the information column, check column, and puncturing column corresponding to the inner code will definitely participate in the outer code encoding; the shortened column of the inner code may participate in the outer code encoding or not.

[0183] 405. The transmitting end sends a symbol sequence after the third bit sequence has been rate matched, and the receiving end receives the symbol sequence accordingly.

[0184] It is understandable that, as described in the above step 403, after the transmitting end performs rate matching on the third bit sequence, it may further perform operations such as modulation and frequency conversion.

[0185] 406. The receiving end obtains information to be decoded of a third bit sequence, where the information to be decoded of the third bit sequence includes information to be decoded of a first bit sequence with a length of N1 and information to be decoded of K2 second bits. The first bit sequence is obtained by encoding the K1 first bits.

[0186] It is understandable that before the receiving end receives the information to be decoded of the third bit sequence, it may further perform operations such as demodulation.

[0187] Optionally, to ensure that the receiving end can correctly decode, the transmitting end may further send indication information to the receiving end, and the indication information may be used to indicate at least one of the following: N1, K1, K2, the position of the first bit sequence in the third bit sequence, and the expansion factor of the check matrix corresponding to the long code. Exemplarily, the indication information may be used to indicate N1, K1, K2, K e (or K n), the expansion factor of the parity check matrix corresponding to the long code. For example, the indication information can be used to indicate N1, K1, K2, coding mode 1 (or coding mode 2), and the expansion factor of the parity check matrix corresponding to the long code. The embodiments of the present application do not limit the specific content of the indication information; however, any information that the receiving end needs to know during decoding can be indicated by the transmitting end to the receiving end. For an explanation of the indication information, refer to the above description of the information including the target bit rate.

[0188] Of course, the content indicated by the indication information shown in the embodiment of the present application can also be defined by a standard, such as being set on both communicating parties when they leave the factory, such as both communicating parties storing the content of the above indication information through a memory.

[0189] 407. The receiving end decodes the information to be decoded of the first bit sequence based on the parity check matrix of the first bit sequence, and performs LDPC decoding on the information to be decoded of the third bit sequence based on the parity check matrix of the third bit sequence.

[0190] For an explanation of the parity check matrix for the third bit sequence, refer to the aforementioned encoding methods 1 and 2 and are not further described here. Exemplarily, the parity check matrix for the third bit sequence is determined based on the correspondence between the first information column and the first base graph, where the first information column corresponds to a first bit sequence of length N1, and the information column in the first base graph corresponds to K2 second bits. Alternatively, the parity check matrix for the third bit sequence corresponds to the second base graph, where the second information column in the second base graph corresponds to the first bit sequence of length N1.

[0191] Optionally, before step 407, the receiving end may receive indication information, decode the information to be decoded of the first bit sequence based on the indication information and the check matrix of the first bit sequence, and perform LDPC decoding on the information to be decoded of the third bit sequence based on the indication information and the check matrix of the third bit sequence.

[0192] It can be understood that the embodiments of the present application do not limit the decoding method used by the receiving end. For example, the decoding method may be a decoding method related to the code rate, code length or application scenario. For example, for LDPC decoding, it may be a belief propagation (BP) decoding algorithm or a min-sum decoding algorithm, etc. For polar decoding, it may be serial cancellation (SC) decoding or serial cancellation list (SCL) decoding, and for algebraic code decoding, it may be ordered statistics decoder (OSD), etc. Specific decoding methods are no longer listed one by one.

[0193] 408. The receiving end determines K1 first bits and K2 second bits based on the decoding result.

[0194] Exemplarily, when a first bit sequence of length N1 fails to pass the check equation and K1 first bits in the first bit sequence of length N1 pass the CRC check, determining the K1 first bits and K2 second bits based on the decoding result includes: performing LDPC decoding on the information to be decoded in the third bit sequence except for the information to be decoded in the first bit sequence, to obtain K2 second bits. That is, when the decoding result of the short code fails to pass the check equation, but the K1 first bits of the short code (i.e., the information bits of the short code) pass the CRC check, the receiving end can encode the check bits of the short code based on the K1 first bits recovered through decoding using the check matrix of the first bit sequence. Then, shortening processing is performed on the corresponding position of the long code based on the short code, and the long code is used to decode the K2 second bits.

[0195] Exemplarily, when the first bit sequence of length N1 passes the check and the third bit sequence fails the check, determining K1 first bits and K2 second bits based on the decoding result includes: performing LDPC decoding on the information to be decoded in the third bit sequence except for the information to be decoded in the first bit sequence, to obtain K2 second bits. In other words, if the decoding result of the short code passes the check equation, the receiving end can perform shortening processing on the corresponding position in the long code, such as setting the LLR symbol corresponding to the position of the short code to the symbol corresponding to the decoding result, with an amplitude of positive infinity (such as Inf or the maximum value of the hardware or a value that cannot be obtained through other digital operations). In other words, during LLR decoding, if the key core bit is decoded, the K2 second bits can be decoded based on the decoded key core bit.

[0196] For example, the general decoding process is as follows: the receiving end determines the LLR based on the received symbols and the channel estimation result, inputs the LLR into the decoder, and then iterates, and then outputs the soft value v of the LLR. all Finally, the codeword corresponding to the LLR is determined to be 1 or 0 based on the decision criteria.

[0197] The decoding process is described in detail below.

[0198] Exemplarily, the decoding process of the key core bit may include: 1. Decoding the short code and the long code separately to obtain the key core bit symbol. 2. Determining the short code separately to obtain the key core bit and outputting the soft value v all1 , decode the long code to get the key core bit, and output the soft value v all2 , according to the decoded v all1 and vall2 To make a hard decision on the symbol, the decoding is judged to be successful by self-checking the short code and long code or by adding CRC in the key core bit. 3. Get the symbol of the key core bit. If the symbol of the key core bit recovered based on the short code or the key core bit recovered by the long code passes the judgment, the corresponding symbol is taken as the decoding result of the key core bit; if the output symbol of the key core bit recovered based on the short code and the key core bit recovered by the long code fails to pass the check, v all1 and v all2 The corresponding key core bit positions are superimposed and then hard-determined, and then verified again. If all judgments fail, the decoding failure is output. It can be understood that the code rate of the short code in the embodiment of the present application is lower than the code rate of the long code.

[0199] For example, the encoding method provided in the embodiments of the present application can be combined with MCS calling, long and short code resource allocation, etc. to ensure that the error probability of key core bits is 1-2 orders of magnitude lower than that of other information bits. Therefore, after decoding to obtain the key core bits, other information bits can be recovered based on the key core bit decoding results. If the long code decoding result passes the check equation or passes the CRC check, the decoding can be directly output as correct. For example, if the long code decoding results fail both the check equation and the CRC check, but the short code decoding results pass the check equation, the corresponding position in the long code is shortened, that is, the LLR symbol at the corresponding position of the short code is set to the symbol corresponding to the decoding result, with an amplitude of positive infinity, and then the shortened long code is used to decode other information bits. Alternatively, if the long code decoding results fail both the check equation and the CRC check, and the short code decoding results fail the check equation, but the information bits of the short code pass the CRC check, the short code check bits can be encoded using the short code's check matrix based on the key core bits recovered through decoding, and then the corresponding position in the long code is shortened, and the shortened long code is used to decode other information bits. If the key core bits all fail the check equation and the CRC check, the decoding is terminated and the decoding fails.

[0200] Figure 6a is a schematic diagram of a decoding process provided by an embodiment of the present application. As shown in Figure 6a, the receiving end determines the LLR and decodes the short code C1 and the long code C2 separately. A self-check (such as a check equation) or CRC check is then performed based on the decoding results of C1 and C2. If at least one of the decoding results of C1 and C2 passes the check, the receiving end can shorten the short code in the long code and decode the shortened long code to recover the second bit. Passing the check for at least one of the decoding results of C1 and C2 includes at least one of the following: both C1 and C2 pass the check equation; both C1 and C2 pass the CRC check; the decoding result of C1 passes the check equation, while the decoding result of C2 fails the check equation and the CRC check; the decoding result of C1 fails the check equation, the information bit of C1 passes the CRC check, and the decoding result of C2 fails the check equation and the CRC check. In other words, if the key core bits are decoded correctly, the long code may also be decoded correctly; however, as long as the key core bits fail to be decoded, the long code will fail to be decoded.

[0201] It can be understood that the decoding process shown in Figure 6a is only an example, and the specific decoding method will not be described in detail in the embodiments of this application.

[0202] For example, when both the short code and the long code use the same LDPC check matrix (different code rates may result in different truncated LDPC check matrices), the chip implementation at the receiving end can be as shown in Figure 6b. It is understood that the relevant description of Figure 6b applies to both encoding methods 1 and 2 described above.

[0203] The initial channel LLR value and the LLR values ​​of other information bits can be placed in the variable node storage position (as shown in part A in Figure 6b). At the same time, the LLR of the key core bit is copied twice, one of which is placed at the variable node corresponding to the key core bit (as shown in part C in Figure 6b), and the other is placed in each variable node storage position used according to the inner code encoding method (as shown in part B in Figure 6b). That is, there are variable nodes that contain other information bits in the long code and also contain short codes (the blocks containing both A and B in Figure 6b).

[0204] It can be seen from Figure 6b that the variable node LLR value of part C and the LLR value of part A together constitute the input LLR value of the long code, and part B is completely orthogonal to these two parts (such as part A and part C), and is the input LLR value of the short code. During the decoding process, the information exchange of the hardware implementation part (such as the information transmission from the calculated variable to the check and from the check to the variable in the decoder) is no different from the traditional decoder, but the information storage and reading include part A and part B at the same time. The quasi-cyclic shift network (QSN) needs to be redesigned to realize the translation value of other information bits and short codes through four-segment functions. During the decoding process of the short code, the inputs of part C and part B are exactly the same, but the decoding results will be different. After the decoding is completed, the storage v of part B and part C are all The soft information of the decoding results of the key core bits recovered by the short code and the key core bits recovered by the long code are respectively hard judged. Then, through the check equation or CRC check, if any part of the check passes, the key core bit decoding is successful, otherwise the v of the two parts is all The code is then overlaid and verified again. During the decoding of other information bits, only when the key core bits are decoded successfully can the other information bits be recovered. In this case, all parts except part A are shortened, and part B can be completely ignored (for example, during the long code decoding process, part B can be ignored). The same hardware process is then used for information transmission.

[0205] In addition to the decoding method provided in the embodiment of the present application, the chip shown in Figure 6b can also implement a hybrid expansion factor (hybrid lifting size). In the case of a single expansion factor, the QSN of the chip is a two-segment piecewise function, and the parts that need to be activated correspond one to one to the 1 of the BG (that is, the position where there is an edge in the base matrix, or the position where the node value is 1). Due to the characteristics of cascade coding, the variable nodes that the chip needs to call contain both short code and long code information. These two parts of information have different lengths and different translation values. Therefore, the two parts called by the calculation unit start with a hybrid expansion factor, and the QSN method to be used is a four-segment function. Regarding the characteristics of the hybrid expansion factor, an explanation can be given in the standard to guide rate matching and the way the receiving end performs decoding; the relevant information of the hybrid expansion factor can also be sent to the receiving end through signaling.

[0206] A method based on long and short code coupling of LDPC codes. The main feature is that the outer code uses LDPC codes through cascade coding to perform unequal protection of information bits. The transmitter indicates the coding method through signaling (such as coding method 1 or coding method 2 shown above), or the coding method is described in the standard.

[0207] The cascade coding method and the cascade decoding method provided by the embodiments of the present application can not only effectively guarantee the performance of key core bits, but also guarantee the performance of other information bits as much as possible, with as little or no loss of performance of other information bits as possible (for example, fewer long code resources can be used to check short codes, minimizing the loss of other information bits of long codes).

[0208] The following is a simulation explanation of the cascade encoding method and the cascade decoding method provided in the embodiments of the present application.

[0209] Simulation 1

[0210] FIG7a is a schematic diagram of a simulation result provided by an embodiment of the present application. The horizontal axis in FIG7a represents the bit rate, such as the bit rate from 0.3 to 1. The vertical axis in FIG7a represents the signal-to-noise ratio (SNR), the unit of which is 10 -2 Decibel (dB). The continuous curve in Figure 7a represents the corresponding simulation performance when a new information column is added on the basis of BG1, and the circles in Figure 7a represent the simulation performance of BG1 at the corresponding bit rate. That is, Figure 7a is a fine-grained simulation of each bit rate of the newly added information column. The new information column is added on the basis of BG1, and then simulation comparison is performed at each bit rate. The addition of additional information columns can achieve lossless performance at a bit rate of 0.33-0.91. As can be seen from Figure 7a, there is no performance loss when the check matrix is ​​obtained based on the correspondence between the newly added information columns and BG1. In other words, although new information columns are added on the basis of BG1, the performance can still maintain the optimal matrix performance.

[0211] Simulation 2

[0212] Figure 7b is a schematic diagram of a simulation result provided by an embodiment of the present application. The horizontal axis in Figure 7b represents SNR (such as Es / N0), the unit is decibel (dB), and the vertical axis represents BLER. The description of each line in Figure 7b corresponds to the number, such as the description of the first line corresponds to the number 1 in Figure 7b, the description of the second line corresponds to the number 2 in Figure 7b, and so on. The relevant descriptions of the lines are as follows: The first line (such as the number 1 in Figure 7b): the long code and the short code are encoded separately, such as the scheme of independently encoding and protecting the key core bits and other information bits. This line corresponds to the long code performance. The second line (such as the number 2 in Figure 7b): the long code and the short code are encoded separately, and the scheme of selecting a reliable position to place the key core bits in the long code corresponds to the key core bit performance. The third line (such as the number 3 in Figure 7b): the scheme provided by the embodiment of the present application, such as the above-mentioned encoding method one, this line corresponds to the long code performance. The fourth line (such as the number 4 in Figure 7b): The solution provided in the embodiment of the present application, such as the above-mentioned encoding method one, this line corresponds to the comprehensive performance of the key core bits, such as the short code performance comes from recovering the key core bits based on the short code and recovering the key core bits based on the long code. The fifth line (such as the number 5 in Figure 7b): The solution provided in the embodiment of the present application, such as the above-mentioned encoding method one, this line corresponds to the performance of recovering the key core bits based on the short code. The sixth line (such as the number 6 in Figure 7b): The solution provided in the embodiment of the present application, this line corresponds to the performance of recovering the key core bits based on the long code.

[0213] As shown in Figure 7b, in an AWGN channel with an integrated code rate of 0.5, the key core bits show significant performance improvements at all operating points compared to the method of differentially protecting the integrated long code based on degree, and a significant performance slope improvement compared to the method of encoding short and long codes separately. The performance gap between the remaining information bits and the baseline is within 0.2dB.

[0214] Simulation 3

[0215] FIG7c is a schematic diagram of a simulation result provided by an embodiment of the present application. For related explanations of FIG7c , please refer to FIG7b , which will not be described in detail here. It is understood that the bit rates of FIG7c and FIG7b are different.

[0216] As shown in Figure 7c, in an AWGN channel with a combined code rate of 0.75, the key core bits show significant performance improvements at all operating points compared to the method of differentially protecting the combined long code based on degree, and a significant performance slope improvement compared to the method of encoding the short and long codes separately. The performance gap between the remaining information bits and the baseline is within 0.2dB.

[0217] Simulation 4

[0218] Figure 7d is a schematic diagram of a simulation result provided by an embodiment of the present application. For the relevant explanation of Figure 7d, please refer to Figure 7b and will not be described in detail here. It can be understood that the code rates of Figures 7d, 7c and 7b are all different. As can be seen from Figure 7d, in a fading channel (such as 3Gpp-ETU), under the condition of an integrated code rate of 0.5, the key core bits have a significant performance improvement at each working point compared to the method of differential protection based on the degree of the integrated long code, and have a significant performance slope improvement compared to the method of encoding the short code and the long code separately. The performance gap of the remaining information bits is within 0.3dB compared to the baseline.

[0219] The following describes a communication device according to an embodiment of the present application.

[0220] The present application divides the functional modules of the communication device according to the above-mentioned method embodiment. For example, each functional module can be divided according to each function, or two or more functions can be integrated into one processing module. The above-mentioned integrated modules can be implemented in the form of hardware or in the form of software functional modules. It should be noted that the division of modules in this application is schematic and is only a logical functional division. There may be other division methods in actual implementation. The communication device of the embodiment of the present application will be described in detail below with reference to Figures 8 to 10.

[0221] Figure 8 is a schematic diagram of the structure of a communication device provided in an embodiment of the present application. As shown in Figure 8, the communication device includes a processing unit 801 and a transceiver unit 802. The transceiver unit 802 can implement corresponding communication functions, and the processing unit 801 is used to process data. For example, the transceiver unit 802 can also be referred to as a communication interface or a communication unit.

[0222] In some embodiments of the present application, the communication device can be used to perform the actions performed by the transmitting end in the above method embodiments. In this case, the communication device can be the transmitting end or a component (such as a chip or system) that can be configured at the transmitting end. The transceiver unit 802 is used to perform the transmitting and receiving related operations of the transmitting end in the above method embodiments, and the processing unit 801 is used to perform the processing related operations of the transmitting end in the above method embodiments. That is, the communication device can be used to execute the steps or functions performed by the transmitting end in the above method embodiments.

[0223] A processing unit 801 is configured to obtain a second bit sequence, where the second bit sequence includes a first bit sequence of length N1 and K2 second bits, where the first bit sequence is obtained by encoding K1 first bits, where K1, K2, and N1 are all positive integers;

[0224] The processing unit 801 is further configured to perform LDPC encoding on the second bit sequence based on a check matrix to obtain a third bit sequence; wherein the check matrix is ​​determined based on a correspondence between the first information column and the first base graph, the first information column corresponds to a first bit sequence having a length of N1, and the information column in the first base graph corresponds to K2 second bits; or, the check matrix corresponds to the second base graph, and the second information column in the second base graph corresponds to the first bit sequence having a length of N1;

[0225] The processing unit 801 is further configured to output a third bit sequence.

[0226] It can be understood that the processing unit shown here outputs the third bit sequence, which can be understood as: the processing unit can send the third bit sequence to other components through the transceiver unit (such as sending it to a device for modulation, or sending it to a device for frequency conversion, etc.), or the processing unit sends the modulation symbol of the third bit sequence to the receiving end through the transceiver unit, etc. The embodiments of the present application will not be listed one by one.

[0227] In one possible implementation, the processing unit 801 is further used to perform rate matching on the third bit sequence; wherein the shortened information bits are included in at least one of the following items: a first bit sequence with a length of N1 corresponding to the first information column, and K2 second bits corresponding to the information column in the second base image; the punctured information bits are included in at least one of the following items: a first bit sequence with a length of N1 corresponding to the first information column, and K2 second bits corresponding to the information column in the second base image; or, the shortened information bits are included in at least one of the following items: a first bit sequence with a length of N1 corresponding to the second information column, and K2 second bits corresponding to other information columns in the second base image except the second information column; the punctured information bits are included in at least one of the following items: a first bit sequence with a length of N1 corresponding to the second information column, and K2 second bits corresponding to other information columns in the second base image except the second information column.

[0228] In a possible implementation, the transceiver unit 802 is configured to send indication information, where the indication information is used to indicate at least one of the following: N1, K1, K2, a position of the first bit sequence in the third bit sequence, and an expansion factor of a check matrix.

[0229] In a possible implementation, the transceiver unit 802 is configured to send indication information, where the indication information is used to indicate one of the following: a shortened position in the third bit sequence or a punctured position in the third bit sequence.

[0230] Optionally, the communication device may further include a storage unit, which may be used to store instructions and / or data. The processing unit 801 may read the instructions and / or data in the storage unit to enable the communication device to implement the aforementioned method embodiment. Exemplarily, the storage unit may be used to store the correspondence between the first information column and the first base graph; or to store the second base graph, etc.

[0231] It is understandable that the specific descriptions of the transceiver unit and the processing unit shown in the embodiments of the present application are only examples. For the specific functions or execution steps of the transceiver unit and the processing unit, reference can be made to the above-mentioned method embodiments, which will not be described in detail here. The descriptions of the processing unit and the transceiver unit shown above are only examples. For the descriptions of the various terms involved above, reference can be made to the method embodiments. For example, for the descriptions of the first bit sequence, the second bit sequence, the third bit sequence, the key core bit, the non-key core bit, the first bit, the second bit, the first information column, the second information column, etc., reference can be made to the above method embodiments, which will not be described in detail here.

[0232] Using Figure 8, in some other embodiments of the present application, the communication device can be used to execute the actions performed by the receiving end in the above method embodiments. In this case, the communication device can be the receiving end or a component configurable at the receiving end. The transceiver unit 802 is used to execute the transceiver-related operations of the receiving end in the above method embodiments, and the processing unit 801 is used to execute the processing-related operations of the receiving end in the above method embodiments. In other words, the communication device can be used to execute the steps or functions performed by the receiving end in the above method embodiments.

[0233] A processing unit 801 is configured to obtain information to be decoded of a third bit sequence, where the information to be decoded of the third bit sequence includes information to be decoded of a first bit sequence of length N1 and information to be decoded of K2 second bits, where the first bit sequence is obtained by encoding the K1 first bits.

[0234] The processing unit 801 is further configured to decode the to-be-decoded information of the first bit sequence based on the check matrix of the first bit sequence, and perform LDPC decoding on the third bit sequence based on the check matrix of the third bit sequence; wherein the check matrix of the third bit sequence is determined based on a correspondence between the first information column and the first base graph, the first information column corresponds to a first bit sequence having a length of N1, and the information column in the first base graph corresponds to K2 second bits; or, the check matrix of the third bit sequence corresponds to the second base graph, and the second information column in the second base graph corresponds to the first bit sequence having a length of N1.

[0235] The processing unit 801 is further configured to determine K1 first bits and K2 second bits based on the decoding result.

[0236] Exemplarily, the transceiver unit 802 may be configured to receive modulation symbols; and the processing unit 801 may be configured to obtain information to be decoded of the third bit sequence based on the input modulation symbols.

[0237] In one possible implementation, when the first bit sequence with a length of N1 fails to pass the check and K1 first bits in the first bit sequence with a length of N1 pass the cyclic redundancy check CRC check, or when the first bit sequence with a length of N1 passes the check and the third bit sequence fails the check, the processing unit 801 is specifically configured to perform LDPC decoding on other to-be-decoded information in the to-be-decoded information of the third bit sequence except the to-be-decoded information of the first bit sequence to obtain K2 second bits.

[0238] In a possible implementation, the transceiver unit 802 is configured to receive indication information, where the indication information is used to indicate at least one of the following: N1, K1, K2, a position of the first bit sequence in the third bit sequence, and an expansion factor of a check matrix.

[0239] In a possible implementation, the transceiver unit 802 is configured to receive indication information, where the indication information is used to indicate one of the following: a shortened position in the third bit sequence or a punctured position in the third bit sequence.

[0240] Optionally, the communication device may further include a storage unit, which may be used to store instructions and / or data. The processing unit 801 may read the instructions and / or data in the storage unit to enable the communication device to implement the aforementioned method embodiment. Exemplarily, the storage unit may be used to store the correspondence between the first information column and the first base graph; or to store the second base graph, etc.

[0241] It is understood that the specific descriptions of the transceiver unit and the processing unit shown in the embodiments of the present application are only examples. For the specific functions or execution steps of the transceiver unit and the processing unit, reference can be made to the above-mentioned method embodiments, which will not be described in detail here. It is understood that the descriptions of the processing unit and the transceiver unit shown above are only examples. For the descriptions of the various terms involved above, reference can be made to the method embodiments. For example, for the descriptions of the first bit sequence, the second bit sequence, the third bit sequence, the key core bit, the non-key core bit, the first bit, the second bit, the first information column, the second information column, etc., reference can be made to the above-mentioned method embodiments, which will not be described in detail here.

[0242] The communication device of the embodiment of the present application is described above. The following describes possible product forms of the communication device. It should be understood that any product having the functions of the communication device described in FIG8 falls within the scope of protection of the embodiment of the present application.

[0243] In one possible implementation, in the communication device shown in FIG8 , the processing unit 801 may be one or more processors, the transceiver unit 802 may be a transceiver, or the transceiver unit 802 may be a transmitting unit and a receiving unit, the transmitting unit may be a transmitter, the receiving unit may be a receiver, and the transmitting unit and the receiving unit are integrated into a single device, such as a transceiver. In the embodiment of the present application, the processor and the transceiver may be coupled, etc., and the embodiment of the present application does not limit the connection method between the processor and the transceiver. During the execution of the above method, the process of sending information in the above method can be understood as the process of the processor outputting the above information. When outputting the above information, the processor outputs the above information to the transceiver so that the transceiver can transmit it. After being output by the processor, the above information may also need to undergo other processing before reaching the transceiver. Similarly, the process of receiving information in the above method can be understood as the process of the processor receiving the input information. When the processor receives the input information, the transceiver receives the above information and inputs it into the processor. Furthermore, after the transceiver receives the above information, the above information may need to be processed further before being input into the processor.

[0244] As shown in FIG. 9 , the communication device 90 includes one or more processors 920 and a transceiver 910 .

[0245] Exemplarily, when the communication device is used to execute the steps, methods, or functions performed by the above-mentioned transmitting end, the processor 920 is used to obtain a second bit sequence; the processor 920 is also used to perform LDPC encoding on the second bit sequence based on the check matrix to obtain a third bit sequence; the processor 920 is also used to output the third bit sequence.

[0246] In a possible implementation, the processor 920 is further configured to perform rate matching on the third bit sequence.

[0247] In one possible implementation, the transceiver 910 is used to send indication information, where the indication information is used to indicate at least one of the following: N1, K1, K2, the position of the first bit sequence in the third bit sequence, the expansion factor of the check matrix, the shortened position in the third bit sequence, and the puncturing position in the third bit sequence.

[0248] Exemplarily, when the communication device is used to execute the steps, methods, or functions performed by the above-mentioned receiving end, the processor 920 is used to obtain the information to be decoded of the third bit sequence; the processor 920 is also used to decode the information to be decoded of the first bit sequence based on the check matrix of the first bit sequence, and perform LDPC decoding on the third bit sequence based on the check matrix of the third bit sequence; the processor 920 is also used to determine K1 first bits and K2 second bits based on the decoding results.

[0249] In one possible implementation, when the first bit sequence with a length of N1 fails to pass the check and K1 first bits in the first bit sequence with a length of N1 pass the cyclic redundancy check CRC check, or when the first bit sequence with a length of N1 passes the check and the third bit sequence fails the check, the processor 920 is specifically configured to perform LDPC decoding on other to-be-decoded information in the to-be-decoded information of the third bit sequence except the to-be-decoded information of the first bit sequence to obtain K2 second bits.

[0250] In one possible implementation, the transceiver 910 is used to receive indication information, where the indication information is used to indicate at least one of the following: N1, K1, K2, the position of the first bit sequence in the third bit sequence, the expansion factor of the check matrix, the shortened position in the third bit sequence, and the puncturing position in the third bit sequence.

[0251] It is understood that for the specific description of the processor and the transceiver, reference can also be made to the introduction of the processing unit and the transceiver unit shown in Figure 8, which will not be repeated here. For the description of the various terms involved above, reference can be made to the method embodiments. For example, for the description of the first bit sequence, the second bit sequence, the third bit sequence, the key core bit, the non-key core bit, the first bit, the second bit, the first information column, the second information column, etc., reference can be made to the method embodiments above, which will not be described in detail here.

[0252] In various implementations of the communication device shown in FIG9 , the transceiver may include a receiver and a transmitter, wherein the receiver is configured to perform a receiving function (or operation) and the transmitter is configured to perform a transmitting function (or operation). The transceiver is configured to communicate with other devices / devices via a transmission medium.

[0253] Optionally, the communication device 90 may further include one or more memories 930 for storing program instructions and / or data, etc. The memory 930 is coupled to the processor 920. The coupling in the embodiment of the present application is an indirect coupling or communication connection between devices, units or modules, which may be electrical, mechanical or other forms, and is used for information interaction between devices, units or modules. The processor 920 may operate in conjunction with the memory 930. The processor 920 may execute program instructions stored in the memory 930. Optionally, at least one of the one or more memories may be included in the processor. Optionally, one or more memories may be used to store the first base map and the correspondence between the first information column (or the third base map) in the embodiment of the present application, or to store the second base map in the embodiment of the present application, etc.

[0254] The specific connection medium between the transceiver 910, processor 920, and memory 930 is not limited in the embodiments of the present application. In Figure 9, the memory 930, processor 920, and transceiver 910 are connected via a bus 940. The bus is represented by a bold line in Figure 9. The connection methods between other components are only for illustrative purposes and are not limiting. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, Figure 9 only uses a single bold line, but this does not mean that there is only one bus or only one type of bus.

[0255] In the embodiments of the present application, the processor may be a general-purpose processor, a digital signal processor, an application-specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, etc., and may implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present application. The general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of the methods disclosed in the embodiments of the present application may be directly implemented as being executed by a hardware processor, or may be executed by a combination of hardware and software modules in the processor, etc.

[0256] In the embodiment of the present application, memory may include but is not limited to non-volatile memories such as hard disk drive (HDD) or solid-state drive (SSD), random access memory (RAM), erasable programmable read-only memory (EPROM), read-only memory (ROM) or portable read-only memory (CD-ROM), etc. Memory is any storage medium that can be used to carry or store program code in the form of instructions or data structures, and can be read and / or written by a computer (such as the communication device shown in the present application), but is not limited thereto. The memory in the embodiment of the present application can also be a circuit or other arbitrarily capable of realizing a storage function, for storing program instructions and / or data.

[0257] Illustratively, the processor 920 is primarily used to process communication protocols and communication data, control the entire communication device, execute software programs, and process software program data. The memory 930 is primarily used to store software programs and data. The transceiver 910 may include a control circuit and an antenna. The control circuit is primarily used to convert baseband signals into radio frequency signals and process radio frequency signals. The antenna is primarily used to transmit and receive radio frequency signals in the form of electromagnetic waves. Input / output devices, such as a touch screen, display, and keyboard, are primarily used to receive user input and output data to the user.

[0258] When the communication device is powered on, the processor 920 can read the software program in the memory 930, interpret and execute the instructions of the software program, and process the data of the software program. When data needs to be sent wirelessly, the processor 920 performs baseband processing on the data to be sent and outputs the baseband signal to the radio frequency circuit. The radio frequency circuit performs radio frequency processing on the baseband signal and then transmits the radio frequency signal to the outside in the form of electromagnetic waves through the antenna. When data is sent to the communication device, the radio frequency circuit receives the radio frequency signal through the antenna, converts the radio frequency signal into a baseband signal, and outputs the baseband signal to the processor 920. The processor 920 converts the baseband signal into data and processes the data.

[0259] In another implementation, the RF circuit and antenna may be provided independently of the processor performing baseband processing. For example, in a distributed scenario, the RF circuit and antenna may be remotely arranged independent of the communication device.

[0260] It is understood that the communication device shown in the embodiment of the present application may also have more components than those in Figure 9, and the embodiment of the present application is not limited to this. The method performed by the processor and transceiver shown above is only an example. For the specific steps performed by the processor and transceiver, please refer to the method described above.

[0261] In another possible implementation, in the communication device shown in FIG8 , the processing unit 801 may be one or more logic circuits, and the transceiver unit 802 may be an input / output interface, or may be called a communication interface, or an interface circuit, or an interface, etc. Alternatively, the transceiver unit 802 may be a sending unit and a receiving unit, the sending unit may be an output interface, the receiving unit may be an input interface, and the sending unit and the receiving unit may be integrated into one unit, such as an input / output interface. As shown in FIG10 , the communication device shown in FIG10 includes a logic circuit 1001 and an interface 1002. That is, the processing unit 801 may be implemented using the logic circuit 1001, and the transceiver unit 802 may be implemented using the interface 1002. The logic circuit 1001 may be a chip, a processing circuit, an integrated circuit, or a system-on-chip (SoC) chip, etc., and the interface 1002 may be a communication interface, an input / output interface, a pin, etc. For example, FIG10 is illustrated using the communication device as a chip, and the chip includes a logic circuit 1001 and an interface 1002.

[0262] In the embodiment of the present application, the logic circuit and the interface may also be coupled to each other. The embodiment of the present application does not limit the specific connection method between the logic circuit and the interface.

[0263] Exemplarily, when the communication device is used to execute the method, function, or step performed by the above-mentioned transmitting end, the logic circuit 1001 is used to obtain a second bit sequence; the logic circuit 1001 is also used to perform LDPC encoding on the second bit sequence based on the check matrix to obtain a third bit sequence; and the interface 1002 is used to output the third bit sequence.

[0264] It is understandable that the interface can output the third bit sequence so that other devices in the transmitting end can process the third bit sequence; or, the interface is used to output the symbol sequence of the third bit sequence after rate matching, modulation, frequency conversion and other operations.

[0265] Optionally, the communication device may further include a memory, which may be used to store the correspondence between the first base graph and the first information column (or the third base graph); or, to store the second base graph.

[0266] In a possible implementation, the logic circuit 1001 is further configured to perform rate matching on the third bit sequence.

[0267] In one possible implementation, interface 1002 is used to output indication information, where the indication information is used to indicate at least one of the following: N1, K1, K2, the position of the first bit sequence in the third bit sequence, the expansion factor of the check matrix, the shortened position in the third bit sequence, and the puncturing position in the third bit sequence.

[0268] Exemplarily, when the communication device is used to execute the method, function, or step performed by the above-mentioned receiving end, the logic circuit 1001 is used to obtain the information to be decoded of the third bit sequence; the logic circuit 1001 is also used to decode the information to be decoded of the first bit sequence based on the check matrix of the first bit sequence, and perform LDPC decoding on the third bit sequence based on the check matrix of the third bit sequence; the logic circuit 1001 is also used to determine K1 first bits and K2 second bits based on the decoding result.

[0269] It is understood that interface 1002 can be used to input signals such as modulation symbols transmitted through a channel, and then logic circuit 1001 can process the signals to obtain information to be decoded of the third bit sequence. Of course, the logic circuit for processing the modulation symbols can be the same as or different from the logic circuit for performing LDPC decoding, and this is not limited in this embodiment of the present application.

[0270] In one possible implementation, when the first bit sequence with a length of N1 fails the check and K1 first bits in the first bit sequence with a length of N1 pass the cyclic redundancy check (CRC) check, or when the first bit sequence with a length of N1 passes the check and the third bit sequence fails the check, the logic circuit 1001 is specifically configured to perform LDPC decoding on other information to be decoded in the information to be decoded of the third bit sequence except the information to be decoded of the first bit sequence to obtain K2 second bits.

[0271] In one possible implementation, interface 1002 is used to input indication information, which is used to indicate at least one of the following: N1, K1, K2, the position of the first bit sequence in the third bit sequence, the expansion factor of the check matrix, the shortened position in the third bit sequence, and the puncturing position in the third bit sequence.

[0272] For descriptions of the various terms mentioned above, please refer to the method embodiments. For example, descriptions of the first bit sequence, second bit sequence, third bit sequence, critical core bit, non-critical core bit, first bit, second bit, first information column, and second information column, etc., can be referred to the method embodiments above and will not be detailed here.

[0273] It can be understood that the communication device shown in the embodiment of the present application can implement the method provided in the embodiment of the present application in the form of hardware, or can implement the method provided in the embodiment of the present application in the form of software, etc., and the embodiment of the present application is not limited to this.

[0274] For the specific implementation of each embodiment shown in FIG10 , reference may also be made to the above embodiments, which will not be described in detail here.

[0275] The present application also provides a wireless communication system including a transmitter and a receiver, which can be used to perform the method of any of the aforementioned embodiments. Alternatively, the transmitter and the receiver can refer to the communication devices shown in Figures 8 to 10.

[0276] In addition, the present application also provides a computer program, which is used to implement the operations and / or processing performed by the sending end in the method provided by the present application.

[0277] The present application also provides a computer program, which is used to implement the operations and / or processing performed by the receiving end in the method provided by the present application.

[0278] The present application also provides a computer-readable storage medium, which stores computer code. When the computer code runs on a computer, the computer executes the operations and / or processing performed by the sending end in the method provided by the present application.

[0279] The present application also provides a computer-readable storage medium, which stores computer code. When the computer code runs on a computer, the computer executes the operations and / or processing performed by the receiving end in the method provided by the present application.

[0280] The present application also provides a computer program product, which includes computer code or computer program. When the computer code or computer program runs on a computer, the operations and / or processing performed by the sending end in the method provided by the present application are executed.

[0281] The present application also provides a computer program product, which includes computer code or computer program. When the computer code or computer program runs on a computer, the operations and / or processing performed by the receiving end in the method provided by the present application are executed.

[0282] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, or can be electrical, mechanical or other forms of connection.

[0283] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected according to actual needs to achieve the technical effects of the solutions provided in the embodiments of the present application.

[0284] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0285] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a readable storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned readable storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk, and other media that can store program code.

[0286] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A concatenated coding method, characterized in that: The method comprises: Obtain a second bit sequence, where the second bit sequence includes a first bit sequence having a length of N1 and K2 second bits, where the first bit sequence is obtained by encoding the K1 first bits, and K1, K2, and N1 are all positive integers; Performing low-density parity check (LDPC) encoding on the second bit sequence based on a check matrix to obtain a third bit sequence; wherein the check matrix is ​​determined based on a correspondence between the first information column and a first base graph, the first information column corresponds to the first bit sequence of length N1, and the information column in the first base graph corresponds to the K2 second bits; or, the check matrix corresponds to a second base graph, and the second information column in the second base graph corresponds to the first bit sequence of length N1; The third bit sequence is output.

2. The method according to claim 1, characterized in that The method further comprises: Rate matching is performed on the third bit sequence; wherein the shortened information bits are included in at least one of the following items: the first bit sequence with a length of N1 corresponding to the first information column, the K2 second bits corresponding to the information column in the first base map, and the punctured information bits are included in at least one of the following items: the first bit sequence with a length of N1 corresponding to the first information column, the K2 second bits corresponding to the information column in the first base map; or, the shortened information bits are included in at least one of the following items: the first bit sequence with a length of N1 corresponding to the second information column, the K2 second bits corresponding to other information columns in the second base map except the second information column, and the punctured information bits are included in at least one of the following items: the first bit sequence with a length of N1 corresponding to the second information column, the K2 second bits corresponding to other information columns in the second base map except the second information column.

3. A cascade decoding method, characterized in that: The method comprises: Obtaining information to be decoded of a third bit sequence, where the information to be decoded of the third bit sequence includes information to be decoded of a first bit sequence having a length of N1 and K2 second bits of information to be decoded, where the first bit sequence is obtained by encoding the K1 first bits; Decoding the to-be-decoded information of the first bit sequence based on the parity check matrix of the first bit sequence, and performing low-density parity check (LDPC) decoding on the to-be-decoded information of the third bit sequence based on the parity check matrix of the third bit sequence; wherein the parity check matrix of the third bit sequence is determined based on a correspondence between the first information column and a first base graph, the first information column corresponds to the first bit sequence of length N1, and the information column in the first base graph corresponds to the K2 second bits; or, the parity check matrix of the third bit sequence corresponds to the second base graph, and the second information column in the second base graph corresponds to the first bit sequence of length N1; The K1 first bits and the K2 second bits are determined based on the decoding result.

4. The method according to claim 3, characterized in that When the first bit sequence with a length of N1 fails to pass the check and K1 first bits in the first bit sequence with a length of N1 pass the cyclic redundancy check (CRC) check, or when the first bit sequence with a length of N1 passes the check and the third bit sequence fails the check, determining the K1 first bits and the K2 second bits based on the decoding result includes: LDPC decoding is performed on the other information to be decoded in the information to be decoded of the third bit sequence except the information to be decoded of the first bit sequence to obtain the K2 second bits.

5. The method according to any one of claims 1 to 4, characterized in that The corresponding relationship of the first information column includes the relationship between the column index in the first information column, the row index of the first information column, and the translation value.

6. The method according to any one of claims 1 to 5, characterized in that The row weight of the first part of the first information column is greater than the row weight of the second part of the first information column, and the first part and the second part do not overlap.

7. The method according to any one of claims 1 to 6, characterized in that The first information row includes a punch hole row.

8. The method according to any one of claims 1 to 7, characterized in that The third bit sequence includes the encoded bits corresponding to the punctured column in the first information column.

9. The method according to any one of claims 1 to 4, characterized in that The second information column is determined based on a first reliability order.

10. The method according to claim 9, characterized in that The first reliability order is determined based on at least one of column weight or puncture column of the information column in the second base graph.

11. The method according to claim 9 or 10, characterized in that The first reliability order is a reliability order determined from a plurality of reliability orders based on at least one of the following: The ratio of K1 to K2, the length N2 of the third bit sequence, and the encoding rate of the second bit sequence are determined.

12. The method according to any one of claims 9 to 11, characterized in that: The second information row includes a punch hole row.

13. The method according to any one of claims 7 to 12, characterized in that: The third bit sequence includes the encoded bits corresponding to the punctured column in the second information column.

14. The method according to claim 1 or 2, characterized in that The method further comprises: Send indication information, where the indication information is used to indicate at least one of the following: N1, K1, K2, a position of the first bit sequence in the third bit sequence, and an expansion factor of the check matrix.

15. The method according to any one of claims 1, 2 or 14, characterized in that The method further comprises: Indication information is sent, where the indication information is used to indicate one of the following: a shortened position in the third bit sequence or a punctured position in the third bit sequence.

16. A communication device, characterized in that: The device comprises: a processing unit, configured to obtain a second bit sequence, where the second bit sequence includes a first bit sequence having a length of N1 and K2 second bits, where the first bit sequence is obtained by encoding the K1 first bits, and K1, K2, and N1 are all positive integers; The processing unit is further configured to perform low-density parity check (LDPC) encoding on the second bit sequence based on a check matrix to obtain a third bit sequence; wherein the check matrix is ​​determined based on a correspondence between the first information column and a first base graph, the first information column corresponds to the first bit sequence of length N1, and the information column in the first base graph corresponds to the K2 second bits; or, the check matrix corresponds to a second base graph, and the second information column in the second base graph corresponds to the first bit sequence of length N1; The processing unit is further configured to output the third bit sequence.

17. The device according to claim 16, characterized in that The processing unit is further used to perform rate matching on the third bit sequence; wherein the shortened information bits are included in at least one of the following items: the first bit sequence with a length of N1 corresponding to the first information column, and the K2 second bits corresponding to the information column in the first base map, and the punctured information bits are included in at least one of the following items: the first bit sequence with a length of N1 corresponding to the first information column, and the K2 second bits corresponding to the information column in the first base map; or, the shortened information bits are included in at least one of the following items: the first bit sequence with a length of N1 corresponding to the second information column, and the K2 second bits corresponding to other information columns in the second base map except the second information column, and the punctured information bits are included in at least one of the following items: the first bit sequence with a length of N1 corresponding to the second information column, and the K2 second bits corresponding to other information columns in the second base map except the second information column.

18. A communication device, characterized in that: The device comprises: a processing unit, configured to obtain information to be decoded of a third bit sequence, the information to be decoded of the third bit sequence comprising information to be decoded of a first bit sequence having a length of N1 and information to be decoded of K2 second bits, wherein the first bit sequence is obtained by encoding the K1 first bits; The processing unit is further configured to decode the to-be-decoded information of the first bit sequence based on the parity check matrix of the first bit sequence, and perform low-density parity check (LDPC) decoding on the to-be-decoded information of the third bit sequence based on the parity check matrix of the third bit sequence; wherein the parity check matrix of the third bit sequence is determined based on a correspondence between first information columns and a first base graph, the first information columns correspond to the first bit sequence of length N1, and the information columns in the first base graph correspond to the K2 second bits; or, the parity check matrix of the third bit sequence corresponds to a second base graph, and the second information columns in the second base graph correspond to the first bit sequence of length N1. The processing unit is further configured to determine the K1 first bits and the K2 second bits based on a decoding result.

19. The device according to claim 18, characterized in that When the first bit sequence with a length of N1 fails to pass the check and K1 first bits in the first bit sequence with a length of N1 pass the cyclic redundancy check CRC check, or when the first bit sequence with a length of N1 passes the check and the third bit sequence fails the check, the processing unit is specifically configured to perform LDPC decoding on other to-be-decoded information in the to-be-decoded information of the third bit sequence except the to-be-decoded information of the first bit sequence to obtain the K2 second bits.

20. The device according to any one of claims 16 to 19, characterized in that The corresponding relationship of the first information column includes the relationship between the column index in the first information column, the row index of the first information column, and the translation value.

21. The device according to any one of claims 16 to 20, characterized in that The row weight of the first part of the first information column is greater than the row weight of the second part of the first information column, and the first part and the second part do not overlap.

22. The device according to any one of claims 16 to 21, characterized in that The first information row includes a punch hole row.

23. The device according to any one of claims 16 to 22, characterized in that The third bit sequence includes the encoded bits corresponding to the punctured column in the first information column.

24. The device according to any one of claims 16 to 19, characterized in that The second information column is determined based on a first reliability order.

25. The device according to claim 24, characterized in that The first reliability order is determined based on at least one of column weight or puncture column of the information column in the second base graph.

26. The device according to claim 24 or 25, characterized in that The first reliability order is a reliability order determined from a plurality of reliability orders based on at least one of the following: The ratio of K1 to K2, the length N2 of the third bit sequence, and the encoding rate of the second bit sequence are determined.

27. The device according to any one of claims 24 to 26, characterized in that The second information row includes a punch hole row.

28. The device according to any one of claims 22 to 27, characterized in that The third bit sequence includes the encoded bits corresponding to the punctured column in the second information column.

29. The device according to claim 16 or 17, characterized in that The device further comprises: The transceiver unit is used to send indication information, where the indication information is used to indicate at least one of the following: N1, K1, K2, the position of the first bit sequence in the third bit sequence, and the expansion factor of the check matrix.

30. The device according to any one of claims 16, 17 or 29, characterized in that The device further comprises: The transceiver unit is used to send indication information, where the indication information is used to indicate one of the following: a shortened position in the third bit sequence or a punctured position in the third bit sequence.

31. A communication device, characterized in that: including processor and memory; The processor is used to store computer instructions; The processor is configured to execute the computer instructions so that the method according to any one of claims 1, 2, 5-15 is executed, or the method according to any one of claims 3-13 is executed.

32. A communication device, characterized in that: comprising a logic circuit and an interface, wherein the logic circuit and the interface are coupled; The interface is used to input data to be processed, the logic circuit processes the data to be processed according to the method according to any one of claims 1 to 15 to obtain processed data, and the interface is used to output the processed data.

33. A computer-readable storage medium, characterized in that The computer-readable storage medium is used to store instructions. When the instructions are executed, the method according to any one of claims 1 to 15 is performed.

34. A computer program product, characterized in that When the instructions are executed on a computer, the method according to any one of claims 1 to 15 is executed.

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