Storage performance optimization method, storage device and electronic device

Abstract

The invention relates to a storage technology, and provides a storage performance optimization method, storage equipment and electronic equipment. The method is applied to the storage device and comprises the steps that whether data stored in a flash memory block of the storage device is invalid data or not is determined; if it is determined that the data stored in the flash memory block is invalid data, the data of all storage units in the flash memory block are programmed into a preset state mode, and the preset state mode is determined and obtained according to the corresponding relation between the number of multiple error bits and the state mode corresponding to each error bit number; and adding the identifier of the flash memory block to a free block list of the storage device. By means of the method, the data storage capacity of the storage device can be improved.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular, to a method for optimizing storage performance, a storage device, and an electronic device. Background Art

[0002] By injecting electrons into the storage units of a storage device, a data writing operation can be achieved. However, over time, the electrons injected into the storage units will gradually dissipate (escape), resulting in errors in the data stored in the storage units, thereby affecting the storage performance of the storage device. Summary of the Invention

[0003] In view of the above, it is necessary to provide a method for optimizing storage performance, a storage device, and an electronic device, which can solve the technical problem that the data stored in the storage units is in error due to electron dissipation, thereby affecting the storage performance of the storage device.

[0004] On the one hand, this application provides a method for optimizing storage performance, which is applied to a storage device. The method includes: determining whether the data stored in the flash memory blocks of the storage device is invalid data; if it is determined that the data stored in the flash memory blocks is invalid data, programming the data of all storage units in the flash memory blocks into a preset state mode, where the preset state mode is determined according to the corresponding relationship between multiple error bit numbers and the state modes corresponding to each error bit number, and adding the identifier of the flash memory block to the free block list of the storage device.

[0005] In some embodiments of this application, the determination of the preset state mode includes: writing data of different state modes to multiple groups of flash memory blocks, where each group of flash memory blocks corresponds to a state mode; after a first preset time of writing the data, erasing the written data from each group of flash memory blocks, and writing the same random data to the multiple groups of flash memory blocks; after a second preset time of writing the random data, reading the data of each group of flash memory blocks to obtain the read data corresponding to each group of flash memory blocks; and determining the preset state mode from multiple state modes based on the read data corresponding to each group of flash memory blocks and the written random data.

[0006] In some embodiments of this application, the determining the preset state mode from multiple state modes based on the read data corresponding to each group of flash memory blocks and the written random data includes: calculating the number of error bits of each group of flash memory blocks according to the read data corresponding to each group of flash memory blocks and the written random data, and determining the preset state mode from the multiple state modes according to the number of error bits of the multiple groups of flash memory blocks.

[0007] In some embodiments of the present application, calculating the number of error bits for each group of flash memory blocks based on the read data and the written random data corresponding to each group of flash memory blocks includes: comparing the read data in each group of flash memory blocks with the corresponding written random data, counting the total number of bits of the read data that is different from the corresponding written random data, and determining the total number of bits as the number of error bits for this group of flash memory blocks.

[0008] In some embodiments of the present application, determining the preset state mode from the multiple state modes according to the number of error bits of the multiple groups of flash memory blocks includes: generating a box plot of the corresponding state mode according to the number of error bits of each group of flash memory blocks, determining the change trend of the number of error bits corresponding to the multiple state modes according to the box plot, and determining the preset state mode from the multiple state modes according to the change trend.

[0009] In some embodiments of the present application, determining whether the data stored in the flash memory block of the storage device is invalid data includes: when receiving a command to write data to the flash memory block, determining that the data stored in the flash memory block is invalid data.

[0010] In some embodiments of the present application, programming the data of all storage units in the flash memory block into the preset state mode includes: programming the data of all storage units into the preset state mode by performing a rewrite operation on the original state mode of all storage units.

[0011] In some embodiments of the present application, the method further includes: when the storage device is in an idle state, programming the data of all storage units in the flash memory block into the preset state mode.

[0012] On the other hand, the present application provides a storage device, which includes: a memory storing at least one instruction, and a controller executing the at least one instruction to implement the storage performance optimization method described above.

[0013] On the other hand, the present application provides an electronic device, which includes: a processing device and the storage device described above.

[0014] Through the above embodiments, since the preset state mode is determined by the number of error bits corresponding to different state modes, and the number of error bits is the number of data errors, the fewer the number of data errors, the higher the storage performance of the flash memory block for data. The preset state mode can be the state mode corresponding to the minimum number of data errors. Therefore, updating the state mode of the storage units in the flash memory block to the preset state mode can reduce the number of data errors, thereby improving the storage capacity of the storage device for data. Description of the Drawings

[0015] Figure 1 It is a schematic structural diagram of a storage device provided by an embodiment of the present application.

[0016] Figure 2 It is a schematic diagram showing the distribution of storage units with threshold voltages for three - layer storage provided by an embodiment of the present application.

[0017] Figure 3 It is a flowchart of a storage performance optimization method provided by an embodiment of the present application.

[0018] Figure 4 It is a flowchart of a method for determining a preset state mode provided by an embodiment of the present application.

[0019] Figure 5 It is a flowchart of a method for determining a preset state mode provided by another embodiment of the present application.

[0020] Figure 6 It is a schematic diagram of a box - and - whisker plot provided by an embodiment of the present application.

[0021] Figure 7 It is a functional module diagram of a storage performance optimization device provided by an embodiment of the present application.

[0022] Figure 8 It is a schematic structural diagram of an electronic device provided by an embodiment of the present application. Detailed implementation manners

[0023] It should be noted that in the present application, "at least one" means one or more, and "a plurality" means two or more than two. "And / or" describes the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone, where A and B can be singular or plural. Terms such as "first", "second", "third", "fourth", etc. (if any) in the specification, claims, and drawings of the present application are used to distinguish similar objects, rather than to describe a specific order or sequence.

[0024] In the embodiments of the present application, words such as "exemplary" or "for example" are used to represent examples, illustrations, or explanations. Any embodiment or design solution described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or having more advantages than other embodiments or design solutions. Exactly, using words such as "exemplary" or "for example" is intended to present related concepts in a specific manner. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0025] By injecting electrons into the storage cells of a storage device, a write operation of data can be achieved. However, over time, the electrons injected into the storage cells will gradually dissipate (escape), resulting in errors in the data stored in the storage cells, thereby affecting the storage performance of the storage device.

[0026] To solve this technical problem, embodiments of the present application provide a storage performance optimization method, a storage device, and an electronic device, which can reduce the number of data errors, thereby improving the data storage capacity of the storage device. The storage performance optimization method provided by the embodiments of the present application can be applied to one or more storage devices, or the storage performance optimization method provided by the embodiments of the present application can be applied to one or more electronic devices including the storage device. The storage performance optimization method will be described below in combination with the application scenario and the flowchart.

[0027] As Figure 1 shown, it is a schematic structural diagram of a storage device provided by an embodiment of the present application. The storage device 10 may be a solid state drive (SSD), a universal flash storage device (UFS), an embedded multi media card (eMMC), etc. The embodiments of the present application do not limit the specific type of the storage device.

[0028] In Figure 1 , the storage device 10 includes a memory 101, a controller 102, and a buffer 103.

[0029] The memory 101 may include one or more non-volatile memories (NVM). The non-volatile memory may include flash memory (NAND Flash), and the flash memory is also called a flash memory chip. The flash memory includes several flash blocks, each flash block includes several pages, and each page includes several storage cells. The capacities of different types of storage cells are different, and the types of storage cells include but are not limited to: single-level cell (SLC), multi-level cell (MLC), trinary-level cell (TLC), quad-level cell (QLC), penta-level cell (PLC), etc.

[0030] Among them, the capacity of the storage cell of the SLC type is 1 bit / cell, that is, each storage cell can store 1 bit of information and has 2 data states (0 and 1). The capacity of the storage cell of the MLC type is 2 bit / cell, that is, each storage cell can store 2 bits of information and has 4 data states (00, 01, 10, and 11). The capacity of the storage cell of the TLC type is 3 bit / cell, that is, each storage cell can store 3 bits of information and has 8 data states (000, 001, 010, 011, 100, 101, 110, and 111). The capacity of the storage cell of the QLC type is 4 bit / cell, that is, each storage cell can store 4 bits of information and has 16 data states. The capacity of the storage cell of the PLC type is 5 bit / cell, that is, each storage cell can store 5 bits of information and has 32 data states.

[0031] Each data state has a corresponding threshold voltage. The threshold voltage can be a value range of the voltage threshold. The threshold voltage is the voltage provided to the storage cell during an erase operation, a program operation, or a read operation on the storage cell.

[0032] Taking TLC as an example, as Figure 2 shown, it is a schematic diagram of the distribution of the threshold voltage of the storage cell of the three-layer storage provided by an embodiment of the present application. In Figure 2 , the 8 data states of the TLC type correspond to 8 different threshold voltages, which are erase, L1, L2, L3, L4, L5, L6, and L7 respectively. Among them, the data state 111 can correspond to the threshold voltage erase, the data state 011 can correspond to the threshold voltage L1, the data state 001 can correspond to the threshold voltage L2, the data state 000 can correspond to the threshold voltage L3, the data state 010 can correspond to the threshold voltage L4, the data state 110 can correspond to the threshold voltage L5, the data state 100 can correspond to the threshold voltage L6, and the data state 101 can correspond to the threshold voltage L7. From Figure 2 it can be seen that from the threshold voltage erase to the threshold voltage L7, the value of the threshold voltage gradually increases, and the threshold voltage L7 is the maximum threshold voltage of TLC.

[0033] The memory 101 is used to store one or more computer programs. The one or more computer programs are configured to be executed by the controller 102. The one or more computer programs include a plurality of instructions. When the plurality of instructions are executed by the controller 102, a storage performance optimization method executed on the storage device 10 can be realized.

[0034] The controller 102 has functions such as managing data read / write, error checking and error correction, and garbage collection. The controller 102 monitors and manages the operation of the memory 101 to ensure data reliability and high performance. For example, the controller 102 is used to execute the computer program stored in the memory 101 to implement the above storage performance optimization method.

[0035] The buffer 103 may include one or more random access memories (RAM). The random access memory can be directly read and written by the controller 102 and can be used to store executable programs (such as machine instructions) of other running programs, and can also be used to store user and application data, etc. The random access memory may include a dynamic random access memory (DRAM). The random access memory can also be used as a cache particle in the storage device 10 to quickly receive external data. For example, data can be first written into the random access memory and then written from the random access memory into the non-volatile memory.

[0036] It can be understood that the structure illustrated in the embodiments of the present application does not constitute a specific limitation on the storage device 10. In other embodiments of the present application, the storage device 10 may include more or fewer components than shown in the figure, or combine certain components, or split certain components, or have different component arrangements. The illustrated components can be implemented in hardware, software, or a combination of software and hardware.

[0037] As Figure 3 shown, it is a flowchart of a storage performance optimization method provided by an embodiment of the present application. According to different requirements, the order of each step in this flowchart can be adjusted according to actual requirements, and some steps can be omitted. Below, the storage performance optimization method will be described by taking it as an example when applied to a storage device (such as Figure 1 the storage device 10 in).

[0038] S11, determine whether the data stored in the flash memory block of the storage device is invalid data.

[0039] In some embodiments, the storage device may be a solid state drive (SSD), a universal flash storage device (UFS), an embedded multi media card (eMMC), or other devices.

[0040] In some embodiments of the present application, determining whether the data stored in the flash memory block of the storage device is invalid data includes: when receiving a command to write data to the flash memory block, the storage device determines that the data stored in the flash memory block is invalid data.

[0041] Among them, the command can be a command sent from the host of the electronic device. The storage device determines whether the data stored in the flash memory block is invalid data through the received command. Among them, the electronic device includes but is not limited to: computers, tablets, smart phones, servers, etc. The present application does not limit the electronic device. The host can be the processing device of the electronic device. The storage device and the host can be connected in various ways. The present application does not limit the connection method between the host and the storage device. For example, the storage device and the host can be connected through a Serial Advanced Technology Attachment (SATA) interface or a Peripheral Component Interconnect Express (PCIe) interface.

[0042] For example, the storage device receives command A sent from the host through an interface (such as a SATA interface). Command A instructs the storage device to write data A to flash memory block A of the storage device. Therefore, the storage device writes data A to flash memory block A according to the received command A. If the storage device receives command B sent from the host again, command B instructs the storage device to write data B to flash memory block A. Since the flash memory has the characteristic of not being able to perform overwrite writing, when receiving the above command B, the storage device can determine that the host wants to overwrite data A in flash memory block A. At this time, it can be determined that data A stored in flash memory block A is invalid data.

[0043] In other embodiments of the present application, the storage device can determine whether the data stored in the flash memory block is invalid data through other methods. The present application does not limit the method for determining whether the data stored in the flash memory block is invalid data. For example, the storage device can obtain the flag bits of each storage unit in the flash memory block and determine whether the data in the corresponding storage unit is invalid data according to the flag bits.

[0044] In this embodiment, if it is determined that the data stored in the flash memory block of the storage device is invalid data, the storage device executes step S12. Or, if it is determined that the data stored in the flash memory block of the storage device is not invalid data, the storage device executes step S14. By determining whether the data stored in the flash memory block is invalid data, it provides a basis for whether to program the data in the flash memory block into a preset state mode in the following text.

[0045] S12, program the data of all storage units in the flash memory block into a preset state mode.

[0046] In some embodiments, the preset state mode can be determined according to the correspondence between a plurality of error bit numbers and the state modes corresponding to each error bit number by writing data of a plurality of state modes into multiple groups of flash memory blocks of a storage device. The storage device performs operations such as erasing, programming (writing), or reading on the storage cells by providing (applying) threshold voltages to the storage cells. Therefore, the state mode refers to the mode of the threshold voltages provided to the storage cells during operations such as erasing, programming (writing), or reading on the storage cells. Each state mode includes one or more data states, each state mode has a corresponding number of error bits, and multiple state modes correspond to multiple error bit numbers.

[0047] For example, continuing with the above embodiments, if the type of the storage cell is TLC, the multiple state modes in this embodiment can be three, namely the erase pattern, the Random pattern, and the L7 pattern. Among them, the data state corresponding to the erase pattern is 111, the Random pattern corresponds to 8 different data states, which are 000,

[0048] 001, 010, 011, 100, 101, 110, and 111, and the data state corresponding to the L7 pattern is 101. Among them, the above multiple state modes are only examples, and are not limited to this in practical applications.

[0049] Eight different threshold voltages can be applied to the storage cells in the Random pattern. For example, if data is written into a flash memory block in the Random pattern, eight different threshold voltages (erase - L7 state) can be provided to the flash memory block, so that the distribution of the storage cells corresponding to the eight different data states is close to an average distribution. For example, if a flash memory block consists of 160,000 storage cells, the number of storage cells corresponding to each of the eight data states is approximately equal to 20,000.

[0050] Since the preset state modes corresponding to each type of storage device are often the same, the preset state mode only needs to be determined through experiments on one storage device, and it is not necessary to perform the determination process of the preset state mode on all storage devices of the same type. Therefore, the determination process of the preset state mode can be performed on the above storage device, or on another storage device of the same type as the above storage device.

[0051] For example, through experiments on storage device A, the number of error bits corresponding to each state mode can be determined, and a preset state mode can be determined from multiple state modes according to the number of error bits. Storage device B can generate an execution instruction according to the determined preset state mode. When it is determined that the data stored in the built-in flash memory block b is invalid data, storage device B can program the data of all storage units in flash memory block b into the preset state mode through the execution instruction. Among them, storage device A and storage device B are of the same type.

[0052] In some embodiments of the present application, programming the data of all storage units in a flash memory block into a preset state mode by the storage device includes: the storage device programs the data of all storage units into the preset state mode by performing a rewrite operation on the original state mode of all storage units. Among them, the operation of rewriting the original state mode of all storage units can refer to related technologies, and the present application will not describe it in detail here.

[0053] In other embodiments of the present application, when the storage device is in an idle state, the storage device programs the data of all storage units in the flash memory block into the preset state mode.

[0054] In this embodiment, programming the data of the storage unit into the preset state mode only when the storage device is in an idle state can avoid affecting the read / write function in the storage device.

[0055] Through the above implementation manner, when it is determined that the data stored in the flash memory block becomes invalid data, the invalid data is written into the preset state mode, which can avoid data errors or losses. In addition, by directly writing the invalid data into the preset state mode without first erasing the invalid data and then writing the data of the preset state mode into the flash memory block, the damage caused by erasing to the flash memory block can be reduced.

[0056] S13, add the identifier of the flash memory block to the free block list of the storage device.

[0057] In this embodiment, the free block list is used to record the identifiers of currently unused flash memory blocks (free blocks) so that when new data needs to be stored, available free blocks can be quickly found.

[0058] S14, do not program the data of all storage units in the flash memory block into the preset state mode.

[0059] In this embodiment, since the data stored in the flash memory block is not invalid data, not programming the data of all storage units in the flash memory block into the preset state mode can avoid data errors or losses.

[0060] Through the above embodiments, since the preset state mode is determined by the number of error bits corresponding to different state modes, and the number of error bits is the number of data errors, the fewer the number of data errors, the higher the storage performance of the flash block for data. The preset state mode can be the state mode corresponding to the minimum number of data errors. Therefore, updating the state mode of the storage units in the flash block to the preset state mode can reduce the number of data errors, thereby improving the storage capacity of the storage device for data.

[0061] In some embodiments of the present application, as Figure 4 shown, it is a flowchart of a method for determining a preset state mode provided by an embodiment of the present application.

[0062] S121, the storage device writes data with different state modes to multiple groups of flash blocks, and each group of flash blocks corresponds to a state mode.

[0063] In this embodiment, the storage device can be the above storage device or another storage device for experiments. The specific content can refer to the description of step S11 above. The number of flash blocks in each group of flash blocks can be set by itself, and the present application does not limit this. To ensure the accuracy of determining the preset state mode, the number of flash blocks between multiple groups of flash blocks is the same.

[0064] For example, if there are 3 state modes, namely the erase state mode, the random state mode, and the L7 state mode, the flash blocks can be divided into 3 groups, and the erase state mode, the random state mode, and the L7 state mode respectively correspond to a group of flash blocks.

[0065] In the embodiments of the present application, the storage device can provide different threshold voltages to multiple groups of flash blocks, and write data corresponding to the state mode to each storage unit in each group of flash blocks, so that the electrons (charges) stored in each storage unit have corresponding threshold voltages.

[0066] S122, after the first preset time of writing data, the storage device erases the written data from each group of flash blocks and writes the same random data to multiple groups of flash blocks.

[0067] In this embodiment, the first preset time can be set by itself, and the present application does not limit this. For example, the first preset time can be 7 days. The random data can be any generated data.

[0068] S123, after the second preset time of writing random data, the storage device reads the data of each group of flash blocks to obtain the read data corresponding to each group of flash blocks.

[0069] In this embodiment, the second preset time can be set by itself, and the present application does not limit this. For example, the second preset time can be three months. The storage device can determine the read data of each storage unit in each group of flash blocks by detecting the threshold voltage of each storage unit in each group of flash blocks and mapping the detected threshold voltage to binary data.

[0070] S124. The storage device determines a preset state mode from multiple state modes based on the read data corresponding to each group of flash blocks and the written random data.

[0071] In some embodiments of the present application, the storage device determines a preset state mode from multiple state modes based on the read data corresponding to each group of flash blocks and the written random data, including: calculating the number of error bits of each group of flash blocks according to the read data corresponding to each group of flash blocks and the written random data, and determining the preset state mode from multiple state modes according to the number of error bits (FailBit Count, FBC) of multiple groups of flash blocks.

[0072] Specifically, the storage device can compare the read data in each group of flash blocks with the corresponding written random data, count the total number of bits of the read data that is different from the corresponding written random data, and determine the total number of bits as the number of error bits of the group of flash blocks.

[0073] For example, if the random data written to a flash block is "1100", after the second preset time, the flash block is read, and the read data obtained is "1000". By comparison, it can be known that there is an inconsistency in the second bit between "1100" and "1000". At this time, the number of error bits can be incremented by one. By analogy, the total number of bits of all flash blocks and / or the corresponding random data of each flash block in each group of flash blocks can be calculated as the number of error bits.

[0074] In some embodiments of the present application, as Figure 5 shown, it is a flowchart of a method for determining a preset state mode provided by another embodiment of the present application.

[0075] S1241. The storage device generates a box plot of the corresponding state mode according to the number of error bits of each group of flash blocks.

[0076] In some embodiments of the present application, each group of flash blocks corresponds to a box plot, and multiple groups of flash blocks can generate multiple box plots. For example, if the flash blocks are divided into 3 groups, the erase state mode, the random state mode, and the L7 state mode respectively correspond to a group of flash blocks. As Figure 6 shown, it is a schematic diagram of a box plot provided by an embodiment of the present application. In Figure 6Among them, the erase pattern, the random pattern, and the L7 pattern have corresponding box plots.

[0077] In this embodiment, by plotting multiple box plots, since box plots have intuitiveness and comparability, it is possible to conveniently compare the changing trends of the number of error bits corresponding to different state patterns.

[0078] S1242. The storage device determines the changing trends of the number of error bits corresponding to multiple state patterns according to the box plots.

[0079] For example, in Figure 6 Among them, the connection lines between the three box plots can reflect the changing trends of the number of error bits corresponding to multiple state patterns. As can be seen from Figure 6 it, the number of error bits corresponding to the erase pattern, the random pattern, and the L7 pattern shows a decreasing (reducing) changing trend in sequence.

[0080] S1243. The storage device determines a preset state pattern from multiple state patterns according to the changing trend.

[0081] For example, in Figure 6 Among them, since the number of error bits corresponding to the erase pattern, the random pattern, and the L7 pattern shows a decreasing (reducing) changing trend in sequence, the number of error bits corresponding to the L7 pattern is the least. Thus, it can be seen that when data in the L7 state pattern has been stored in the flash memory block, the number of errors in the random numbers subsequently written to this flash memory block is the least. Therefore, the data in the L7 state pattern can improve the storage performance of the flash memory block for subsequent data, and thus the L7 state pattern can be determined as the preset state pattern.

[0082] In some embodiments of the present application, different types of storage devices will correspond to different preset state patterns. The process of determining the L7 state pattern as the preset state pattern above is only an example and does not constitute a limitation on the preset state pattern.

[0083] In other embodiments of the present application, the storage device can determine the preset state pattern from multiple state patterns by other means, and the present application does not limit the method for determining the preset state pattern.

[0084] As Figure 7 shown, it is a functional module diagram of a storage performance optimization device provided by an embodiment of the present application. The storage performance optimization device 104 includes a determination unit 1041, a programming unit 1042, and an addition unit 1043. The modules / units referred to in the present application refer to a kind of entity that can be Figure 1acquired by the controller 102 therein, and is a series of computer-readable instruction segments capable of performing fixed functions, which are stored in Figure 1 the memory 101 therein. In this embodiment, the functions of each module / unit will be described in detail in subsequent embodiments.

[0085] A determination unit 1041, configured to determine whether the data stored in the flash memory block of the storage device is invalid data.

[0086] A programming unit 1042, configured to, if it is determined that the data stored in the flash memory block is invalid data, program the data of all storage units in the flash memory block into a preset state mode, where the preset state mode is determined according to the correspondence between a plurality of error bit numbers and the state modes corresponding to each error bit number.

[0087] An adding unit 1043, configured to add an identifier of the flash memory block to a free block list of the storage device.

[0088] In some embodiments of the present application, the above storage performance optimization method can also be applied to an electronic device including the above storage device. As Figure 8 shown, it is a schematic structural diagram of an electronic device provided in an embodiment of the present application. Figure 8 The electronic device 1 therein can be an electronic device such as a mobile phone, a tablet computer, a notebook computer, and a server, and the specific type of the electronic device 1 is not limited in the embodiments of the present application.

[0089] In Figure 8 the electronic device 1 may include a storage device 10, a processing device 12, a communication module 14, an input / output (I / O) interface 16, and a bus 18. Among them, the processing device 12 is respectively coupled to the storage device 10, the communication module 14, and the input / output interface 16 through the bus 18. The specific structure of the storage device 10 can refer to Figure 1 this application, and will not be described again here.

[0090] The communication module 14 may include a wired communication module and / or a wireless communication module. The wired communication module may provide one or more of the solutions for wired communication such as universal serial bus (USB), Controller Area Network (CAN), etc. The wireless communication module may provide one or more of the solutions for wireless communication such as wireless fidelity (Wi-Fi), Bluetooth (BT), mobile communication network, frequency modulation (FM), near field communication (NFC), infrared (IR), etc.

[0091] The processing device 12 may include one or more processing units. For example, the processing device 12 may include an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), and / or a neural-network processing unit (NPU), etc. Among them, different processing units may be independent devices or integrated in one or more processors.

[0092] The processing device 12 provides computing and control capabilities. For example, the processing device 12 may act as a host by sending commands to the storage device 10 to implement the above storage performance optimization method.

[0093] The input / output interface 16 is used to provide channels for user input or output. For example, the input / output interface 16 can be used to connect various input and output devices, such as a mouse, a keyboard, a touch device, a display screen, etc., so that the user can enter information or visualize the information.

[0094] The bus 18 is at least used to provide a communication channel for mutual communication between the communication module 14, the storage device 10, the processing device 12, and the input / output interface 16 in the electronic device 1.

[0095] It can be understood that the structure illustrated in the embodiments of the present application does not constitute a specific limitation on the electronic device 1. In other embodiments of the present application, the electronic device 1 may include more or fewer components than shown in the figures, or combine certain components, or split certain components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0096] In several embodiments provided in the present application, it should be understood that the disclosed systems, devices, and methods may be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the modules is only a logical function division, and there may be other division methods in actual implementation.

[0097] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0098] In addition, in each embodiment of the present application, the various functional modules may be integrated in a processing unit, or each unit may exist physically separately, or two or more units may be integrated in one unit. The above-mentioned integrated units may be implemented in the form of hardware, or in the form of a combination of hardware and software functional modules.

[0099] Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the present application is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be included in the present application. Any reference signs in the claims should not be regarded as limiting the claimed rights.

[0100] In addition, obviously, the term "including" does not exclude other units or steps, and the singular does not exclude the plural. The multiple units or devices described in the present application may also be implemented by one unit or device through software or hardware. The terms such as first and second are used to represent names and do not indicate any specific order.

[0101] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application and not to limit them. Although the present application has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present application may be modified or equivalently replaced without departing from the spirit and scope of the technical solutions of the present application.

Claims

1. A storage performance optimization method, applied to a storage device, characterized in that, The method includes: Determining whether the data stored in the flash memory block of the storage device is invalid data; If it is determined that the data stored in the flash memory block is invalid data, programming the data of all storage units in the flash memory block into a preset state mode, where the preset state mode is determined according to the corresponding relationship between a plurality of error bit counts and the state modes corresponding to each error bit count; Adding the identifier of the flash memory block to the free block list of the storage device.

2. The storage performance optimization method according to claim 1, wherein, The determination of the preset state mode includes: Writing data of different state modes to multiple groups of flash memory blocks, with each group of flash memory blocks corresponding to a state mode; After a first preset time of writing the data, erasing the written data from each group of flash memory blocks and writing the same random data to the multiple groups of flash memory blocks; After a second preset time of writing the random data, reading the data of each group of flash memory blocks to obtain the read data corresponding to each group of flash memory blocks; Based on the read data corresponding to each group of flash memory blocks and the written random data, determining the preset state mode from a plurality of state modes.

3. The storage performance optimization method according to claim 2, wherein, The determining the preset state mode from a plurality of state modes based on the read data corresponding to each group of flash memory blocks and the written random data includes: Calculating the error bit count of each group of flash memory blocks according to the read data corresponding to each group of flash memory blocks and the written random data; Determining the preset state mode from the plurality of state modes according to the error bit counts of the multiple groups of flash memory blocks.

4. The storage performance optimization method according to claim 3, wherein The calculating the error bit count of each group of flash memory blocks according to the read data corresponding to each group of flash memory blocks and the written random data includes: Comparing the read data in each group of flash memory blocks with the corresponding written random data, counting the total number of bits of the read data that is different from the corresponding written random data, and determining the total number of bits as the error bit count of the group of flash memory blocks.

5. The storage performance optimization method according to claim 3, characterized in that The determining the preset state mode from the plurality of state modes according to the error bit counts of the multiple groups of flash memory blocks includes: Generating a box plot of the state mode corresponding to each group of flash memory blocks according to all the error bit counts of each group of flash memory blocks; Determining the change trend of the error bit counts corresponding to the plurality of state modes according to the box plot; Determining the preset state mode from the plurality of state modes according to the change trend.

6. The storage performance optimization method according to claim 1, wherein The determining whether the data stored in the flash memory block of the storage device is invalid data includes: When receiving a command to write data to the flash memory block, determining that the data stored in the flash memory block is invalid data.

7. The storage performance optimization method according to claim 1, wherein The programming the data of all storage units in the flash memory block into a preset state mode includes: By performing a rewrite operation on the original state mode of all the storage units, programming the data of all the storage units into the preset state mode.

8. The storage performance optimization method according to claim 1, wherein The method further includes: When the storage device is in an idle state, programming the data of all storage units in the flash memory block into the preset state mode.

9. A storage device, characterized in that, The storage device includes: A memory storing at least one instruction; and A controller that executes the at least one instruction to implement the storage performance optimization method according to any one of claims 1 to 8.

10. An electronic device, characterized in that, The electronic device includes: a processing device and a storage device as described in claim 9.

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