Devices, systems, and methods for low latency selection policies for memory commands

Abstract

The disclosure relates to devices, systems, and methods for low latency selection policies for memory commands. Memory controller commands to be sent to a memory device may be prioritized based on one or more factors. For example, a memory controller may employ a first ready first come first service (FRFCFS) policy in which certain types of commands (e.g., reads) are prior to other types of commands (e.g., writes). The policy may be modified such that, upon determining which bank is to be opened, the bank with the oldest read command is opened. While commands continue to be issued according to this modified FRFCFS policy, the controller may record banks whose pages are ready to receive their respective read commands. Once the number of ready banks meets or exceeds a threshold, issuing of write commands is suspended and read commands for the ready banks are issued.

Description

Technical Field

[0001] The present disclosure generally relates to memories, and more particularly, to devices and methods associated with command selection strategies. Background Art

[0002] Memory devices are typically provided as internal semiconductor integrated circuits in a computer or other electronic device. Data may be stored in memory cells that can be arranged in an array, where the array is used in the memory device. There are many different types of memories, including volatile and non-volatile memories. Volatile memories may require power to maintain their data and include random access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), etc. Non-volatile memories can provide permanent data by retaining the stored data when not powered, and can include NAND flash memory, NOR flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), and resistive change memories (such as phase change random access memory (PCRAM)), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), etc.

[0003] Various computing systems include processing resources (such as a processor) that are typically coupled to a memory device via a memory controller. A computing system (such as a host system) can access the memory device via the memory controller in association with executing a set of instructions (such as a program, an application, etc.). The instructions can cause the memory controller to issue commands to the memory device. The memory device, the memory controller, and / or both can implement a scheduling strategy for determining the order in which commands (such as reads and writes) are executed by the memory device and / or sent by the memory controller based on the instructions received from the processing resources. Such scheduling strategies affect computing system performance, for example, because the execution time of a program on the computing system is affected by the execution time associated with access requests to the memory device. Summary of the Invention

[0004] In one aspect, the present disclosure relates to a method that includes: receiving a plurality of commands at a controller; organizing the plurality of commands into a priority queue; and selecting a command from the plurality of commands from the priority queue to issue to a memory device based on a first-ready-first-come-first-served (FRFCFS) command selection strategy, where the FRFCFS command selection strategy is modified such that a bank of the memory device associated with the oldest read command is opened.

[0005] On the other hand, the present disclosure relates to an apparatus comprising: device timing parameter logic configured to store timing constraints of a memory device; a command queue configured to store a plurality of commands; and priority sorting logic configured to select commands from the plurality of commands for issuance to the memory device, wherein the commands are selected at least in part based on the timing constraints and a first-ready-first-come-first-served (FRFCFS) command selection policy, and wherein the FRFCFS command selection policy is modified such that a bank of the memory device associated with the oldest read command is opened.

[0006] In another aspect, the present disclosure relates to a system comprising: a memory system including a plurality of memory devices; a host system configured to issue a plurality of commands; and a controller configured to receive the plurality of commands from the host system and issue the plurality of commands to the memory system, wherein the controller issues the plurality of commands at least in part based on a first-ready-first-come-first-served (FRFCFS) command selection policy, and wherein the FRFCFS command selection policy is modified such that a bank of at least one of the plurality of memory devices associated with the oldest read command is opened. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram of an apparatus in the form of a computing system including a memory system and capable of implementing a command selection policy, in accordance with several embodiments of the present disclosure.

[0008] Figure 2 is a block diagram of a controller capable of implementing a command selection policy, in accordance with several embodiments of the present disclosure.

[0009] Figure 3 is a functional block diagram of a priority sorting logic, in accordance with several embodiments of the present disclosure.

[0010] Figure 4 is a timing diagram illustrating when a priority logic determines that a bank is ready, in accordance with several embodiments of the present disclosure.

[0011] Figure 5 illustrates an example of a command associated with implementing a command selection policy, in accordance with several embodiments of the present disclosure.

[0012] Figure 6 is a flowchart of a method, in accordance with several embodiments of the present disclosure. DETAILED DESCRIPTION

[0013] This disclosure includes systems, devices, and methods related to command selection strategies. The command selection strategy can schedule commands using command queue status and memory device row status. In some applications, the techniques disclosed herein can reduce latency with minimal impact on data bus utilization (e.g., bandwidth).

[0014] The following description of certain embodiments is exemplary only and is in no way intended to limit the scope of the disclosure or its application or uses. In the following detailed description of embodiments of the invention's systems and methods, reference is made to the accompanying drawings, which form a part hereof and show, by way of illustration, specific embodiments in which the described systems and methods may be practiced. The embodiments are described in sufficient detail to enable those skilled in the art to practice the presently disclosed systems and methods, and it is to be understood that other embodiments may be utilized and structural and logical changes may be made without departing from the spirit and scope of the disclosure. Additionally, for clarity, detailed descriptions of certain features that are apparent to those skilled in the art will not be set forth so as not to obscure the description of the embodiments of the disclosure. Accordingly, the following detailed description is not to be taken in a limiting sense, and the scope of the disclosure is defined only by the appended claims.

[0015] In the following detailed description of the disclosure, reference is made to the accompanying drawings, which form a part of the disclosure and in which are shown, by way of illustration, several embodiments of how the disclosure may be practiced. The embodiments are described in sufficient detail to enable those of ordinary skill in the art to practice the embodiments of the disclosure, and it is to be understood that other embodiments may be utilized and process, electrical, and / or structural changes may be made without departing from the scope of the disclosure. As used herein, the indicator "N" indicates that the several specific features so labeled may be included in several embodiments of the disclosure.

[0016] As used herein, "several" of something may refer to one or more of such things. For example, several memory devices may refer to one or more of the memory devices. "A plurality" of something is intended to be two or more. Additionally, as used herein, designators such as "N", particularly with respect to reference numerals in the figures, indicate that the several specific features so labeled may be included in several embodiments of the disclosure.

[0017] The figures herein follow a numbering convention where the first or first few digits correspond to the figure number and the remaining digits identify an element or component in the figure. As should be appreciated, elements shown in the various embodiments herein may be added, exchanged, and / or eliminated to provide several additional embodiments of the disclosure. Additionally, the proportions and relative scales of the elements provided in the figures are intended to illustrate the various embodiments of the disclosure and are not to be used in a limiting sense.

[0018] Those skilled in the art will understand that memories and memory arrays can be logically or physically or both logically and physically organized into columns and rows. Thus, as used herein, a "column" command refers to a command that is directed to an address of an open (e.g., activated) row (e.g., page) of an array corresponding to a memory device, and a "row" command refers to a command that is directed to an address of a closed (e.g., deactivated) row of an array. Additionally, several embodiments can be implemented by executing instructions stored on a machine-readable medium, which can include various non-transitory media, including but not limited to volatile and / or non-volatile memories such as solid-state memory, phase-change memory, ferroelectric memory, optical media, and / or magnetic media, and other types of machine-readable media.

[0019] DRAM command scheduling is a complex operation in which numerous physical and timing constraints must be considered in order to maximize bandwidth, minimize latency, reduce power, or some combination thereof. Examples of existing command selection strategies include FCFS (First-Come, First-Served) and FRFCFS (First-Ready, First-Come, First-Served).

[0020] The FCFS strategy can include scheduling commands for execution by a memory device (e.g., main memory such as a DRAM device) based on the order in which the commands are received (e.g., decoded) at the memory controller (e.g., from a host system). Thus, the oldest command is executed first. However, various memory systems include timing constraints that can affect whether a command can be issued (e.g., from the memory controller to the memory device). For example, various support circuitry associated with the memory array (e.g., row decoding circuitry, column decoding circuitry, sense amplifier circuitry, precharge circuitry, refresh circuitry, etc.) can include timing constraints that determine when / if the memory device is ready to execute a particular command. Thus, the FCFS strategy can increase execution latency because a newer command, if issued by the controller, may be able to be executed by the memory device (e.g., based on the timing constraints), but the command cannot be provided to the memory device until an older command is executed according to the FCFS strategy.

[0021] Compared to the FCFS strategy, the FRFCFS strategy can reduce latency. For example, in the FRFCFS strategy, the memory controller can iterate through the command queue and select the first command it encounters that can be issued because the memory device is ready to execute the command. Thus, older commands for which the memory device is not ready to execute (e.g., based on timing constraints) can be skipped in favor of newer pending commands for which the memory device is ready to execute. A command can be referred to as "ready to be issued from the controller" or "issuable from the controller" when the command can be executed by the memory device (e.g., the memory device is "ready" to execute the command).

[0022] Neither the FCFS policy nor the FRFCFS policy prioritizes the type of access command (e.g., a read command over a write command). U.S. Patent 10,409,739, incorporated herein by reference for any purpose, describes prioritizing read commands, which can improve system performance because the various instructions executed by a processing resource (e.g., a central processing unit) can depend on the execution of other instructions. The '739 patent describes a command selection policy that prioritizes read commands over write commands, which can provide benefits such as reducing the latency associated with read access requests to a memory device. While this is an advancement in the art, further improvements in latency and bandwidth may be desired.

[0023] The present disclosure describes a command selection policy that can reduce latency and can further have a negligible impact on bandwidth. Based on the embodiments disclosed herein, the command policy can follow the FRFCFS policy with the following modifications. When selecting a bank of an open memory device (which can include selecting which ACT command to terminate), the bank associated with the oldest read command can be selected by the controller. Additionally, when issuing commands according to the modified FRFCFS policy, the controller can record the number of banks (e.g., ready banks) that have pages ready to receive read commands. In some embodiments, a bank can be considered "ready" when a row-to-column timing constraint (tRCD), also known as a RAS-to-CAS delay, has passed. Once the number of ready banks exceeds a threshold, the controller can stop issuing write commands and issue read commands associated with the ready banks according to the modified FRFCFS policy. Once the read commands associated with the ready banks have been issued, the controller can return to issuing commands according to the modified FRFCFS policy.

[0024] Optionally, the threshold for the number of ready banks can be dynamic based on the percentage of commands in the command queue that are read commands. For example, the threshold can be lower when there are fewer read commands and higher when there are more read commands.

[0025] Optionally, the time at which a bank is considered a ready bank can be adjusted to a time before tRCD has passed. When a bank is determined to be ready after tRCD, there can be a delay in issuing a read command due to write-to-read turnaround time. To reduce the delay, the bank can be determined to be ready at a time earlier than tRCD. This earlier time can be based on the length of the write-to-read turnaround time. In this embodiment, the read command can be issued closer to the tRCD of the memory. This can reduce or eliminate incurring an additional write-to-read turnaround time penalty, which can further improve latency and / or bandwidth.

[0026] Figure 1is a block diagram of an apparatus in the form of a computing system 100 that includes a memory system 120 and is capable of implementing a command selection strategy, in accordance with at least one embodiment of the present disclosure. As used herein, "apparatus" may refer to, but is not limited to, various structures or combinations of structures, such as circuits or circuit systems, one or more dies, one or more modules, one or more devices, or one or more systems. For example, the controller 104, the host 102, the system 120, and / or the devices 110-1 to 110-N may each be referred to as an "apparatus" individually.

[0027] In this example, the computing system 100 includes a host 102 coupled to a controller 104 (e.g., via an interface 103), and the controller 104 is coupled to the memory system 120 (e.g., via an interface 105). The computing system 100 may be a laptop computer, a personal computer, a digital camera, a digital recording and playback device, a mobile phone, a PDA, a memory card reader, an interface hub, a sensor, an Internet of Things (IoT)-capable device, and other systems, and the host 102 may include several processing resources (e.g., one or more processors) capable of accessing the memory system 120 (e.g., via the controller 104). The host 102 may be responsible for the execution of an operating system (OS) and / or various application programs that may be loaded into it (e.g., from the memory system 120 via the controller 104).

[0028] The controller 104 may receive instructions from the host 102, which may include memory transaction requests (e.g., in the form of read and write commands, which may be referred to as load and store commands, respectively). The controller 104 may transfer commands and / or data between the host 102 and the memory system 120 via the interfaces 103 and 105, which may include physical interfaces, such as, for example, a bus employing a suitable protocol. This protocol may be custom or proprietary, or one or both of the interfaces 103 and 105 may employ a standardized protocol, such as Peripheral Component Interconnect Express (PCIe), Gen-Z, CCIX, or the like. The controller 104 may include control circuitry in the form of hardware, firmware, software, or any combination of the three. As an example, the controller 104 may include a state machine, a sequence generator, and / or some other type of control circuitry, which may be implemented in the form of an application specific integrated circuit (ASIC) coupled to a printed circuit board. Although the controller 104 is shown as being separate from the host 102 in Figure 1 it may be co-located with the host 102 in several embodiments (e.g., in a system-on-chip (SOC) configuration). In several embodiments, the controller 104 may be co-located with the memory system 120. For example, the controller 104 may be, for example, with Figure 2a controller of the controller 204 described in association therewith and configurable to implement a command selection strategy in accordance with several embodiments of the present disclosure, as further described below.

[0029] As Figure 1 shown, the memory system 120 includes several memory devices 110-1, 110-2, …, 110-N, which may be collectively referred to as memories 110. The memories 110 may include several physical memory “chips” or dies, each of which may include several memory cell arrays (e.g., banks) and corresponding support circuitry (e.g., address circuitry, I / O circuitry, control circuitry, read / write circuitry, etc.) associated with accessing the arrays (e.g., to read data from the arrays and write data to the arrays). As an example, the memory devices 110-1 to 110-N may include several DRAM devices, SRAM devices, PCRAM devices, RRAM devices, FeRAM, phase change memory, 3DXpoint, and / or flash memory devices. In several embodiments, the memory system 120 may be used as the main memory of a computing system. Although Figure 1 shown several memory devices 110-1, 110-2, …, 110-N, in some embodiments, the memory system 120 may include a single memory device 110.

[0030] Figure 2 is a block diagram of a controller capable of implementing a command selection strategy in accordance with several embodiments of the present disclosure. In some embodiments, the controller 204 may be at least a portion of a controller (e.g., Figure 1 the controller 104 shown). For example, the controller 204 may represent a command selection subsystem of the controller 104 for implementing a particular command selection strategy. As used herein, a command selection strategy may be referred to as a command scheduling strategy and may refer to selecting commands and / or scheduling commands (e.g., prioritizing them) for issuance to a memory device.

[0031] The controller 204 includes a command queue 230 for storing commands 232-0, 232-1, 232-2, …, 232-(i-1) (collectively referred to as commands 232) received from a device such as a host (e.g., 102) associated with incoming access requests to a memory system (e.g., 120). The controller 204 may decode incoming access requests (represented by arrow 203) and classify the corresponding commands 232 according to a desired command selection strategy. As an example, the received commands 232 may be classified based on various factors, including but not limited to command type (e.g., read or write), command address (e.g., whether the command is targeted at an open row or a closed row of the memory device), and / or command age (e.g., the time since the command was received), as well as various other factors, including the relationship of one command to another (e.g., read-after-write dependencies).

[0032] As Figure 2 shown in Figure 2 , the controller 204 may include command selection logic 240 for implementing a desired command selection policy. In this example, the command selection logic 240 includes prioritized (priority) queues 248-0 (Q0), 248-1 (Q1), 248-2 (Q2),..., 248-(k-1) (Qk-1) that may be collectively referred to as the prioritized queue 248, and device timing parameters 242 and prioritization logic 244 for implementing the desired command selection policy. Although Figure 2 shown in Figure 2 there are multiple prioritized queues 248, in some embodiments, only one prioritized queue 248 may be included.

[0033] The device timing parameter logic 242 may be responsible for tracking and accessing various timing constraints associated with the memory device to which commands will be issued. Such timing constraints may include, for example, constraints on the timing of various control signals (e.g., read / write enable signals) and / or address signals (e.g., row / column address signals) and various other signals. For example, if the memory device is a DRAM device, such timing parameters may include the minimum time required between an activate command (also known as an activation command) and a column command (e.g., tRCD), the minimum time required between column commands (e.g., tCCD), the minimum time between a precharge command and an activate command (e.g., tRP), and various other timing parameters (e.g., tRAS, tCAS, tCP, tASR, tASC, tCAH, etc.). The various timing parameters may be provided to the timing parameter logic 242 from a memory system, a memory device, and / or a host system coupled to the controller. In some embodiments, the timing parameters may be stored in the controller (e.g., registers and / or other storage devices), either within the device timing parameter logic 242 or in a separate component accessible to the device timing parameter logic 242.

[0034] For example, the device timing parameter logic 242 may be used to determine whether a command in the prioritized queue 248 is ready to be issued (e.g., whether the command can be sent to the memory device for execution without violating the device timing parameters). As used herein, the term "queue" is not intended to be limited to a particular data structure implementation, but rather the term queue may refer to a collection of elements organized in various ways and that may have one or more different types of queues and / or lists (e.g., lists, linked lists, etc.) and other characteristics.

[0035] The priority sorting logic 244 can be responsible for iterating through the commands 232 in the queue 230, determining the specified priority class of the received command 232, inserting the command 232 into the selected one in the priority queue 248, and iterating through the queue 248 (in priority order) to select a specific command to issue to the memory device. In Figure 2 In it, the arrow 247 represents the selected command sent to the memory device, and the arrow 249 represents the response from the memory device (e.g., corresponding to the selected command). The arrow 233 represents the command 232 that is provided to the command selection logic 240 to be inserted into one of the priority queues 248 based on its specified class and corresponding priority level. The arrow 235 represents the control signal associated with, for example, the command selection logic 240 iterating through the command 232 and removing it from the queue 230 once the command 232 has been issued to the memory device.

[0036] In several embodiments, the prioritized queue 248 is indexed in priority order such that the queue 248-0 has the highest priority and the queue 248-(k - 1) has the lowest priority. Queues with different priorities can be referred to as having a first priority, a second priority, a third priority, and the like. The difference in the priority of one queue is relative to another queue. Thus, a "higher" priority queue is given, or it has a priority over another queue. The highest priority queue thus has the highest priority of the prioritized queue 248, and the lowest priority queue has the lowest priority of the prioritized queue 248.

[0037] In some embodiments, the priority sorting logic 244 can assign a priority label to each command 232. The priority label can correspond to the respective different priority queues 248 and / or the position of a specific priority queue. For example, a command receiving a label corresponding to the highest priority is inserted into the highest priority queue 248-0, a command receiving a label corresponding to the next highest priority is inserted into the next highest priority queue 248-1, and so on. Additionally or alternatively, the priority label can determine the position where the command is inserted into a specific priority queue 248. The specified priority class of each command 232 can be determined based on various factors, including but not limited to whether the command is a read or write command, the type of read / write command (e.g., whether the command is a column read / write or a row read / write command), the age of the command, or a combination thereof.

[0038] The priority order of commands 232 within one or more corresponding priority queues 248 can be at least partially based on the age of the commands, such that the oldest command in the corresponding queue 248 has the highest priority and will be encountered first when iterating through the corresponding queue. As an example, iterating through at least some or a portion of one of the priority queues 248 in the priority queue 248 can include using the FRFCFS policy, where the first command encountered that is ready to be issued (e.g., based on device timing parameters) is selected for issuance. However, when determining which bank of an open memory device, the bank associated with the oldest read command can be selected by the priority sorting logic 244 to be issued by the controller 204 to the memory device. In some examples, this can result in read commands taking precedence over write commands.

[0039] Based at least in part on commands issued from the priority queue 248, the priority sorting logic 244 can record the number of banks of the memory device having pages ready to receive commands. For example, the priority sorting logic 244 can include a counter that increments when a precharge command for a bank has been issued and tRCD has passed and decrements when an activate command for the bank has been issued. In other embodiments, other techniques can be used for counting the number of ready banks. Before and / or after issuing a command from the priority queue 248, the priority sorting logic can compare the value in the counter (which represents the number of ready banks) with a threshold. Based on the comparison, the priority sorting logic 244 can preempt the FRFCFS policy and issue a read command from the priority queue 248 associated with the ready banks. For example, if the number of ready banks is equal to or greater than the threshold, then the priority sorting logic 244 can preempt the FRFCFS policy. In some embodiments, the FRFCFS policy can be applied to determine the order of issuance of read commands from the priority queue 248 associated with the ready banks. After the read commands associated with the ready banks have been issued, the controller can return to issuing commands according to the modified FRFCFS policy.

[0040] Optionally, in some embodiments, the threshold may be dynamic based on the conditions of the priority queue 248. For example, in some embodiments, the threshold may be based on the number of read commands in the priority queue 248. The priority sorting logic 244 may record the number of read commands in the priority queue 248. For example, the priority sorting logic 244 may include a counter that increments when a read command is provided from the command queue 230 and may decrement when a read command is issued from the priority queue 248 to the memory device. In some embodiments, the priority sorting logic 244 may have a single counter for all priority queues 248-0…248-(K-1). In other embodiments, the priority sorting logic 244 may have a separate counter for each priority queue 248. Before and / or after issuing a command from the priority queue 248, the priority sorting logic 244 may use the value in the counter representing the number of read commands in the priority queue 248 to select a threshold for determining whether the FRFCFS policy should be preempted. In some embodiments, the priority sorting logic 244 may make a determination globally based on the conditions of all queues 248. In other embodiments, the priority sorting logic 244 may make a determination individually for each queue 248.

[0041] Table 1 provides an example of how the threshold may be selected based on the number of read commands in the priority queue 248. The number of read commands is expressed as a percentage of the commands in the priority and queue 248 that are read commands, because the present disclosure is not limited to queues that can hold a specific number of commands.

[0042] Table 1: Thresholds Based on Read Command Percentage

[0043] Read % in Queue Threshold of Ready Banks 0% to 25% 1 25.01% to 50% 2 50.01% to 60% 6 60.01% to 100% 8

[0044] The values shown in Table 1 are for illustration only. In other embodiments, different percentages of read commands may be associated with different thresholds. Additionally, in some embodiments, the thresholds in Table 1 may be for a 1-rank memory system. In a 2-rank memory system, the threshold may be twice the threshold shown. For example, when the read commands represent 0 to 25% of the commands in the priority queue 248, for a 2-rank memory system, the threshold may be 2. In some applications, having a dynamic threshold may reduce the risk that write commands are unacceptably delayed by being frequently preempted by the FRFCFS policy.

[0045] Although the controller 204 is shown as having both a command queue 230 and a priority queue 248, in some embodiments, the controller 204 may omit the priority queue 248. In this embodiment, the priority sorting logic 244 may assign a priority label to commands and directly select commands to issue from the command queue 230 by iterating through the commands and / or based on a command selection policy.

[0046] Figure 3 is a functional block diagram of a priority sorting logic according to several embodiments of the present disclosure. In some embodiments, the priority sorting logic 344 may be included in the Figure 2 priority sorting logic 244 shown in. The priority sorting logic 344 includes a ready bank counter 350, a comparator 354, a threshold storage device 356, and queue logic 358. Optionally, the priority sorting logic 344 may include a read command counter 352. The priority sorting logic 344 may receive commands from a command queue (such as command queue 230) and may provide control signals to the command queue. The priority sorting logic 344 may provide commands to a device interface, such as a memory device interface. For example, commands may be provided to a memory system, such as memory system 120.

[0047] The queue logic 358 may receive commands from the command queue and place the commands in an appropriate position in a priority queue (such as priority queue 248) (or in one of multiple priority queues). In some embodiments described with reference to Figure 2 the queue logic 358 may assign a priority label to the received commands. According to an embodiment of the present disclosure, the queue logic 358 may further select commands to issue to the device interface based on a command selection policy. The queue logic 358 may provide signals indicating the commands that have been issued to the ready bank counter 350 and the read command counter 352.

[0048] The ready bank counter 350 may receive, for example, device timing parameters (and / or information related to device timing parameters) from the device timing parameter logic 242 and signals indicating the commands that have been issued from the queue logic 358. At least in part based on the issued commands and the device timing parameters, the ready bank counter may count the number of banks with open pages ready to receive commands (such as read and write commands). Optionally, in some embodiments, the ready bank counter also stores the addresses of the ready banks and may provide them to the queue logic 358. In other embodiments, the addresses may be stored in the queue logic 358 or another component of the priority logic 344. The ready bank counter 350 may increment the value of the number of ready banks when tRCD has elapsed after an activation command is issued for a bank. The ready bank counter 350 may decrement when a precharge command is issued for a bank. In other embodiments, other techniques may be used to count the number of ready banks. The ready bank counter 350 may provide the value of the number of ready banks (RBV) to the comparator 354.

[0049] Comparator 354 may receive the number of ready banks RBV from the ready bank counter and a threshold (TV) from the threshold storage device 356. Comparator 354 may compare the number of ready banks with the threshold and provide the comparison result to queue logic 358. In some embodiments, the result may be provided after a command is issued to the device interface, before a command is issued to the device interface, or a combination thereof.

[0050] In some embodiments, the threshold storage device 356 may include one or more registers for storing one or more thresholds. However, in other embodiments, other storage techniques may be used. Optionally, the threshold provided by the threshold storage device 356 may be dynamic.

[0051] In some embodiments, the read command counter 352 may count the number of read commands in the priority queue. In some embodiments, the read command counter 352 may increment through the priority queue to directly count the number of read commands. In some embodiments, the read command counter 352 may increment the value of the number of read commands in the priority queue each time a read command is received from the command queue and decrement the value of the number of read commands in the priority queue each time a read command is issued by the queue logic 358. In other embodiments, other techniques for counting the number of read commands in the priority queue may be used.

[0052] A value (RCV) indicating the number of read commands in the priority queue may be provided from the read command counter 352 to the threshold storage device 356. In these embodiments, the threshold storage device 356 may further include a comparator or other selection logic that receives the RCV and determines which one of a plurality of thresholds to provide to the comparator 354 based on the RCV. An example of how a threshold may be selected based on the RCV is shown in Table 1 and its accompanying description.

[0053] Queue logic 358 may be configured to organize the priority queue and issue commands based in part on commands received from the command queue and device timing parameters. Commands may be issued according to the FRFCFS policy, except that when determining which bank of the open memory device, the bank associated with the oldest read command may be selected (e.g., a modified FRFCFS policy). Queue logic 358 may further receive the result from comparator 354. Based on the result, queue logic 358 may preempt the modified FRFCFS policy. For example, if the result indicates that the number of ready banks is equal to or greater than the threshold, then queue logic 358 may issue the read commands associated with the ready banks from the priority queue rather than following the modified FRFCFS policy. After the read commands have been issued, queue logic 358 may return to issuing commands based on the modified FRFCFS policy.

[0054] Figure 4It is a timing diagram illustrating when the priority logic according to several embodiments of the present disclosure determines that a bank is ready. Timing diagram 400 shows two instances 402A and 402B of when the priority logic determines that a bank is ready. In some embodiments, the determination made is at least partially made by a ready bank counter (such as ready bank counter 350).

[0055] In instance 402A, at or around time T0, a command (CMD0) is issued to the memory device. In some embodiments, the command may be an activate command. After a tRCD period has elapsed, at or around time T2, the bank associated with CMD0 may be determined to be ready. However, in some cases (e.g., the previous access command was a write command), a write-to-read turnaround time (tWR-RD) may need to elapse before a read command RDCMD is issued at or around time T3. This can result in a delay in issuing the command, especially for read commands during preemption of the modified FRFCFS policy.

[0056] In instance 402B, again at or around time T0, the command CMD0 is issued to the memory device. However, unlike in instance 402A, instead of determining that the bank is ready at or around time T2 after time tRCD has elapsed, the bank is determined to be ready at or around time T1. Time T1 may be a time equal to (tRCD - tWR-RD). Thus, the turnaround between the write command and the read command causes tRCD and tWR-RD to elapse simultaneously or almost simultaneously. A subsequent read command RDCMD may then be issued at or around time T2 instead of at time T3. In some embodiments, this can reduce the delay in issuing the command, which can reduce the latency.

[0057] Optionally, in some embodiments, the bank may be determined to be ready at a time later than (tRCD - tWR-RD), such that the read command RDCMD is issued after time T2 (but before T3). This may be desirable in applications where there are concerns about some variations in tRCD and / or tWR-RD that could cause the read command to be issued before tRCD.

[0058] Figure 5Illustrate examples of commands associated with an implementation command selection policy according to several embodiments of the present disclosure. In this example, command 532 includes several fields: an address field 541 (ADDR), a data field 543 (DATA), a command type field 545 (TYPE), and a priority indication field 547 (PD). The embodiments are not limited to a specific command structure, number of fields, etc. In this example, the address field 541 may include the row and column addresses of the command, the data field 543 may include data corresponding to the command (e.g., data to be stored in the memory or data read from the memory), the command type field 545 may indicate the command type (e.g., whether the command is a read or write), and the priority indication field 547 may indicate additional status information that can be used by the command selection policy, such as the age of the command and whether the command targets the current open bank and other status information. For example, the priority indication field 547 may contain information indicating the priority indication, as referenced Figure 2 discussed. Figure 5 The commands shown in Figure 5 are for illustration only, and in other embodiments, the commands may have different structures.

[0059] Figure 6 is a flowchart of a method according to several embodiments of the present disclosure. In some embodiments, method 600 may be executed by a controller (e.g., controller 104 and / or controller 204). In some embodiments, method 600 may be executed entirely or partially by command selection logic (e.g., command selection logic 240).

[0060] At block 602, "Receive a plurality of commands" may be executed. In some embodiments, the commands may be received at a controller (e.g., controller 104 and / or controller 204).

[0061] At block 604, "Organize the plurality of commands into a priority queue" may be executed. In some embodiments, the organization may be performed by priority sorting logic (e.g., priority sorting logic 244 and / or 344).

[0062] At block 606, "Select a command from the plurality of commands from the priority queue to issue to the memory device" may be executed. The selection may be performed by the priority sorting logic. In some embodiments, the selection may be based on a first ready first come first served (FRFCFS) command selection policy, where the FRFCFS command selection policy is modified such that the bank of the memory device associated with the oldest read command is opened.

[0063] In some embodiments, method 600 may further include block 608, where "Count the number of banks ready to receive commands" may be executed. In some embodiments, the counting may be performed by a counter (e.g., counter 350).

[0064] At block 610, "comparing the number of ready banks with a threshold" can be performed. In some embodiments, the comparison can be performed by a comparator (e.g., comparator 354). In some embodiments, the threshold can be received from a threshold storage device (e.g., threshold storage device 356).

[0065] Based on the comparison, at block 612, "preempting the modified FRFCFS command policy" can be performed. Preemption can include selecting at least one read command from among a plurality of commands associated with at least one of the banks ready to receive commands and issuing it to the memory device. In some embodiments, method 600 can further include selecting a second command from among the plurality of commands and issuing it to the memory device according to the modified FRFCFS policy after at least one read command has been issued.

[0066] Optionally, method 600 can further include block 614 where "counting the number of read commands in the priority queue" and block 616 where "selecting a threshold from among a plurality of thresholds". In some embodiments, the counting can be performed by counter 352. The selection can be at least partially based on the number of read commands in the priority queue. Although blocks 614 and 616 are shown after block 608, blocks 614 and / or 616 can be performed before block 608 and / or at least partially concurrently with block 608.

[0067] In some embodiments, the threshold is larger when the number of read commands in the priority queue is large, and the threshold is lower when the number of read commands in the priority queue is low.

[0068] In some embodiments, counting the number of banks ready to receive commands includes determining that a bank is ready at least partially based on the timing parameters of the memory device. In some embodiments, the timing parameters include the row-to-column timing constraint (tRCD) of the memory device. In some embodiments, it is determined that the bank is ready after tRCD has elapsed. In some embodiments, it is determined that the bank is ready at a time before tRCD has elapsed at least partially based on the write-to-read turnaround time of the memory device.

[0069] Based on the embodiments disclosed herein, the command policy may follow the FRFCFS policy with the following modifications. When selecting a bank of an open memory device, the bank associated with the oldest read command may be selected by the controller. Additionally, when issuing commands according to the modified FRFCFS policy, the controller may record the number of banks (e.g., ready banks) having pages ready to receive read commands. Once the number of ready banks exceeds a threshold (which may be dynamic), the controller may stop issuing write commands and issue read commands associated with the ready banks according to the modified FRFCFS policy, and then return to issuing commands according to the modified FRFCFS policy. The command selection policy and the apparatus and method for implementing the command selection policy disclosed herein may reduce latency and may further have a negligible impact on bandwidth.

[0070] It should be understood that any of the examples, embodiments, or processes described herein may be combined with one or more other examples, embodiments, and / or processes and / or may be separated and / or executed among separate devices or portions of devices in accordance with the systems, apparatuses, and methods of the present invention.

[0071] Finally, the foregoing discussion is intended to illustrate only the systems of the present invention and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Thus, although the systems of the present invention have been described in particular detail with reference to exemplary embodiments, it should also be understood that those of ordinary skill in the art may devise numerous modifications and alternative embodiments without departing from the broader and intended spirit and scope of the systems of the present invention as set forth in the appended claims. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense and are not intended to limit the scope of the appended claims.

Claims

1. A method, comprising: Receiving a plurality of commands at a controller; Organizing the plurality of commands into a priority queue; Selecting a command from the plurality of commands from the priority queue for issuance to a memory device based on a first-ready first-come first-served (FRFCFS) command selection policy, wherein the FRFCFS command selection policy is modified such that a bank of the memory device associated with the oldest read command is opened.

2. The method of claim 1, further comprising: Counting, by the controller, the number of banks of the memory device ready to receive a command; Comparing the number of the ready banks with a threshold; And Based on the comparison, preempting the modified FRFCFS command policy and selecting at least one read command from the plurality of commands associated with at least one of the banks ready to receive a command for issuance to the memory device.

3. The method of claim 2, further comprising selecting a second command from the plurality of commands for issuance to the memory device according to the modified FRFCFS policy after the at least one read command has been issued.

4. The method of claim 2, further comprising: Counting, by the controller, the number of read commands in the priority queue; And Selecting the threshold from a plurality of thresholds based at least in part on the number of read commands in the priority queue.

5. The method of claim 4, wherein the threshold is larger when the number of read commands in the priority queue is larger, and the threshold is lower when the number of read commands in the priority queue is lower.

6. The method of claim 2, wherein counting the number of banks ready to receive a command comprises determining that a bank is ready based at least in part on timing parameters of the memory device.

7. The method of claim 6, wherein the timing parameters include a row-to-column timing constraint tRCD of the memory device.

8. The method of claim 7, wherein it is determined that the bank is ready after the tRCD has elapsed.

9. The method of claim 7, wherein it is determined that the bank is ready at a time before the tRCD has elapsed based at least in part on a write-to-read turnaround time of the memory device.

10. An apparatus, comprising: Device timing parameter logic configured to store timing constraints of a memory device; A command queue configured to store a plurality of commands; And Priority sorting logic configured to select commands from the plurality of commands for issuance to the memory device, wherein the commands are selected based at least in part on the timing constraints and a first-ready first-come first-served (FRFCFS) command selection policy, wherein the FRFCFS command selection policy is modified such that a bank of the memory device associated with the oldest read command is opened.

11. The apparatus of claim 10, further comprising: A counter configured to count the number of banks of the memory device ready to receive a command; A threshold storage device configured to store a threshold; and a comparator configured to compare the number of ready banks with the threshold and provide the result to the priority sorting logic, wherein the priority sorting logic is further configured to preempt the modified FRFCFS command policy and select at least one read command from the plurality of commands associated with at least one of the banks ready to receive a command to issue to the memory device.

12. The apparatus according to claim 11, further comprising: a second counter configured to count the number of read commands in the command queue and provide the number to the threshold storage device, wherein the threshold storage device is configured to store a plurality of thresholds, and the threshold is selected from the plurality of thresholds based on the number of read commands in the command queue to be provided to the comparator.

13. The apparatus according to claim 12, wherein the plurality of thresholds are larger when the memory device is a multi - rank memory device and lower when the memory device is a single - rank memory device.

14. The apparatus according to claim 11, wherein the counter is configured to count the banks of the memory device ready to receive a command when the row - to - column timing constraint tRCD of the memory device has passed.

15. The apparatus according to claim 11, wherein the counter is configured to count the banks of the memory device ready to receive a command when a time less than the tRCD but not less than a time equal to the tRCD minus the write - to - read turnaround time of the memory device has passed.

16. A system, comprising: a memory system including a plurality of memory devices; a host system configured to issue a plurality of commands; and a controller configured to receive the plurality of commands from the host system and issue the plurality of commands to the memory system, wherein the controller issues the plurality of commands at least in part based on a first - ready - first - come - first - served (FRFCFS) command selection policy, and wherein the FRFCFS command selection policy is modified such that a bank of at least one of the plurality of memory devices associated with the oldest read command is made available.

17. The system according to claim 16, wherein based on the number of banks of the plurality of memory devices ready to receive a command, the controller preempts the modified FRFCFS command policy and issues at least one read command from the plurality of commands associated with at least one of the banks ready to receive a command to at least one of the plurality of memory devices.

18. The system according to claim 17, wherein the number of banks ready to receive a command that causes the controller to preempt the modified FRFCFS command policy is at least in part based on the number of read commands included in the plurality of commands.

19. The system of claim 17, wherein the number of banks ready to receive a command that causes the controller to preempt the modified FRFCFS command policy is at least partially based on the number of memory devices included in the memory system.

20. The system of claim 17, wherein the controller is configured to resume the modified FRFCFS command policy after issuing the at least one read command.

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