Flash memory device supporting pseudo operation pause and recovery and control method

Abstract

The invention provides flash memory equipment supporting pseudo operation pause and recovery and a control method. The equipment comprises a pseudo operation pause and recovery control module, a Flash array basic operation module and a capacity-customizable Flash array, the pseudo operation pause and recovery control module is used for receiving and processing an operation command sent by an upper computer and sending the processed command to the Flash array basic operation module; the Flash array basic operation module is used for processing received reading, programming and erasing operation commands, and ensuring that the flash memory correctly executes reading, programming and erasing operations through scheduling control of a plurality of eFLSAH IPs; and the Flash array with the customizable capacity is used for executing various command operations. According to the invention, the programming / erasing pause and recovery operation of the flash memory is realized, the correct response of the programming pause command and the erasing pause command is ensured, and the efficiency and the reliability of the memory are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of flash memory, and in particular, to a flash memory device and a control method that support pseudo-operation pause and resume. Background Art

[0002] Flash memory, as an electrically erasable programmable memory, has deeply penetrated into many key fields such as embedded systems, aerospace, and consumer electronics by virtue of its remarkable characteristics such as non-volatility, high-speed reading and writing, strong seismic resistance, low power consumption, and small size. As one of the cores of modern storage technologies, flash memory not only shoulders the heavy responsibility of data storage, but also plays an indispensable role in promoting the progress of information technology. Flash memory includes NOR flash and NAND flash; among them: the basic storage unit of NOR flash is a bit, and users can randomly access the information of any bit; while the basic storage unit of NAND flash is a page (Page), and erase operations can be performed at the block level (sector), and programming operations or reading operations can be performed at the page level (page).

[0003] The basic operations of flash memory cover three categories: reading, programming (writing), and erasing; the reading operation is fast and direct, while programming and erasing are relatively time-consuming. Especially during the programming or erasing process, if the user needs to temporarily process other tasks, the operation pause and resume function of flash memory becomes particularly important. However, current technologies that support operation pause and resume mostly rely on the design optimization of the underlying hardware storage circuit of flash memory. This method not only has a high design cost, but also has limited flexibility. Once the operation is paused, the initial operation will be interrupted, resulting in a significant reduction in the working efficiency of flash memory. Therefore, current flash memories are facing unprecedented challenges; on the one hand, the requirements for storage density, reading speed, and erasing and writing speed are increasing day by day; on the other hand, flexibility has also become an important indicator for measuring the performance of flash memory.

[0004] To meet these requirements, developers have tried to implement a flash memory with customizable capacity by splicing and expanding multiple eFLASH IPs; however, this solution is not perfect. Since most foundries' eFLASH IPs do not support the operation pause function, once an operation (such as erasing or programming) starts, it is necessary to wait for the current operation to complete before receiving new commands. This limitation may not only lead to untimely processing or even loss of commands, but also cannot meet the user's need to pause the current operation to perform other tasks, thus reducing the reliability and flexibility of the memory. Summary of the Invention

[0005] Aiming at the deficiencies of the existing technology, the present invention provides a flash memory device and a control method that support pseudo-operation pause and resume, which are specifically implemented through the following technical solutions: On the one hand, a flash memory device that supports pseudo-operation pause and resume is provided. The device consists of three modules: a pseudo-operation pause and resume control module, a Flash array basic operation module, and a capacity-customizable Flash array. The pseudo-operation pause and resume control module is responsible for receiving and processing operation commands such as read, program, erase, and program / erase pause and resume sent by the host computer, and sending the processed commands to the Flash array basic operation module. The Flash array basic operation module is responsible for processing the received read, program, and erase operation commands, controlling the capacity-customizable Flash array through the scheduling of multiple eFLSAH IPs, and ensuring the correct execution of read, program, and erase operations of the flash memory. The capacity-customizable Flash array is used to execute various command operations; this module uses multiple eFLASH IPs to splice and expand, and the eFLASH IPs respectively correspond to the sectors of the flash memory to achieve a structured division of the hardware circuit.

[0006] Furthermore, the interface signals of the flash memory device include chip select (ce_n), output enable (oe_n), operation command (command), address line (addr), data line (data), and ready / busy (ryby), etc.; among them: the ready / busy (ryby) signal is used to indicate whether the flash memory is in an idle or busy state; when the flash memory is not performing any operation, this signal is idle; otherwise, this signal is busy. Generally, the flash memory can receive new program or erase commands only in the idle state.

[0007] Furthermore, in the pseudo-operation pause and resume control module, there is also a command arbitration unit, which is used to process new commands received during the pseudo-operation pause by arbitrating the priority levels of the initial operation and the new command.

[0008] Furthermore, in the pseudo-operation pause and resume control module, there is also: When the received operation command is a program / erase pause or resume, the pseudo-operation pause and resume control module enters or exits the pseudo-program / erase pause state. When the received operation commands are read, program, and erase, it is necessary to determine whether the pseudo-operation pause and resume control module is in the pseudo-program / erase pause state, where: If it is in the pseudo-program / erase pause state, after passing through the internal control logic and command arbitration of the pseudo-operation pause and resume control module, it is then determined whether to send the command to the Flash array basic operation module. If not in the pause state of pseudo-programming / erasing, the received command is directly transmitted to the Flash array basic operation module.

[0009] Furthermore, in the Flash array basic operation module, the Flash array basic operation module realizes read, program, and erase operations by controlling multiple eFLSAH IPs. Specifically: The read operation is divided into two types: read data operation and read status operation; when the capacity-customizable Flash array is performing a program / erase operation, the read operation is a read status operation, and what is read out is the status of the flash memory; otherwise, the read operation is a read data operation, and what is read out is the data at the flash memory address. For the program / erase operation, an operation register and a data memory are used to store the operation information of multiple eFLSAH IPs. Among them: the operation register is divided into a program operation register and an erase operation register, which are respectively used to store the sector / eFLSAH IP information of the program and erase operations; the data memory is used to store the data of the program operation.

[0010] Furthermore, in the capacity-customizable Flash array, the capacity-customizable Flash array divides the hardware circuit of the flash memory according to the splicing and expansion of multiple eFLASH IPs. One or more eFLASH IPs respectively correspond to one or more sectors (SAs) of the memory, realizing a structured flash memory storage array.

[0011] On the other hand, the present invention also provides a control method for a flash memory device supporting pseudo-operation pause and resume. The method includes the following steps: Step 1: The pseudo-operation pause and resume module receives a new command sent by the host computer in the pseudo-programming / erasing pause state, and determines whether the state of the initial program / erase operation performed by the eFLASH IP that is paused from programming / erasing in the capacity-customizable Flash array has been completely ended. Based on this state, the new command is transmitted to the Flash array basic operation module; Step 2: The Flash array basic operation module receives the new command sent by the pseudo-operation pause and resume module, generates a control signal and timing for the eFlash IP to execute the new command operation, and transmits the control signal to the capacity-customizable Flash array according to the timing; Step 3: The capacity-customizable Flash array receives the control signal and executes the new command operation of the flash memory.

[0012] Furthermore, in Step 1, the new command includes a read operation command, a program operation command, and an erase operation command. Among them: The read operation command is controlled by the chip select signal (ce_n), output enable signal (oe_n), etc. sent by the host computer. If the signals are all active low, when both ce_n and oe_n are low, the flash memory recognizes it as a read command and performs the read operation; The programming operation command and the erase operation command are sent by the host computer with corresponding operation instructions. Among them: the erase operation command includes a sector erase command and a full chip erase command.

[0013] Further, in step 1, determining whether the state of the initial programming / erase operation executed by the eFLASHIP where the capacity-customizable Flash array is programmed / erased and paused is completely ended, and based on the state, transmitting a new command to the Flash array basic operation module further includes: Step 101: If the state is ended, it means that the capacity-customizable Flash array is completely in an idle state, and directly transmit the new command to the Flash array basic operation module; Step 102: If the state is not ended, start the corresponding command arbitration mechanism and determine the priority levels of the initial operation and the new command through the command arbitration mechanism, process the new command, and transmit the processed new command to the Flash array basic operation module.

[0014] Further, in step 102, the command arbitration mechanism includes two types: the command arbitration mechanism during pseudo-programming pause and the command arbitration mechanism during pseudo-erase pause.

[0015] Further, in step 102, starting the corresponding command arbitration mechanism and determining the priority levels of the initial operation and the new command through the command arbitration mechanism, processing the new command, and transmitting the processed new command to the Flash array basic operation module further includes: Step 1021: If the capacity-customizable Flash array receives a new command during the execution of the initial programming operation, start the command arbitration mechanism during pseudo-programming pause; Step 1022: If the capacity-customizable Flash array receives a new command during the execution of the initial erase operation, start the command arbitration mechanism during pseudo-erase.

[0016] Further, in step 1021, if the capacity-customizable Flash array receives a new command during the execution of the initial programming operation, starting the command arbitration mechanism during pseudo-programming pause further includes: Step 1021-1: If the new command is a read operation command, determine the read type and perform the corresponding operation according to the working state of the sector where the read address is located, where: If the working state of the sector where the read address is located is idle, the read type is to read data; If the working state of the sector where the read address is located is busy, the read type is read status; Step 1021-2: If the new command is a programming operation command or an erase operation command, determine whether the sector where the operation address corresponding to the new command is located is idle, where: If it is idle, it means that the new command and the initial command do not conflict with each other and are commands with the same priority. The new command can be immediately sent to the Flash array basic operation module to execute the new command operation; If it is busy, it means that the operation address of the new command is exactly in the sector in pseudo-programming pause. At this time, it is necessary to determine whether the new command type is a programming operation command or an erase operation command, including: If it is a programming operation command, for the initial programming operation, define the programming command in the sector in pseudo-programming pause as an operation command with a lower priority. After the initial programming operation ends, send the programming command to the Flash array basic operation module, and the flash memory executes the new programming command; If it is an erase operation command, define the erase command in the sector in pseudo-programming pause as an operation command with a higher priority, send the erase command to the Flash array basic operation module, and the flash memory can directly terminate the initial programming operation and immediately execute the erase operation.

[0017] Further, in step 1022, when the capacity-customizable Flash array receives a new command during the execution of the initial erase operation, start the command arbitration mechanism during pseudo-erase, and further include: Step 1022-1: If the new command is a read operation command, determine the read type and execute the corresponding operation according to the working state of the sector where the read address is located, where: If the working state of the sector where the read address is located is idle, the read type is read data; If the working state of the sector where the read address is located is busy, the read type is read status; Step 1022-2: For a programming operation command or an erase operation command, it is necessary to determine whether the sector where the operation address corresponding to the new command is located is idle, where: If it is idle, it means that the new command and the initial command do not conflict with each other and are commands with the same priority. The new command can be immediately sent to the Flash array basic operation module to execute the new command operation; If it is busy, it means that the operation address of the new command is exactly in the sector in pseudo-erase pause, and the next arbitration is required, including: If it is a programming operation command, for the initial erase operation, define the programming command in the sector in pseudo-erase pause as an operation command with a lower priority. After the initial erase operation ends, send the programming command to the Flash array basic operation module, and the flash memory executes the new programming command; If it is a sector erase command, define the same sector erase command as a redundant command and discard it directly. If it is a full chip erase command, define the full chip erase command as an operation with the same priority, and send the full chip erase command to the Flash array basic operation module. The flash memory can immediately execute the full chip erase operation.

[0018] Further, in step 3, when the capacity-customizable Flash array receives a control signal and executes a new command operation of the flash memory, the idle / busy flag signal ryby of the flash memory enters the busy flag state.

[0019] Further, in the control method of the flash memory device supporting pseudo-operation pause and resume, it further includes: When the capacity-customizable Flash array is in the pseudo-programming / erase pause state, if the host computer sends a programming / erase resume command (resume) to the pseudo-operation pause and resume control module again to end the operation pause, and if the pseudo-operation pause and resume control module receives the command when the new command operation has not ended, ignore this command; otherwise, judge whether the initial programming / erase operation has been completed during the pseudo-programming / erase pause, where: If it has been completed, the idle / busy flag signal (ryby) of the flash memory returns to idle. If it has not been completed, the capacity-customizable Flash array continues to execute the initial operation, the idle / busy flag signal (ryby) of the flash memory re-enters the busy state, and after the initial programming / erase operation is completed, it returns to idle.

[0020] Compared with the prior art, the present invention has the following advantages: 1. Through the flash memory device provided by the present invention, while meeting the memory capacity to be designed, the functions of pausing and resuming flash operations are realized, and different operations can be carried out simultaneously through different eFLASH IPs, thereby greatly improving the working efficiency of the flash memory.

[0021] 2. The control method of the flash memory device provided by the present invention realizes correct responses to programming pause commands and erase pause commands through pseudo-operation pause and resume control. At the same time, during the operation pause, a command arbitration mechanism is used to select and process commands with different priorities, thereby improving the efficiency and reliability of the memory.

[0022] Other features and advantages of the present invention will be described in the subsequent specification, and part of them will be obvious from the specification or understood by implementing the present invention. The objectives and other advantages of the present invention can be achieved and obtained through the structures pointed out in the specification, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0024] Figure 1 It is a structural block diagram of a flash memory device that supports pseudo-operation suspension and resume.

[0025] Figure 2 It is a structural block diagram of a flash memory array and its basic operation module.

[0026] Figure 3 It is a flowchart of a flash memory control method that supports pseudo-operation suspension and resume.

[0027] Figure 4 It is a flowchart of programming suspension and resume.

[0028] Figure 5 It is a flowchart of pseudo-erase suspension and resume. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0029] In order to make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the present invention.

[0030] In an exemplary device, please refer to Figure 1 , a flash memory device that supports pseudo-operation suspension and resume is provided, Figure 1 which is a structural block diagram of a flash memory device that supports pseudo-operation suspension and resume; the flash memory device includes three modules: a pseudo-operation suspension and resume control module, a Flash array basic operation module, and a capacity-customizable Flash array, where: The pseudo-operation suspension and resume control module is responsible for receiving and processing the operation commands of reading, programming, erasing, and programming / erasing suspension and resume sent by the host computer, and sending the processed commands to the Flash array basic operation module; Further, in the pseudo-operation suspension and resume control module, it also includes: When receiving an operation command for pausing or resuming programming / erasing, the pseudo-operation pause and resume control module enters or exits the pseudo-programming / erasing pause state; When receiving operation commands for reading, programming, or erasing, it is necessary to determine whether the pseudo-operation pause and resume control module is in the pseudo-programming / erasing pause state, where: If it is in the pseudo-programming / erasing pause state, after passing through the internal control logic and command arbitration of the pseudo-operation pause and resume control module, it is further determined whether to transmit the command to the Flash array basic operation module; If it is not in the pseudo-programming / erasing pause state, the received command is directly transmitted to the Flash array basic operation module.

[0031] Furthermore, the pseudo-operation pause and resume control module further includes a command arbitration unit for processing new commands received during the pause by arbitrating the priority levels of the initial operation and the new command.

[0032] The Flash array basic operation module is responsible for processing the received operation commands for reading, programming, and erasing, controlling the capacity-customizable Flash array through the scheduling of multiple eFLSAH IPs, and ensuring that the flash memory correctly executes operations such as reading, programming, and erasing; The capacity-customizable Flash array is used to execute various command operations; this module uses multiple eFLASH IPs spliced and extended, and the eFLASH IPs respectively correspond to the sectors of the flash memory to achieve a structured division of the hardware circuit.

[0033] Furthermore, the flash memory device further includes interface signals, and the interface signals include chip select (ce_n), output enable (oe_n), operation command (command), address line (addr), data line (data), and idle / busy (ryby), etc.; where: the idle / busy (ryby) signal is used to indicate whether the flash memory is in an idle or busy state; when the flash memory is not performing any operations, this signal is idle; otherwise, this signal is busy. Generally, the flash memory can receive new programming or erasing commands only in the idle state.

[0034] In an exemplary device, please refer to Figure 2 , Figure 2 is a structural block diagram of the Flash array and its basic operation module; for different application scenarios, there are different requirements for the bit width and capacity of the flash memory. Developing a new flash memory is not only difficult to implement but also requires a large amount of human input. Therefore, in this embodiment, the process factory eFLASH IP is used to implement a capacity-customizable flash memory; specifically: In a capacity-customizable Flash array, according to the splicing and expansion of multiple eFLASH IPs, the hardware circuit of the flash memory is partitioned. One or more eFLASH IPs respectively correspond to one or more sectors (SAs) of the flash memory, realizing a structured flash storage array. In the basic operation module of the Flash array, by controlling multiple eFLSAH IPs, basic operations such as reading, programming, and erasing are realized, where: The reading operation is divided into two types: read data operation and read status operation. When the capacity-customizable Flash array is performing a programming / erasing operation, the reading operation is a read status operation, and the readout is the status of the flash memory. Otherwise, the reading operation is a read data operation, and the readout is the data at the flash memory address. For the programming operation, operation registers and data memories are used to store the operation information of multiple eFLSAH IPs. Among them, the operation registers are divided into a programming operation register and an erase operation register, which are respectively used to store the sector / eFLSAH IP information of programming and erasing operations. The data memory is used to store the data of the programming operation. In this embodiment, taking a single eFLASH IP under a certain process that can support storing up to 64KB of data at an 8-bit width, that is, the data width is 16 as an example, the operations in the basic operation module of the Flash array are further described: To implement a 2M-capacity flash memory (including 32 sectors (SAs), each sector being 64KB), 32 eFLASH IPs can be spliced, and each eFLASH_IP respectively corresponds to a storage sector. These 32 IPs are numbered from 0 to 31 as Flash_0~Flash31, corresponding to SA0-SA31 of the chip respectively. The high five bits of the input address are used to identify the eFLASH IP number corresponding to the sector where the address is located. According to the received operation command, the control signal of the corresponding IP is enabled, and the identified programming and erase operation IP numbers are respectively stored in the programming operation register PROGRAM_ID[31:0] and the erase operation register ERASE_ID[31:0]. PROGRAM_ID[i]=1 indicates a programming operation on the i-th IP; ERASE_ID[i]=1 indicates an erase operation on the i-th IP. If a programming command is received, the programming data is simultaneously stored in the data register PROGRAM_DATA. The sixteenth bit of the input address serves as the input address for the executing operation IP, thereby controlling the eFLASH IP to complete the operation.

[0035] In the above manner, while meeting the capacity requirements of the flash memory to be designed, it is possible to pause and resume the operation of the flash memory, that is, different operations can be carried out simultaneously through different eFLASH IPs to achieve the pause and resume operations of the flash memory, thereby greatly improving the working efficiency of the flash memory.

[0036] In one embodiment, continuing with the above technical solution, a capacity-customizable Flash array is implemented by splicing and expanding multiple eFLASH IPs, and the Flash array basic operation module controls multiple eFLASH IPs to perform normal read, program, and erase operations; if an operation pause command sent by the host computer is received during the process of the Flash array basic operation module controlling multiple eFLASH IPs to perform program and erase operations, the pseudo-operation pause and resume control module will enter the pseudo-programming / erase pause state.

[0037] When the pseudo-operation pause and resume control module is in the pseudo-programming / erase pause state, the idle / busy flag signal (ryby) of the flash memory is restored to idle, that is, it can receive and process new commands; however, the eFLASH IP that is being programmed / erased and paused in the capacity-customizable Flash array will continue to execute the initial programming / erase operation. Therefore, in the pseudo-programming / erase pause state, when the pseudo-operation pause and resume control module receives a new read, program, or erase command, it judges the priority levels of the initial operation and the new command through the command arbitration mechanism and processes the new command.

[0038] For this process, please refer to Figure 3 , a flash memory control method supporting pseudo-operation pause and resume is provided. Figure 3 It is a flowchart of the flash memory control method supporting pseudo-operation pause and resume, and the method includes: Step S1: When the pseudo-operation pause and resume module is in the pseudo-programming / erase pause state, it receives a new command sent by the host computer and judges whether the state of the initial programming / erase operation executed by the eFLASH IP that is programmed / erased and paused in the capacity-customizable Flash array is completely ended, and based on this state, transmits the new command to the Flash array basic operation module; Further, the new command includes a read operation command, a program operation command, and an erase operation command, where: The read operation command is controlled by the chip select signal (ce_n), output enable signal (oe_n), etc. sent by the host computer. If the signals are all low-level effective, when both ce_n and oe_n are low, the flash memory recognizes it as a read command and executes the read operation; The programming operation command and the erasing operation command are sent with corresponding operation instructions by the host computer, where: the erasing operation command includes a sector erasing command and a full-chip erasing command.

[0039] Further, to determine whether the state of the initial programming / erasing operation executed by the eFLASH IP that pauses the programmable-capacity Flash array from being programmed / erased is completely ended, and based on this state, send a new command to the Flash array basic operation module, the following steps are further included: Step S101: If the state is ended, it indicates that the programmable-capacity Flash array is completely in an idle state, and directly send the new command to the Flash array basic operation module; Step S102: If the state is not ended, start the corresponding command arbitration mechanism and determine the priority levels of the initial operation and the new command through the command arbitration mechanism, process the new command, and send the processed new command to the Flash array basic operation module.

[0040] Further, the command arbitration mechanism includes two types: the command arbitration mechanism during pseudo-programming pause and the command arbitration mechanism during pseudo-erasing pause.

[0041] Further, in step S102, please refer to Figure 4 and Figure 5 inside the red dashed box in Figure 4 which is the flowchart of pseudo-programming pause and resume, Figure 5 and which is the flowchart of pseudo-erasing pause and resume; the step of starting the corresponding command arbitration mechanism and determining the priority levels of the initial operation and the new command through the command arbitration mechanism, processing the new command, and sending the processed new command to the Flash array basic operation module specifically includes the following steps: Figure 4 Step A: If a new command is received during the execution of the initial programming operation by the programmable-capacity Flash array, start the command arbitration mechanism during pseudo-programming pause; please refer to which specifically includes: Step A-1: If the new command is a read operation command, determine the read type and execute the corresponding operation according to the working state of the sector where the read address is located, where: If the working state of the sector where the read address is located is idle, the read type is to read data; If the working state of the sector where the read address is located is busy, the read type is to read the status; If it is idle, it indicates that the new command and the initial command do not conflict with each other and are commands with the same priority. The new command can be immediately sent to the Flash array basic operation module to execute the new command operation; If it is busy, it means that the operation address of the new command is exactly in the sector where the pseudo-programming is paused. At this time, it is necessary to determine whether the new command type is a programming operation command or an erase operation command, including: If it is a programming operation command, for the initial programming operation, the programming command in the sector where the pseudo-programming is paused is defined as an operation command with a lower priority. After the initial programming operation is completed, the programming command is sent to the Flash array basic operation module, and the flash memory executes the new programming command; If it is an erase operation command, the erase command in the sector where the pseudo-programming is paused is defined as an operation command with a higher priority. The erase command is sent to the Flash array basic operation module, and the flash memory can directly terminate the initial programming operation and immediately execute the erase operation.

[0042] Step B: If the capacity-customizable Flash array receives a new command during the execution of the initial erase operation, start the command arbitration mechanism during the pseudo-erase period; please refer to Figure 5 , and its specific operations include: Step B-1: If the new command is a read operation command, determine the read type and execute the corresponding operation according to the working status of the sector where the read address is located, where: If the working status of the sector where the read address is located is idle, the read type is to read data; If the working status of the sector where the read address is located is busy, the read type is to read the status.

[0043] Step B-2: For a programming operation command or an erase operation command, it is necessary to determine whether the sector where the operation address corresponding to the new command is located is idle, where: If it is idle, it indicates that the new command and the initial command do not conflict with each other and are commands with the same priority. The new command can be immediately sent to the Flash array basic operation module to execute the new command operation; If it is busy, it means that the operation address of the new command is exactly in the sector where the pseudo-erase is paused, and the next arbitration is required, including: If it is a programming operation command, for the initial erase operation, the programming command in the sector where the pseudo-erase is paused is defined as an operation command with a lower priority. After the initial erase operation is completed, the programming command is sent to the Flash array basic operation module, and the flash memory executes the new programming command; If it is a sector erase command, the same-sector erase command is defined as a redundant command and is directly discarded; If it is a full - chip erase command, the full - chip erase command is defined as an operation with the same priority, and the full - chip erase command is sent to the Flash array basic operation module. The flash memory can immediately execute the full - chip erase operation.

[0044] Step S2: The Flash array basic operation module receives the new command sent by the pseudo - operation pause and resume module, generates the control signal and timing for the eFlash IP to execute the new command operation, and transmits the control signal to the capacity - customizable Flash array according to the timing. Step S3: The capacity - customizable Flash array receives the control signal and executes the new command operation of the flash memory.

[0045] Furthermore, in Step S3, when the capacity - customizable Flash array receives the control signal and executes the new command operation of the flash memory, the idle / busy flag signal ryby of the flash memory enters the busy flag state.

[0046] In an embodiment, when the capacity - customizable Flash array is in the pseudo - programming / erase pause state, and the host computer sends a programming / erase resume command (resume) to the pseudo - operation pause and resume control module again to end the operation pause. At this time, if the pseudo - operation pause and resume control module receives the command and the new command operation has not ended, this command is ignored; otherwise, it is necessary to determine whether the initial programming / erase operation has been completed during the pseudo - programming / erase pause, where: If it has been completed, the idle / busy flag signal (ryby) of the flash memory is restored to idle. If it has not been completed, the capacity - customizable Flash array continues to execute the initial operation, the idle / busy flag signal (ryby) of the flash memory re - enters the busy state, and after the initial programming / erase operation is completed, it is restored to idle.

[0047] Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A flash memory device supporting pause and resume of pseudo-operations, characterized in that, It consists of three modules: a pseudo-operation pause and resume control module, a Flash array basic operation module, and a capacity-customizable Flash array, where: The pseudo-operation pause and resume control module is responsible for receiving and processing operation commands such as read, program, erase, and program / erase pause and resume sent by the host computer, and sending the processed commands to the Flash array basic operation module; The Flash array basic operation module is responsible for processing the received read, program, and erase operation commands, controlling the capacity-customizable Flash array through the scheduling of multiple eFLSAH IPs to ensure that the flash memory correctly executes read, program, and erase operations; The capacity-customizable Flash array is used to execute various command operations.

2. A flash memory device supporting pseudo-operation pause and resume according to claim 1, characterized in that: The flash memory device also has interface signals, including chip select ce_n, output enable oe_n, operation command command, address line addr, data line data, and idle / busy ryby, where: The idle / busy ryby signal is used to indicate whether the flash memory is in an idle or busy state. When the flash memory is not performing any operation, this signal is idle; otherwise, this signal is busy.

3. A flash memory device supporting pseudo-operation pause and resume according to claim 1, characterized in that: The pseudo-operation pause and resume control module further includes a command arbitration unit for processing new commands received during the pseudo-operation pause by arbitrating the priority levels of the initial operation and the new command.

4. A flash memory device supporting pseudo-operation pause and resume according to claim 3, characterized in that: When the pseudo-operation pause and resume control module receives an operation command for program / erase pause or resume, the pseudo-operation pause and resume control module enters or exits the program / erase pause state; When the pseudo-operation pause and resume control module receives operation commands for read, program, sector erase, and chip erase, it is necessary to determine whether the pseudo-operation pause and resume control module is in the program / erase pause state, where: If the pseudo-operation pause and resume control module is in the program / erase pause state, after passing through the internal control logic and command arbitration of the pseudo-operation pause and resume control module, it is further determined whether to send the command to the Flash array basic operation module; If the pseudo-operation pause and resume control module is not in the program / erase pause state, the received command is directly sent to the Flash array basic operation module.

5. A flash memory device supporting pseudo-operation pause and resume according to claim 1, characterized in that: The capacity-customizable Flash array divides the flash hardware circuit according to the splicing and expansion of multiple eFLASH IPs. One or more eFLASH IPs respectively correspond to one or more sectors SA of the memory, realizing a structured flash storage array; The Flash array basic operation module realizes read, program, and erase operations by controlling multiple eFLSAH IPs.

6. A flash memory device supporting pseudo-operation pause and resume as claimed in claim 5, characterized in that: The read operation is divided into two types: read data operation and read status operation, where: When the capacity-customizable Flash array executes a program / erase operation, the read operation is a read status operation, and what is read out is the status of the flash memory; Otherwise, the read operation is a read data operation, and what is read out is the data at the flash memory address; For the program operation, the operation information of multiple eFLSAH IPs is stored using an operation register and a data memory, where: The operation register is divided into a program operation register and an erase operation register, which are respectively used to store the sector / eFLSAH IP information of the program and erase operations; The data memory is used to store the data of the program operation.

7. A control method for a flash memory device supporting pseudo-operation suspension and resume according to any one of claims 1-6, characterized in that, It includes: In the pseudo-program / erase pause state, the pseudo-operation pause and resume module receives a new command sent by the host computer, and determines whether the state of the initial program / erase operation executed by the eFLASH IP paused by the capacity-customizable Flash array for programming / erasing has completely ended. Based on this state, the new command is transmitted to the Flash array basic operation module; The Flash array basic operation module receives the new command sent by the pseudo-operation pause and resume module, generates a control signal and timing for the eFlashIP to execute the new command operation, and transmits the control signal to the capacity-customizable Flash array according to the timing; The capacity-customizable Flash array receives the control signal and executes the new command operation of the flash memory.

8. A control method for a flash memory device supporting pseudo-operation pause and resume as claimed in claim 7, characterized in that: The new command includes a read operation command, a program operation command, and an erase operation command, where: The read operation command is controlled by the chip select signal ce_n and the output enable signal oe_n sent by the host computer. If both signals are low-level effective, when both ce_n and oe_n are low level, the flash memory recognizes it as a read command and executes a read operation; The program operation command and the erase operation command are sent by the host computer with corresponding operation instructions, where: the erase operation command includes a sector erase command and a full-chip erase command.

9. A control method for a flash memory device supporting pseudo-operation pause and resume as claimed in claim 8, characterized in that When determining whether the state of the initial program / erase operation executed by the eFLASH IP paused by the capacity-customizable Flash array for programming / erasing has completely ended, and based on this state, transmitting the new command to the Flash array basic operation module, where: If the state is ended, it means that the capacity-customizable Flash array is completely in an idle state, and the new command is directly transmitted to the Flash array basic operation module; If the state is not ended, start the corresponding command arbitration mechanism, determine the priority levels of the initial operation and the new command through the command arbitration mechanism, process the new command, and transmit the processed new command to the Flash array basic operation module.

10. The control method of a flash memory device supporting pseudo-operation pause and resume according to claim 9, characterized in that: The command arbitration mechanism includes two types: the command arbitration mechanism during pseudo-programming pause and the command arbitration mechanism during pseudo-erasure pause.

11. The control method of a flash memory device supporting pseudo-operation pause and resume according to claim 10, characterized in that The step of starting the corresponding command arbitration mechanism, determining the priority levels of the initial operation and the new command through the command arbitration mechanism, processing the new command, and transmitting the processed new command to the Flash array basic operation module includes: When the capacity-customizable Flash array receives a new command during the execution of an initial programming operation, start the command arbitration mechanism during pseudo-programming pause; When the capacity-customizable Flash array receives a new command during the execution of an initial erasure operation, start the command arbitration mechanism during pseudo-erasure.

12. The control method of a flash memory device supporting pseudo-operation pause and resume as claimed in claim 11, wherein, The step of starting the command arbitration mechanism during pseudo-programming pause includes: If the new command is a read operation command, determine the read type and execute the corresponding operation according to the working state of the sector where the read address is located, where: If the working state of the sector where the read address is located is idle, the read type is reading data; If the working state of the sector where the read address is located is busy, the read type is reading status; If the new command is a programming operation command or an erasure operation command, determine whether the sector where the operation address corresponding to the new command is located is idle, where: If the sector where the operation address corresponding to the new command is located is idle, it means that the new command and the initial command do not conflict and are commands with the same priority level. The new command can be immediately sent to the Flash array basic operation module to execute the new command operation; If the sector where the operation address corresponding to the new command is located is busy, it means that the operation address of the new command is exactly in the sector of pseudo-programming pause. At this time, it is necessary to determine whether the new command type is a programming operation command or an erasure operation command, including: If the new command type is a programming operation command, for the initial programming operation, define the programming command in the sector of pseudo-programming pause as an operation command with a lower priority level. After the initial programming operation ends, send the programming command to the Flash array basic operation module, and the flash memory executes the new programming command; If the new command type is an erasure operation command, define the erasure command in the sector of pseudo-programming pause as an operation command with a higher priority level, send the erasure command to the Flash array basic operation module, and the flash memory can directly terminate the initial programming operation and immediately execute the erasure operation.

13. The control method of a flash memory device supporting pseudo-operation suspension and resume according to claim 11, wherein, The step of starting the command arbitration mechanism during pseudo-erasure includes: If the new command is a read operation command, determine the read type and execute the corresponding operation according to the working state of the sector where the read address is located, where: If the working state of the sector where the read address is located is idle, the read type is reading data; If the working state of the sector where the read address is located is busy, the read type is reading status; For a programming operation command or an erase operation command, it is necessary to determine whether the sector where the operation address corresponding to the new command is located is idle, where: If the sector where the operation address corresponding to the new command is located is idle, it means that the new command and the original command do not conflict with each other and are commands with the same priority. The new command can be immediately sent to the Flash array basic operation module to execute the new command operation; If the sector where the operation address corresponding to the new command is located is busy, it means that the operation address of the new command is exactly in the sector with pseudo-erase pause. Further arbitration of the new command is required, including: If the new command is a programming operation command, for the original erase operation, the programming command in the sector with pseudo-erase pause is defined as an operation command with a lower priority. After the original erase operation is completed, the programming command is sent to the Flash array basic operation module, and the flash memory executes the new programming command; If the new command is a sector erase command, the same-sector erase command is defined as a redundant command and is directly discarded; If the new command is a full-chip erase command, the full-chip erase command is defined as an operation with the same priority, and the full-chip erase command is sent to the Flash array basic operation module, and the flash memory can immediately execute the full-chip erase operation.

14. The control method of a flash memory device supporting pseudo-operation pause and resume according to claim 7, characterized in that: When the capacity-customizable Flash array receives a control signal and executes a new command operation of the flash memory, the idle / busy flag signal ryby of the flash memory enters the busy flag state.

15. A control method for a flash memory device supporting pseudo-operation pause and resume according to any one of claims 7 to 14, characterized in that, It further includes: When the capacity-customizable Flash array is in the pseudo-programming / erase pause state, if the host computer sends a programming / erase resume command to the pseudo-operation pause and resume control module again to end the operation pause, and if the pseudo-operation pause and resume control module receives the command when the new command operation has not ended, this command is ignored; Otherwise, it is judged whether the original programming / erase operation has been completed during the programming / erase pause, where: If the original programming / erase operation has been completed during the programming / erase pause, the idle / busy flag signal ryby of the flash memory is restored to idle; If the original programming / erase operation has not been completed during the programming / erase pause, the capacity-customizable Flash array continues to execute the original operation, the idle / busy flag signal ryby of the flash memory enters the busy state again, and after the original programming / erase operation is completed, it returns to idle.

Images