Power simulation waveform real-time acquisition method based on FPGA

Abstract

The invention discloses a power simulation waveform real-time acquisition method based on an FPGA (Field Programmable Gate Array), which comprises the following steps of: configuring sampling parameters and channel mapping in an upper computer, and issuing a generated configuration file to the FPGA; the FPGA analyzes the configuration file to generate a corresponding sampling parameter and channel mapping lookup table and performs data mapping and channel merging processing on a data source signal transmitted into the FPGA to realize synchronous data acquisition; and the FPGA generates a trigger signal according to the trigger mode, calculates a corresponding variable pre-trigger cache, a post-trigger cache and a trigger window proportion, and transmits cache information and to-be-tested data back to the upper computer for signal observation and analysis. Compared with the prior art, signal waveform synchronous sampling with higher frequency is achieved, parallel storage of multiple trigger modes and multiple paths of data can be completed in a single clock period, possible potential address conflicts are avoided, and the signal observation flexibility and the testing efficiency of the virtual oscilloscope can be effectively improved.

Description

Technical Field

[0001] The present invention relates to the technical field of power simulation, and particularly relates to a method for high-speed real-time acquisition and display of power simulation waveforms based on FPGA, which is particularly suitable for accurately observing high-frequency signals and applications in the fields of new energy, small-step power simulation, etc. Background Art

[0002] With the rapid development of the new energy industry and the continuous upgrading of the power system, the requirements for the accuracy and reliability of power simulation are getting higher and higher. In the field of new energy, such as wind power generation, solar power generation, energy storage technology, etc., it is necessary to accurately monitor and analyze complex electrical signals to ensure the stable operation of the system. In the field of power simulation, accurately observing signals such as voltage and current is crucial for verifying power system models and optimizing system designs.

[0003] Due to the limitations of its own architecture, the traditional virtual oscilloscope has a low sampling frequency and usually cannot meet the observation requirements for high-frequency signals. When high-frequency signals need to be observed, it is often necessary to rely on an external physical oscilloscope, but there are many problems in the use of an external physical oscilloscope. On the one hand, DAC fluctuations will occur in the external oscilloscope, which may cause instability and errors in the signal during the conversion process. On the other hand, line transmission loss is also a problem that cannot be ignored. The signal will lose part of its energy due to factors such as line impedance during transmission, and there are problems such as signal attenuation and phase distortion, which will affect the accuracy and integrity of the signal and have a negative impact on the observation of high-frequency signals.

[0004] As the technical solution disclosed in Chinese Patent Application CN202411196306.9, the cache management of the existing virtual oscilloscope is relatively static, usually with a fixed cache size, and long-term triggering is likely to cause data read-write conflicts. At the same time, as the solution disclosed in Chinese Patent Application CN201811218880.4, the adjustment mechanism for the cache is not flexible enough, and only calculates the cache based on the DMA transfer length, resulting in a low cache utilization rate. This also indirectly leads to a single triggering mode, which can only trigger at intervals through a sampling counter or analyze the input data to mark the trigger point, and cannot meet the complex triggering requirements in new energy power simulation. Therefore, the current virtual oscilloscope technology still has the following defects:

[0005] 1. The sampling rate is low, and accurate sampling of high-frequency signals cannot be achieved, and there is a problem of spectral aliasing.

[0006] 2. The triggering conditions are single and cannot meet the requirements of different trigger positions and conditions in new energy power simulation.

[0007] 3. The cache management is static and cannot adapt to the usage scenarios of long-term triggering and the changing signal observation requirements. Summary of the Invention

[0008] The object of the present invention is to overcome the problems existing in the above-mentioned prior art, such as the low sampling frequency of traditional virtual oscilloscopes, the lack of flexibility in signal observation, and the negative effects of transmission loss and coefficient gain loss in external physical oscilloscopes, which make it difficult to accurately observe high-frequency signals. A high-speed real-time acquisition and display method for power simulation waveforms based on FPGA is provided, which can realize a fast signal observation method with high speed and high precision, and meet the observation requirements for high-frequency signals in fields such as new energy and small-step power simulation.

[0009] The object of the present invention can be achieved by the following technical solutions:

[0010] The present invention provides a real-time acquisition method for power simulation waveforms based on FPGA, and the steps include:

[0011] The host computer receives the oscilloscope sampling parameters and mapping configurations, and generates a corresponding configuration file, and the generated configuration file is sent to the FPGA through RT.

[0012] After receiving the configuration file, the FPGA enables the parameter configuration state machine to parse the configuration file, maps the configuration parameters to the FPGA local parameter register type, and generates a sampling parameter lookup table and a channel mapping lookup table.

[0013] The FPGA enables the data mapping IP, traverses the channel mapping lookup table, distributes the data to be measured to the corresponding pre-mapped cache, performs loop unrolling and circuit replication on the analog data volume, performs channel merging on the digital data volume, completes the synchronous mapping of the output port and generates a trigger signal.

[0014] The data that has completed the synchronous mapping of the output port is input to the subsequent data acquisition module, samples the data to be measured according to the trigger control signal to generate a sampling address, and based on the sampling address, jointly determines the sampling data address segment according to the variable pre-trigger cache and post-trigger cache, and outputs the sampling data and relevant cache information.

[0015] As a preferred technical solution, the RT reads the sampling parameters and channel mapping configuration files from the host computer, and detects whether the data flag bits are correct:

[0016] If the detection is correct, RT distributes the configuration file to the FPGA through the custom DMA read / write control module, which includes: a custom DMA read / write state machine for controlling the read / write state transition of the DMA channel and implementing control signal interaction; a read / write channel polling arbiter for generating read / write addresses, read / write enables, and read / write channel switching logic. The DMA read / write state machine receives configuration parameters from the AXI interface, triggers the DMA read / write state machine to enter the configuration state, generates corresponding request signals, allocates a channel ID after the read / write channel polling arbiter responds, and then the DMA read / write state machine starts data transmission. After the transmission is completed, it notifies the upper layer with the Status signal.

[0017] If the detection is incorrect, discard the configuration file and send an error warning to the host computer.

[0018] As a preferred technical solution, the number of states of the parameter configuration state machine matches the type of parameters configured in the host computer. Each configuration parameter has a corresponding configuration parameter index, and the configuration parameter index and the parameter register preset locally in the FPGA form a key-value pair.

[0019] The configuration parameters are parsed by the parameter configuration state machine, and the end of each state in the parameter configuration state machine represents the completion of the parsing of a configuration parameter.

[0020] The parameter configuration state machine maps and stores the parsed configuration parameter data and the parameter register locally in the FPGA based on the data type of the configuration parameter index in the issued configuration parameter key-value pair, and uses three BRAMs to store analog signals, digital signals, and trigger mode parameters respectively.

[0021] When the frame header data is detected again, it indicates that the current parameter configuration state machine has finished running.

[0022] As a preferred technical solution, the FPGA performs output port synchronous mapping and generates a trigger signal specifically as follows:

[0023] Enable the data mapping IP, traverse the channel mapping lookup table, and distribute the analog data source signal and the digital data source signal to the corresponding data channel pre-mapping cache according to the configuration requirements.

[0024] Take the pre-mapping cache of the analog data channel to be measured as the data source, perform circuit replication at the register transfer level, expand the loop to process each path of analog data, and complete the data channel synchronous mapping of each path of analog data.

[0025] Take the pre-mapping cache of the digital data channel to be measured as the data source, and perform channel merging on each path of digital data channels.

[0026] Traverse the sampling parameter lookup table, determine the trigger mode and generate the corresponding trigger signal for data sampling.

[0027] As a preferred technical solution, for analog quantities, FPGA includes multiple analog data channels, and pre-mapped caches are allocated to different analog quantities received by FPGA according to channel configuration; the channel mapping lookup table is traversed and an address counter is maintained for each analog data channel to generate a DDR mapping address; FPGA determines the specific channel number and address of the current data storage according to the channel mapping and the address counter, loop-unrolls the mapping loop, and replicates the value circuit at the RTL level to achieve data synchronous mapping;

[0028] For digital quantities, FPGA includes multiple digital data channels, which are merged into multi-bit width sampling data in FPGA, and the post-stage data acquisition module separates the data through array register index.

[0029] As a preferred technical solution, after the FPGA enters the operation stage, the acquisition memory address is counted, and when a trigger signal is received, the current acquisition memory address is stored as the acquisition data starting address;

[0030] FPGA traverses the sampling parameter lookup table, determines the trigger window length, trigger point value and trigger condition, and calculates the pre-trigger buffer and post-trigger buffer size;

[0031] After receiving the given trigger signal, the post-buffer counting starts. When the counter value reaches the post-trigger cache size, the counting stops. The acquisition completion signal is given and the cache information and the starting address of the acquired data are returned to the host computer. At the same time, the acquisition completion signal is used as a reset signal to control the global system reset.

[0032] As a preferred technical solution, the calculation of the pre-trigger cache is as follows:

[0033] Buffer pre =TrigWin×Value trig

[0034] Among them, Buffer pre is the size of the pre-trigger buffer, TrigWin is the trigger window length, Value trig is the trigger point value, Buffer pre , TrigWin and Value trig All are obtained through sampling parameter lookup table;

[0035] The post-trigger cache is calculated as follows:

[0036] Buffer post= TrigWin × (1 - Value trig )

[0037] where Value trig is a variable trigger point value, and the trigger point value is controlled by the host computer.

[0038] As a preferred technical solution, the FPGA outputs the sampled data and related cache information to the DDR for loopback storage:

[0039] A continuous address space of a fixed size is allocated in the DDR; when the system is in the conditional trigger working mode, the sampled data is loopback stored, and the newly sampled data overwrites the old sampled data that has completed transmission, forming a closed-loop storage stream with the head and tail connected.

[0040] As a preferred technical solution, the FPGA uses an AXI BRAM controller to implement the communication between the local Bram and the AXI bus, and completes the transmission of the data to be measured between the FPGA and the host computer and the interaction of the cache information through the DMA channel.

[0041] As a preferred technical solution, for multiple signals to be stored, the FPGA calculates the storage addresses of each data to be stored in parallel through a parallel bus address generator:

[0042] addr i = baseAddr + offset i + addrIncre

[0043] where addr i represents the storage address of the i-th data; baseAddr represents the base address; offset i represents the address offset of the i-th channel; addrIncre represents the address increment value.

[0044] Compared with the prior art, the present invention has the following beneficial effects:

[0045] 1) The present invention proposes a method for real-time acquisition of power simulation waveforms based on FPGA. The sampling configuration file is mapped to the local parameter register of the FPGA through a parameter configuration state machine, and a sampling parameter lookup table and a channel mapping lookup table are generated; the data to be measured is distributed to the corresponding pre-mapped cache, the analog data volume is loop-unrolled and the circuit is replicated, and the digital data volume is channel-merged; the sampling of the data to be measured is completed based on the trigger signal. Compared with the traditional virtual oscilloscope based on CPU, the solution for power simulation waveform acquisition by the FPGA of the present invention can achieve a sampling frequency of up to 20 MHz, has a higher time-domain resolution, can obtain more signal details, more accurately restore the original waveform of the signal, reduce signal distortion, avoid problems such as spectral aliasing, and is convenient for measuring and analyzing high-frequency signals.

[0046] 2) In the present invention, the host computer and the FPGA complete the distribution of configuration parameters and the upload of sampled data through RT via the DMA channel. Among them, RT completes the distribution of the configuration file through a custom DMA read / write control module. The read / write state machine of DMA controls the transfer of the read / write state of the DMA channel and realizes the interaction of control signals to achieve efficient and accurate DMA read / write operations. The read / write channel polling arbiter generates read / write addresses, read / write enables, and read / write channel switching logic to ensure that initialization data of different types in different channels can be correctly distributed. The local Bram of the FPGA communicates through the AXI bus and completes the transmission of the data to be measured between the FPGA and the host computer and the interaction of cache information through the DMA channel to realize the fast observation of high-frequency signals of small-step power simulation of the virtual oscilloscope.

[0047] 3) The present invention distributes the data to be measured to the corresponding pre-mapped cache by traversing the channel mapping lookup table. For the analog quantity to be measured, each analog data channel maintains an address counter for generating the mapping address. The FPGA determines the specific channel number and address where the current data is stored according to the lookup table and the address counter. For the digital quantity to be measured, after the multiplexed digital data channels are merged, the data can be separated through register indexing. And the FPGA provides a parallel bus address generator to calculate the storage addresses of each piece of data to be stored in parallel, and can complete the parallel storage of multiplexed data within a single clock cycle and avoid potential address conflicts.

[0048] 4) The present invention sets variable trigger point values to allocate the proportion of the pre-trigger cache and the post-trigger cache in the trigger window, and stores the sampled data and the cache information of the relevant data storage addresses in a loop in the DDR, avoiding the buffer overflow problem that is likely to occur in traditional linear storage. Description of the Drawings

[0049] Figure 1 It is a flowchart of the operation of a method for high-speed real-time acquisition and display of power simulation waveforms based on FPGA provided by an embodiment of the present invention;

[0050] Figure 2 It is a flowchart of the initialization configuration of a method for high-speed real-time acquisition and display of power simulation waveforms based on FPGA provided by an embodiment of the present invention;

[0051] Figure 3 It is a schematic diagram of the data mapping module of a method for high-speed real-time acquisition and display of power simulation waveforms based on FPGA provided by an embodiment of the present invention;

[0052] Figure 4 It is a control block diagram of data acquisition of a method for high-speed real-time acquisition and display of power simulation waveforms based on FPGA provided by an embodiment of the present invention;

[0053] Figure 5 This is a schematic diagram of the waveform display on the host computer for a high-speed real-time acquisition and display method of power simulation waveforms based on FPGA provided by an embodiment of the present invention. Specific implementation manners

[0054] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. This embodiment is implemented on the premise of the technical solution of the present invention, and detailed implementation manners and specific operation procedures are given, but the protection scope of the present invention is not limited to the following embodiments.

[0055] Embodiment 1

[0056] A high-speed real-time acquisition and display method of power simulation waveforms based on FPGA, as Figure 1 shown, includes the following steps:

[0057] Step 1: Complete the sampling parameters and display configuration of the high-speed oscilloscope on the host computer, generate a corresponding initialization configuration file through the host computer configuration, and send the initialization configuration file to the real-time system (Real-Time, RT).

[0058] Specifically, the initialization configuration in Step 1 includes the following steps:

[0059] Step 1a: The front end of the host computer establishes an Ethernet communication with the corresponding emulator device through a preset device IP address, and completes the sampling parameter and channel mapping configuration on the host computer. Among them, the sampling parameters include, but are not limited to, sampling rate, sampling duration, trigger mode, channel data type, sampling data volume, analog channel mapping, data volume channel mapping, etc. The sampling parameter and channel mapping configuration in this embodiment are specifically as follows:

[0060] Sampling rate: Supports multiple sampling rate configurations such as 50kHZ, 200kHz, 500kHz, 1MHz, 2MHz, 10Mhz, 20MHz, etc.

[0061] Sampling time: The required sampling time can be manually input.

[0062] Trigger mode: Manual trigger, conditional trigger, forced trigger. Among them, the conditional trigger can be divided into rising edge trigger or falling edge trigger, and the data to be measured needs to meet the trigger threshold. When the conditional trigger cannot generate a conditional trigger response, a forced trigger can be performed to immediately capture the current data for observation.

[0063] Channel type: Analog quantity, digital quantity. Such as PWM wave, high-frequency voltage and current ripple, etc.

[0064] Trigger source: Select the signal for which the rising edge needs to be configured.

[0065] Trigger threshold: The preset value of the trigger waveform, used for the conditional trigger mode.

[0066] Channel settings: Include analog channel settings and digital channel settings, used to determine the data source channels to be mapped, determine the channel names, and the oscilloscope numbers for observation.

[0067] Step 1b: The upper computer backend reads the configuration information generated by the front end and generates the corresponding configuration file. Establishes communication with the RT through the TCP protocol and distributes the configuration file.

[0068] Step 2: The RT reads the sampling parameters and channel mapping configuration file from the upper computer and transfers the configuration file to the FPGA through the Direct Memory Access (DMA) channel.

[0069] Specifically, Step 2 includes the following steps:

[0070] Step 2a: The RT reads the configuration file received from the upper computer and checks whether the data flag bit is correct.

[0071] Step 2b: If the detection is correct, the configuration file is sent to the FPGA, the configuration data signal width is set to 32 bits, and the FPGA is controlled to enter the parameter configuration mode. If the detection is incorrect, the configuration file is discarded and an error warning is sent to the upper computer.

[0072] Furthermore, in Step 2b, the distribution of the configuration file is completed through a custom DMA read / write control module. The DMA read / write control module includes a custom DMA read / write state machine, which is used to control the read / write state transition of the DMA channel and implement control signal interaction; a read / write channel polling arbiter, which is used to generate read / write addresses, read / write enables, and read / write channel switching logic to ensure that the initialization data of different channels and different types can be correctly sent. The DMA read / write state machine receives configuration parameters from the AXI interface, triggers the DMA read / write state machine to enter the configuration state, generates corresponding request signals, allocates channel IDs after the read / write channel polling arbiter responds, and the DMA read / write state machine starts data transmission. After the transmission is completed, it notifies the upper layer with the Status signal. The combination of the two meets the dynamic configuration requirements for high-frequency signal acquisition in the power system.

[0073] Step 3: After receiving the configuration file, the FPGA enables the parameter configuration state machine to parse the configuration file according to the preset configuration file structure, generates sampling parameters and a channel mapping lookup table, and completes the program initialization configuration.

[0074] Specifically, Step 3 includes the following steps:

[0075] Step 3a: The RT checks whether the FPGA configuration file has been successfully sent.

[0076] Step 3b: The FPGA parses the configuration file, creates sampling parameters and a channel mapping lookup table, outputs a configuration completion signal, and the RT controls the FPGA to enter the operating phase.

[0077] Further, the FPGA parses the configuration file through a running parameter configuration state machine. The number of states of the parameter configuration state machine is determined by the parameter types configured by the host computer. Each configuration parameter has a corresponding configuration parameter index, which forms a key-value pair with the registers preset locally in the FPGA, including a sampling rate key-value pair, a sampling time key-value pair, a trigger mode key-value pair, a channel type key-value pair, a trigger source key-value pair, a trigger threshold key-value pair, a channel setting key-value pair, etc. The end of each state in the parameter configuration state machine represents the completion of the parsing of a configuration parameter. As Figure 2 shown, the parameter configuration state machine stores the parsed configuration parameters. Three BRAMs are used to store analog signals, digital signals, and trigger mode parameters respectively. In subsequent processing, the BRAMs can be directly accessed to obtain the desired data or configuration signals. The stored data and the local parameter registers in the FPGA are mapped through the data type index in the issued data key-value pair for subsequent data processing and system control. When the frame header data is detected again, it indicates the end of the operation of the current parameter configuration state machine.

[0078] Step 4: The measured signals to be collected are sent by the controller to the emulator. The signal types include but are not limited to voltage, current, power, PWM control signals, high-frequency voltage and current ripples, etc. The FPGA traverses the channel mapping lookup table, distributes the data to be measured to the corresponding pre-mapped caches, performs loop unrolling and circuit replication on the analog data volume, performs channel merging on the digital data volume, completes the synchronous mapping of the output ports, and generates a trigger signal to control sampling.

[0079] Specifically, Step 4 includes the following steps:

[0080] Step 4a: The FPGA enables the data mapping IP, traverses the channel mapping lookup table, and distributes the analog data source signals and digital data source signals to the corresponding data channel pre-mapped caches according to the requirements configured by the host computer.

[0081] Step 4b: Using the pre-mapped cache of the analog data channel to be measured as the data source, circuit replication is performed at the Register Transfer Level (RTL), the loop is unrolled to process each path of analog data, and the data channel synchronous mapping of each path of analog data is completed.

[0082] Step 4c: Traverse the sampling parameter lookup table, determine the trigger mode, and generate the corresponding trigger signal for high-precision data sampling.

[0083] Further, as Figure 3As shown, for analog signals, it supports multiple analog data channels. According to the channel configuration requirements of the host computer, pre-mapped caches are allocated to different analog signals received by the FPGA. The channel mapping lookup table is traversed and an address counter is maintained for each analog data channel to generate the DDR mapping address. The FPGA determines the specific channel number and address for the current data storage based on the channel mapping lookup table and the address counter, unfolds the mapping loop, and replicates the value-taking circuit at the RTL level to achieve data synchronous mapping. For digital signals, it supports multiple digital data channels. In the FPGA, multiple digital data channels are merged into multi-bit-width sampled data, and the subsequent data acquisition module can separate the data by means of array register indexing and observe and analyze the required data channels.

[0084] Furthermore, it supports multiple triggering methods including conditional triggering, manual triggering, and forced triggering. In the conditional triggering mode, the data mapping IP will generate a conditional trigger response signal to determine whether the measured data x(i,n) meets the edge trigger condition and trigger threshold set by the host computer. Here, i is the channel number representing the source of the measured data. i = 0 indicates that this data comes from the first analog data channel, and so on. n is the time series of 0, 1, 2, 3... If the measured data x(i,n) all meet the trigger condition and trigger threshold, a trigger response is issued. Under the rising edge trigger condition, the measured data needs to meet:

[0085] x(i,n)>x(i,n - 1) and x(i,n)>threshold i

[0086] Under the falling edge trigger condition, the measured data needs to meet:

[0087] x(i,n)<x(i,n + 1) and x(i,n)<threshold i

[0088] where, threshold i represents the trigger threshold of the i-th channel configured by the host computer.

[0089] In the manual triggering and forced triggering modes, the trigger signal is given by the host computer, and the final trigger signal is jointly determined by the conditional trigger response, manual trigger signal, and forced trigger signal.

[0090] Step 5: As Figure 4As shown in the figure, the data after mapping is input into the subsequent data acquisition module. Sampling trigger addresses are generated according to the trigger control signal to sample the data. The variable pre-trigger cache and post-trigger cache sizes are calculated based on the trigger point value and the sampling window length. Taking the sampling trigger address as the base point, the sampling data address segment is determined jointly by the pre-trigger cache and the post-trigger cache, and the sampled data and relevant cache information are output to the DDR for loopback storage.

[0091] Specifically, step 5 includes the following steps:

[0092] Step 5a: After the FPGA enters the running stage, the address of the acquisition memory is counted, and when the trigger signal is received, the current acquisition memory address is registered as the starting address of the acquired data.

[0093] Step 5b: Traverse the sampling parameter look-up table to determine the trigger window length, trigger point value, and trigger condition, and calculate the sizes of the pre-trigger cache and the post-trigger cache.

[0094] Step 5c: After receiving the high-level trigger signal from the upper level, start post-cache counting. When the counter reaches the post-cache size, it represents the end of the current sampling. The FPGA sends out a sampling end signal and transmits the cache information and the starting address of the acquired data back to the host computer to determine the range of the data to be measured.

[0095] Furthermore, the generated data storage address adopts a loopback mechanism. A continuous address space of a fixed size is opened up in the DDR for sampling data caching. When the system is in the conditional trigger working mode, there may be a situation where the trigger response cannot be generated for a long time. Sampling loopback storage can overwrite the old data that has completed transmission with new data, forming a closed-loop storage stream that connects the head and the tail. Through the dynamic update mechanism, the buffer overflow problem that is prone to occur in traditional linear storage is fundamentally avoided.

[0096] Furthermore, the calculation method of the pre-trigger cache is as follows:

[0097] Buffer pre =TrigWin×Valu trig

[0098] Where Buffer pre is the size of the pre-trigger cache, TrigWin is the trigger window length, and Value trig is the trigger point value. Buffer pre , TrigWin, and Value trig can all be obtained through the sampling parameter look-up table.

[0099] The calculation method of the post-trigger cache can be referred to:

[0100] Buffer post= TrigWin × (1 - Value trig )

[0101] Variable trigger point value Value trig The upper computer controls the trigger point value. The FPGA calculates the proportions of the pre-trigger cache and the post-trigger cache in the trigger window according to the trigger point value, which is used to determine the display position of the data generated by the conditional trigger in the upper computer on the waveform diagram. After the pre-trigger cache and the post-trigger cache are calculated, the counting of the collected data starts. When the value of the counter reaches the size of the post-trigger cache, the counting stops, and a data acquisition completion signal is given back to the upper computer. At the same time, this signal is used as a reset signal to control the global system reset.

[0102] Step 6: The FPGA uploads the high-precision sampled data to the upper computer. The upper computer receives the data for data display and provides a parameter configuration interface. The waveform display of the upper computer is as Figure 5 shown.

[0103] Specifically, Step 6 includes the following steps:

[0104] Step 6a: The FPGA uses the AXI BRAM controller to implement the communication between the local Bram and the AXI bus and completes the transmission of the data to be measured and the interaction of cache information between the FPGA and the upper computer through the DMA channel.

[0105] Step 6b: The RT side analyzes and uploads the data to be measured according to the structure of the sampled data and the requirements of the upper computer parameters. The upper computer can perform real-time observation on various signal data of the small-step power simulation.

[0106] Furthermore, for multiple signals to be stored, a parallel bus address generator is provided to calculate the storage addresses of each path of data to be stored in parallel:

[0107] addr i = baseAddr + offset i + addrIncre

[0108] where addr i represents the storage address of the i-th path of data; baseAddr is a constant representing the base address; offset i is a constant representing the address offset of the i-th channel; addrIncre is a constant representing the address increment value. It can be seen from the formula that each path of data to be measured has its own different storage address, so as to be able to complete the parallel storage of multiple paths of data within a single clock cycle and avoid potential address conflicts.

[0109] Compared with the sampling frequencies of 10 kHz and 20 kHz of traditional CPU-based virtual oscilloscopes, the present invention provides a sampling frequency of up to 20 MHz, has a higher time-domain resolution, can obtain more signal details, more accurately restore the original waveform of the signal, reduce signal distortion, avoid problems such as spectral aliasing, and facilitate the measurement and analysis of high-frequency signals. At the same time, the present invention avoids problems such as signal attenuation and phase distortion caused by external physical oscilloscopes while retaining high-speed and high-precision sampling data, improving the accuracy and reliability of measurement. It has the effect of quickly observing high-frequency signals of small-step power simulation using a virtual oscilloscope. In addition, users can complete the configuration of sampling parameters and channel mapping through the host computer, can be customized according to different measurement requirements, meet the test requirements of various complex scenarios, and have higher convenience and flexibility.

[0110] All the above-described details are merely part of the more preferred presentation forms among the numerous feasible implementation manners of the present invention. It should be emphasized that the present invention is by no means confined to these mentioned implementation examples. For those ordinary technical personnel who are deeply involved in this technical field and have solid professional knowledge and rich practical experience, after they deeply understand and accurately master the core points, key technologies, and innovative concepts recorded in the present invention, as long as they can ensure that they always follow the basic principles on which the present invention depends and do not deviate from its established technical track, they are fully capable and have the space to perform a series of reasonable and creative equivalent transformation operations on the existing invention content, as well as adopt alternative solutions with equivalent functions. These equivalent transformations and substitutions should also be regarded as belonging to the protection scope of the present invention.

Claims

1. A real-time acquisition method for power simulation waveforms based on FPGA, characterized in that the steps Including: The upper computer receives the oscilloscope sampling parameters and mapping configurations, and generates corresponding configuration files, which are sent to the FPGA through RT; After receiving the configuration file, the FPGA enables the parameter configuration state machine to parse the configuration file, maps the configuration parameters to the types of local parameter registers in the FPGA, and generates a sampling parameter lookup table and a channel mapping lookup table; The FPGA enables the data mapping IP, traverses the channel mapping lookup table, distributes the data to be measured to the corresponding pre-mapped cache, performs loop unrolling and circuit replication on the analog data volume, merges channels for the digital data volume, completes the synchronous mapping of the output port and generates a trigger signal; The data that has completed the synchronous mapping of the output port is input to the subsequent data acquisition module. The sampling trigger address is generated according to the trigger control signal to sample the data to be measured, and the variable pre-trigger cache and post-trigger cache sizes are calculated based on the trigger point value and the sampling window length; Based on the sampling trigger address, the sampling data address segment is obtained according to the variable pre-trigger cache and post-trigger cache, and the sampling data and relevant cache information are output.

2. The real-time acquisition method of power simulation waveforms based on FPGA according to claim 1, characterized in that The RT reads the sampling parameters and channel mapping configuration files from the upper computer, and detects whether the data flag bits are correct: If the detection is correct, the RT sends the configuration file to the FPGA through a custom DMA read / write control module. The custom DMA read / write control module includes: a custom DMA read / write state machine for controlling the read / write state transition of the DMA channel and implementing control signal interaction; a read / write channel polling arbiter for generating read / write addresses, read / write enables, and read / write channel switching logic. The DMA read / write state machine receives configuration parameters from the AXI interface, triggers the DMA read / write state machine to enter the configuration state, generates corresponding request signals, allocates channel IDs after the read / write channel polling arbiter responds, and the DMA read / write state machine starts data transmission. After the transmission is completed, it notifies the upper layer with the Status signal; If the detection is incorrect, the configuration file is discarded and an error warning is sent to the upper computer.

3. A real-time acquisition method for power simulation waveforms based on FPGA according to claim 1, characterized in that The number of states of the parameter configuration state machine matches the types of parameters configured in the upper computer. Each configuration parameter has a corresponding configuration parameter index, and the configuration parameter index and the local preset parameter registers in the FPGA form a key-value pair; The configuration parameters are parsed through the parameter configuration state machine, and the end of each state in the parameter configuration state machine represents the completion of the parsing of a configuration parameter; The parameter configuration state machine maps and stores the parsed configuration parameter data and the local parameter registers in the FPGA based on the data type of the configuration parameter index in the issued configuration parameter key-value pair, and uses three BRAMs to store analog signals, digital signals, and trigger mode parameters respectively; When the frame header data is detected again, it indicates that the current parameter configuration state machine has finished running.

4. A real-time acquisition method for power simulation waveforms based on FPGA according to claim 1, characterized in that, The specific process of the FPGA performing output port synchronous mapping and generating a trigger signal is as follows: Enable the data mapping IP, traverse the channel mapping lookup table, and distribute the analog data source signal and the digital data source signal to the corresponding data channel pre-mapped cache according to the configuration requirements; Taking the pre-mapped cache of the analog data channel to be measured as the data source, circuit replication is performed at the register transfer level, the loop is unrolled to process each path of analog data, and data channel synchronization mapping of each path of analog data is completed; Taking the pre-mapped cache of the digital data channel to be measured as the data source, channel merging is performed on each path of digital data channels; Traverse the sampling parameter lookup table, determine the trigger mode and generate the corresponding trigger signal for data sampling.

5. A real-time acquisition method for power simulation waveforms based on FPGA according to claim 4, characterized in that For analog signals, the FPGA includes multiple analog data channels, and pre-mapped caches are allocated to different analog signals received by the FPGA according to the channel configuration; Traverse the channel mapping lookup table and maintain an address counter for each path of analog data channel to generate the DDR mapping address; The FPGA determines the specific channel number and address of the current data storage according to the channel mapping and the address counter, unrolls the mapping loop, and replicates the value-taking circuit at the RTL level to achieve data synchronization mapping; For digital signals, the FPGA includes multiple digital data channels. In the FPGA, multiple digital data channels are merged into multi-bit wide sampled data, and the subsequent data acquisition module separates the data through array register indexing.

6. A real-time acquisition method for power simulation waveforms based on FPGA according to claim 1, characterized in that, After the FPGA enters the running stage, the address of the acquisition memory is counted. When a trigger signal is received, the current acquisition memory address is latched as the starting address of the acquired data; The FPGA traverses the sampling parameter lookup table, determines the trigger window length, trigger point value and trigger condition, and calculates the sizes of the pre-trigger cache and post-trigger cache; After receiving the given trigger signal, start post-cache counting. Stop counting when the value of the counter reaches the size of the post-trigger cache, give the acquisition completion signal and send the cache information and the starting address of the acquired data back to the host computer. At the same time, the acquisition completion signal is used as a reset signal to control the global system reset.

7. A real-time acquisition method for power simulation waveforms based on FPGA according to claim 6, characterized in that The calculation of the pre-trigger cache is as follows: Buffer pre = TrigWin × Value trig Among them, Buffer pre is the size of the pre-trigger cache, TrigWin is the trigger window length, and Value trig is the trigger point value. Buffer pre , TrigWin, and Value trig are all obtained through the sampling parameter look-up table; The calculation method of the post-trigger cache is as follows: Buffer post = TrigWin × (1 - Value trig ) Among them, Value trig is a variable trigger point value, and the trigger point value is controlled by the host computer.

8. A real-time acquisition method for power simulation waveforms based on FPGA according to claim 6, characterized in that, The FPGA outputs the sampled data and related cache information to the DDR for loopback storage: Allocate a continuous address space of a fixed size in the DDR; When the system is in the conditional trigger working mode, loopback store the sampled data, overwrite the old sampled data that has completed transmission with the new sampled data, and form a closed-loop storage stream with the head and tail connected.

9. A real-time acquisition method for power simulation waveforms based on FPGA according to claim 1, characterized in that, The FPGA uses the AXI BRAM controller to realize the communication between the local Bram and the AXI bus, and completes the transmission of the data to be measured between the FPGA and the host computer and the interaction of the cache information through the DMA channel.

10. A real-time acquisition method for power simulation waveforms based on FPGA according to claim 1, characterized in that, The FPGA calculates the storage address for each path of data to be stored in parallel through the parallel bus address generator for multiple paths of signals to be stored: addr i = baseAddr + offset i + addrIncre Among them, addr i represents the storage address of the i-th data; baseAddr represents the base address; offset i represents the address offset of the i-th channel; addrIncre represents the address increment value.

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