High-speed interface, chip and multi-channel data synchronization method of high-speed interface

Abstract

The invention provides a high-speed interface, a chip and a multi-channel data synchronization method of the high-speed interface. The high-speed interface comprises a plurality of channels; the synchronous control circuit is used for carrying out synchronous processing on a plurality of control signals output by the plurality of digital circuit parts in the plurality of channels to generate a plurality of first synchronous control signals and a plurality of second synchronous control signals which are synchronous with the high-speed clock signal and / or the low-speed clock signal; each first synchronous control signal controls the data transmission process between the digital circuit part and the analog circuit part in the corresponding channel, and each second synchronous control signal controls the parallel-serial conversion process of data in the analog circuit of the corresponding channel. According to the scheme, synchronous control is added between the digital circuit and the analog circuit and between the analog circuit and the digital circuit, the multi-channel data deviation of the high-speed interface is reduced, multi-channel data synchronization is achieved, and the compatibility of high-speed interface equipment is improved.

Description

Technical Field

[0001] The present application relates to the technical field of digital signal processing, and specifically relates to a high-speed interface, a chip, and a multi-channel data synchronization method for a high-speed interface. Background Art

[0002] In a high-speed interface, due to the limitations of the speed of a single channel and the overall data throughput, multiple channels are often used. In modern electronic devices, the data transmitted between different channels of a high-speed interface is prone to deviation or inconsistency, and such data deviation will have a negative impact on system performance and data integrity. Therefore, during the data transmission process, it is necessary to perform data synchronization control on the multi-channel data of the high-speed interface to reduce the data deviation between different channels.

[0003] There are multiple cross-clock domains in the multi-channel data transmitted by the high-speed interface, including from the protocol layer to the physical layer, and from the low-speed clock of the physical layer to the high-speed clock. It is difficult for existing multi-channel data synchronization methods to achieve strict data synchronization between different channels, or existing multi-channel data synchronization methods cannot meet the requirements for the multi-channel data deviation of the high-speed interface. Summary of the Invention

[0004] In order to solve the above technical problems, the present application provides a high-speed interface, a chip, and a multi-channel data synchronization method for a high-speed interface, aiming to reduce the multi-channel data deviation of the high-speed interface and improve the compatibility of high-speed interface devices.

[0005] According to a first aspect of the present application, a high-speed interface is provided, including:

[0006] Multiple channels, each channel including a corresponding digital circuit part and an analog circuit part, and the digital circuit part outputs a control signal;

[0007] A synchronization control circuit, which receives multiple control signals output by multiple digital circuit parts in the multiple channels, performs synchronization processing on the multiple control signals, generates multiple first synchronization control signals, and multiple second synchronization control signals synchronized with a high-speed clock signal and / or a low-speed clock signal, and respectively outputs them to multiple analog circuit parts in the multiple channels,

[0008] Each first synchronization control signal is used to control the data transmission process between the digital circuit part and the analog circuit part of the corresponding channel, and each second synchronization control signal is used to control the serial-to-parallel conversion process of the data in the analog circuit of the corresponding channel. The high-speed clock signal and the low-speed clock signal are used to implement the serial-to-parallel conversion of the data.

[0009] Optionally, the synchronization control circuit includes:

[0010] Multiple first retiming units respectively receive the multiple control signals, perform retiming processing on the multiple control signals respectively, and output multiple synchronized control signals.

[0011] Optionally, the synchronization control circuit further includes:

[0012] Multiple delay control units are respectively connected to the multiple first retiming units, and are used for respectively performing delay control on the output signals of the multiple first retiming units, and outputting the multiple first synchronization control signals.

[0013] Optionally, the delay amounts of the output signals of the multiple first retiming units by the multiple delay control units are all equal.

[0014] Optionally, the delay amounts of the output signals of the multiple first retiming units by the multiple delay control units are not equal or not completely equal.

[0015] Optionally, the synchronization control circuit further includes:

[0016] A multiplexer respectively receives the multiple control signals, selects one of the multiple control signals for output;

[0017] A second retiming unit is connected to the output end of the multiplexer, and is used for performing retiming processing on the output signal of the multiplexer, and outputting the multiple second synchronization control signals.

[0018] Optionally, each channel terminal analog circuit part includes:

[0019] A clock port for outputting a clock signal to the corresponding digital circuit part;

[0020] A data port for receiving a data signal output by the corresponding digital circuit part;

[0021] A first synchronization control port for receiving the corresponding first synchronization control signal;

[0022] A second synchronization control port for receiving the corresponding second synchronization control signal;

[0023] A differential output port for realizing signal communication with an external device.

[0024] According to a second aspect of the present application, there is provided a chip, including: the high-speed interface as described in any embodiment of the present application.

[0025] According to a third aspect of the present application, there is provided a multi-channel data synchronization method for a high-speed interface, the high-speed interface includes multiple channels, and each channel includes a corresponding digital circuit part and an analog circuit part.

[0026] The multi-channel data synchronization method includes:

[0027] Synchronize the multiple control signals output by the multiple digital circuit parts in the multiple channels to generate multiple first synchronous control signals, and each first synchronous control signal is used to control the data transmission process between the digital circuit part and the analog circuit part of the corresponding channel;

[0028] Synchronize the multiple control signals output by the multiple digital circuit parts in the multiple channels to generate multiple second synchronous control signals synchronized with the high-speed clock signal and / or low-speed clock signal in the serial-to-parallel conversion, and respectively output them to the multiple analog circuit parts in the multiple channels. Each second synchronous control signal is used to control the serial-to-parallel conversion process of the data in the analog circuit of the corresponding channel.

[0029] Optionally, synchronizing the multiple control signals output by the multiple digital circuit parts in the multiple channels to generate multiple first synchronous control signals includes:

[0030] Perform retiming processing on the multiple control signals respectively to generate multiple synchronous first synchronous control signals;

[0031] Alternatively, perform retiming processing on the multiple control signals respectively to generate multiple synchronous control signals, and perform delay control on the multiple synchronous control signals respectively to generate the multiple first synchronous control signals.

[0032] Optionally, synchronizing the multiple control signals output by the multiple digital circuit parts in the multiple channels to generate multiple second synchronous control signals includes:

[0033] Select one of the multiple control signals;

[0034] Perform retiming processing on the selected control signal to generate the multiple second synchronous control signals.

[0035] The beneficial effects of this application at least include:

[0036] In the embodiment of this application, an independent synchronous control circuit is provided in the high-speed interface. The first synchronous control signal and the second synchronous control signal respectively generated by the synchronous control circuit according to the multiple control signals output by the digital circuit part of the physical layer of the high-speed interface are used to respectively control the signal synchronization processing between the digital circuit part and the analog circuit part, and between the low-speed circuit and the high-speed circuit in the analog circuit part. Compared with the existing scheme, the scheme of this application can effectively reduce the multi-channel data deviation of the high-speed interface, thereby realizing the synchronous transmission of multi-channel data and improving the compatibility of the high-speed interface device.

[0037] It should be noted that the above general description and the following detailed description are only exemplary and explanatory, and do not limit this application. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 Schematic diagram showing the internal circuit of a high-speed interface in the related art;

[0039] Figure 2 Schematic diagram showing the internal circuit of a high-speed interface provided according to an embodiment of this application;

[0040] Figure 3 Showing Figure 2 Partial schematic diagram of the internal circuit of the synchronization control circuit in

[0041] Figure 4 Showing Figure 2 Partial schematic diagram of the internal circuit of the synchronization control circuit in

[0042] Figure 5 Schematic flowchart showing the multi-channel data synchronization method of the high-speed interface provided according to an embodiment of this application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0043] To facilitate the understanding of this application, the following will describe this application more comprehensively with reference to the relevant drawings. The preferred embodiments of this application are shown in the drawings. However, this application can be implemented in different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosed content of this application more thorough and comprehensive.

[0044] The reference to "one embodiment" or "some embodiments" etc. described in this specification means that a specific feature, structure or characteristic described in connection with the embodiment is included in one or more embodiments of this application. Thus, the statements "in one embodiment", "in some embodiments", "in other some embodiments", "in still other embodiments" etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "comprising", "including", "having" and their variants all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0045] In the description of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments. The "and / or" herein describes an association relationship between associated objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. "Plurality" means two or more than two. Additionally, in order to clearly describe the technical solutions of the embodiments of this application, words such as "first" and "second" are used to distinguish identical or similar items with basically the same functions and roles. Those skilled in the art can understand that the words "first", "second", etc. do not limit the quantity and execution order, and the words "first", "second", etc. do not necessarily limit to being different.

[0046] In addition, the same reference numerals in the figures represent the same or similar structures, so the repeated description thereof will be omitted. That is, each part in this specification is described in a combined manner of parallelism and progression. The key point of each part is to illustrate the differences from other parts, and the same or similar parts between each part can be referred to each other.

[0047] A high-speed interface refers to an interface used for transmitting data between chips or between a chip and an external device, and usually has a relatively high data transmission rate and bandwidth. These interfaces can be various standard interfaces, such as PCI Express, USB, HDMI, Ethernet, etc.

[0048] The high-speed interface includes a protocol layer and a physical layer. Its physical layer usually includes at least one of digital circuits such as a data buffer circuit, a control circuit, an error detection and correction circuit, etc., and at least one of analog circuits such as an analog-to-digital conversion circuit (ADC), a digital-to-analog conversion circuit (DAC), an operational amplifier circuit, a high-speed clock circuit, a driver circuit, etc. Among them, the functions and connection relationships of each digital circuit and each analog circuit can be understood with reference to existing technical solutions and will not be elaborated herein.

[0049] Figure 1 The internal circuit schematic diagram of a high-speed interface in the related art is shown, such as Figure 1 As shown, in this related art, the high-speed interface includes a plurality of channels 10~1x, where x is an integer greater than 1. The physical layer circuit of each channel includes a digital circuit part and an analog circuit part.

[0050] Taking channel 10 as an example, channel 10 includes a digital circuit part 0 and an analog circuit part 0. Among them, the analog circuit part 0 outputs a clock signal clk0 to the digital circuit part 0. The digital circuit part 0 generates a data signal data0 based on the clock signal clk0 and transmits it to the analog circuit part 0. At the same time, the digital circuit part 0 also outputs a control signal ctrl0 to the analog circuit part 0 to control the operation of the analog circuit part 0. The analog circuit part 0 also includes differential signal output terminals padp0 and padn0. Channel 10 is docked with other devices based on these differential signal output terminals padp0 and padn0. The same applies to other channels 11 to 1x.

[0051] In current high-speed interface protocols, some protocols such as DisplayPort define four channels and have strict requirements for multi-channel data deviation, such as less than 2UI. Some protocols such as MIPI do not have clear requirements for multi-channel data deviation. From the perspective of compatibility between actual devices, it is often desirable that this deviation is as small as possible. And in Figure 1 the high-speed interface shown, after the digital circuit part in each channel outputs the corresponding control signal, it is directly output to the corresponding analog circuit part, which is equivalent to independently controlling each channel during the data transmission process of multiple channels. In this way, when there are multiple clock domains in multiple channels, the data deviation between channels is often greater than 2UI, making it difficult to meet the relevant protocol requirements and achieve synchronous data transmission between different channels.

[0052] Based on the solution shown in Figure 1 this application, corresponding synchronous control strategies are added respectively between the digital circuit part and the analog circuit part of each channel, and between the low-speed circuit and the high-speed circuit in the analog circuit. Synchronous processing is performed on the signals in the two core areas affected by multi-channel data deviation, effectively reducing the multi-channel data deviation of the high-speed interface, and thus improving the compatibility of high-speed interface devices.

[0053] Figure 2 shows a schematic diagram of the internal circuit of the high-speed interface provided by an embodiment of this application. As Figure 2 shown, the high-speed interface disclosed in this embodiment includes: a plurality of data transmission channels (abbreviated as channels in this article) 20 to 2x (x is an integer greater than 1), and a synchronous control circuit 200.

[0054] Among multiple channels 20 to 2x, the physical layer circuit of each channel includes a digital circuit part and an analog circuit part. Taking channel 20 as an example, channel 20 includes a digital circuit part 0 and an analog circuit part 0. Among them, the analog circuit part 0 outputs a clock signal clk0 to the digital circuit part 0 based on its clock port. The digital circuit part 0 generates a data signal data0 based on the clock signal clk0 and transmits it to the data port of the analog circuit part 0. At the same time, the digital circuit part 0 also outputs a control signal ctrl0. After being synchronized by the synchronization control circuit 200, the control signal ctrl0 outputs a first synchronization control signal ctrl_sync01 to the first synchronization control port of the analog circuit part 0, and outputs a second synchronization control signal ctrl_sync02 to the second synchronization control port of the analog circuit part 0. In addition, the analog circuit part 0 also includes differential signal output terminals padp0 and padn0. Channel 20 realizes docking and communication with other devices or chips based on the differential signal output ports padp0 and padn0. The same applies to other channels 21 to 2x.

[0055] The synchronization control circuit 200 receives multiple control signals ctrl0 to ctrlx output by multiple digital circuit parts (including digital circuit parts 0 to x) in multiple channels 20 to 2x. The synchronization control circuit 200 is used to synchronize the multiple received control signals ctrl0 to ctrlx, generate multiple first synchronization control signals ctrl_sync01 to ctrl_syncx1, and multiple second synchronization control signals ctrl_sync02 to ctrl_syncx2, and output them to the corresponding analog circuit parts in multiple channels 20 to 2x respectively. Among them, the multiple second synchronization control signals ctrl_sync02 to ctrl_syncx2 generated by the synchronization control circuit 200 are synchronized with the high-speed clock signal and / or low-speed clock signal in the corresponding analog circuit part, preferably synchronized with the high-speed clock signal.

[0056] As Figure 2 shown, the synchronization control circuit 200 outputs a first synchronization control signal ctrl_sync01 and a second synchronization control signal ctrl_sync02 to the analog circuit part 0, outputs a first synchronization control signal ctrl_sync11 and a second synchronization control signal ctrl_sync12 to the analog circuit part 1, and so on, outputs a first synchronization control signal ctrl_syncx1 and a second synchronization control signal ctrl_syncx2 to the analog circuit part x. Among them, each first synchronization control signal is used to control the data transmission process between the digital circuit part and the analog circuit part of the corresponding channel, and each second synchronization control signal is used to control the parallel-to-serial conversion process of the data in the analog circuit of the corresponding channel. The high-speed clock signal and the low-speed clock signal are used to realize the parallel-to-serial conversion of the data.

[0057] In specific implementation, the synchronization control circuit 200 further includes: a plurality of first retiming units and a plurality of delay control units. Among them, the plurality of first retiming units respectively receive a plurality of control signals ctrl0~ctrlx, and perform retiming processing on the plurality of control signals ctrl0~ctrlx respectively, and output a plurality of synchronized control signals. The plurality of delay control units are respectively connected to the plurality of first retiming units, and are used to perform delay control on the output signals of the plurality of first retiming units respectively, and output a plurality of first synchronization control signals ctrl_sync01~ctrl_syncx1.

[0058] As Figure 3 shown, in the synchronization control circuit 200, the plurality of first retiming units include a first retiming unit 0 to a first retiming unit x, and the plurality of delay control units include a delay control unit 0 to a delay control unit x. Among them, the input end of the first retiming unit 0 receives the control signal ctrl0, the output end of the first retiming unit 0 is connected to the input end of the delay control unit 0, and the output end of the delay control unit 0 outputs the first synchronization control signal ctrl_sync01; similarly, the input end of the first retiming unit 1 receives the control signal ctrl1, the output end of the first retiming unit 1 is connected to the input end of the delay control unit 1, and the output end of the delay control unit 1 outputs the first synchronization control signal ctrl_sync11, the input end of the first retiming unit x receives the control signal ctrlx, the output end of the first retiming unit x is connected to the input end of the delay control unit x, and the output end of the delay control unit x outputs the first synchronization control signal ctrl_syncx1.

[0059] Optionally, the retiming processing performed by the plurality of first retiming units on the plurality of control signals ctrl0~ctrlx respectively includes, for example: obtaining the time difference between the plurality of control signals ctrl0~ctrlx by calculation, so as to adjust the timestamps of each control signal according to these time differences to eliminate the time offset between the plurality of control signals ctrl0~ctrlx, so that the plurality of control signals ctrl0~ctrlx are aligned at the same time point. Or, a timestamp synchronization protocol can also be used to synchronize the plurality of control signals ctrl0~ctrlx by inserting timestamps into the plurality of control signals ctrl0~ctrlx and parsing them. Based on the retiming processing principle, it can be understood that the plurality of control signals output by the plurality of first retiming units are synchronized with each other. In this way, the deviation of data when transmitted from the digital circuit part to the analog circuit part in the multi-channels of the high-speed interface can be eliminated.

[0060] Optionally, in some embodiments, the delay amounts of the output signals of the multiple first retiming units by the multiple delay control units are all equal. In these embodiments, the multiple first synchronization control signals ctrl_sync01 to ctrl_syncx1 output by the synchronization control circuit 200 are synchronized or aligned with each other.

[0061] In other embodiments, the delay amounts of the output signals of the multiple first retiming units by the multiple delay control units are not equal or not completely equal. In these embodiments, the multiple first synchronization control signals ctrl_sync01 to ctrl_syncx1 output by the synchronization control circuit 200 are no longer synchronized.

[0062] That is to say, by simultaneously arranging multiple first retiming units and multiple delay control units in the synchronization control circuit 200 in the embodiments of the present application, the high-speed interface disclosed in the embodiments of the present application can be applied to general application scenarios where the multiple first synchronization control signals ctrl_sync01 to ctrl_syncx1 output to the analog circuit parts in multiple channels need to be completely aligned, and can also be applied to special requirement scenarios of special devices where the multiple first synchronization control signals ctrl_sync01 to ctrl_syncx1 output to the analog circuit parts in multiple channels need not be completely aligned. In the case of realizing cross-clock-domain multi-channel data synchronous transmission, the function is stronger and the compatibility of the high-speed interface can be improved.

[0063] Of course, in some implementation scenarios that only need to ensure that the multiple first synchronization control signals ctrl_sync01 to ctrl_syncx1 are completely aligned, the multiple delay control units in the synchronization control circuit 200 can also be omitted. At this time, the synchronized multiple control signals output by the multiple first retiming units can be directly used as the multiple first synchronization control signals ctrl_sync01 to ctrl_syncx1.

[0064] Alternatively, in some other embodiments, multiple delay control units can also be used to directly perform delay control on multiple control signals ctrl0 to ctrlx to output multiple first synchronization control signals ctrl_sync01 to ctrl_syncx1.

[0065] Further, referring to Figure 4, in some embodiments, the synchronization control circuit 200 further includes: a multiplexer 41 and a second retiming unit 42. Among them, the multiplexer 41 receives multiple control signals ctrl0~ctrlx respectively, and selects one of the multiple control signals ctrl0~ctrlx for output; the second retiming unit 42 is connected to the output end of the multiplexer 41, and is used to perform retiming processing on the output signal of the multiplexer 41, and output multiple second synchronization control signals ctrl_sync02~ctrl_syncx2.

[0066] It can be understood that in this embodiment, the multiplexer 41 can select control signals from any channel through configuration, which improves the flexibility of the device. After the second retiming unit 42 performs retiming on the output signal of the multiplexer 41, control signals for all channels are generated. Through the joint processing of the multiplexer 41 and the second retiming unit 42, the multiple second synchronization control signals ctrl_sync02~ctrl_syncx2 output by the synchronization control circuit 200 to multiple channels can be synchronized with the high-speed clock signal and / or low-speed clock signal required when the corresponding analog circuit part implements serial-to-parallel conversion, so as to eliminate the deviation between the low-speed circuit and the high-speed circuit in the analog circuits of each channel in the multi-channel of the high-speed interface.

[0067] In summary, the embodiment of the present application provides an independent synchronization control circuit in the high-speed interface. By inserting different synchronization control logics at two core nodes introducing multi-channel data deviation (between the digital circuit part and the analog circuit part of each channel, and between the low-speed circuit and the high-speed circuit in the analog circuit part of each channel), the multi-channel data deviation of the high-speed interface is effectively reduced, ensuring the complete synchronization of multi-channel data of the high-speed interface, with less hardware overhead and higher device compatibility.

[0068] Furthermore, the present application also provides a chip, which integrates the high-speed interface disclosed in any embodiment of the present application. By integrating the above high-speed interface in the chip, high-speed data communication between internal functional modules of the chip, or between the chip and external devices or other chips can be determined, and the stability, accuracy, and reliability of data transmission are higher.

[0069] Furthermore, the present application also provides a multi-channel data synchronization method for a high-speed interface, which can be applied to the high-speed interface disclosed in any of the above embodiments of the present application. Specifically, as Figure 5 shown, the multi-channel data synchronization method includes the following steps:

[0070] In step 510, synchronization processing is performed on multiple control signals output by multiple digital circuit parts in multiple channels to generate multiple first synchronization control signals, and each first synchronization control signal is used to control the data transmission process between the digital circuit part and the analog circuit part of the corresponding channel.

[0071] In this step, performing synchronization processing on multiple control signals output by multiple digital circuit parts in multiple channels to generate multiple first synchronization control signals includes: performing retiming processing on the multiple control signals respectively to generate multiple synchronized first synchronization control signals; or, performing retiming processing on the multiple control signals respectively to generate multiple synchronized control signals, and performing delay control on the multiple synchronized control signals respectively to generate multiple first synchronization control signals.

[0072] In step 520, synchronization processing is performed on multiple control signals output by multiple digital circuit parts in multiple channels to generate multiple second synchronization control signals synchronized with the high-speed clock signal and / or the low-speed clock signal in the serial-to-parallel conversion process, and the multiple second synchronization control signals are respectively output to multiple analog circuit parts in multiple channels, and each second synchronization control signal is used to control the serial-to-parallel conversion process of data in the analog circuit of the corresponding channel.

[0073] In this step, performing synchronization processing on multiple control signals output by multiple digital circuit parts in multiple channels to generate multiple second synchronization control signals includes: selecting one of the multiple control signals; performing retiming processing on the selected control signal to generate multiple second synchronization control signals.

[0074] It should be noted that the serial-to-parallel conversion process described herein refers to the data conversion process provided in the analog circuit part of the high-speed interface.

[0075] In specific implementation, the specific implementation of each step in the multi-channel data synchronization method of the high-speed interface described above and the beneficial technical effects that can be achieved after the implementation can be referred to the respective embodiments of the high-speed interface described above, and will not be elaborated here.

[0076] Finally, it should be noted that: Obviously, the above embodiments are only examples for clearly illustrating the present application, rather than limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation manners here. And the obvious changes or modifications derived therefrom are still within the protection scope of the present application.

Claims

1. A high-speed interface, comprising: A plurality of channels, each channel including a corresponding digital circuit part and an analog circuit part; A synchronization control circuit, receiving a plurality of control signals output by a plurality of digital circuit parts in the plurality of channels, synchronizing the plurality of control signals, generating a plurality of first synchronization control signals, and a plurality of second synchronization control signals synchronized with a high-speed clock signal and / or a low-speed clock signal, and respectively outputting the signals to the plurality of analog circuit parts in the plurality of channels, Each first synchronization control signal is used to control the data transmission process between the digital circuit part and the analog circuit part of the corresponding channel, and each second synchronization control signal is used to control the parallel-to-serial conversion process of the data in the analog circuit of the corresponding channel. The high-speed clock signal and the low-speed clock signal are used to implement the parallel-to-serial conversion of the data.

2. The high-speed interface according to claim 1, wherein The synchronization control circuit includes: A plurality of first retiming units, respectively receiving the plurality of control signals, and respectively performing retiming processing on the plurality of control signals, and outputting the synchronized plurality of control signals.

3. The high-speed interface according to claim 2, wherein, The synchronization control circuit further includes: A plurality of delay control units, respectively connected to the plurality of first retiming units, for respectively performing delay control on the output signals of the plurality of first retiming units, and outputting the plurality of first synchronization control signals.

4. The high-speed interface according to claim 3, wherein, The delay amounts of the output signals of the plurality of first retiming units by the plurality of delay control units are all equal.

5. The high-speed interface according to claim 3, wherein, The delay amounts of the output signals of the plurality of first retiming units by the plurality of delay control units are not equal or not completely equal.

6. The high-speed interface according to any one of claims 1-5, wherein, The synchronization control circuit further includes: A multiplexer, respectively receiving the plurality of control signals, and selecting one of the plurality of control signals for output; A second retiming unit, connected to the output end of the multiplexer, for performing retiming processing on the output signal of the multiplexer, and outputting the plurality of second synchronization control signals.

7. The high-speed interface according to claim 1, wherein, Each channel terminal analog circuit part includes: A clock port, for outputting a clock signal to the corresponding digital circuit part; A data port, for receiving a data signal output by the corresponding digital circuit part; A first synchronization control port, for receiving the corresponding first synchronization control signal; A second synchronization control port, for receiving the corresponding second synchronization control signal; A differential output port, for implementing signal communication with an external device.

8. A chip, comprising: The high-speed interface according to any one of claims 1-7.

9. A multi-channel data synchronization method for a high-speed interface, the high-speed interface including a plurality of channels, each channel including a corresponding digital circuit part and an analog circuit part, The multi-channel data synchronization method includes: Synchronizing a plurality of control signals output by a plurality of digital circuit parts in the plurality of channels, generating a plurality of first synchronization control signals, and each first synchronization control signal is used to control the data transmission process between the digital circuit part and the analog circuit part of the corresponding channel; Synchronize the multiple control signals output by the multiple digital circuit parts in the multiple channels to generate multiple second synchronization control signals synchronized with the high-speed clock signal and / or the low-speed clock signal in the serial-to-parallel conversion, and output them to the multiple analog circuit parts in the multiple channels respectively. Each second synchronization control signal is used to control the serial-to-parallel conversion process of data in the analog circuit of the corresponding channel.

10. The multi-channel data synchronization method according to claim 9, wherein, Synchronizing the multiple control signals output by the multiple digital circuit parts in the multiple channels to generate multiple first synchronization control signals includes: Performing retiming processing on the multiple control signals respectively to generate multiple synchronized first synchronization control signals; Alternatively, performing retiming processing on the multiple control signals respectively to generate multiple synchronized control signals, and performing delay control on the multiple synchronized control signals respectively to generate the multiple first synchronization control signals.

11. The multi-channel data synchronization method according to claim 9, wherein, Synchronizing the multiple control signals output by the multiple digital circuit parts in the multiple channels to generate multiple second synchronization control signals includes: Select one of the multiple control signals; Performing retiming processing on the selected control signal to generate the multiple second synchronization control signals.

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