Gate driver and display device including the same

Abstract

The invention discloses a gate driver and a display device including the same. The gate driver includes: a level shifter that outputs a first mode gate clock in a normal scan rate mode and outputs a second mode gate clock in a high scan rate mode; and a gate shift register outputting a normal scan rate scan signal synchronized with the first mode gate clock in a normal scan rate mode, and outputting a high scan rate scan signal synchronized with the second mode gate clock in a high scan rate mode. Adjacent gate clocks among the first mode gate clocks have a delay difference equal to one horizontal period, and the second mode gate clocks include first to fourth gate clocks whose phases are sequentially shifted. The first and third gate clocks have a delay difference equal to one horizontal period, the first and second gate clocks have a delay difference equal to a time less than one horizontal period, and the third and fourth gate clocks have a delay difference equal to a time less than one horizontal period.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10 - 2024 - 0003435, filed on January 9, 2024, which is hereby incorporated by reference as if fully set forth herein. Technical field

[0003] The present disclosure relates to a gate driver and a display device including the gate driver. Background art

[0004] A display device includes a gate driver for driving gate lines of a display panel.

[0005] Recently, gate drivers are designed to selectively implement a normal scan rate mode and a high scan rate mode. The gate driver can provide a scan signal shifted by one row unit to the gate lines to implement the normal scan rate, and can provide a scan signal shifted by two - row units to the gate lines to implement the high scan rate.

[0006] In the high scan rate mode, a pair of scan signals having the same phase are provided to two adjacent gate lines. That is, pairs of gate lines are sequentially scanned by pairs of scan signals whose phases are sequentially shifted. Compared with the normal scan rate mode, in the high scan rate mode, the frame time is reduced by half.

[0007] In the high scan rate mode, the gate driver outputs a pair of scan signals having the same phase based on a pair of gate clocks having the same phase. The magnitude of the ripple occurring in the control nodes of the gate driver can increase synchronously with the rising or falling edge of the pair of gate clocks having the same phase. In the high scan rate mode, compared with the normal scan rate mode, the magnitude of the ripple occurring in the control nodes of the gate driver increases by about two times. When the magnitude of the ripple increases, the operation of the gate driver is unstable. Summary of the invention

[0008] To overcome the above problems of the related art, the present disclosure can provide the following gate driver and a display device including the gate driver: which can reduce the magnitude of the ripple occurring in the high scan rate mode to a level corresponding to the normal scan rate mode.

[0009] To achieve these objects and other advantages and in accordance with the purpose of the present disclosure, as embodied and broadly described herein, a gate driver includes: a level shifter configured to output a first-mode gate clock in a normal scan rate mode and a second-mode gate clock in a high scan rate mode having a scan rate greater than the normal scan rate mode; and a gate shift register configured to output a normal scan rate scan signal synchronized with the first-mode gate clock in the normal scan rate mode and a high scan rate scan signal synchronized with the second-mode gate clock in the high scan rate mode. Adjacent gate clocks in the first-mode gate clock have a delay difference equal to one horizontal period. The second-mode gate clock includes a first gate clock to a fourth gate clock whose phases are sequentially shifted. The first gate clock and the third gate clock have a delay difference equal to one horizontal period. The first gate clock and the second gate clock have a delay difference equal to a time less than one horizontal period. The third gate clock and the fourth gate clock have a delay difference equal to a time less than one horizontal period. Description of the Drawings

[0010] The drawings are included to provide a further understanding of the present disclosure and are incorporated into and constitute a part of this application. The drawings illustrate embodiments of the present disclosure and, together with the description, are used to explain the principles of the present disclosure. In the drawings:

[0011] Figure 1 is a diagram showing a display device according to the present embodiment;

[0012] Figure 2 schematically shows Figure 1 the pixel shown;

[0013] Figure 3 is a diagram showing a connection configuration between a timing controller and a gate driver in a display device according to the present embodiment;

[0014] Figure 4 is a diagram showing an example of selectively performing a normal scan rate mode and a high scan rate mode based on a mode control signal;

[0015] Figure 5 is a diagram schematically showing a stage configuration included in a gate shift register;

[0016] Figure 6 is a diagram showing an example of implementing a screen with a first resolution in the normal scan rate mode and a screen with a second resolution in the high scan rate mode;

[0017] Figures 7 to 10 is a diagram describing the operation of a panel driver for implementing a screen with a first resolution in the normal scan rate mode; and

[0018] Figures 11 to 19 It is a diagram depicting the operation of a panel driver for implementing a screen with a second resolution in a high scan rate mode. Detailed Description

[0019] Hereinafter, the present disclosure will be described more fully with reference to the drawings showing exemplary embodiments of the present disclosure. However, the present disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the present disclosure to those skilled in the art.

[0020] The display device according to the present disclosure can be applied to a television (TV), a video player, a personal computer (PC), a home theater, vehicle electronic devices, and a smart phone, but is not limited thereto. The display device according to the present disclosure can be implemented as a light-emitting display device, a quantum dot display (QDD) device, or a liquid crystal display (LCD) device. Hereinafter, for ease of description, a light-emitting display device based on an inorganic light-emitting diode or an organic light-emitting diode will be described, for example.

[0021] In addition, examples in which the light-emitting display device described below includes an n-type or p-type transistor will be described, but the light-emitting display device can be implemented as a type in which an n-type transistor and a p-type transistor are jointly provided. The transistor can be a three-electrode element including a gate, a source, and a drain. The source and the drain of the transistor can be switched based on an applied voltage. Based on this, in the following description, examples in which one of the source and the drain is a first electrode and the other of the source and the drain is a second electrode will be described.

[0022] Figure 1 It is a diagram showing the display device according to the present embodiment. Figure 2 It schematically shows Figure 1 the pixels shown.

[0023] As Figure 1 and Figure 2 shown, the display device according to the present embodiment may include a host system 110, a timing controller 120, a gate driver 130, a data driver 140, a display panel 150, and a power supply circuit 180. Depending on the implementation type of the display device, one or more of the timing controller 120, the gate driver 130, and the data driver 140 may be integrated into a single integrated circuit (IC).

[0024] The host system 110 may provide a synchronous timing signal and video data to the timing controller 120. The host system 110 is one of a television (TV), a set-top box, a navigation system, a personal computer (PC), a home theater, an in-vehicle display system, a mobile device, and a wearable device.

[0025] The timing controller 120 may output a gate timing control signal GDC for controlling the operation timing of the gate driver 130 and a data timing control signal DDC for controlling the operation timing of the data driver 140 based on the synchronous timing signal. The timing controller 120 may provide image data DATA and the data timing control signal DDC to the data driver 140. The timing controller 120 may be formed in an IC type and may be mounted on a printed circuit board (PCB), but is not limited thereto.

[0026] The gate driver 130 may output a scan signal based on the gate timing control signal GDC provided from the timing controller 120. The gate driver 130 may provide the scan signal to pixels PIX of the display panel 150 through a plurality of gate lines GL1 to GLm. The gate driver 130 may be formed in an IC type or may be directly formed in an in-panel gate (GIP) type on the display panel 150, but is not limited thereto.

[0027] The data driver 140 may sample and latch the image data DATA based on the data timing control signal DDC provided from the timing controller 120, and may map the latched data to a gamma compensation voltage to generate an analog data voltage. The data driver 140 may provide the data voltage to pixels PIX of the display panel 150 through a plurality of data lines DL1 to DLn. The data driver 140 may be formed in an IC type and may be bonded to or mounted on the PCB, but is not limited thereto.

[0028] The power circuit 180 may generate a high-level first panel power EVDD and a low-level second panel power EVSS based on a direct current (DC) input voltage provided from the outside. The power circuit 180 may also generate a gate high voltage VGH and a gate low voltage VGL required to drive the gate driver 130, and a source voltage required to drive the data driver 140.

[0029] The display panel 150 may include a screen for displaying an input image. The screen may be configured with a pixel array. The pixel array may include a plurality of data lines DL1 to DLn, a plurality of gate lines GL1 to GLm intersecting the data lines DL1 to DLn, and a plurality of pixels PIX.

[0030] Pixels PIX can be arranged on screen AA in a matrix type defined by data lines DL1 to DLn and gate lines GL1 to GLm. Pixels PIX can be arranged on the screen in various types, such as stripe type, diamond type, and matrix type.

[0031] The pixel array can include a plurality of pixel columns and a plurality of pixel rows intersecting the pixel columns. Each of the pixel columns can include pixels PIX arranged in the Y-axis direction. The pixel rows can include pixels PIX arranged in the X-axis direction. One vertical period can be the time for one frame required to write image data DATA of one frame to all pixels PIX of the screen. One horizontal period can be the time obtained by dividing one frame period by the number of pixel rows L1 to Ln. One horizontal period can be the time required to write image data DATA of one pixel row sharing gate line GL to the pixels PIX of one pixel row.

[0032] Pixels PIX can include red (R) pixels, green (G) pixels, blue (B) pixels, and white (W) pixels for color implementation. Each of the pixels PIX can include a pixel circuit, which includes a light-emitting device, a driving element, a switching element, and a capacitor. Each of the driving element and the switching element can be implemented as a thin-film transistor (TFT). The TFT can be implemented as a P-type, an N-type, or a hybrid type in which P-type and N-type are jointly provided. In addition, the semiconductor layer of each TFT can include amorphous silicon, polysilicon, or oxide.

[0033] Figure 3 is a schematic diagram showing the connection configuration between the timing controller and the gate driver in the display device according to the present embodiment. Figure 4 is a diagram showing an example of selectively executing the normal scan rate mode and the high scan rate mode based on the mode control signal. Figure 5 is a diagram schematically showing the configuration of one stage included in the gate shift register.

[0034] Referring to Figure 3 , the gate driver 130 can include a level shifter 135 and a gate shift register 131.

[0035] The level shifter 135 can generate a gate clock GCLK based on the gate timing control signal GDC (i.e., start signal VST, on clock (On CLK), and off clock (Off CLK)) input from the timing controller 120 and the gate high voltage VGH and the gate low voltage VGL both input from the power supply circuit 180.

[0036] As Figure 4As shown, the level shifter 135 can generate a first mode gate clock GCLK_MOD1 and a second mode gate clock GCLK_MOD2 for implementing a scan rate mode based on a mode control signal CMOD input from the timing controller 120, and output them to the gate shift register 131.

[0037] The level shifter 135 can output the first mode gate clock GCLK_MOD1 to the gate shift register 131 in response to a mode control signal CMOD of a first logic voltage H. The first mode gate clock GCLK_MOD1 can be used to implement a normal scan rate mode MODE1. In the first mode gate clock GCLK_MOD1, adjacent gate clocks can have a delay difference equal to one horizontal period.

[0038] The level shifter 135 can output the second mode gate clock GCLK_MOD2 to the gate shift register 131 in response to a mode control signal CMOD of a second logic voltage L. The second mode gate clock GCLK_MOD2 can be used to implement a high scan rate mode MODE2. In the second mode gate clock GCLK_MOD2, some adjacent gate clocks can have a delay difference equal to one horizontal period, while other adjacent gate clocks can have a delay difference equal to a specific time ΔT. Here, ΔT can be a time much shorter than one horizontal period.

[0039] The level shifter 135 can provide the first mode gate clock GCLK_MOD1 to the gate shift register 131 through a plurality of clock lines in the normal scan rate mode MODE1, and can provide the second mode gate clock GCLK_MOD2 to the gate shift register 131 through a clock line in the high scan rate mode MODE2.

[0040] The level shifter 135 can also output a start signal VST to the gate shift register 131 through a start line in both the normal scan rate mode MODE1 and the high scan rate mode MODE2.

[0041] The gate shift register 131 can generate a normal scan rate scan signal SCAN synchronized with the first mode gate clock GCLK_MOD1 in the normal scan rate mode MODE1 and output it to the gate line.

[0042] The gate shift register 131 can generate a high scan rate scan signal SCAN synchronized with the second mode gate clock GCLK_MOD2 in the high scan rate mode MODE2 and output it to the gate line.

[0043] The gate shift register 131 may include a plurality of gate stages STG1 to STG(m / 4) connected independently of each other. To reduce the circuit area occupied by the gate shift register 131, the gate shift register 131 may be designed such that m / 4 gate stages drive m gate lines.

[0044] For this purpose, as Figure 5 shown in the figure, one-stage STG1 according to the present embodiment may include four output nodes OP1 to OP4, and may output four scan signals SCAN1 to SCAN4 through the output nodes OP1 to OP4.

[0045] One-stage STG1 according to the present embodiment may include a first output circuit connected to the first output node OP1, a second output circuit connected to the second output node OP2, a third output circuit connected to the third output node OP3, and a fourth output circuit connected to the fourth output node OP4. One-stage STG1 according to the present embodiment may include a node control circuit NC for controlling the operations of the first output circuit to the fourth output circuit. A start signal VST, a high-level driving voltage GVDD, and a low-level driving voltage GVSS may be provided to the node control circuit NC.

[0046] The first output circuit to the fourth output circuit may share a first control node Q and a second control node QB of the node control circuit NC. When the voltage of the first control node Q is maintained at an effective level, the voltage of the second control node QB may be maintained at an ineffective level. In addition, when the voltage of the first control node Q is maintained at an ineffective level, the voltage of the second control node QB may be maintained at an effective level.

[0047] The gate electrodes of the first pull-up transistors PU1 to the fourth pull-up transistors PU4 included in the first output circuit to the fourth output circuit may be commonly connected to the first control node Q. When the voltage of the first control node Q is at an effective level, the first gate clock SCLK1 to the fourth gate clock SCLK4 may be applied to the first output node OP1 to the fourth output node OP4 through the first pull-up transistors PU1 to the fourth pull-up transistors PU4. Therefore, the first scan signal SCAN1 to the fourth scan signal SCAN4 output from the first output node OP1 to the fourth output node OP4 may be synchronized with the first gate clock SCLK1 to the fourth gate clock SCLK4.

[0048] The first gate clock SCLK1 to the fourth gate clock SCLK4 may be a first-mode gate clock GCLK_MOD1 in a normal scan rate mode MODE1, and may be a second-mode gate clock GCLK_MOD2 in a high scan rate mode MODE2.

[0049] The gate electrodes of the first to fourth pull-down transistors PD1 to PD4 included in the first to fourth output circuits may be commonly connected to the second control node QB. When the voltage of the second control node QB has an effective level, the low-level driving voltage GVSS may be applied to the first to fourth output nodes OP1 to OP4 through the first to fourth pull-down transistors PD1 to PD4.

[0050] Figure 6 is a diagram showing the following example: implementing a screen with a first resolution in a normal scan rate mode and implementing a screen with a second resolution in a high scan rate mode.

[0051] Referring to Figure 6 , a screen with a first resolution of UHD can be implemented in the normal scan rate mode MODE1, and a screen with a second resolution of FHD can be implemented in the high scan rate mode MODE2. In the high scan rate mode MODE2, sequential scanning can be performed on two gate lines in the same gate line pair with a time difference △T much shorter than one horizontal period. Therefore, compared with the normal scan rate mode, each of the horizontal resolution and the vertical resolution of the screen can be reduced by half.

[0052] In the normal scan rate mode MODE1, a screen with a first resolution of UHD can be implemented by a normal scan rate scanning signal. The normal scan rate scanning signal may be synchronized with the first mode gate clock GCLK_MOD1. "DLG: OFF" can be implemented by the first mode gate clock GCLK_MOD1. "DLG: OFF" may indicate that the resolution reduction function is deactivated. In the normal scan rate mode MODE1, the input image data can be displayed on the screen without omission.

[0053] In the high scan rate mode MODE2, a screen with a second resolution of FHD can be implemented by a high scan rate scanning signal. The high scan rate scanning signal may be synchronized with the second mode gate clock GCLK_MOD2. "DLG: ON" can be implemented by the second mode gate clock GCLK_MOD2. "DLG: ON" may indicate that the resolution reduction function is activated. In the high scan rate mode MODE2, the input image data can be displayed on the screen in a state where a part of the input image data is omitted.

[0054] Figures 7 to 10 is a diagram describing the operation of a panel driver for implementing a screen with a first resolution in a normal scan rate mode.

[0055] Referring to Figures 7 to 10, in the normal scan rate mode MODE1, the gate driver can respectively provide the first normal scan rate scan signal SCAN1 to the m-th normal scan rate scan signal SCANm with a delay difference equal to one horizontal period 1HT to the first gate line to the m-th gate line, so as to realize the screen of the first resolution UHD.

[0056] In this case, the data driver can synchronize the input image data with the first normal scan rate scan signal SCAN1 to the m-th normal scan rate scan signal SCANm and output it to the data line without reduction.

[0057] That is to say, the data driver can output the first data voltage D1 during the first horizontal period H1 overlapping with the first normal scan rate scan signal SCAN1, output the second data voltage D2 during the second horizontal period H2 overlapping with the second normal scan rate scan signal SCAN2, output the third data voltage D3 during the third horizontal period H3 overlapping with the third normal scan rate scan signal SCAN3, and output the fourth data voltage D4 during the fourth horizontal period H4 overlapping with the fourth normal scan rate scan signal SCAN4. In this way, the data driver can output the m-th data voltage Dm during the m-th horizontal period Hm overlapping with the m-th normal scan rate scan signal SCANm.

[0058] Therefore, during one vertical period (one frame period), the first data voltage D1 to the m-th data voltage Dm can be sequentially provided to all pixel lines of the display panel, so that the screen of the first resolution UHD can be completed.

[0059] In the normal scan rate mode MODE1, the first normal scan rate scan signal SCAN1 to the fourth normal scan rate scan signal SCAN4 can be synchronized with the first mode gate clock GCLK_MOD1. That is to say, in one stage, the first mode gate clock GCLK_MOD1 can be output to the first normal scan rate scan signal SCAN1 to the fourth normal scan rate scan signal SCAN4.

[0060] As Figure 10As shown, the first mode gate clock GCLK_MOD1 can be implemented using first to fourth gate clocks SCLK1 to SCLK4 having a delay difference equal to one horizontal period 1HT between adjacent gate clocks. That is, the rising edges RE of the first mode gate clock GCLK_MOD1 can be distributed in time with a delay difference equal to one horizontal period 1HT. Similarly, the falling edges FE of the first mode gate clock GCLK_MOD1 can also be distributed in time with a delay difference equal to one horizontal period 1HT. Therefore, at the timing where the rising edge RE and the falling edge FE of the first mode gate clock GCLK_MOD1 are synchronized with each other, the magnitude of the ripple appearing in the first control node ( Figure 5 's Q) can be small.

[0061] Figures 11 to 19 is a diagram illustrating the operation of a panel driver for implementing a screen with a second resolution in a high scan rate mode.

[0062] Referring to Figure 11 , in order to implement a screen with a second resolution FHD in the high scan rate mode MODE2, compared with normal, the gate driver can reduce a vertical period (corresponding to the vertical resolution) by approximately half based on the second mode gate clock GCLK_MOD2, and compared with normal, the data driver can reduce the input image data to reduce the horizontal resolution by approximately half.

[0063] In the high scan rate mode MODE2, compared with normal, the vertical resolution of the screen can be reduced by y, and compared with normal, the horizontal resolution of the screen can be reduced by x. The second resolution FHD can be approximately 1 / 4 of the first resolution UHD (width 1 / 2 * length 1 / 2).

[0064] The first scan control concept and the second scan control concept can be considered to reduce a vertical period in the high scan rate mode MODE2. The first scan control concept is shown in Figures 12 to 14 , and the second scan control concept is shown in Figures 15 to 17 .

[0065] As Figures 12 to 14 shown, the first scan control concept can configure gate line pairs each including two gate lines, and can sequentially scan the gate line pairs having a delay difference equal to one horizontal period 1HT. For example, two gate lines in the same gate line pair can be scanned simultaneously. For example, the first high scan rate scan signal SCAN1 and the second high scan rate scan signal SCAN2 respectively provided to the first gate line and the second gate line can be synchronized with each other, and the third high scan rate scan signal SCAN3 and the fourth high scan rate scan signal SCAN4 respectively provided to the third gate line and the fourth gate line can be synchronized with each other.

[0066] A second-mode gate clock GCLK_MOD2 may be required to implement the first scan control concept as Figure 14 shown. The second-mode gate clock GCLK_MOD2 may include a first gate clock SCLK1 and a second gate clock SCLK2 having the same phase, and a third gate clock SCLK3 and a fourth gate clock SCLK4 having the same phase. In this case, the phases of the third gate clock SCLK3 and the fourth gate clock SCLK4 may be one horizontal period 1HT later than the phases of the first gate clock SCLK1 and the second gate clock SCLK2.

[0067] In the second-mode gate clock GCLK_MOD2 for implementing the first scan control concept, as Figure 14 shown, the rising edges RE may be concentrated two by two at the same timing. In addition, the falling edges FE may be concentrated two by two at the same timing. Therefore, there may be a drawback that the magnitude of the ripple appearing in the first control node ( Figure 5 Q) increases at the timing when the rising edge RE and the falling edge FE of the second-mode gate clock GCLK_MOD2 are synchronized with each other.

[0068] The second scan control concept may be used to compensate for the drawbacks of the first scan control concept.

[0069] As Figures 15 to 17 shown, the second scan control concept may configure gate line pairs each including two gate lines, and may sequentially scan the gate line pairs having a delay difference equal to one horizontal period 1HT. And for example, it may sequentially scan two gate lines in the same gate line pair having a time difference △T much shorter than one horizontal period 1HT. For example, the first high scan rate scan signal SCAN1 and the second high scan rate scan signal SCAN2 respectively provided to the first gate line and the second gate line may have a time difference △T, and the third high scan rate scan signal SCAN3 and the fourth high scan rate scan signal SCAN4 respectively provided to the third gate line and the fourth gate line may have a time difference △T.

[0070] A second-mode gate clock GCLK_MOD2 may be required to implement the concepts as Figure 15 and Figure 16The second scan control concept shown. The second mode gate clock GCLK_MOD2 may include a first gate clock SCLK1 to a fourth gate clock SCLK4 whose phases are sequentially shifted. The first gate clock SCLK1 and the third gate clock SCLK3 may have a delay difference equal to one horizontal period 1HT. The first gate clock SCLK1 and the second gate clock SCLK2 may have a delay difference equal to a time ΔT smaller than one horizontal period 1HT. The third gate clock SCLK3 and the fourth gate clock SCLK4 may have a delay difference equal to the time ΔT less than one horizontal period.

[0071] In the second mode gate clock GCLK_MOD2 for implementing the second scan control concept, as Figure 15 and Figure 16 shown, the rising edge RE and the falling edge FE may be distributed in time. Therefore, the magnitude of the ripple that appears in the high scan rate mode MODE2 can be reduced to a level corresponding to the normal scan rate mode MODE1.

[0072] In the high scan rate mode MODE2, a first pixel and a second pixel that are connected to the same data line and are adjacent to each other may be charged with the same image data voltage. According to the first scan control concept, it is possible to ensure that the charging time of the first pixel and the charging time of the second pixel are equal to each other. However, according to the second scan control concept, the charging time of the first pixel and the charging time of the second pixel may be different.

[0073] That is to say, in the second mode gate clock GCLK_MOD2 as Figure 15 shown, the charging time of the second pixel may be shorter than Figure 17 that of the first pixel. On the other hand, in the second mode gate clock GCLK_MOD2 as Figure 16 shown, the charging time of the second pixel may be longer than Figure 17 that of the first pixel.

[0074] In order to prevent image quality defects caused by charging time deviations between adjacent pixels from being recognized, this embodiment may assign the second mode gate clock GCLK_MOD2 as Figure 15 shown to odd frames and assign the second mode gate clock GCLK_MOD2 as Figure 16 shown to even frames. Therefore, alternate driving can be implemented as Figure 17 in.

[0075] Refer to Figure 15, in the second-mode gate clock GCLK_MOD2 of odd frames assigned to the high scan rate mode MODE2, the rising edge RE of the third gate clock SCLK3 can be one horizontal period 1HT later in phase than the rising edge RE of the first gate clock SCLK1, the rising edge RE of the second gate clock SCLK2 can be a time ΔT (which can be less than one horizontal period 1HT) later in phase than the rising edge RE of the first gate clock SCLK1, and the rising edge RE of the fourth gate clock SCLK4 can be a time ΔT (which can be less than one horizontal period 1HT) later in phase than the rising edge RE of the third gate clock SCLK3.

[0076] Refer to Figure 16 , in the second-mode gate clock GCLK_MOD2 of even frames assigned to the high scan rate mode MODE2, the rising edge RE of the third gate clock SCLK3 can be one horizontal period 1HT later in phase than the rising edge RE of the first gate clock SCLK1, the rising edge RE of the second gate clock SCLK2 can be a time ΔT (which can be less than one horizontal period 1HT) earlier in phase than the rising edge RE of the first gate clock SCLK1, and the rising edge RE of the fourth gate clock SCLK4 can be a time ΔT (which can be less than one horizontal period 1HT) earlier in phase than the rising edge RE of the third gate clock SCLK3.

[0077] Figure 18 and Figure 19 shows a modified example of the second scan control concept implemented in the high scan rate mode MODE2.

[0078] Refer to Figure 18 and Figure 19 , each of the second-mode gate clocks GCLK_MOD2 implemented in the high scan rate mode MODE2 can include at least one inflection point among the rising edge and the falling edge. Based on the gate clock modulation, the magnitude of the ripple occurring in the high scan rate mode MODE2 can be further reduced to less than or equal to the level corresponding to the normal scan rate mode MODE1.

[0079] Figure 18 and Figure 19 The implementation manners of Figures 15 to 17 can include the alternate driving scheme and effects of the second scan control concept described above with reference to

[0080] This implementation manner can reduce the magnitude of the ripple occurring in the high scan rate mode to the level corresponding to the normal scan rate mode, so the operation of the gate driver can be stabilized and the image quality can be improved.

[0081] The effects according to the present disclosure are not limited to the above examples, and various other effects may be included in the specification.

[0082] Although the present disclosure has been specifically shown and described with reference to exemplary embodiments thereof, those of ordinary skill in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. A gate driver, comprising: A level shifter configured to output a first-mode gate clock in a normal scan rate mode and a second-mode gate clock in a high scan rate mode, the high scan rate mode having a scan rate greater than that of the normal scan rate mode; And A gate shift register configured to output a normal scan rate scan signal synchronized with the first-mode gate clock in the normal scan rate mode and a high scan rate scan signal synchronized with the second-mode gate clock in the high scan rate mode, Wherein, adjacent gate clocks in the first-mode gate clock have a delay difference equal to one horizontal period, The second-mode gate clock includes a first gate clock to a fourth gate clock whose phases are sequentially shifted, and The first gate clock and the third gate clock have a delay difference equal to the one horizontal period, the first gate clock and the second gate clock have a delay difference equal to a time less than the one horizontal period, and the third gate clock and the fourth gate clock have a delay difference equal to a time less than the one horizontal period.

2. The gate driver according to claim 1, wherein, In odd frames of the high scan rate mode, Compared with the rising edge of the first gate clock, the rising edge of the third gate clock is delayed by the one horizontal period in phase, Compared with the rising edge of the first gate clock, the rising edge of the second gate clock is delayed by a time less than the one horizontal period in phase, and Compared with the rising edge of the third gate clock, the rising edge of the fourth gate clock is delayed by a time less than the one horizontal period in phase.

3. The gate driver according to claim 1, wherein In even frames of the high scan rate mode, Compared with the rising edge of the first gate clock, the rising edge of the third gate clock is delayed by the one horizontal period in phase, Compared with the rising edge of the first gate clock, the rising edge of the second gate clock is advanced by a time less than the one horizontal period in phase, and Compared with the rising edge of the third gate clock, the rising edge of the fourth gate clock is advanced by a time less than the one horizontal period in phase.

4. The gate driver according to claim 1, wherein, Each of the first gate clock to the fourth gate clock includes at least one inflection point in its rising edge and falling edge.

5. The gate driver according to claim 4, wherein, In odd frames of the high scan rate mode, Compared with the rising edge of the first gate clock, the rising edge of the third gate clock is delayed by the one horizontal period in phase, Compared with the rising edge of the first gate clock, the rising edge of the second gate clock is delayed by a time less than the one horizontal period in phase, and Compared with the rising edge of the third gate clock, the rising edge of the fourth gate clock is delayed by a time less than the one horizontal period in phase.

6. The gate driver according to claim 4, wherein, In even frames of the high scan rate mode, Compared with the rising edge of the first gate clock, the rising edge of the third gate clock is delayed by the one horizontal period in phase, Compared with the rising edge of the first gate clock, the rising edge of the second gate clock is advanced by a time less than the one horizontal period in phase, and Compared with the rising edge of the third gate clock, the rising edge of the fourth gate clock is advanced in phase by a time less than the one horizontal period.

7. A display device, comprising: A display panel, which includes a plurality of pixels, a plurality of gate lines connected to the plurality of pixels, and a plurality of data lines connected to the plurality of pixels; A gate driver configured to drive the plurality of gate lines; And A data driver configured to drive the plurality of data lines, Wherein, the gate driver includes: A level shifter configured to: output a first-mode gate clock in a normal scanning rate mode and output a second-mode gate clock in a high scanning rate mode, the high scanning rate mode having a scanning rate larger than that of the normal scanning rate mode; and A gate shift register configured to: output a normal scanning rate scanning signal synchronized with the first-mode gate clock to the plurality of gate lines in the normal scanning rate mode and output a high scanning rate scanning signal synchronized with the second-mode gate clock to the plurality of gate lines in the high scanning rate mode, Adjacent gate clocks in the first-mode gate clock have a delay difference equal to one horizontal period, The second-mode gate clock includes a first gate clock to a fourth gate clock whose phases are sequentially shifted, and The first gate clock and the third gate clock have a delay difference equal to the one horizontal period, the first gate clock and the second gate clock have a delay difference equal to a time less than the one horizontal period, and the third gate clock and the fourth gate clock have a delay difference equal to a time less than the one horizontal period.

8. The display device according to claim 7, wherein, In the normal scanning rate mode, the data driver synchronizes the voltage of the image data corresponding to the first resolution with the normal scanning rate scanning signal to output to the plurality of data lines, and In the high scanning rate mode, the data driver synchronizes the voltage of the image data corresponding to the second resolution with the high scanning rate scanning signal to output to the plurality of data lines, wherein the second resolution is less than the first resolution.

9. The display device according to claim 8, wherein, In the high scanning rate mode, a first pixel and a second pixel that are connected to the same data line and are adjacent to each other are charged with the same image data voltage.

10. The display device according to claim 9, wherein, In odd frames of the high scanning rate mode, the data charging time of the first pixel is longer than that of the second pixel, and In even frames of the high scanning rate mode, the data charging time of the first pixel is shorter than that of the second pixel.

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