Display substrate and display device

Abstract

The invention discloses a display substrate and a display device. The problem of uneven display of the display substrate can be solved. The display substrate comprises a substrate, the substrate comprises a plurality of pixel circuit areas, and the pixel circuit areas are provided with pixel circuits and auxiliary structures; the pixel circuit comprises a driving transistor and a bypass transistor, a first electrode of the driving transistor is used for being electrically connected with a light-emitting device, and a first electrode of the bypass transistor is electrically connected with a first electrode of the driving transistor through a first connecting structure; the orthographic projection of the auxiliary structure on the substrate is not overlapped with the orthographic projection of the first connecting structure, the first electrode of the driving transistor and the first electrode of the bypass transistor on the substrate; a first insulating layer is arranged between the first connecting structure and the substrate, the orthographic projection of the first insulating layer on the substrate covers the orthographic projections of the first connecting structure and the auxiliary structure on the substrate, and the light reflectivity of the surface of the side, away from the substrate, of the auxiliary structure is larger than that of the surface of the side, away from the substrate, of the first insulating layer.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and particularly to a display substrate and a display device. Background Art

[0002] Currently, with the continuous development of display technologies, the consumer market has increasingly higher requirements for the performance of display products. Generally, a display substrate is provided with a plurality of pixels, and the display of the pixels is realized by driving with a pixel circuit. The pixel circuit includes a plurality of thin-film devices, and different thin-film devices are interconnected by metal wires. However, due to the differences in the thin-film structure environment around the metal wires in different pixel regions, the reflection effects of the metal wires on light are different, which easily causes uneven display on the display substrate and affects the display effect. Summary of the Invention

[0003] Embodiments of the present disclosure provide a display substrate and a display device, which can improve the problem of uneven display on the display substrate and further improve the display effect of the display substrate.

[0004] The first aspect of the present disclosure provides a display substrate, including:

[0005] A substrate, the substrate includes a plurality of pixel circuit regions, and pixel circuits and auxiliary structures are provided in the pixel circuit regions;

[0006] The pixel circuit includes a driving transistor and a bypass transistor. A first electrode of the driving transistor is used for electrically connecting to a light-emitting device. A first electrode of the bypass transistor is electrically connected to the first electrode of the driving transistor through a first connection structure. The first electrode of the transistor is one of a source electrode and a drain electrode;

[0007] The orthographic projection of the auxiliary structure on the substrate does not overlap with the orthographic projections of the first connection structure, the first electrode of the driving transistor, and the first electrode of the bypass transistor on the substrate;

[0008] A first insulating layer is provided between the first connection structure and the substrate. The orthographic projection of the first insulating layer on the substrate covers the orthographic projections of the first connection structure and the auxiliary structure on the substrate. The light reflectivity of the surface of the auxiliary structure facing away from the substrate is greater than the light reflectivity of the surface of the first insulating layer facing away from the substrate.

[0009] In some embodiments, the auxiliary structure is located on a side of the first connection structure away from the gate of the bypass transistor.

[0010] In some embodiments, the display substrate further includes:

[0011] A conductive layer, the auxiliary structure and the first connection structure are provided on the same conductive layer, or,

[0012] The auxiliary structure is disposed on the same layer as the gate of the bypass transistor.

[0013] In some embodiments, the display substrate further includes:

[0014] A gate layer, a first conductive layer, and a second conductive layer, the first conductive layer is disposed between the substrate and the second conductive layer, the gate layer is disposed between the first conductive layer and the substrate, and the gate of the transistor is disposed on the gate layer;

[0015] The auxiliary structure is disposed on the first conductive layer, and the first connection structure is disposed on the second conductive layer; and / or,

[0016] The auxiliary structure is disposed on the second conductive layer, and the first connection structure is disposed on the first conductive layer.

[0017] In some embodiments, the gate of the bypass transistor is electrically connected to the second connection structure, and the second connection structure is disposed on the conductive layer;

[0018] The second connection structure and the auxiliary structure are respectively located on two sides of the first connection structure in a first direction, the first direction intersects with a second direction, and the second direction is the direction from the first electrode of the bypass transistor to the first electrode of the driving transistor.

[0019] In some embodiments, in the second direction, the two ends of the auxiliary structure are respectively a first end and a second end, the two ends of the second connection structure are respectively a third end and a fourth end, the first end and the third end are located on the same side, and the second end and the fourth end are located on the same side;

[0020] The first end and the third end are flush in the first direction, and / or the second end and the fourth end are flush in the first direction; and / or,

[0021] The size of the auxiliary structure in the second direction is the same as the size of the second connection structure in the second direction; and / or,

[0022] In some embodiments, in the second direction, the two ends of the auxiliary structure are respectively a first end and a second end, the two ends of the second connection structure are respectively a third end and a fourth end, the first end and the third end are located on the same side, and the second end and the fourth end are located on the same side;

[0023] The sizes of the auxiliary structure and the second connection structure in the second direction are both smaller than the size of the first connection structure in the second direction; and / or,

[0024] The size of the auxiliary structure in the first direction is greater than or equal to the size of the first connection structure in the first direction; and / or

[0025] The size of the second connection structure in the first direction is greater than or equal to the size of the first connection structure in the first direction.

[0026] In some embodiments, along the first direction, the perpendicular distance between the auxiliary structure and the first connection structure is a first distance, and the perpendicular distance between the second connection structure and the first connection structure is a second distance;

[0027] The first distance is the same as the second distance, and / or, the values of the first distance in different pixel circuit regions are the same, and / or, the values of the second distance in different pixel circuit regions are the same.

[0028] In some embodiments, the orthographic projection of the first connection structure on the substrate covers the median line of the pixel circuit region, and the length of the median line of the pixel circuit region extends along the second direction; and / or,

[0029] The first insulating layer includes a first via and a second via. The first connection structure is electrically connected to the first electrode of the bypass transistor through the first via, and the second connection structure is electrically connected to the gate of the bypass transistor through the second via; the orthographic projection of the first via on the substrate covers the median line of the pixel circuit region, and / or, the orthographic projection of the second via on the substrate covers the median line of the gate of the bypass transistor, and the length of the median line of the gate of the bypass transistor extends along the second direction.

[0030] In some embodiments, the pixel circuit region includes a third connection structure, and the orthographic projection of the third connection structure on the substrate partially surrounds the orthographic projection of the bypass transistor on the substrate;

[0031] The third connection structure is electrically connected to the substrate and the second electrode of the bypass transistor respectively;

[0032] The third connection structure includes a first structural portion, a second structural portion, and a third structural portion. The third structural portion is connected between the first structural portion and the second structural portion. The first structural portion and the second structural portion are respectively located at opposite side edges of the pixel circuit region in the first direction, and the third structural portion is located at a side edge adjacent to both the first structural portion and the second structural portion;

[0033] The first structural part is disposed closer to the auxiliary structure than the second connection structure, and the second structural part is disposed closer to the second connection structure than the auxiliary structure.

[0034] In some embodiments, the pixel circuit region includes a fourth connection structure, and the fourth connection structure is electrically connected to the first electrode of the bypass transistor;

[0035] The size of the fourth connection structure in the first direction is greater than the size of the auxiliary structure in the second direction;

[0036] The fourth connection structure is disposed on the same layer as the auxiliary structure, or the fourth connection structure is disposed on the same layer as the first connection structure, or the fourth connection structure is disposed on the same layer as the second connection structure.

[0037] In some embodiments, the first direction intersects the second direction, and the second direction is the direction from the first electrode of the bypass transistor to the first electrode of the driving transistor;

[0038] In the first direction, at least two second electrodes of the bypass transistors in adjacent pixel circuit regions are shared, and the second electrode of the transistor is the other of the source electrode and the drain electrode.

[0039] In some embodiments, the first direction intersects the second direction, and the second direction is the direction from the first electrode of the bypass transistor to the first electrode of the driving transistor;

[0040] In the first direction, at least two bypass transistors in adjacent pixel circuit regions are symmetric about the boundary line between the two adjacent pixel circuit regions; and / or,

[0041] In the first direction, at least two first connection structures in adjacent pixel circuit regions are symmetric about the boundary line between the two adjacent pixel circuit regions; and / or,

[0042] In the first direction, at least two auxiliary structures in adjacent pixel circuit regions are symmetric about the boundary line between the two adjacent pixel circuit regions; and / or,

[0043] In the second direction, at least two bypass transistors in adjacent pixel circuit regions are symmetric about the boundary line between the two adjacent pixel circuit regions; and / or,

[0044] In the second direction, at least two first connection structures in adjacent pixel circuit regions are symmetric about the boundary line between the two adjacent pixel circuit regions; and / or,

[0045] In the second direction, there are at least two auxiliary structures adjacent to the pixel circuit regions that are symmetric about the boundary line between two adjacent pixel circuit regions.

[0046] In some embodiments, the first direction intersects the second direction, and the second direction is the direction in which the first electrode of the bypass transistor points to the first electrode of the driving transistor;

[0047] In the first direction, there are at least two pixel circuits adjacent to the pixel circuit regions that are symmetric about the boundary line between two adjacent pixel circuit regions; and / or,

[0048] In the second direction, there are at least two pixel circuits adjacent to the pixel circuit regions that are symmetric about the boundary line between two adjacent pixel circuit regions.

[0049] In some embodiments, along the first direction, the perpendicular distance between the first structural portion and the auxiliary structure is a third distance, and the perpendicular distance between the second structural portion and the second connection structure is a fourth distance;

[0050] For two pixel circuit regions adjacent in the first direction, which are a first pixel circuit region and a second pixel circuit region, the third distance of the first pixel circuit region is greater than the third distance of the second pixel circuit region; and / or,

[0051] The third distance of the first pixel circuit region is the same as the fourth distance of the second pixel circuit region, and / or, the fourth distance of the first pixel circuit region is the same as the third distance of the second pixel circuit region; and / or,

[0052] The first connection structures of the first pixel circuit region and the second pixel circuit region have the same size.

[0053] In some embodiments, the third distance and the fourth distance of the same pixel circuit region are the same.

[0054] In some embodiments, in the second direction, the two ends of the auxiliary structure are a first end and a second end respectively, the two ends of the second connection structure are a third end and a fourth end respectively, the first end and the third end are on the same side, and the second end and the fourth end are on the same side;

[0055] In the second direction, the first end of the auxiliary structure extends beyond the free end of the first structural portion; and / or,

[0056] The third end of the second connection structure is flush with the free end of the second structural portion in the first direction.

[0057] In some embodiments, the pixel circuit region includes a first transistor, a second transistor, a first capacitor, and a second capacitor;

[0058] The second electrode of the first transistor is used to connect to a data signal line, and the first electrode of the first transistor is electrically connected to the gate of the driving transistor;

[0059] The first electrode of the second transistor is electrically connected to the second electrode of the driving transistor, and the second electrode of the second transistor is used to connect to a first power signal;

[0060] Both ends of the first capacitor are electrically connected to the gate of the driving transistor and the first electrode of the second transistor respectively;

[0061] Both ends of the second capacitor are electrically connected to the first electrode and the second electrode of the second transistor respectively.

[0062] In some embodiments, the auxiliary structure and the substrate are electrically connected through a third via hole in the first insulating layer.

[0063] In a second aspect of the present application, there is provided a display device, including:

[0064] The display substrate as described in the first aspect.

[0065] For the display substrate provided by the embodiments of the present application, the setting of the auxiliary structure can fill the structural clearance area around the first connection structure, reduce the difference in the film layer structure environment around the first connection structure in different pixel circuit regions. The light reflection effect of the auxiliary structure can play an auxiliary light reflection role. Under the interference of reflected light, refracted light, etc., when the film layer structure environments around the first connection structures in adjacent pixel circuit regions are different, the display unevenness problem caused by the difference in the light reflection effect of the first connection structure can be compensated by means of the light reflection effect of the auxiliary structure, thereby weakening or even eliminating the difference in the light reflection effect around the first connection structure in different pixel circuit regions, and being able to improve the problem of display unevenness and enhance the display effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] Figure 1 It is a schematic partial structural diagram of a display panel provided by an embodiment of the present application;

[0067] Figure 2 It is a schematic partial structural diagram of another display substrate provided by an embodiment of the present application;

[0068] Figure 3 It is a schematic cross-sectional view of another display substrate along B1 - B2 provided by an embodiment of the present application;

[0069] Figure 4 A schematic equivalent circuit diagram of a pixel circuit provided by an embodiment of the present application;

[0070] Figure 5 A schematic partial structure diagram of another display substrate provided by an embodiment of the present application;

[0071] Figure 6 A schematic cross-sectional view of another display substrate along C1-C2 provided by an embodiment of the present application;

[0072] Figure 7 A schematic partial structure diagram of yet another display substrate provided by an embodiment of the present application;

[0073] Figure 8 A schematic partial structure diagram of a display substrate provided by an embodiment of the present application;

[0074] Figure 9 A schematic cross-sectional view of a display substrate along D1-D2 provided by an embodiment of the present application;

[0075] Figure 10 A schematic partial structure diagram of another display substrate provided by an embodiment of the present application;

[0076] Figure 11 A schematic cross-sectional view of another display substrate along E1-E2 provided by an embodiment of the present application;

[0077] Figure 12 A schematic cross-sectional view of yet another display substrate along E1-E2 provided by an embodiment of the present application;

[0078] Figure 13 A schematic cross-sectional view of still another display substrate along E1-E2 provided by an embodiment of the present application;

[0079] Figure 14 A schematic structure diagram of a display device provided by an embodiment of the present application. Detailed implementation manners

[0080] To better understand the technical solutions provided by the embodiments of this specification, the technical solutions of the embodiments of this specification will be described in detail below through the accompanying drawings and specific embodiments. It should be understood that the specific features in the embodiments of this specification and the embodiments are detailed descriptions of the technical solutions of the embodiments of this specification, rather than limitations on the technical solutions of this specification. Without conflict, the technical features in the embodiments of this specification and the embodiments can be combined with each other.

[0081] In this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element. The term "more than two" includes two or more than two cases.

[0082] In display technology, integrated circuit design started from bipolar processes. To meet more and more usage scenarios and performance requirements, it has gradually developed to the current MOS (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET) integrated circuits, with the size continuously shrinking and the PPI (resolution) continuously increasing. With the continuous development of display technology, users' requirements for displays are also getting higher and higher. In the display field, the most important problem is the problem of display mura (color unevenness). Mura is a visual phenomenon caused by uneven brightness of light-emitting units. The reasons for the generation of mura are diverse, including circuit design, layout, process, pixel driving, etc. Generally, the directions for eliminating mura are roughly divided into three types: (1) Improvement of uniformity at the process level: At the process level, including processes such as lithography, film formation, and etching, strive to ensure the uniformity of film thickness and size. If each MOS transistor can be made completely consistent in terms of process, then the mura defect can be fundamentally solved. The reality is that it is impossible to make any process completely consistent, and it is impossible to completely eliminate mura from the process. (2) Internal circuit compensation: By analyzing the circuit principle, it is found that the occurrence of mura is highly related to the influence of the threshold voltage Vth. Therefore, a pixel circuit capable of performing Vth compensation can be designed to eliminate mura from the drive, but the compensation of Vth has a certain range, and the compensation will fail if the deviation exceeds this range. (3) External compensation: That is, the demura (mura elimination) technology. First, measure the non-uniform range, and then implement different pixel signal inputs for the non-uniformity to make the pixels in different regions display consistently. This method can achieve precise compensation, but the efficiency of its application is not high.

[0083] In addition to the uneven brightness caused by the non-uniform light emission of the pixels themselves, there is also metal reflection mura caused by inconsistent metal wiring in the layout design. This is mainly due to the differences in the metal wiring within each pixel, and the brightness differences shown by the light emitted by the pixels or the external light reflected by the metal lines. It will form dot-like or line-like mura, and its obviousness will vary to some extent with different viewing angles.

[0084] Generally, in order to save pixel space and increase PPI, the bypass transistors in adjacent pixel circuits share an electrode. Then, the bypass transistors in adjacent pixel circuits can be symmetric about the shared electrode. However, due to some differences in relative positions, the structural environments around some connection line structures in adjacent pixel circuits will be different. If the sizes or relative positions of some connection line structures in adjacent pixel circuits are different, then the capacitances of some connection line structures in adjacent pixel circuits will also be different, resulting in differences in the resistance and RC delay (the time delay of the circuit composed of resistance and capacitance) in this area of the two pixel circuits, and further affecting the difference in the light emission brightness of the pixels, causing problems such as uneven display color and affecting the display effect.

[0085] Figure 1 FIG. is a schematic partial structural diagram of a display panel provided by an embodiment of the present application. Exemplarily, as Figure 1 shown, the display panel includes a pixel circuit region 110. Pixel circuits are arranged in the pixel circuit region 110. The pixel circuit includes a driving transistor TD and a bypass transistor T3. The first electrode 201 of the driving transistor TD is connected to the first electrode 201 of the bypass transistor T3 through a connection line. The second electrodes 202 of the bypass transistors T3 in two adjacent pixel circuit regions 110 are shared. The connection lines in two adjacent pixel circuit regions 110 are respectively a first connection line A1 and a second connection line A2. Generally, the first connection line A1 and the second connection line A2 can be made of a metal material and have a certain light reflection effect. The second electrodes 202 of two adjacent bypass transistors T3 are shared. However, due to the arrangement and wiring limitations of other devices in the pixel circuit, the positions of the first connection line A1 and the second connection line A2 in adjacent pixel circuit regions 110 are different, and the surrounding film layer structures are also different, so there are differences in the light reflection effect, and it is easy to cause uneven brightness of the display screen. In addition, since the sizes and shapes of the first connection line A1 and the second connection line A2 are both different, the parasitic capacitances corresponding to the connection lines are also different, and the two pixel circuits belonging to them are prone to electrical differences, thereby causing uneven colors of the emitted light in different pixel circuit regions and affecting the display effect.

[0086] Figure 2 FIG. is a schematic partial structural diagram of another display substrate provided by an embodiment of the present application; Figure 3Another schematic cross-sectional view of the display substrate provided by the embodiment of the present application along B1-B2. Exemplarily, refer to Figure 2 and Figure 3 , the display substrate includes: a substrate 100, a first conductive layer 200, a first insulating layer 300, and a gate insulating layer 400. The substrate 100 includes a plurality of pixel circuit regions 110, and the pixel circuit regions 110 are provided with pixel circuits 200 and auxiliary structures 210; the pixel circuit includes a driving transistor TD and a bypass transistor T3, a first electrode 201 of the driving transistor TD is used for electrically connecting to a light-emitting device, and a first electrode 201 of the bypass transistor T3 is electrically connected to the first electrode 201 of the driving transistor TD through a first connection structure 220. The first electrode of the transistor is one of the source electrode and the drain electrode, and the second electrode of the transistor is the other of the source electrode and the drain electrode. The pixel circuit can be used to drive the light-emitting device to emit light to realize screen display.

[0087] Exemplarily, the substrate 100 can be a single-crystalline silicon wafer substrate, and the substrate 100 can also be a glass substrate, a flexible substrate, etc.

[0088] Exemplarily, the transistor can be an N-type transistor or a P-type transistor.

[0089] Exemplarily, the materials of the first insulating layer 300 and the gate insulating layer 400 can be the same or different. The material of the gate insulating layer 400 can include silicon oxide; the material of the first insulating layer 300 can include a single layer of silicon oxide or a single layer of silicon nitride, and can also be an alternating stacked layer of silicon oxide and silicon nitride.

[0090] Exemplarily, refer to Figure 2 , the first conductive layer 200 is disposed on a side of the gate 203 away from the substrate 100, the first insulating layer 300 is disposed between the first conductive layer 200 and the substrate 100, the first insulating layer 300 is disposed between the gate 203 and the first conductive layer 200, and the gate insulating layer 400 is disposed between the gate 203 and the substrate 100. The auxiliary structure 210 and the first connection structure 220 are both disposed on the first conductive layer 200.

[0091] Exemplarily, the display substrate can include multiple conductive layers, and the auxiliary structure 210 and the first connection structure 220 can be disposed on the same conductive layer or on different conductive layers, which is not specifically limited in the embodiment of the present application.

[0092] Exemplarily, refer to Figure 2, the orthographic projection of the auxiliary structure 210 on the substrate 100 does not overlap with the orthographic projections of the first connection structure 220, the first electrode 201 of the driving transistor TD, and the first electrode 201 of the bypass transistor T3 on the substrate 100; that is, the auxiliary structure 210 is disposed in the clearance area near the first connection structure 220, and the clearance area refers to the area where no other connection or electrode structure is disposed. A first insulating layer 300 is disposed between the first connection structure 220 and the substrate 100. The auxiliary structure 210 and the first connection structure 220 are disposed on the same layer. The orthographic projection of the first insulating layer 300 on the substrate 100 covers the orthographic projections of the first connection structure 220 and the auxiliary structure 210 on the substrate 100, that is, both the auxiliary structure 210 and the first connection structure 220 are located above the first insulating layer 300; the light reflectivity of the surface of the auxiliary structure 210 facing away from the substrate 100 is greater than the light reflectivity of the surface of the first insulating layer 300 facing away from the substrate 100, that is, the light reflectivity of the upper surface of the auxiliary structure 210 is greater than the light reflectivity of the upper surface of the surrounding first insulating layer 300. The light reflectivity of the surface of the first connection structure 220 on the side of the substrate 100 is greater than the light reflectivity of the surface of the first insulating layer 300 facing away from the substrate 100. The first insulating layer 300 serves as a dielectric layer, and the dielectric material generally has a poor light reflection effect and a good light transmission effect. Therefore, the exposed area of the first insulating layer 300 around the first connection structure 220 does not produce a light reflection compensation effect on the first connection structure 220. On the contrary, the first connection structure 220 is a conductive structure and generally has a relatively higher light reflectivity than the dielectric material. The auxiliary structure 210 can serve as a light reflection compensation structure for the first connection structure 220, so the light reflectivity of the auxiliary structure 210 is higher than that of the first insulating layer 300. The reflected light of the auxiliary structure 210, the reflected light of the first connection structure 220, and the reflected light of other film layer structures can interfere with each other. The auxiliary structure 210, the first connection structure 220, and other film layer structures can also have interference effects such as reflected light and refracted light, finally realizing the auxiliary compensation of the light unevenness by the auxiliary structure 210, thereby solving the problem of display unevenness and improving the display effect.

[0093] It should be noted that the source of the reflected light of the auxiliary structure 210, the first connection structure 220, and other film layer structures can be external natural light or light with different propagation paths of internal emitted light.

[0094] In the display substrate provided by the embodiment of the present application, the setting of the auxiliary structure 210 can fill the structural clearance area around the first connection structure 220, reduce the difference in the film layer structure environment around the first connection structure 220 in different pixel circuit regions 110. The light reflection effect of the auxiliary structure 210 can play a role in assisting light reflection. Under the interference of reflected light, refracted light, etc., when the film layer structure environments around the first connection structures 220 in adjacent pixel circuit regions 110 are different, the display unevenness problem caused by the difference in the light reflection effect of the first connection structure 220 can be compensated by means of the light reflection effect of the auxiliary structure 210, thereby weakening or even eliminating the difference in the light reflection effect around the first connection structure 220 in different pixel circuit regions 110, improving the display unevenness problem, and enhancing the display effect.

[0095] In some embodiments, referring to Figure 2 and Figure 3 , the auxiliary structure 210 is located on the side of the first connection structure 220 away from the gate 203 of the bypass transistor T3. The side of the first connection structure 220 away from the gate 203 of the bypass transistor T3 is a clearance area of a first conductive layer 200, and this clearance area has a relatively large blank space compared to other areas. The auxiliary structure 210 can be set to compensate for the light reflection effect of the first connection structure 220. In addition, due to the differences in the shape and size of the first connection structure 220 in adjacent pixel circuit regions 110, the shape and area of the clearance area are different. After the auxiliary structure 210 is set, the spatial shape of the clearance area is changed, so that the difference degree of the film layer structure in adjacent pixel circuit regions 110 can be reduced, and further the difference in the light reflection effect can be reduced, improving the display uniformity and enhancing the display effect.

[0096] Exemplarily, the pixel circuit can be a 4T2C circuit structure, that is, 4 TFTs (Thin Film Transistors) and 2 capacitors. The pixel circuit can also be circuit structures such as 7T1C, 8T2C, 9T2C, etc., and the embodiments of the present application do not make specific limitations.

[0097] Figure 4 is a schematic equivalent circuit diagram of a pixel circuit provided by an embodiment of the present application; Figure 5 is a schematic partial structural diagram of another display substrate provided by an embodiment of the present application. In some embodiments, referring to Figure 4 and Figure 5, taking the 4T2C pixel circuit as an example for illustration, the pixel circuit region 110 of the display panel includes a first transistor T1, a second transistor T2, a first capacitor C1, and a second capacitor C2; the second electrode 202 of the first transistor T1 is used to connect to the data signal line, and the data signal line is used to transmit the data signal Data. The first electrode 201 of the first transistor T1 is electrically connected to the gate 203 of the driving transistor TD, and the first electrode 201 of the first transistor T1 and the gate 203 of the driving transistor TD are both electrically connected to the first node G; the first electrode 201 of the second transistor T2 is electrically connected to the second electrode 202 of the driving transistor TD, and the first electrode 201 of the second transistor T2 and the second electrode 202 of the driving transistor TD are both electrically connected to the second node S, and the second electrode 202 of the second transistor T2 is used to connect to the first power signal ELVDD; the two ends of the first capacitor C1 are respectively electrically connected to the gate 203 of the driving transistor TD and the first electrode 201 of the second transistor T2; the two ends of the second capacitor C2 are respectively electrically connected to the first electrode 201 and the second electrode 202 of the second transistor T2. The first electrodes 201 of the driving transistor TD and the bypass transistor T3 are both used to connect to the anode of the light-emitting device OLED, and the cathode of the light-emitting device OLED can be connected to the second power signal. The gates of the first transistor T1, the second transistor T2, the driving transistor TD, and the bypass transistor T3 are all connected to their respective corresponding gate signals.

[0098] Exemplarily, referring to Figure 4 , the first transistor T1 is a grayscale voltage writing switch transistor, the second transistor T2 is a threshold voltage compensation switch transistor, T3 is an OLED bypass switch transistor, and T3 can function as a reset transistor, which can reset the anode of the light-emitting device OLED to a low potential. The driving transistor TD is a pixel driving transistor, the first capacitor C1 is a driving transistor voltage storage capacitor, and the second capacitor C2 is a grayscale writing load capacitor. Exemplarily, T1, T2, and TD can all be PMOS transistors, and the placement positions within each pixel circuit region 110 can be the same. T3 can be an NMOS transistor. To save pixel space, the sources of T3 in two adjacent pixel circuit regions can be shared, so T3 in the two pixel circuit regions 110 is symmetric with respect to the pixel circuit region boundary. In the two pixel circuit regions 110, the relative positions of TD and T3 are inconsistent. After the drains of TD and T3 are connected, near the drain of T3, the first connection structure 220 will be different, and the metal reflection of the conductive layer will also be different. In addition, due to the inconsistent lengths and shapes of the metal wires, the resistances of the two wires and the capacitances to the surrounding signal lines also have differences, resulting in differences in the resistances and RC delays of the two pixels in this region, which in turn affects the difference in the light emission brightness of the pixels. To solve the metal wiring reflection mura, it is necessary to ensure that the metal wiring within each pixel circuit region is completely consistent to reduce the display unevenness caused by the reflection difference and electrical difference.

[0099] In some embodiments, referring to Figure 5 , the gate 203 of the bypass transistor T3 is electrically connected to the second connection structure 230, and the second connection structure 230 is disposed in the conductive layer. The second connection structure 230 and the auxiliary structure 210 are respectively located on both sides of the first connection structure 220 in the first direction X, and the first direction X intersects the second direction Y, where the second direction Y is the direction from the first electrode 201 of the bypass transistor T3 to the first electrode 201 of the driving transistor TD. The second connection structure 230 is disposed in the conductive layer. Generally, the light reflectivity of the conductive layer is greater than that of the dielectric material. Then, the second connection structure 230 and the auxiliary structure 210 are respectively disposed on opposite sides of the first connection structure 220. Thus, the second connection structure 230 and the auxiliary structure 210 can provide a more symmetric and uniform light reflection effect compensation for the first connection structure 220, and improve the display unevenness problem caused by the uneven light reflection effect due to the environmental difference around the first connection structure 220.

[0100] Exemplarily, the second connection structure 230 can be disposed on the same layer as the first connection structure 220, and both can be disposed on the first conductive layer 200.

[0101] Exemplarily, the first direction X can be perpendicular to the second direction Y.

[0102] In some embodiments, referring to Figure 5 , in the second direction Y, the two ends of the auxiliary structure 210 are respectively a first end 211 and a second end 212, the two ends of the second connection structure 230 are respectively a third end 231 and a fourth end 232, the first end 211 and the third end 231 are located on the same side, and the second end 212 and the fourth end 232 are located on the same side; the first end 211 and the third end 231 are both close to the driving transistor TD; the second end 212 and the fourth end 232 are both close to the bypass transistor T3.

[0103] Exemplarily, the first connection structure 220 can be strip-shaped, and the length direction of the first connection structure 220 extends along the second direction Y.

[0104] In some examples, referring to Figure 5 , the first end 211 and the third end 231 are flush in the first direction X. This can improve the consistency of the structural environment around the first connection structure 220 in different pixel circuit regions 110.

[0105] In some examples, referring to Figure 5 , the second end 212 and the fourth end 232 are flush in the first direction X. This can further improve the consistency of the structural environment around the first connection structure 220 in different pixel circuit regions 110.

[0106] In some embodiments, referring toFigure 5 Along the first direction X, the perpendicular distance between the auxiliary structure 210 and the first connection structure 220 is the first distance L1, and the perpendicular distance between the second connection structure 230 and the first connection structure 220 is the second distance L2.

[0107] In some examples, referring to Figure 5 the first distance L1 is less than the second distance L2. The value of the first distance L1 within different pixel circuit regions 110 is the same, and the second distance L2 within different pixel circuit regions 110 is the same. This can further improve the consistency of the structural environment around the first connection structure 220 within different pixel circuit regions 110.

[0108] In some examples, the first distance L1 is the same as the second distance L2, and the auxiliary structure 210 and the second connection structure 230 can be symmetric about the first connection structure 220, which can further improve the consistency of the structural environment around the first connection structure 220 within different pixel circuit regions 110.

[0109] Exemplarily, the size of the pixel circuit region 110 along the first direction X is the sub-pixel width L, and the first distance L1 can be about one-eighth of the size of the sub-pixel width L, which is beneficial to realizing the symmetric setting of the auxiliary structure 210 in the first direction X in two pixel circuit regions 110. The second distance L2 can be about one-eighth of the sub-pixel width L, which is beneficial to realizing the symmetric setting of the second connection structure 230 in the first direction X in two pixel circuit regions 110.

[0110] Exemplarily, the value range of the first distance L1 can be from 0.2 μm to 0.8 μm, such as 0.3 μm, 0.45 μm, 0.5 μm, 0.6 μm, 0.7 μm, etc.; the value range of the second distance L2 can be from 0.2 μm to 0.8 μm, such as 0.3 μm, 0.45 μm, 0.5 μm, 0.6 μm, 0.7 μm, etc.

[0111] In some examples, the size of the auxiliary structure 210 in the second direction Y can be the same as the size of the second connection structure 230 in the second direction Y. The size of the auxiliary structure 210 in the second direction Y and the size of the second connection structure 230 in the second direction Y are both smaller than the size of the first connection structure 220 in the second direction Y.

[0112] In some examples, the size of the auxiliary structure 210 in the first direction X is greater than or equal to the size of the first connection structure 220 in the first direction X. The size of the auxiliary structure 210 in the first direction X is greater than or equal to 2 μm, and the size of the first connection structure 220 in the first direction X is greater than or equal to 2 μm.

[0113] In some examples, the dimension of the second connection structure 230 in the first direction X is greater than or equal to the dimension of the first connection structure 220 in the first direction X. The dimension of the second connection structure 230 in the first direction X is greater than or equal to 2 μm.

[0114] Exemplarily, the widths of the auxiliary structure 210 and the second connection structure 230 are greater than the width of the first connection structure 220, and the lengths of the auxiliary structure 210 and the second connection structure 230 are less than the length of the first connection structure 220, so that the auxiliary structure 210 and the second connection structure 230 can achieve a greater light reflection compensation effect.

[0115] In some embodiments, referring to Figure 5 , the orthographic projection of the first connection structure 220 on the substrate 100 covers the median line 115 of the pixel circuit region 110. The median line of the pixel circuit region 110 is the first median line 115, and the length of the first median line 115 extends along the second direction Y. The first connection structure 220 is disposed on the first median line 115, and the auxiliary structure 210 and the second connection structure 230 on both sides of the width of the first connection structure 220 are symmetrically disposed, so that the surrounding structure environment of the first connection structure 220 in different pixel circuit regions 110 can be made consistent, and the display unevenness problem caused by the surrounding environment difference can be eliminated. When the relative positions of other transistors and connection structures in different pixel circuit regions 110 are also the same, the structural consistency of each pixel circuit region can be maintained to a greater extent, and the display uniformity can be improved. When the auxiliary structure 210 and the connection structure are both located in the same conductive layer, the wiring consistency can be achieved to a greater extent.

[0116] In some examples, the median line of the first connection structure 220 in the first direction may coincide with the first median line 115.

[0117] Figure 6 FIG. 15 is a schematic cross-sectional view of another display substrate provided by an embodiment of the present application along C1-C2.

[0118] In some embodiments, referring to Figure 5 and Figure 6 , the first insulating layer 300 includes a first via 301 and a second via 302. The first connection structure 220 is electrically connected to the first electrode 201 of the bypass transistor T3 through the first via 301, and the second connection structure 230 is electrically connected to the gate 203 of the bypass transistor T3 through the second via 302; the orthographic projection of the first via 301 on the substrate 100 covers the first median line 115. Exemplarily, the median line of the first via 301 in the first direction X may coincide with the first median line.

[0119] In some embodiments, referring to Figure 5 and Figure 6The middle line of the gate 203 of the bypass transistor T3 is the second middle line 116, and the length of the second middle line 116 extends along the second direction. The positive projection of the second via 302 on the substrate 100 covers the second middle line 116. Exemplarily, the middle line of the second via 302 in the first direction X may coincide with the second middle line.

[0120] In some examples, referring to Figure 6 , the manufacturing process of the display substrate may include the following steps:

[0121] Prepare the substrate 100. Perform N-type heavy doping on one side of the substrate to form an N-type heavy doping layer 102, continue with P-type doping to obtain a P-type doping layer 103, perform an isolation process on the N-well region N+ and the P-well region P+ to obtain an isolation region STI, continue to perform N-doping and P-doping on the active regions respectively to obtain the N-well region N+ and the P-well region P+, and form a substrate layer 101 on the side of the substrate away from the active region to obtain the substrate 100.

[0122] Prepare the gate insulating layer 400; among them, other gate insulating layers 400 under the gate 203 can be removed through film formation, photolithography, and etching.

[0123] Prepare the gate 203. Exemplarily, the gate 203 may include a polysilicon material.

[0124] Perform a sidewall process on the side of the gate structure to form a gate side structure 203-1 to prevent gate leakage.

[0125] Perform ion implantation on the source region and the drain region respectively.

[0126] Perform high-impedance ion implantation on the gate.

[0127] Perform the Salicide process (metal silicide process). That is, form a metal silicide on the substrate and polysilicon without oxide coverage, thereby obtaining a low-resistance active region and polysilicon. Specifically, a layer of metal, such as Ti, Co, or NiPt, can be deposited above the gate and the active region, and then two rapid thermal annealings and one selective wet etching treatment are performed. Finally, metal silicon oxides, such as TiSi2, CoSi2, or NiPtSi, are formed on the surface of the gate and the active region. Metals Ti, Co, and NiPt do not react with dielectric materials to form metal silicon oxides, but only react with directly contacted polysilicon and active regions to form metal silicon oxides, which can reduce the sheet resistance and contact resistance of polysilicon and active regions, reduce the RC delay, and improve the speed of the circuit.

[0128] A first insulating layer 300 is provided, and vias are etched in the first insulating layer 300, including a first via 301 and a second via 302, and also vias for connecting the third connection structure 240 to the substrate 100, etc.

[0129] A first conductive layer 200 is provided on the first insulating layer 300. The first conductive layer 200 includes an auxiliary structure 210, a first connection structure 220, and a third connection structure 240. The first conductive layer 200 can be a metal layer.

[0130] An insulating layer and other conductive layers can also be provided above the first conductive layer 200 to form a pixel circuit.

[0131] It should be noted that Figure 2 and Figure 5 The small dashed boxes in both are vias on the insulating layer, and the outer dashed box is the virtual boundary of the pixel circuit region 110.

[0132] In some embodiments, referring to Figure 5 and Figure 6 The pixel circuit region 110 includes a third connection structure 240. The orthographic projection part of the third connection structure 240 on the substrate 100 surrounds the orthographic projection of the bypass transistor T3 on the substrate 100. The third connection structure 240 is electrically connected to the substrate 100 and the second electrode 202 of the bypass transistor T3 respectively. The third connection structure 240 includes a first structure part 241, a second structure part 242, and a third structure part 243. The third structure part 243 is connected between the first structure part 241 and the second structure part 242. The first structure part 241 and the second structure part 242 are respectively located at opposite side edges of the pixel circuit region 110 in the first direction X. The third structure part 243 is located at a side edge adjacent to both the first structure part 241 and the second structure part 242. The second structure part 242 is located at the edge of the pixel circuit region 110 where the second electrodes 202 of two adjacent bypass transistors T3 are shared. The first structure part 241 is located at the edge of the pixel circuit region 110 opposite to the second structure part 242. The third structure part 243 is connected to the same side of the first structure part 241 and the second structure part 242. The first structure part 241 is electrically connected to the P-well P+ on the substrate 100, and the second structure part 242 is electrically connected to the N-well N+ on the substrate 100, so as to electrically connect the second electrode 202 of the bypass transistor T3 to the substrate 100, and make the second electrode 202 of the bypass transistor T3 access a stable low potential. The part of the third connection structure 240 that surrounds the bypass transistor T3 can play a role in signal shielding. The first structure part 241 is arranged closer to the auxiliary structure 210 than the second connection structure 230, and the second structure part 242 is arranged closer to the second connection structure 230 than the auxiliary structure 210.

[0133] In some embodiments, referring toFigure 5 Along the first direction X, the perpendicular distance between the first structural part 241 and the auxiliary structure 210 is the third distance L3, and the perpendicular distance between the second structural part 242 and the second connection structure 230 is the fourth distance L4. Two adjacent pixel circuit regions 110 in the first direction X are the first pixel circuit region 111 and the second pixel circuit region 112.

[0134] In some examples, referring to Figure 5 the third distance L3 is greater than the fourth distance L4.

[0135] In some examples, the third distance L3 and the fourth distance L4 of the same pixel circuit region 110 are the same.

[0136] In some examples, the first distance L1, the second distance L2, and the fourth distance L4 are all the same

[0137] In some examples, the first distance L1, the second distance L2, the third distance L3, and the fourth distance L4 can all be the same. The first structural part 241, the auxiliary structure 210, the first connection structure 220, the second connection structure 230, and the second structural part 242 can be arranged at equal intervals, so that a uniform light reflection effect can be achieved, and the display unevenness problem caused by uneven light reflection can be improved.

[0138] In some examples, referring to Figure 5 the third distance L3 of the first pixel circuit region 111 is the same as the fourth distance L4 of the second pixel circuit region. The auxiliary structure 210, the first connection structure 220, the second connection structure 230, and the second structural part 242 can be arranged at equal intervals, so that a uniform light reflection effect can be achieved, and the display unevenness problem caused by uneven light reflection can be improved.

[0139] In some examples, the third distance L3 of different pixel circuit regions 110 is the same. The fourth distance L4 of different pixel circuit regions 110 is the same. The structural consistency of different pixel circuit regions 110 can be improved, and the display uniformity can be improved.

[0140] In some examples, the third distance L3 of the first pixel circuit region 111 is greater than the third distance L3 of the second pixel circuit region 112.

[0141] In some examples, the fourth distance L4 of the first pixel circuit region 111 is the same as the third distance L3 of the second pixel circuit region 112.

[0142] In some examples, the first connection structure 220 in the first pixel circuit region 111 has the same size as the first connection structure 220 in the second pixel circuit region 112. The auxiliary structure 210 in the first pixel circuit region 111 has the same size as the auxiliary structure 210 in the second pixel circuit region 112. Then, the structural uniformity of the first connection structures 220 in different pixel circuit regions 110 can be enhanced.

[0143] In some embodiments, referring to Figure 5 , in the second direction Y, the first end 211 of the auxiliary structure 210 extends beyond the free end of the first structural portion 241. The connection end of the first structural portion 241 is connected to the third structural portion 243, and the free end of the first structural portion 241 is the end far from the third structural portion 243. The distance between the first end 211 of the auxiliary structure 210 and the third structural portion 243 is greater than the distance between the free end of the first structural portion 241 and the third structural portion 243.

[0144] In some embodiments, referring to Figure 5 , the third end 231 of the second connection structure 230 is flush with the free end of the second structural portion 242 in the first direction X. The distance between the third end 231 of the second connection structure 230 and the third structural portion 243 is equal to the distance between the free end of the second structural portion 242 and the third structural portion 243.

[0145] In some examples, referring to Figure 5 , the distance between the first end 211 and the third structural portion 243 is equal to the distance between the third end 231 and the third structural portion 243.

[0146] In some examples, referring to Figure 5 , the distance between the second end 212 and the third structural portion 243 is equal to the distance between the fourth end 232 and the third structural portion 243.

[0147] In some examples, referring to Figure 5 , the distance between the free end of the second structural portion 242 and the third structural portion 243 is greater than the distance between the free end of the first structural portion 241 and the third structural portion 243.

[0148] In some embodiments, referring to Figure 2 , Figure 5 and Figure 6 , in the first direction X, the second electrodes 202 of the bypass transistors T3 of at least two adjacent pixel circuit regions 110 are shared, and the second electrode of the transistor is the other of the source electrode and the drain electrode.

[0149] In some examples, referring to Figure 5 , the first pixel circuit region 111 and the second pixel circuit region 112 adjacent in the first direction share a second structural portion 242.

[0150] In some examples, refer to Figure 5 , the second electrode 202 of the bypass transistor T3 in the first pixel circuit region 111 is shared with the second electrode 202 of the bypass transistor T3 in the second pixel circuit region 112.

[0151] In some embodiments, in the first direction, there are at least two bypass transistors of adjacent pixel circuit regions that are symmetric about the boundary line between the two adjacent pixel circuit regions.

[0152] Exemplarily, refer to Figure 5 , the bypass transistor T3 in the first pixel circuit region 111 is symmetric with the bypass transistor T3 in the second pixel circuit region 112 about the common boundary of the first pixel circuit region 111 and the second pixel circuit region 112. The bypass transistor T3 includes a first electrode 201, a second electrode 202, a gate 203, and a second connection structure 230.

[0153] In some embodiments, in the first direction, there are at least two auxiliary structures of adjacent pixel circuit regions that are symmetric about the boundary line between the two adjacent pixel circuit regions.

[0154] Exemplarily, refer to Figure 5 , the auxiliary structure 210 in the first pixel circuit region 111 is symmetric with the auxiliary structure 210 in the second pixel circuit region 112 about the common boundary of the first pixel circuit region 111 and the second pixel circuit region 112.

[0155] Exemplarily, refer to Figure 5 , the third connection structure 240 in the first pixel circuit region 111 is symmetric with the third connection structure 240 in the second pixel circuit region 112 about the common boundary of the first pixel circuit region 111 and the second pixel circuit region 112.

[0156] In some embodiments, in the first direction X, there are at least two first connection structures 220 of adjacent pixel circuit regions 110 that are symmetric about the common boundary line between the two adjacent pixel circuit regions 110.

[0157] In some embodiments, in the first direction, there are at least two pixel circuits of adjacent pixel circuit regions that are symmetric about the common boundary line between the two adjacent pixel circuit regions. The pixel circuit includes a first transistor T1, a second transistor T2, a driving transistor TD, a bypass transistor T3, a first capacitor C1, a second capacitor C2, and a plurality of connection structures and an auxiliary structure 210. The symmetry of the pixel circuit can improve the structural consistency of different pixel circuit regions.

[0158] In some embodiments, refer to Figure 5, the bypass transistor T3 and the auxiliary structure 210 can both be mirror - arranged with respect to the common boundary between the first pixel circuit region 111 and the second pixel circuit region 112. The relative positions of the first connection structure 220, the driving transistor TD, the first transistor T1, the second transistor T2, the first capacitor C1, the second capacitor C2, and other connection structures within different pixel circuit regions 110 can all be the same, that is, the other structures in the first pixel circuit region 111 except for the bypass transistor T3 and the auxiliary structure 210 are translated to the same relative positions in the second pixel circuit region 112.

[0159] Figure 7 This is a schematic partial structural diagram of another display substrate provided by an embodiment of the present application. In some examples, referring to Figure 7 , the pixel circuit region includes a third pixel circuit region 113 and a fourth pixel circuit region 114. The first pixel circuit region 111 is adjacent to the third pixel circuit region 113 in the second direction Y, the second pixel circuit region 112 is adjacent to the fourth pixel circuit region 114 in the second direction Y, and the third pixel circuit region 113 is adjacent to the fourth pixel circuit region 114 in the first direction X.

[0160] In some embodiments, in the second direction, the bypass transistors of at least two adjacent pixel circuit regions are symmetric with respect to the boundary line between the two adjacent pixel circuit regions. Two adjacent pixel circuit regions share a third structural part in the second direction.

[0161] Exemplarily, referring to Figure 7 , in the second direction Y, the bypass transistor T3 of the first pixel circuit region 111 and the bypass transistor T3 of the third pixel circuit region 113 are symmetric with respect to the common boundary line between the two pixel circuit regions. The bypass transistor T3 of the second pixel circuit region 112 and the bypass transistor T3 of the fourth pixel circuit region 114 are symmetric with respect to the common boundary line between the two pixel circuit regions.

[0162] In some embodiments, in the second direction, the first connection structures of at least two adjacent pixel circuit regions are symmetric with respect to the boundary line between the two adjacent pixel circuit regions.

[0163] Exemplarily, referring to Figure 7 , in the second direction Y, the first connection structure 220 of the first pixel circuit region 111 and the first connection structure 220 of the third pixel circuit region 113 are symmetric with respect to the common boundary line between the two pixel circuit regions. The first connection structure 220 of the second pixel circuit region 112 and the first connection structure 220 of the fourth pixel circuit region 114 are symmetric with respect to the common boundary line between the two pixel circuit regions.

[0164] In some embodiments, in the second direction, there are at least two auxiliary structures of adjacent pixel circuit regions that are symmetric about the boundary line between the two adjacent pixel circuit regions.

[0165] Exemplarily, referring to Figure 7 , in the second direction Y, the auxiliary structure 210 of the first pixel circuit region 111 and the auxiliary structure 210 of the third pixel circuit region 113 are symmetric about the common boundary line between the two pixel circuit regions. The auxiliary structure 210 of the second pixel circuit region 112 and the auxiliary structure 210 of the fourth pixel circuit region 114 are symmetric about the common boundary line between the two pixel circuit regions.

[0166] In some embodiments, in the second direction, there are at least two pixel circuits of adjacent pixel circuit regions that are symmetric about the boundary line between the two adjacent pixel circuit regions.

[0167] Exemplarily, referring to Figure 7 , in the second direction Y, the pixel circuit of the first pixel circuit region 111 and the pixel circuit of the third pixel circuit region 113 are symmetric about the common boundary line between the two pixel circuit regions. The pixel circuit of the second pixel circuit region 112 and the pixel circuit of the fourth pixel circuit region 114 are symmetric about the common boundary line between the two pixel circuit regions.

[0168] Exemplarily, referring to Figure 5 , the pixel circuit regions 110 to which two mutually symmetric bypass transistors T3 belong can form a smallest repeating unit and be arranged in an array on the display substrate.

[0169] Exemplarily, referring to Figure 7 , the pixel circuit regions 110 to which four mutually symmetric bypass transistors T3 belong can form a smallest repeating unit and be arranged in an array on the display substrate.

[0170] Figure 8 FIG. is a schematic partial structural diagram of a display substrate provided by an embodiment of the present application; Figure 9 FIG. is a schematic cross-sectional view of a display substrate provided by an embodiment of the present application along D1-D2.

[0171] In some embodiments, referring to Figure 8 , the pixel circuit region 110 includes a fourth connection structure 250, and the fourth connection structure 250 is electrically connected to the first electrode 201 of the bypass transistor T3; the size of the fourth connection structure 250 in the first direction X is greater than the size of the auxiliary structure 210 in the second direction Y; the length direction of the fourth connection structure 250 may intersect with the length direction of the first connection structure 220.

[0172] In some examples, referring to Figure 8, the fourth connection structures 250 in the first pixel circuit region 111 have the same size as the fourth connection structures 250 in the second pixel circuit region 112. The structural uniformity of the first connection structures 220 in different pixel circuit regions 110 can be enhanced.

[0173] The fourth connection structures 250 can also play an auxiliary role in light effect, which can further improve the display uniformity and alleviate the non-uniformity problem.

[0174] In some examples, the first distance L1 is greater than the second distance L2, and the third distance L3 is greater than the fourth distance L4. The second distance L2 is the same as the fourth distance L4.

[0175] In some embodiments, the display substrate may include: a gate layer, a first conductive layer, and a second conductive layer. The first conductive layer is disposed between the substrate and the second conductive layer, the gate layer is disposed between the first conductive layer and the substrate, and the gate of the transistor is disposed on the gate layer.

[0176] Exemplarily, the material of the first conductive layer may include copper or aluminum. A tungsten layer may be disposed on the inner wall of the via in the insulating layer to improve the film adhesion and conductive connection of the conductive layer. The material of the first conductive layer may include copper or aluminum.

[0177] In some examples, the auxiliary structure is disposed on the first conductive layer, and the first connection structure is disposed on the second conductive layer, that is, the auxiliary structure and the first connection structure are disposed on different conductive layers.

[0178] In some examples, the auxiliary structure is disposed on the second conductive layer, and the first connection structure is disposed on the first conductive layer.

[0179] In some examples, the auxiliary structure is disposed on the gate layer. The auxiliary structure and the gate of the bypass transistor are disposed on the same layer. The material of the gate layer may include polysilicon, and polysilicon also has a certain light reflection effect. Disposing the auxiliary structure on the gate layer can achieve a light reflection compensation effect.

[0180] Exemplarily, auxiliary structures may be disposed on the gate layer, the first conductive layer, and the second conductive layer to avoid additional film light effects caused by uneven film thickness in the auxiliary structure region, thereby generating light interference.

[0181] Exemplarily, the film stack of the auxiliary structure 210 may be the same as the film stack of the first conductive connection structure 220, so that the film consistency of the light reflection structure can be maintained and the light effect consistency can be improved.

[0182] In some examples, the fourth connection structure and the auxiliary structure are disposed on the same layer.

[0183] In some examples, the fourth connection structure and the first connection structure are disposed on the same layer.

[0184] In some examples, the fourth connection structure is disposed on the same layer as the second connection structure.

[0185] Exemplarily, referring to Figure 8 and Figure 9 , the first connection structure 220 is disposed on the second conductive layer 600, and a second insulating layer 500 is disposed between the first conductive layer 200 and the second conductive layer 600. The third connection structure 240 and the fourth connection structure 250 are both disposed on the first conductive layer 200. The fourth connection structure 250 is connected to the first connection structure 220 through a via hole in the second insulating layer 500.

[0186] Exemplarily, the second connection structure 230 may be disposed on the second conductive layer 600.

[0187] Exemplarily, referring to Figure 8 , the display substrate further includes a fifth connection structure 260. The fifth connection structure 260 is disposed above the driving transistor TD, that is, the orthographic projection of the fifth connection structure 260 on the substrate 100 covers at least part of the orthographic projection of the driving transistor TD on the substrate 100. The fifth connection structure 260 is electrically connected to the substrate through an insulating layer via hole. The fifth connection structure 260 may be disposed on the first conductive layer or on other conductive layers. The first conductive layer 200 above the TD may be mainly used to connect the PMOS transistor substrate and the high-level power signal. The main purpose of the fifth connection structure 260 covering the TD is to increase the parasitic capacitance at the S point and indirectly compensate for the C2 capacitance. Here, the first conductive layer 200 cannot be connected to the G point. The C2 electrode plate is disposed on the fifth conductive metal layer.

[0188] Figure 10 Schematic partial structural diagram of another display substrate provided by an embodiment of the present application; Figure 11 Schematic cross-sectional view of another display substrate along E1-E2 provided by an embodiment of the present application.

[0189] In some embodiments, referring to Figure 10 and Figure 11 , the display substrate further includes a third insulating layer 700 and a third conductive layer 810. A third via hole 303 is disposed on the third insulating layer 700. The auxiliary structure 210 is electrically connected to the third conductive layer 810 through the third via hole 303. The auxiliary structure 210 can be connected to a low potential through the third conductive layer 810 to reduce the parasitic capacitance brought by the auxiliary structure 210.

[0190] Exemplarily, the third conductive layer 810 can be used to prepare the anode or cathode of the light-emitting device.

[0191] Figure 12 Schematic cross-sectional view of yet another display substrate along E1-E2 provided by an embodiment of the present application. Exemplarily, referring to Figure 12, the display substrate may include a fourth insulating layer 900 and a fourth conductive layer 820. The third conductive layer 810 may be used to set the anode of the light-emitting device, and the fourth conductive layer 820 may be used to set the cathode of the light-emitting device. The third via 303 may be disposed on the fourth insulating layer 900, and the third conductive layer 810 row may also be provided with a fifth connection structure 811. The auxiliary structure 210 is connected to the fourth conductive layer 820 through the fifth connection structure 811.

[0192] Figure 13 This is a schematic cross-sectional view of another display substrate provided by the embodiment of the present application along E1-E2. Exemplarily, refer to Figure 13 , a third via 303 is disposed on the first insulating layer 300, and the auxiliary structure 210 is electrically connected to the substrate 100 through the third via 303 on the first insulating layer 300, and the auxiliary structure 210 can also be connected to a low potential.

[0193] Exemplarily, the auxiliary structure 210 can be used as a shielding structure and can be connected to a constant voltage to achieve a shielding function. For example, it can be connected to a constant high level or a constant low level, etc.

[0194] Exemplarily, the plates of the first capacitor C1 and the second capacitor C2 can be disposed on other conductive layers above the second conductive layer.

[0195] It should be noted that the display substrate can continue to provide a pixel electrode, a liquid crystal layer, and a color filter substrate on the side of the pixel circuit away from the substrate according to the specific display type to obtain a liquid crystal display substrate.

[0196] Exemplarily, the display substrate can be provided with a light-emitting device on the side of the pixel circuit away from the substrate to obtain an organic light-emitting display substrate.

[0197] In some embodiments, the embodiment of the present application provides a display panel, which may include the display substrate provided in any of the above embodiments.

[0198] It should be noted that the display panel can be a liquid crystal display panel, an organic light-emitting display panel, or a laser display panel. The organic light-emitting display panel can also include a silicon-based display panel and a flexible display panel. The silicon-based display panel uses single-crystalline silicon as the substrate, and the flexible display panel uses a flexible material as the substrate. It should be noted that there is also a type of organic light-emitting display panel with a glass substrate to provide a rigid substrate, and the embodiments of the present application do not make specific limitations.

[0199] Exemplarily, in a liquid crystal display panel, a color filter substrate is disposed on one side of the display substrate where the circuit is provided. A liquid crystal layer is disposed between the display substrate and the color filter substrate. The display substrate drives the rotation of the liquid crystal molecules in the liquid crystal layer under the action of a driving signal, thereby controlling the transmittance of the liquid crystal layer in different pixel regions, and the light of the backlight source is transmitted through and then emitted from the color filter substrate to realize image display. The color filter substrate may be provided with a color filter layer and a light-shielding matrix, and can realize the display of a color image.

[0200] Exemplarily, in an organic light-emitting display panel, a light-emitting device, a packaging layer, etc. may be further disposed on one side of the display substrate where the circuit is provided.

[0201] For the display panel of the embodiment of the present application, the light reflectivity of the surface of the auxiliary structure 210 facing away from the substrate 100 on the display substrate is greater than the light reflectivity of the surface of the first insulating layer 300 facing away from the substrate 100, that is, the light reflectivity of the upper surface of the auxiliary structure 210 is greater than the light reflectivity of the upper surface of the surrounding first insulating layer 300. The light reflectivity of the surface of the first connection structure 220 on the side of the substrate 100 is greater than the light reflectivity of the surface of the first insulating layer 300 facing away from the substrate 100. The first insulating layer 300 serves as a dielectric layer, and the dielectric material generally has a poor light reflection effect and a good light transmission effect. Therefore, the exposed area of the first insulating layer 300 around the first connection structure 220 does not produce a light reflection compensation effect on the first connection structure 220. On the contrary, the first connection structure 220 is a conductive structure and generally has a relatively higher light reflectivity than the dielectric material. The auxiliary structure 210 can serve as a light reflection compensation structure for the first connection structure 220, so the light reflectivity of the auxiliary structure 210 should be higher than that of the first insulating layer 300. The reflected light of the auxiliary structure 210, the reflected light of the first connection structure 220, and the reflected light of other film layer structures can interfere with each other. The auxiliary structure 210, the first connection structure 220, and other film layer structures can also have interference effects such as the interference between reflected light and refracted light. Finally, the auxiliary compensation for the uneven light by the auxiliary structure 210 is realized, thereby solving the problem of uneven display and improving the display effect.

[0202] In some embodiments, a display module is provided, including the display panel or the display substrate provided in the above embodiments. The display module includes a driving chip and a flexible circuit board. The driving chip can be bonded to the display substrate, and the flexible circuit board can also be bonded to the display substrate. Exemplarily, the driving chip can also be integrated with the flexible circuit board, and the flexible circuit board is bonded to the display substrate.

[0203] Exemplarily, a backlight module is further included in the liquid crystal display module.

[0204] Figure 14 It is a schematic structural diagram of a display device provided by an embodiment of the present application. In some embodiments, refer to Figure 14, the display device includes: a display substrate 1000 provided in any of the above embodiments.

[0205] In some examples, the display device may include a display panel provided in the above embodiments.

[0206] In the display device according to the embodiments of the present application, by setting the light reflectivity of the surface of the auxiliary structure 210 facing away from the substrate 100 to be greater than the light reflectivity of the surface of the first insulating layer 300 facing away from the substrate 100, that is, the light reflectivity of the upper surface of the auxiliary structure 210 is greater than the light reflectivity of the upper surface of the surrounding first insulating layer 300. The light reflectivity of the surface of the first connection structure 220 facing the substrate 100 is greater than the light reflectivity of the surface of the first insulating layer 300 facing away from the substrate 100. The first insulating layer 300 serves as a dielectric layer, and the dielectric material generally has a poor light reflection effect and a good light transmission effect. Therefore, the exposed area of the first insulating layer 300 around the first connection structure 220 does not produce a light reflection compensation effect on the first connection structure 220. On the contrary, the first connection structure 220 serves as a conductive structure and generally has a relatively higher light reflectivity than the dielectric material. The auxiliary structure 210 can serve as a light reflection compensation structure for the first connection structure 220, so the light reflectivity of the auxiliary structure 210 should be higher than that of the first insulating layer 300. The reflected light of the auxiliary structure 210, the reflected light of the first connection structure 220, and the reflected light of other film layer structures can interfere with each other. The auxiliary structure 210, the first connection structure 220, and other film layer structures can also have interference effects such as reflected light and refracted light. Finally, the auxiliary structure 210 realizes auxiliary compensation for uneven light, thereby solving the problem of uneven display and improving the display effect.

[0207] It should be noted that the display devices provided in the examples of the present disclosure may include smartphones, tablet computers, laptop computers, televisions, and smart wearable display devices, etc. The smart wearable display devices may include smart watches, VR (augmented reality) displays, AR (virtual reality) displays, etc. The embodiments of the present disclosure do not make specific limitations.

[0208] The above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them; although the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure.

[0209] Although the preferred embodiments of this specification have been described, those skilled in the art can make additional changes and modifications once they learn the basic creative concepts. Therefore, the appended claims are intended to be construed to include the preferred embodiments as well as all changes and modifications falling within the scope of this specification.

[0210] Obviously, those skilled in the art can make various modifications and variations to this specification without departing from the spirit and scope of this specification. Thus, if these modifications and variations of this specification fall within the scope of the claims of this specification and their equivalent technologies, this specification is also intended to include these modifications and variations.

Claims

1. A display substrate, characterized in that, Comprising: A substrate, the substrate comprising a plurality of pixel circuit regions, wherein pixel circuits and auxiliary structures are provided in the pixel circuit regions; The pixel circuit includes a driving transistor and a bypass transistor, a first electrode of the driving transistor is used for electrically connecting to a light-emitting device, a first electrode of the bypass transistor is electrically connected to the first electrode of the driving transistor through a first connection structure, and the first electrode of the transistor is one of a source electrode and a drain electrode; A positive projection of the auxiliary structure on the substrate does not overlap with positive projections of the first connection structure, the first electrode of the driving transistor, and the first electrode of the bypass transistor on the substrate; A first insulating layer is provided between the first connection structure and the substrate, a positive projection of the first insulating layer on the substrate covers positive projections of the first connection structure and the auxiliary structure on the substrate, and a light reflectivity of a surface of the auxiliary structure facing away from the substrate is greater than a light reflectivity of a surface of the first insulating layer facing away from the substrate.

2. The display substrate according to claim 1, wherein: The auxiliary structure is located on a side of the first connection structure away from a gate of the bypass transistor.

3. The display substrate according to claim 1, wherein Further comprising: A conductive layer, the auxiliary structure and the first connection structure are provided on the same conductive layer, or The auxiliary structure and a gate of the bypass transistor are provided on the same layer.

4. The display substrate according to claim 1, wherein Further comprising: A gate layer, a first conductive layer, and a second conductive layer, the first conductive layer is provided between the substrate and the second conductive layer, the gate layer is provided between the first conductive layer and the substrate, and a gate of the transistor is provided on the gate layer; The auxiliary structure is provided on the first conductive layer, and the first connection structure is provided on the second conductive layer; And / or The auxiliary structure is provided on the second conductive layer, and the first connection structure is provided on the first conductive layer.

5. The display substrate according to claim 1, wherein: A gate of the bypass transistor is electrically connected to a second connection structure, and the second connection structure is provided on a conductive layer; The second connection structure and the auxiliary structure are respectively located on two sides of the first connection structure in a first direction, the first direction intersects a second direction, and the second direction is a direction from the first electrode of the bypass transistor to the first electrode of the driving transistor.

6. The display substrate according to claim 5, wherein: In the second direction, two ends of the auxiliary structure are respectively a first end and a second end, two ends of the second connection structure are respectively a third end and a fourth end, the first end and the third end are located on the same side, and the second end and the fourth end are located on the same side; The first end and the third end are flush in the first direction, and / or the second end and the fourth end are flush in the first direction; and / or A dimension of the auxiliary structure in the second direction is the same as a dimension of the second connection structure in the second direction.

7. The display substrate according to claim 5, wherein: In the second direction, two ends of the auxiliary structure are a first end and a second end respectively, two ends of the second connection structure are a third end and a fourth end respectively, the first end and the third end are located on the same side, and the second end and the fourth end are located on the same side; The size of the auxiliary structure in the second direction and the size of the second connection structure in the second direction are both smaller than the size of the first connection structure in the second direction; and / or The size of the auxiliary structure in the first direction is greater than or equal to the size of the first connection structure in the first direction; and / or The size of the second connection structure in the first direction is greater than or equal to the size of the first connection structure in the first direction.

8. The display substrate according to claim 5, wherein Along the first direction, the perpendicular distance between the auxiliary structure and the first connection structure is a first distance, and the perpendicular distance between the second connection structure and the first connection structure is a second distance; The first distance is the same as the second distance, and / or, the values of the first distance in different pixel circuit regions are the same, and / or, the values of the second distance in different pixel circuit regions are the same.

9. The display substrate according to claim 5, wherein The orthographic projection of the first connection structure on the substrate covers the median line of the pixel circuit region, and the length of the median line of the pixel circuit region extends along the second direction; and / or The first insulating layer includes a first via hole and a second via hole. The first connection structure is electrically connected to the first electrode of the bypass transistor through the first via hole, and the second connection structure is electrically connected to the gate of the bypass transistor through the second via hole; The orthographic projection of the first via hole on the substrate covers the median line of the pixel circuit region, and / or, the orthographic projection of the second via hole on the substrate covers the gate median line of the bypass transistor, and the length of the gate median line of the bypass transistor extends along the second direction.

10. The display substrate according to claim 5, wherein The pixel circuit region includes a third connection structure, and the orthographic projection of the third connection structure on the substrate partially surrounds the orthographic projection of the bypass transistor on the substrate; The third connection structure is electrically connected to the substrate and the second electrode of the bypass transistor respectively; The third connection structure includes a first structural portion, a second structural portion, and a third structural portion. The third structural portion is connected between the first structural portion and the second structural portion. The first structural portion and the second structural portion are respectively located at opposite side edges of the pixel circuit region in the first direction, and the third structural portion is located at a side edge adjacent to both the first structural portion and the second structural portion; The first structural portion is arranged closer to the auxiliary structure than the second connection structure, and the second structural portion is arranged closer to the second connection structure than the auxiliary structure.

11. The display substrate according to claim 5, wherein The pixel circuit region includes a fourth connection structure, and the fourth connection structure is electrically connected to the first electrode of the bypass transistor; The size of the fourth connection structure in the first direction is greater than the size of the auxiliary structure in the second direction; The fourth connection structure is disposed on the same layer as the auxiliary structure, or the fourth connection structure is disposed on the same layer as the first connection structure, or the fourth connection structure is disposed on the same layer as the second connection structure.

12. The display substrate according to any one of claims 1 to 11, wherein The first direction intersects the second direction, and the second direction is the direction from the first electrode of the bypass transistor to the first electrode of the driving transistor; In the first direction, at least two second electrodes of the bypass transistors in adjacent pixel circuit regions are shared, and the second electrode of the transistor is the other of the source electrode and the drain electrode.

13. The display substrate according to any one of claims 1 to 11, wherein The first direction intersects the second direction, and the second direction is the direction from the first electrode of the bypass transistor to the first electrode of the driving transistor; In the first direction, at least two bypass transistors in adjacent pixel circuit regions are symmetric about the boundary line between the two adjacent pixel circuit regions; and / or In the first direction, at least two first connection structures in adjacent pixel circuit regions are symmetric about the boundary line between the two adjacent pixel circuit regions; and / or In the first direction, at least two auxiliary structures in adjacent pixel circuit regions are symmetric about the boundary line between the two adjacent pixel circuit regions; and / or In the second direction, at least two bypass transistors in adjacent pixel circuit regions are symmetric about the boundary line between the two adjacent pixel circuit regions; and / or In the second direction, at least two first connection structures in adjacent pixel circuit regions are symmetric about the boundary line between the two adjacent pixel circuit regions; and / or In the second direction, at least two auxiliary structures in adjacent pixel circuit regions are symmetric about the boundary line between the two adjacent pixel circuit regions.

14. The display substrate according to any one of claims 1 to 11, wherein The first direction intersects the second direction, and the second direction is the direction from the first electrode of the bypass transistor to the first electrode of the driving transistor; In the first direction, at least two pixel circuits in adjacent pixel circuit regions are symmetric about the boundary line between the two adjacent pixel circuit regions; and / or In the second direction, at least two pixel circuits in adjacent pixel circuit regions are symmetric about the boundary line between the two adjacent pixel circuit regions.

15. The display substrate according to claim 10, wherein Along the first direction, the vertical distance between the first structural portion and the auxiliary structure is a third distance, and the vertical distance between the second structural portion and the second connection structure is a fourth distance; Two adjacent pixel circuit regions in the first direction are a first pixel circuit region and a second pixel circuit region, and the third distance of the first pixel circuit region is greater than the third distance of the second pixel circuit region; and / or, the third distance of the first pixel circuit region is the same as the fourth distance of the second pixel circuit region, and / or, the fourth distance of the first pixel circuit region is the same as the third distance of the second pixel circuit region; and / or, the first connection structures of the first pixel circuit region and the second pixel circuit region have the same size.

16. The display substrate according to claim 15, wherein the third distance and the fourth distance of the same pixel circuit region are the same.

17. The display substrate according to claim 10, wherein in the second direction, two ends of the auxiliary structure are a first end and a second end respectively, two ends of the second connection structure are a third end and a fourth end respectively, the first end and the third end are on the same side, and the second end and the fourth end are on the same side; in the second direction, the first end of the auxiliary structure extends beyond the free end of the first structural part; and / or, the third end of the second connection structure is flush with the free end of the second structural part in the first direction.

18. The display substrate according to claim 1, wherein the pixel circuit region includes a first transistor, a second transistor, a first capacitor, and a second capacitor; the second electrode of the first transistor is used to access a data signal line, and the first electrode of the first transistor is electrically connected to the gate of the driving transistor; the first electrode of the second transistor is electrically connected to the second electrode of the driving transistor, and the second electrode of the second transistor is used to access a first power signal; two ends of the first capacitor are electrically connected to the gate of the driving transistor and the first electrode of the second transistor respectively; two ends of the second capacitor are electrically connected to the first electrode and the second electrode of the second transistor respectively.

19. The display substrate according to claim 1, wherein the auxiliary structure is electrically connected to the substrate through a third via hole in the first insulating layer.

20. A display device, characterized in that, Comprising: The display substrate according to any one of claims 1 to 19.

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