Channel decoding method and device, electronic equipment and storage medium

Abstract

The invention discloses a channel decoding method and device, electronic equipment and a storage medium. The method comprises the following steps: acquiring log-likelihood ratio information to be decoded; obtaining a preset decoding instruction sequence; and decoding the log-likelihood ratio information according to the decoding instruction sequence, and outputting decoding bit information. According to the invention, automatic channel decoding can be realized based on the decoding instruction sequence, the decoding efficiency, accuracy and flexibility are improved, the cost is reduced, the hardware resource occupation is reduced, and the method can be widely applied to the technical field of channel coding and decoding.

Description

Technical Field

[0001] This application relates to the field of channel coding and decoding technologies, and particularly to a channel decoding method, device, electronic device, and storage medium. Background Art

[0002] In the 5G protocol of the mobile communication network, most communication systems (such as the SparkLink system, etc.) adopt polar codes as the coding scheme for the control channel. The transmitting-end device determines the segmentation and the number of segments based on the parameters associated with the coding of the information bits, encodes the information bits according to the number of parity bits, and sends the encoded information bits (polar code encoded data) to the receiving-end device.

[0003] In the existing solutions, after the receiving-end device receives the encoded information bits, a dedicated decoding accelerator is usually designed and adopted to decode them. However, the decoding accelerator often has a complex algorithm, cannot be changed after being designed and formed, has poor flexibility, and the design cost remains high, occupying a large amount of hardware resources and having low hardware utilization. Summary of the Invention

[0004] The main purpose of the embodiments of this application is to propose a channel decoding method, device, electronic device, and storage medium, which can realize automatic decoding of log-likelihood ratio information and improve the decoding efficiency and accuracy.

[0005] On the one hand, the embodiments of this application propose a channel decoding method, and the method includes the following steps: Obtain the log-likelihood ratio information to be decoded; Obtain a preset decoding instruction sequence; According to the decoding instruction sequence, perform decoding processing on the log-likelihood ratio information and output decoded bit information.

[0006] In some embodiments, the method further includes: Construct a soft decision metric graph structure template, where the soft decision metric graph structure template includes soft decision metric input information, soft decision metric output information, and decoding processing instruction information; Generate a corresponding hard decision metric graph structure template according to the soft decision metric graph structure template.

[0007] In some embodiments, the obtaining of the log-likelihood ratio information to be decoded specifically includes: Obtain a polar code encoded signal; Process the polar code encoded signal to generate a soft decision input sequence; According to the preset decoding path state and the soft decision metric graph structure template, decode the soft decision input sequence to generate a corresponding soft decision metric graph structure, and use the soft decision metric graph structure as the log-likelihood ratio information.

[0008] In some embodiments, the obtaining of the preset decoding instruction sequence specifically includes: Obtain the current decoding processing path; Generate the decoding instruction sequence according to the current decoding processing path, the hard decision metric graph structure template, and the soft decision metric graph structure template.

[0009] In some embodiments, the decoding the log-likelihood ratio information according to the decoding instruction sequence and outputting the decoded bit information specifically includes: Generate the hard decision metric graph structure corresponding to the soft decision metric graph structure according to the hard decision metric graph structure template; Sequentially obtain each decoding instruction in the decoding instruction sequence, and determine the data reading position, the decoding processing instruction position, and the data writing position corresponding to each decoding instruction according to each decoding instruction; Read the corresponding decoding input information from the soft decision metric graph structure according to the data reading position corresponding to each decoding instruction, and read the corresponding target decoding processing instruction according to the decoding processing instruction position; Decode the decoding input information according to the target decoding processing instruction to generate the soft decision bit information and the hard decision bit information corresponding to each decoding instruction; Determine the first data writing position from the soft decision metric graph structure and the second data writing position from the hard decision metric graph structure according to the data writing position corresponding to each decoding instruction, write the soft decision bit information to the first data writing position, and write the hard decision bit information to the second data writing position.

[0010] In some embodiments, the decoding the soft decision input sequence according to the preset decoding path state and the soft decision metric graph structure template to generate the corresponding soft decision metric graph structure specifically includes: Decode the soft decision input sequence according to the soft decision metric graph structure template and the decoding path state, and output the corresponding soft decision sequence decoding information; Obtain the data writing position of the soft decision metric input information in the soft decision metric graph structure template; Update the soft decision metric graph structure template according to the soft decision sequence decoding information and the data writing position to generate the soft decision metric graph structure.

[0011] In some embodiments, the sequentially obtaining each decoding instruction in the decoding instruction sequence and determining the data reading position, the decoding processing instruction position, and the data writing position corresponding to each decoding instruction according to each decoding instruction specifically includes: Obtain the entry instruction in the decoding instruction sequence as the current decoding instruction; Perform instruction parsing on the current decoding instruction to determine the current data reading position, the current decoding processing instruction position, and the current data writing position; When the current decoding instruction is the termination instruction in the decoding instruction sequence, stop performing instruction parsing; When the current decoding instruction is not the termination instruction, obtain the next instruction of the current decoding instruction as the current decoding instruction, and then return to the step of performing instruction parsing on the current decoding instruction to determine the current data reading position, the current decoding processing instruction position, and the current data writing position.

[0012] On the other hand, an embodiment of the present application proposes a channel decoding device, which includes: A first module for obtaining log-likelihood ratio information to be decoded; A second module for obtaining a preset decoding instruction sequence; A third module for performing decoding processing on the log-likelihood ratio information according to the decoding instruction sequence and outputting decoded bit information.

[0013] On the other hand, an embodiment of the present application proposes an electronic device, which includes a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, the foregoing channel decoding method is implemented.

[0014] On the other hand, an embodiment of the present application proposes a computer-readable storage medium, which stores a computer program, and when the computer program is executed by a processor, the foregoing channel decoding method is implemented.

[0015] The embodiments of the present application at least include the following beneficial effects: A channel decoding method, device, electronic device, and storage medium provided by the present application obtain log-likelihood ratio information to be decoded, obtain a preset decoding instruction sequence, perform decoding processing on the log-likelihood ratio information according to the decoding instruction sequence, and output decoded bit information. The present application can realize automated channel decoding based on the decoding instruction sequence, improve the efficiency, accuracy, and flexibility of decoding, reduce costs, and reduce the occupation of hardware resources. Description of the Drawings

[0016] The accompanying drawings here are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present invention, and are used together with the specification to explain the principles of the present invention.

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following briefly introduces the drawings required for the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0018] Figure 1 is a flowchart of a channel decoding method provided by an embodiment of the present application; Figure 2 is a schematic structural diagram of Polar decoding in an embodiment of the present application; Figure 3 is a schematic diagram of the register arrangement in an embodiment of the present application; Figure 4 is a flowchart of step S303 in an embodiment of the present application; Figure 5 is a flowchart of step S103 in an embodiment of the present application; Figure 6 is a schematic diagram of the decoding process in an embodiment of the present application; Figure 7 is another schematic diagram of the decoding process in an embodiment of the present application; Figure 8 is a flowchart of step S502 in an embodiment of the present application; Figure 9 is a schematic structural diagram of a channel decoding device provided by an embodiment of the present application; Figure 10 is a schematic hardware structure diagram of an electronic device provided by an embodiment of the present application. Specific Embodiments

[0019] In order to make the objectives, technical solutions, and advantages of the present application more clear, the following further details the present application in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the embodiments of the present application. They are only examples of devices and methods consistent with some aspects of the embodiments of the present application as detailed in the appended claims.

[0020] It can be understood that the terms "first", "second", etc. used in this application may be used herein to describe various concepts, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of this application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, as used herein, the words "if", "when" may be interpreted as "when...", "while...", or "in response to determining".

[0021] The terms "at least one", "a plurality", "each", "any one", etc. used in this application, at least one includes one, two or more than two, a plurality includes two or more than two, each refers to each one of the corresponding plurality, and any one refers to any one of the plurality.

[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0023] Before elaborating on the embodiments of this application in detail, some nouns and terms involved in the embodiments of this application are first explained, and the nouns and terms involved in the embodiments of this application are applicable to the following explanations.

[0024] 1) ASIC: Application Specific Integrated Circuit, an integrated circuit designed specifically for a certain specific application. Different from general integrated circuits, ASIC has the characteristics of customized design, can meet the needs of specific applications, and usually has high performance and low power consumption.

[0025] 2) RISC-V: RISC-V is an open-source instruction set architecture (ISA).

[0026] 3) LLR: Log Likelihood Ratio: In the fields of mathematics and communication, LLR is the abbreviation of Log Likelihood Ratio, which is commonly used in communication algorithms to achieve soft demodulation by calculating the log likelihood ratio.

[0027] In the 5G protocol of mobile communication networks, Polar codes are selected as the coding scheme for control channels. For example, the Polar coding method involved in 3GPP TS38.212 is used for channels PBCH, PDCCH, PUCCH, PUSCH.

[0028] For a control channel (PDCCH) with a relatively low data throughput rate, after the receiving-end device receives the encoded information bits transmitted by the transmitting end (i.e., the polar code encoded signal), most existing solutions mainly use a dedicated decoding accelerator to decode the encoded information bits. However, the algorithms of dedicated decoding accelerators are complex (such as the CASCL series), and the corresponding ASIC solutions are inflexible as they cannot be changed after being designed, have poor flexibility, high design costs, occupy a large amount of hardware resources, and have low hardware utilization rates.

[0029] Based on this, the embodiments of the present application propose a channel decoding method, device, electronic device, and storage medium, which generate typical operation functions in the polar decoder into RISC-V custom instructions, optimize the register arrangement in the polar decoder, and implement automatic decoding of the polar decoder based on the custom instructions and the decoding instruction sequence, thereby improving the decoding efficiency and accuracy.

[0030] Refer to Figure 1 , Figure 1 is an optional flowchart of a channel decoding method provided by the embodiments of the present application. The method may include but is not limited to steps S101 to S103: Step S101, obtain the log-likelihood ratio information to be decoded; Step S102, obtain a preset decoding instruction sequence; Step S103, perform decoding processing on the log-likelihood ratio information according to the decoding instruction sequence, and output decoded bit information.

[0031] In some embodiments, the above method further includes steps S201 to S202: Step S201, construct a soft decision metric graph structure template, where the soft decision metric graph structure template includes soft decision metric input information and soft decision metric output information; Step S202, generate a corresponding hard decision metric graph structure template according to the soft decision metric graph structure template.

[0032] In step S102 of some embodiments, optionally, obtain the current decoding processing path, and generate a decoding instruction sequence according to the current decoding processing path, the hard decision metric graph structure template, and the soft decision metric graph structure template. The decoding instruction sequence is stored in a general-purpose register.

[0033] Taking N = 8: codeword length (8 bits), n = 3: polarization level as an example, refer to Figure 2 , the decoding of polar consists of N decoding trees. The decoding tree essentially realizes the bit-by-bit decision of the polar code through multi-level LLR merging. Each decoding tree corresponds to the decision process of one bit. The black dashed box represents the first decoding tree, and the other decoding tree structures are similar but have different input dependency relationships.

[0034] Taking the bit decision of the first decoding tree as an example, its operation direction is from right to left, and the specific steps are as follows: 1) Input LLR sequence: The rightmost node receives the LLR values of 8 channel outputs; 2) Recursive LLR calculation: Step 1 (the rightmost): The initial LLR directly comes from the channel (such as ); Step 2: Combine adjacent LLRs through butterfly operations (for example: ); Step 3: Further combine to obtain the final LLR for deciding u1 (such as ); 3) Bit decision (the leftmost white circle): Decide u1 according to the sign of : If ≥0, u1 is decided as 0 (frozen bits are fixed as 0), if <0, u1 is decided as 1; 4) Advance bit by bit: After the decision of u1 is completed, its value will participate in the LLR calculation of subsequent bits (u2 to u8).

[0035] The complete decoding process (N = 8) is as follows: Step 1, initialization: Receive all channel LLRs; Step 2, bit-by-bit decoding: Execute in sequence for u1 to u8: Calculate the LLR of the current bit along the corresponding decoding tree; Combine the frozen bit information for decision; c. Feed the decision value back to the LLR calculation of subsequent bits; Step 3, information output: Restore the original information bit sequence.

[0036] Then, according to the above decoding process of polar decoding, that is, the current decoding processing path, combined with the register arrangement structure of the internal registers in the polar decoder, a decoding instruction sequence is generated. Among them, the register arrangement structure includes a hard decision metric graph structure template and a soft decision metric graph structure template.

[0037] Generate the corresponding hard decision metric graph structure template and soft decision metric graph structure template according to the current decoding processing path. Exemplarily, refer to Figure 3, the hard decision metric graph structure template is a Bit matrix in the internal register, and the soft decision metric graph structure template is an LLR matrix in the internal register. In the LLR matrix, the LLR stored in each matrix cell is represented in signed integer type, and the quantization bit number is N bit, where N is a positive integer, and its specific value can be determined by itself, generally ranging from 4 to 12. The receiver demodulates the polar code encoded signal, calculates the log-likelihood ratio (LLR) of each bit, and forms an LLR matrix. The LLR matrix is used to provide the reliability information (soft information) of each bit for the decoder to recursively merge and transmit. In the Bit matrix, the quantization bit number of each Bit stored in each matrix cell is 1 bit. The decoder makes a hard decision for each bit according to the LLR matrix and the structure of the polar code (such as the position of frozen bits), and the Bit matrix is used to store the hard decision result, including the final decoded bit sequence or the temporary decision value of the intermediate bit.

[0038] In some embodiments, step S101 may include but is not limited to steps S301 to S303: Step S301, obtaining the polar code encoded signal; Step S302, processing the polar code encoded signal to generate a soft decision input sequence; Step S303, decoding the soft decision input sequence according to the preset decoding path state and the soft decision metric graph structure template to generate a corresponding soft decision metric graph structure, and using the soft decision metric graph structure as the log-likelihood ratio information.

[0039] In some embodiments, optionally, receiving the polar code encoded signal, demodulating the polar code encoded signal to obtain soft bits or symbol-level probability information, and based on the soft bits or symbol-level probability information, calculating the LLR using the channel model and outputting a corresponding LLR sequence, that is, the above-mentioned soft decision input sequence. Inputting the LLR sequence into the decoder for polar code decoding, and generating a corresponding LLR matrix according to the preset decoding path state and the soft decision metric graph structure template, that is, the above-mentioned soft decision metric graph structure, and using the soft decision metric graph structure as the log-likelihood ratio information to be decoded.

[0040] In some embodiments, referring to Figure 4 , Figure 4 is an optional flowchart of step S303 in the embodiments of the present application. Step S303 may include but is not limited to steps S401 to S403: Step S401, decoding the soft decision input sequence according to the soft decision metric graph structure template and the decoding path state, and outputting the corresponding soft decision sequence decoding information; Step S402, obtaining the data writing position of the soft decision metric input information in the soft decision metric graph structure template; Step S403: Update the soft decision metric graph structure template according to the soft decision sequence decoding information and the data writing position, and generate a soft decision metric graph structure.

[0041] In some embodiments, write the soft decision sequence decoding information (such as ) to the corresponding data writing position in the soft decision metric graph structure template to complete data filling and generate a soft decision metric graph structure.

[0042] In some embodiments, refer to Figure 5 , Figure 5 is an optional flowchart of step S103 in the embodiments of the present application. Step S103 may include but is not limited to steps S501 to S505: Step S501: Generate a hard decision metric graph structure corresponding to the soft decision metric graph structure according to the hard decision metric graph structure template; Step S502: Sequentially obtain each decoding instruction in the decoding instruction sequence, and determine the data reading position, decoding processing instruction position, and data writing position corresponding to each decoding instruction according to each decoding instruction; Step S503: Read the corresponding decoding input information from the soft decision metric graph structure according to the data reading position corresponding to each decoding instruction, and read the corresponding target decoding processing instruction according to the decoding processing instruction position; Step S504: Perform decoding processing on the decoding input information according to the target decoding processing instruction to generate soft decision bit information and hard decision bit information corresponding to each decoding instruction; Step S505: Determine a first data writing position from the soft decision metric graph structure and a second data writing position from the hard decision metric graph structure according to the data writing position corresponding to each decoding instruction, write the soft decision bit information to the first data writing position, and write the hard decision bit information to the second data writing position.

[0043] In some embodiments, optionally, the register can execute load / store instructions to load any content in the register into a general register or a dedicated register in the polar decoder. Specifically, refer to Figure 6 and Figure 7, first, the register executes the load instruction. According to the input data addresses, such as Addrx and Addry, it reads the input data x and y from the LLR matrix, and according to the input bit address, such as Addru, it reads the input bit u from the Bit matrix. Then, the decoder decodes the input data x and y to output the hard decision bit information u_bit and the soft decision bit information u_LLR (such as the above-mentioned soft decision metric output information). Finally, the register executes the store instruction. According to the input bit address Addru, it stores the hard decision bit information u_bit into the element corresponding to the input bit address Addru in the Bit matrix, and according to the write data address Addr_out, it stores the soft decision bit information u_LLR into the element corresponding to the write data address Addr_out in the LLR matrix.

[0044] In some embodiments, by way of example, the configuration of the decoding instruction is as follows: 0 / 1 / 2 / 3 / 4 / 5 / 6 / 7 idxBit / flagGF / addr_u / addr_a / addr_b / col_in / addr_o / col_out Among them, idxBit is the bit to be decoded, which is the logical index pointing to the leftmost column of the Bit matrix and is used to identify the target bit of the current decoding operation. idxBit corresponds to the original N coded bits (including information bits and frozen bits), which are represented by n bits, where n = log2N, that is, idxBit is an n-bit binary number with a value range of 0 to N - 1. For example, if N = 8 (n = 3), then idxBit ∈ {000, 001,..., 111} (decimal 0 to 7), and the value of idxBit is directly mapped to the row number of the Bit matrix. For example, when idxBit = 3, it points to the leftmost bit in the 3rd row of the Bit matrix; flag is the flag bit of the customized instruction (such as customized instruction G and customized instruction F), that is, the flag bit of the above-mentioned target decoding processing instruction, 1 bit; addr_u is the address of the input bit u (the definition of u is the input bit of the customized instruction G) and is used to read the input bit from the Bit matrix; addr_a is the row index of the LLR matrix and is used to read the input data from the LLR matrix; addr_b is the row index of the LLR matrix and is used to read the input data from the LLR matrix; addr_o is the row index of the LLR matrix and is used to write the output data; col_in is the column index of the LLR matrix and is used to read the input data; col_out is the column index of the LLR matrix and is used to write the output data.

[0045] In some embodiments, based on the RISC-V instruction set or other instruction sets, etc., the above-mentioned customized instructions are generated and stored in the general-purpose register. The customized instructions are the relevant hardware instructions of the polar decoder. Optionally, the customized instructions include customized instruction G and customized instruction F, etc. Customized instruction F is used to implement the non-linear operation based on the symbol and the minimum absolute value, and customized instruction G is used to implement the linear combination operation based on the conditional symbol flip.

[0046] The specific form of customized instruction F is as follows: decF(Lc,Ld) => La Input Lc, 8 bits; Input Ld, 8 bits; Output La, 8 bits; Procedure: signC = sign(Lc): Take the sign of Lc (such as +1 or -1); signD = sign(Ld): Take the sign of Ld (such as +1 or -1); La = signC * signD * MIN(ABS(Lc), ABS(Ld)): MIN(ABS(Lc), ABS(Ld)) is used to take the smaller one of the absolute values of Lc and Ld.

[0047] The specific form of customized instruction G is as follows: decG(Lc,Ld) => La; Input Lc, 8 bits; Input Ld, 8 bits; Input u, 1 bit; Output Lb, 8 bits; Procedure: If u = 0, signT = 1 else signT = -1; Lb = signT * Lc + Ld: Add Ld after adjusting the sign of Lc.

[0048] In some embodiments, referring to Figure 8 , Figure 8 is an optional flowchart of step S502 in the embodiments of the present application. Step S502 may include but is not limited to steps S601 to S604: Step S601, obtain the entry instruction in the decoding instruction sequence as the current decoding instruction; Step S602: Parse the current decoding instruction to determine the current data reading position, the current decoding processing instruction position, and the current data writing position; Step S603: When the current decoding instruction is the termination instruction in the decoding instruction sequence, stop instruction parsing; Step S604: When the current decoding instruction is not the above termination instruction, obtain the next instruction of the current decoding instruction as the current decoding instruction, and then return to the above Step S602.

[0049] In some embodiments, the decoding instruction sequence is stored in a dedicated register in the polar decoder. Assume that the decoding instruction sequence includes instructions 1 to N, and instructions 1 to N are sequentially executed. When the current decoding instruction is instruction N, stop instruction parsing.

[0050] Refer to Figure 9 , Figure 9 is an optional structural schematic diagram of a channel decoding device provided by an embodiment of the present application. This device is used to implement the above channel decoding method, and this device may include: The first module is used to obtain the log-likelihood ratio information to be decoded; The second module is used to obtain a preset decoding instruction sequence; The third module is used to perform decoding processing on the log-likelihood ratio information according to the decoding instruction sequence and output decoded bit information.

[0051] It can be understood that the content in the above method embodiments is applicable to the device embodiments of the present application. The functions specifically implemented by the device embodiments of the present application are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those of the above method embodiments.

[0052] An embodiment of the present application also provides an electronic device. The electronic device includes a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, the above channel decoding method is implemented. The electronic device may be any intelligent terminal including a tablet computer, etc.

[0053] It can be understood that the content in the above method embodiments is applicable to the device embodiments of the present application. The functions specifically implemented by the device embodiments of the present application are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those of the above method embodiments.

[0054] Please refer to Figure 10 , Figure 10 schematically shows the hardware structure of an electronic device in another embodiment. The electronic device includes: The processor 901 can be implemented in the form of a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, etc., and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present application; The memory 902 can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM), etc. The memory 902 can store an operating system and other application programs. When implementing the technical solutions provided in the embodiments of this specification through software or firmware, the relevant program codes are stored in the memory 902 and are called by the processor 901 to execute the channel decoding method of the embodiments of the present application; The input / output interface 903 is used to implement information input and output; The communication interface 904 is used to implement communication interaction between this device and other devices, and can implement communication through a wired method (such as USB, network cable, etc.) or through a wireless method (such as mobile network, WIFI, Bluetooth, etc.); The bus 905 transmits information between the various components of the device (such as the processor 901, the memory 902, the input / output interface 903, and the communication interface 904); Among them, the processor 901, the memory 902, the input / output interface 903, and the communication interface 904 are communicatively connected to each other inside the device through the bus 905.

[0055] The embodiments of the present application also provide a computer-readable storage medium, which stores a computer program, and when the computer program is executed by a processor, the above-mentioned channel decoding method is implemented.

[0056] It can be understood that the content in the above method embodiments is applicable to the embodiments of this storage medium. The functions specifically implemented by the embodiments of this storage medium are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those of the above method embodiments.

[0057] The memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. In addition, the memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state storage devices. In some embodiments, the memory may optionally include a memory remotely located relative to the processor, and these remote memories can be connected to the processor through a network. Examples of the above-mentioned network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0058] A channel decoding method, apparatus, electronic device, and storage medium provided by an embodiment of the present application obtain log-likelihood ratio information to be decoded, obtain a preset decoding instruction sequence, and perform decoding processing on the log-likelihood ratio information according to the decoding instruction sequence to output decoded bit information. It can achieve automated channel decoding based on the decoding instruction sequence, improve the efficiency, accuracy, and flexibility of decoding, reduce costs, and reduce the occupation of hardware resources.

[0059] The embodiments described in the embodiments of the present application are for more clearly illustrating the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. Those skilled in the art know that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of the present application are equally applicable to similar technical problems.

[0060] Those skilled in the art can understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and may include more or fewer steps than those shown in the figures, or combine certain steps, or different steps.

[0061] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, that is, they may be located in one place, or may be distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0062] Those of ordinary skill in the art can understand that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices can be implemented as software, firmware, hardware, and appropriate combinations thereof.

[0063] In the description of this application and the above-mentioned accompanying drawings, terms such as "first", "second", "third", "fourth", etc. (if any) are used to distinguish similar objects and do not necessarily describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances so that the embodiments of this application described here can be implemented in an order different from those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that comprises a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0064] It should be understood that in this application, "at least one (item)" means one or more, and "a plurality" means two or more. "And / or" is used to describe the association relationship of associated objects and indicates that three relationships can exist. For example, "A and / or B" can mean: only A exists, only B exists, and both A and B exist simultaneously. Among them, A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one (one) of the following" or its similar expressions refer to any combination of these items, including any combination of single items (ones) or plural items (ones). For example, at least one (one) of a, b, or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0065] In several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the above-mentioned division of units is only a logical function division. In actual implementation, there can be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection to each other can be through some interfaces. The indirect coupling or communication connection of devices or units can be in electrical, mechanical, or other forms.

[0066] The units described above as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0067] In addition, in each embodiment of the present application, each functional unit can be integrated into a processing unit, can exist separately as individual physical units, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

[0068] It should be recognized that the embodiments of the present invention can be implemented or carried out by computer hardware, a combination of hardware and software, or by computer instructions stored in a non-transitory computer-readable memory. The method can be implemented in a computer program using standard programming techniques including a non-transitory computer-readable storage medium configured with the computer program, wherein the storage medium so configured causes the computer to operate in a specific and predefined manner - according to the methods and drawings described in the specific embodiments. Each program can be implemented in a high-level procedural or object-oriented programming language to communicate with the computer system. However, if desired, the program can be implemented in assembly or machine language. In any case, the language can be a compiled or interpreted language. In addition, for this purpose the program is capable of running on a dedicated integrated circuit programmed for this purpose.

[0069] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or all or part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods in each embodiment of the present application. The aforementioned storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROM for short), random access memories (RAM for short), magnetic disks, or optical discs that can store programs.

[0070] The preferred embodiments of the embodiments of the present application have been described above with reference to the accompanying drawings, and thus do not limit the scope of the rights of the embodiments of the present application. Any modifications, equivalent replacements, and improvements made by those skilled in the art without departing from the scope and essence of the embodiments of the present application shall be within the scope of the rights of the embodiments of the present application.

Claims

1. A channel decoding method, characterized in that, The method includes the following steps: Obtain the log-likelihood ratio information to be decoded; Obtain a preset decoding instruction sequence; According to the decoding instruction sequence, perform decoding processing on the log-likelihood ratio information and output decoded bit information.

2. The channel decoding method according to claim 1, wherein The method further includes: Construct a soft decision metric graph structure template, where the soft decision metric graph structure template includes soft decision metric input information, soft decision metric output information, and decoding processing instruction information; Generate a corresponding hard decision metric graph structure according to the soft decision metric graph structure template.

3. The channel decoding method according to claim 2, wherein The obtaining of the log-likelihood ratio information to be decoded specifically includes: Obtain a polar code encoded signal; Process the polar code encoded signal to generate a soft decision input sequence; According to a preset decoding path state and the soft decision metric graph structure template, decode the soft decision input sequence to generate a corresponding soft decision metric graph structure, and use the soft decision metric graph structure as the log-likelihood ratio information.

4. The channel decoding method according to claim 2, wherein The obtaining of the preset decoding instruction sequence specifically includes: Obtain the current decoding processing path; Generate the decoding instruction sequence according to the current decoding processing path, the hard decision metric graph structure template, and the soft decision metric graph structure template.

5. The channel decoding method according to claim 3, wherein The performing of decoding processing on the log-likelihood ratio information according to the decoding instruction sequence and outputting decoded bit information specifically includes: Generate a hard decision metric graph structure corresponding to the soft decision metric graph structure according to the hard decision metric graph structure template; Successively obtain each decoding instruction in the decoding instruction sequence, and according to each decoding instruction, determine the data reading position, decoding processing instruction position, and data writing position corresponding to each decoding instruction; According to the data reading position corresponding to each decoding instruction, read the corresponding decoding input information from the soft decision metric graph structure, and according to the decoding processing instruction position, read the corresponding target decoding processing instruction; Perform decoding processing on the decoding input information according to the target decoding processing instruction to generate soft decision bit information and hard decision bit information corresponding to each decoding instruction; According to the data writing position corresponding to each decoding instruction, determine a first data writing position from the soft decision metric graph structure, determine a second data writing position from the hard decision metric graph structure, write the soft decision bit information to the first data writing position, and write the hard decision bit information to the second data writing position.

6. The channel decoding method according to claim 3, wherein The decoding of the soft decision input sequence according to a preset decoding path state and the soft decision metric graph structure template to generate a corresponding soft decision metric graph structure specifically includes: Decode the soft decision input sequence according to the soft decision metric graph structure template and the decoding path state, and output corresponding soft decision sequence decoding information; Obtain the data writing position of the soft decision metric input information in the soft decision metric graph structure template; Update the soft decision metric graph structure template according to the soft decision sequence decoding information and the data writing position to generate the soft decision metric graph structure.

7. The channel decoding method according to claim 5, characterized in that, Successively obtain each decoding instruction in the decoding instruction sequence, and determine, according to each of the decoding instructions, the data reading position, the decoding processing instruction position, and the data writing position corresponding to each of the decoding instructions, specifically including: Obtain the entry instruction in the decoding instruction sequence as the current decoding instruction; Perform instruction parsing on the current decoding instruction to determine the current data reading position, the current decoding processing instruction position, and the current data writing position; When the current decoding instruction is the termination instruction in the decoding instruction sequence, stop performing instruction parsing; When the current decoding instruction is not the termination instruction, obtain the next instruction of the current decoding instruction as the current decoding instruction, and then return to the step of performing instruction parsing on the current decoding instruction to determine the current data reading position, the current decoding processing instruction position, and the current data writing position.

8. A channel decoding device, characterized in that, The device includes: A first module, configured to obtain log-likelihood ratio information to be decoded; A second module, configured to obtain a preset decoding instruction sequence; A third module, configured to perform decoding processing on the log-likelihood ratio information according to the decoding instruction sequence, and output decoded bit information.

9. An electronic device, characterized in that, The electronic device includes a memory and a processor, the memory stores a computer program, and when the processor executes the computer program, the channel decoding method according to any one of claims 1 to 7 is implemented.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, the channel decoding method according to any one of claims 1 to 7 is implemented.

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