A channel estimation device based on power delay profile estimation

Abstract

This invention discloses a channel estimation device based on power delay spectrum estimation. First, resource particles for pilots are extracted from the frequency domain resource grid for different physical channels, and LS channel estimation is performed with the generated local pilots. Then, according to different physical channels, two strategies are employed: segmented calculation and inverted edge data, transforming the data into a power of 2 number of points. A radix-2 IFFT fast algorithm is used to convert the channel estimate at the pilot to the delay domain. A power delay spectrum window is calculated in the delay domain, and noise reduction processing is applied to the channel estimate at the pilot in the delay domain. Finally, a radix-2 FFT fast algorithm is used to interpolate and obtain the channel estimate in the full frequency domain. The data is then integrated and output according to different physical channels. This invention balances performance and implementation complexity, handles delay and hardware resources, improves the system's versatility, compatibility, portability, and scalability, and effectively solves the channel estimation problem based on FPGA or ASIC implementations.

Description

Technical Field

[0001] This invention belongs to the field of wireless technology, and specifically relates to a channel estimation device based on power delay spectrum estimation. Background Technology

[0002] Wireless communication environments are highly complex and variable, often influenced by factors such as terrain, buildings, and weather. These factors introduce challenges such as multipath effects, channel fading, time-varying characteristics, and frequency selectivity, making signals susceptible to interference and attenuation during transmission. In such environments, channel estimation plays a crucial role. Its core function is to accurately understand the impact on signals during transmission by estimating the state of the transmission channel. Channel estimation helps the system effectively compensate for signal distortion, track dynamic changes in the channel in real time, and adjust communication parameters according to current channel conditions. This capability enables the system to maintain a low bit error rate and strong anti-interference ability even in complex environments, ensuring stable communication quality.

[0003] Currently, there are relatively few implementations of the Minimum Mean Square Error (MMSE) channel estimation algorithm. Existing MMSE channel estimation algorithms require the results of least squares (LS) channel estimation and prior information such as the cross-correlation matrix of the frequency domain pilot band and the frequency domain full-band channel, as well as the autocorrelation matrix of the frequency domain pilot band.

[0004] Because the MMSE channel estimation algorithm involves matrix inversion and matrix multiplication, it is not conducive to hardware implementation on Field Programmable Gate Arrays (FPGAs) or Application Specific Integrated Circuits (ASICs). Therefore, MMSE channel estimation needs to be approximated and simplified to balance performance with requirements regarding implementation complexity, computational latency, and FPGA or ASIC hardware resource consumption. Furthermore, to use the radix-2 Fast Fourier Transform (FFT), the number of data points to be processed needs to be a power of 2. Currently, the mainstream algorithm pads non-power-of-2 data points with zeros to make them powers of 2; however, this strategy results in more severe spectral leakage and a significant performance degradation for the MMSE algorithm. Summary of the Invention

[0005] Purpose of the invention: To address the problems of current MMSE channel estimation algorithms being computationally complex and difficult to implement in hardware, and the severe spectral leakage and performance degradation when using the radix-2 FFT fast algorithm after padding non-power-of-2 data with zeros, the purpose of this invention is to provide a channel estimation device based on power delay spectrum estimation, which reduces the complexity of hardware implementation without sacrificing algorithm performance as much as possible.

[0006] Technical Solution: To achieve the above-mentioned objectives, this invention discloses a channel estimation device based on power delay spectrum estimation, used for receiver signal processing in wireless channels, specifically including:

[0007] The resource particle extraction module is used on the base station side or user terminal to extract resource particles that place pilots in the frequency domain resource grid according to the 3GPP protocol for different physical channels; the different physical channels include Physical Downlink Shared Channel (PDSCH), Physical Broadcast Channel (PBCH) and Physical Control Channel (PDCCH).

[0008] The LS channel estimation module is used to generate local pilot sequences and perform LS channel estimation with the received pilots;

[0009] The IFFT operation module is used to transform the data into a power of 2 number of points by employing two strategies: segmented calculation and inverted edge data, depending on different physical channels. The LS channel estimate at the pilot is then converted to the time delay domain through the inverse fast fourier transform (IFFT).

[0010] The power delay spectrum estimation and noise reduction module is used to calculate the power delay spectrum window in the time delay domain and to perform noise reduction processing on the channel estimate at the pilot in the time delay domain.

[0011] The FFT operation module is used to interpolate and obtain the channel estimate in the full frequency domain using the radix-2 FFT fast algorithm;

[0012] The integrated output module is used to integrate and output data based on different physical channels.

[0013] Furthermore, the device is deployed on an FPGA or ASIC hardware platform, with a unified fixed-point data bit width. The top-level module, internal sub-modules, and calling IP all use the unified AXI4-Stream interface protocol. The internal IPs of the modules all adopt a pipelined structure, and data processing adopts a parallel processing method.

[0014] Furthermore, the local pilot sequence is generated according to the protocol, specifically by modulating the gold pseudo-random sequence using Quadrature Phase Shift Keying (QPSK). In the physical shared channel, the generation of the gold sequence is related to factors such as the slot's sequence number in the radio frame, the scrambling ID, the number of Orthogonal Frequency Division Multiplexing (OFDM) symbols in a slot, and the OFDM symbol index placed by the DMRS in a slot. In the physical broadcast channel, the generation of the gold sequence is related to factors such as the SS / PBCH block index, the cell ID, and the half-frame indicator. In the physical control channel, the generation of the gold sequence is related to factors such as the slot's sequence number in the radio frame, the scrambling ID, the number of OFDM symbols in a slot, and the OFDM symbol index placed by the DMRS in a slot.

[0015] Furthermore, in the physical shared channel, different Bandwidth Part (BWP) configurations are supported. Therefore, based on the configuration information, such as the input RB size, the number of input frequency domain data points needs to be calculated. Then, a table is consulted to find the largest power of 2 point value less than the number of input frequency domain data points, and the input data is segmented according to the table lookup result. Specifically, the data is divided into two segments: the first half consists of data points with the first power of 2 points, and the second half consists of data points with the last power of 2 points. The first half starts from the top of the complete frequency domain data, and the second half starts from the bottom of the complete frequency domain data, with some overlap between the two ends. If the size of the input frequency domain data is exactly a power of 2, then both segments are the same size as the input frequency domain data itself, i.e., the original data is not segmented, which improves the versatility of the entire module. Then, IFFT fast calculations are performed on the two segments of data respectively.

[0016] Furthermore, in the physical broadcast channel, the pilot signals on the complete OFDM symbols in columns 2 and 4 of the physical broadcast block are used for estimation. Since the OFDM symbols in columns 2 and 4 of the synchronization broadcast block occupy 240 subcarriers in the frequency domain, and the pilots are spaced four times more sparsely, each column has a fixed 60 pilot data points. The last 4 data points are inverted, and the total data is padded to 64 points, then a 64-point IFFT fast operation is performed.

[0017] Furthermore, in the physical control channel, due to its resource mapping characteristics, pilot symbols are distributed across 1-3 OFDM symbols, exhibiting a four-fold sparse placement in the frequency domain. Therefore, based on configuration information such as the input RB size, it is necessary to calculate the number of input frequency domain data points, then look up the table to find the largest power of 2 points less than the input data size, and segment the input data according to the lookup result. Specifically, the data is divided into two segments: the first half consists of data with the first power of 2 points, and the second half consists of data with the last power of 2 points. The first half starts from the top of the complete frequency domain data, and the second half starts from the bottom, with some overlap between the two ends. If the input frequency domain data size is exactly a power of 2, then both segments are the same size as the input frequency domain data itself, meaning the original data is not segmented, thus improving the overall versatility of the module. Next, IFFT fast calculations are performed on both segments of data.

[0018] Furthermore, the power delay spectrum estimation includes the following steps:

[0019] (a) The LS channel estimate in the time delay domain is truncated and the first noise reduction is performed. The noise reduction window length is configured externally to the module.

[0020] (b) Calculate the power of the estimated LS channel at the pilot in the time delay domain;

[0021] (c) Calculate the average value of the estimated power values ​​of the LS channel on the same subcarrier within the same time slot or multiple time slots;

[0022] (d) Calculate the power spectrum soft window in the time delay domain by combining the noise power. The noise power is input from outside the module and then compared with the average power in the time delay domain obtained on the same subcarrier to obtain the numerator and denominator of the power time delay spectrum window. If the time delay domain power is less than the noise power and the noise power is 0, the denominator of the power time delay spectrum window is 1. If the time delay domain power is less than the noise power and the noise power is not 0, the denominator of the power time delay spectrum window is the noise power. Otherwise, the denominator of the power time delay spectrum window is the time delay domain power. If the time delay domain power is not less than the noise power, the numerator of the power time delay spectrum window is the time delay domain power minus the noise power. Otherwise, it is 0.

[0023] (e) Add a soft window to the LS channel estimate at the pilot in the time delay domain for secondary noise reduction.

[0024] Furthermore, in the physical shared channel, since the pilots are placed in a double-sparse manner, the LS channel estimate after time delay domain noise reduction is first padded with zeros so that the amount of data after zero padding is twice the amount of pilot data after segmentation. Then, the corresponding number of FFT calculations are performed to complete the frequency domain interpolation. Finally, the overlapping part of the frequency domain channel estimate obtained from the two interpolations is merged, and the complete frequency domain full channel estimate is output.

[0025] Furthermore, in the physical broadcast channel, since the pilots are placed in a four-fold sparse distribution, the LS channel estimate after time delay domain noise reduction is first padded with zeros so that the amount of data after zero padding is four times the amount of pilot data after segmentation. Then, the corresponding number of FFT calculations are performed to complete the frequency domain interpolation. Finally, the data is truncated to 240 points. The channel estimate on the third column of OFDM symbols of the SSB block can be obtained by averaging or interpolating the channel estimates on the second and fourth columns of OFDM symbols.

[0026] Furthermore, in the physical control channel, since the pilots are placed in a four-fold sparse manner, the LS channel estimate after time delay domain noise reduction is first padded with zeros so that the amount of data after zero padding reaches four times the amount of pilot data after segmentation. Then, the corresponding number of FFT calculations are performed to complete the frequency domain interpolation. Finally, the overlapping part of the frequency domain channel estimate obtained from the two interpolations is merged, and the complete frequency domain full channel estimate is output.

[0027] Beneficial effects: Compared with the prior art, the present invention has the following advantages:

[0028] 1. The architecture can support receiver channel estimation processing for multiple physical channels, including physical shared channels, physical broadcast channels, and physical control channels. It has good channel estimation performance under channel conditions such as Additive White Gaussian Noise (AWGN) and multipath channels, which improves the versatility of the module.

[0029] 2. By using segmented and reversed edge data, the data volume is controlled to a power of 2, making it easier to implement the FFT fast algorithm in hardware. This optimizes the spectrum leakage caused by zero padding and solves the problem of severe performance degradation caused by spectrum leakage.

[0030] 3. Data processing adopts a pipelined parallel processing method, which effectively reduces data processing latency;

[0031] 4. For the physical shared channel, it can support the configuration of different bandwidths; for the physical control channel, it can support channel estimation when the resource grid is discontinuous in the frequency domain due to interleaving, thus improving the system's compatibility.

[0032] 5. The rational design of the computing structure has unified the fixed-point data bit width, thereby saving hardware implementation resources;

[0033] 6. Use the unified AXI4-Stream interface protocol to improve module portability;

[0034] 7. The hardware implementation logic of the data processing module has been optimized, improving the module's scalability: When averaging the signal power value in the time delay domain, the average can be taken from multiple sets of additional pilots within a time slot or multiple sets of pilots and additional pilots within multiple time slots, thereby improving the overall performance. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of the channel estimation device based on power delay spectrum estimation according to a specific embodiment of the present invention.

[0036] Figure 2 This is a schematic diagram of the frequency domain resource grid structure of the PDSCH channel.

[0037] Figure 3 This is a schematic diagram of the implementation structure of the LS channel estimation module in a specific embodiment of the present invention.

[0038] Figure 4 This is a schematic diagram of the data segmentation implementation structure in a specific embodiment of the present invention.

[0039] Figure 5 This is a schematic diagram of the power delay spectrum window implementation structure in a specific embodiment of the present invention.

[0040] Figure 6 This is a schematic diagram of the power accumulation and averaging module implementation structure in a specific embodiment of the present invention.

[0041] Figure 7 This is a flowchart illustrating the power delay spectrum window calculation in a specific embodiment of the present invention.

[0042] Figure 8 This is a schematic diagram of the zero-padding module implementation structure in a specific embodiment of the present invention. Detailed Implementation

[0043] The technical solution of the present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0044] This invention discloses a channel estimation device structure based on power delay spectrum estimation, which can be deployed and implemented on an FPGA or ASIC hardware platform.

[0045] like Figure 1As shown, the channel estimation device based on power delay spectrum estimation includes a resource particle extraction module, an LS channel estimation module, an IFFT operation module, a power delay spectrum estimation and noise reduction module, an FFT operation module, and an integrated output module. The resource particle extraction module, used by the base station or user terminal, extracts the resource particles for placing pilots in the frequency domain resource grid according to the 3GPP protocol for different physical channels; these different physical channels include PDSCH, PBCH, and PDCCH channels. The LS channel estimation module generates a local pilot sequence according to the protocol and performs LS channel estimation with the received pilots. The IFFT operation module transforms the data into powers of 2 points according to different physical channels and converts the LS channel estimate at the pilot to the time delay domain using a radix-2 IFFT fast algorithm. The power delay spectrum estimation and noise reduction module calculates the power delay spectrum window in the time delay domain and performs noise reduction processing on the channel estimate at the pilot in the time delay domain. The FFT operation module interpolates and obtains the channel estimate in the full frequency domain using a radix-2 FFT fast algorithm. The integrated output module integrates and outputs the data according to different physical channels.

[0046] The workflow of the channel estimation device based on power delay spectrum estimation is as follows: At the receiving end, the upper-level module inputs frequency domain data, noise variance, and system configuration information, such as the size of the RB to be processed, and frame timing information including subcarrier index, OFDM symbol index, slot number index, and frame number index. After the frequency domain data is processed by the above process, the frequency domain channel coefficient estimate is output in units of slots.

[0047] In this embodiment, in the PDSCH, the time-frequency resource location of the demodulation reference signal (DMRS) is related to factors such as the duration of the physical channel within a time slot, the mapping method of the DMRS, and the additional pilot configuration. In the PBCH, the time-frequency resource location of the DMRS is placed on the 2nd, 3rd, and 4th symbols of the Synchronization Signal / PBCH (SSB). Within each Resource Block (RB), the specific mapping location of the DMRS is related to the cell ID configuration. In the PDCCH, the position of the DMRS on the resource grid is the 1st, 5th, and 9th resource particles in each resource block.

[0048] Figure 2 This is a schematic diagram of the frequency domain resource grid structure of a PDSCH channel. Taking the PDSCH channel as an example, in the resource particle extraction module, pilot symbols are first extracted based on the frequency domain location of the physical shared channel indicated in the physical control channel and the pilot mapping method, for subsequent channel estimation. There are various pilot mapping methods in the physical shared channel, such as... Figure 2As shown, the pilots are mapped onto the 3rd and 10th OFDM symbols in the time domain, and the frequency domain uses a 2x sparse mapping method.

[0049] For the PBCH channel, it is necessary to first locate the resource grid where the SSB is located, and then extract the complete pilot symbols in columns 2 and 4 of the PBCH for subsequent channel estimation.

[0050] For the PDCCH channel, blind detection is required, and then pilot symbols in the continuous frequency domain on the Control Resource Set (CORESET) are extracted for subsequent channel estimation.

[0051] Figure 3 This diagram illustrates the implementation structure of the LS channel estimation module. The main function of the LS channel estimation module is to perform LS channel estimation on the extracted received pilot and locally generated pilot sequences. Due to the special nature of the local pilot sequence, its magnitude is 1, and the only difference between different pilot symbols is their phase. The local pilot sequence is generated according to the protocol, specifically by performing orthogonal phase-shift coding (QPSK) modulation on the gold pseudo-random sequence. In the PDSCH channel, the generation of the gold sequence is related to factors such as the slot's sequence number in the radio frame, the scrambling ID, the number of OFDM symbols contained in a slot, and the OFDM symbol index placed by the DMRS in a slot. In the PBCH channel, the generation of the gold sequence is related to factors such as the SS / PBCH block index, the cell ID, and the half-frame indicator. In the PDCCH channel, the generation of the gold sequence is related to factors such as the slot's sequence number in the radio frame, the scrambling ID, the number of OFDM symbols contained in a slot, and the OFDM symbol index placed by the DMRS in a slot.

[0052] Specifically, the local pilot signal in the PDSCH channel is generated by QPSK modulation of the gold pseudo-random sequence, i.e.:

[0053]

[0054] Where r represents the generated demodulated reference signal, m represents the modulated symbol number, and c represents the pseudo-random sequence, which is generated as follows:

[0055] c(n) = [x1(n+N)] c )+x2(n+N c )]mod2

[0056] Where, N c =1600, the sequences x1(n) and x2(n) are defined as follows:

[0057] x1(n+31)=[x1(n+3)+x1(n)]mod2

[0058] x2(n+31)=[x2(n+3)+x2(n+2)+x2(n+1)+x2(n)]mod2

[0059] The initial values ​​of x1(n) and x2(n) are as follows:

[0060]

[0061] in, in, The number of OFDM symbols in a time slot. Here, l is the slot number within a frame, l is the OFDM symbol index for placing the DMRS within a slot, and n is the time slot number. SCID To scramble the ID, n SCID ∈{0,1} is given by the DMRS initialization field. Indicates an identifier associated with the reference signal. The parameters are given in the DMRS-DownlinkConfig IE. If the DMRS-DownlinkConfig IE is not provided, then... in The physical cell ID for the serving cell.

[0062] In the PBCH channel, the reference sequence and pseudo-random sequence are generated in the same way as those in the PDSCH channel, and the initialization values ​​are generated as follows:

[0063]

[0064] Where, n hf For PBCH half-frame indication, i SSB For the index of the SS / PBCH block, The physical cell ID for the serving cell.

[0065] In the PDCCH channel, the reference sequence and pseudo-random sequence are generated in the same way as the PDSCH, and the initialization values ​​are generated as follows:

[0066]

[0067] in, The number of OFDM symbols in a time slot. N is the slot number within a frame, l is the OFDM symbol index within a slot, and N is the time slot number. ID To scramble ID, N ID ∈{0,1} is given by the DMRS initialization field, N IDThe values ​​∈{0,1,…,65535} are given by the relevant parameters in pdcch-DMRS-ScramblingID. If pdcch-DMRS-ScramblingID is not provided, then… in The physical cell ID for the serving cell.

[0068] Due to the unique characteristics of the local pilot sequence, the hardware implementation of the LS channel estimation algorithm can leverage the CORDIC algorithm to transform division into phase rotation of the local pilot, thereby reducing hardware resource consumption and processing latency for FPGAs or ASICs. The module outputs the LS channel estimate at the pilot symbol.

[0069] The IFFT module primarily segments the frequency-domain LS channel estimate into powers of 2, then performs a fast IFFT operation to convert it into a delay-domain LS channel estimate. In a physical shared channel, different bandwidth configurations are supported. Therefore, based on configuration information such as the input RB size, the number of input frequency-domain data points needs to be calculated. Then, a table is consulted to find the largest power of 2 point value less than the number of input frequency-domain data points, and the input data is segmented according to the table lookup result. Specifically, the data is divided into two segments: the first half consists of data points with powers of 2, and the second half consists of data points with powers of 2. The first half starts from the beginning of the complete frequency-domain data, and the second half starts from the end, with some overlap between the two ends. If the input frequency-domain data size is exactly a power of 2, then both segments are the same size as the original input frequency-domain data, meaning the original data is not segmented, thus improving the module's versatility. Finally, a fast IFFT operation is performed on each of the two data segments.

[0070] In the physical broadcast channel, the pilot signals on the complete OFDM symbols in columns 2 and 4 of the physical broadcast block are used for estimation. Since the OFDM symbols in columns 2 and 4 of the synchronization broadcast block occupy 240 subcarriers in the frequency domain, and the pilots are spaced four times more sparsely, each column has a fixed 60 pilot data points. The last 4 data points are inverted, and the total data is padded to 64 points before a 64-point IFFT fast operation is performed.

[0071] In the physical control channel, due to its resource mapping characteristics, pilot symbols are distributed across 1-3 OFDM symbols, exhibiting a four-fold spacing in the frequency domain. Therefore, based on configuration information such as the input RB size, the number of input frequency domain data points needs to be calculated. Then, a table is consulted to find the largest power-of-two points less than the input data size, and the input data is segmented according to the table lookup result. Specifically, the data is divided into two segments: the first half consists of data with the first power-of-two points, and the second half consists of data with the last power-of-two points. The first half starts from the top of the complete frequency domain data, and the second half starts from the bottom, with some overlap between the two ends. If the input frequency domain data size is exactly a power of 2, then both segments are the same size as the original input frequency domain data, meaning no segmentation of the original data is performed, thus improving the overall versatility of the module. Next, IFFT fast calculations are performed on both segments of data.

[0072] For example, Figure 4 A schematic diagram illustrating the data segmentation structure. (Example) Figure 4 As shown in (a), for LS channel estimates with non-power-of-2 points in PDCCH and PDSCH, the data is divided into two segments of power-of-2 data, with some overlap between the two segments. If the LS channel estimate itself has a data size that is exactly a power of 2, then both segments are the original data, thus improving the module's versatility. The lengths of the extracted power-of-2 data segments can be obtained by looking up a table based on the input system configuration information, such as RB size.

[0073] like Figure 4 As shown in (b), for PBCH, the LS channel estimate is fixed at 60 data points. Therefore, the last data is reversed by 4 bits, that is, the 56th to 59th data points are directly reversed and concatenated after the 60th data point to form 64 data points, which is the smallest power of two data points greater than 60. This approach has better algorithm performance than segmenting into two 32-point data points.

[0074] like Figure 4 As shown in (c), the hardware implementation of the IFFT operation is as follows: the FFTIP core in an FPGA or ASIC hardware platform performs serial IFFT operations corresponding to powers of 2. By counting the frame timing information, the input delay domain channel estimate is divided into two segments of data with powers of 2. For the PDSCH and PDCCH channels, a FIFO IP is used for buffering; for the PBCH channel, a stack module is used to invert the data. Finally, the two segments of data are serially input into the FFT IP core. Based on externally input system configuration information, such as resource block size, the number of operation points, the flag bit of the last data, and the data validity flag bit are configured for dynamic FFT operation point configuration by the FFT IP.

[0075] Since the received data may be affected by noise, a first noise reduction operation is required for the time-delay domain data. The noise reduction window length is configured externally to the module; one window can be configured before and after the entire data segment to address frequency domain leakage. The output data of the FFT IP is truncated according to the window length, retaining the data within the preceding and following windows, while setting the data outside the windows to zero. The window length can be configured externally, improving the system's versatility and flexibility.

[0076] The power delay spectrum estimation and noise reduction module mainly calculates the power delay spectrum window in the delay domain and performs noise reduction on the channel estimate at the pilot in the delay domain. The power delay spectrum estimation includes the following steps: (a) truncating the LS channel estimate in the delay domain for the first noise reduction; (b) calculating the power of the LS channel estimate at the pilot in the delay domain; (c) calculating the average power value of the LS channel estimate on the same subcarrier within the same or multiple time slots; (d) calculating the power spectrum soft window in the delay domain in combination with the noise power; (e) adding the soft window to the LS channel estimate at the pilot in the delay domain for the second noise reduction.

[0077] Figure 5 This diagram illustrates the structure of the power delay spectral window implementation. The module primarily consists of a power accumulation and averaging module, a power delay spectral windowing module, a secondary windowing module, and a zero-padding module. The module calculates the power of the input complex signal data and averages the power over the same subcarrier of multiple OFDM symbols within the same time slot, or over the same subcarrier of multiple OFDM symbols within multiple time slots. The module supports window length calculation for both single and multi-time slots, improving its scalability and versatility.

[0078] The schematic diagram of the power accumulation and averaging module is shown below. Figure 6As shown, it mainly consists of two DSPIPs. The time-delay domain data after the first noise reduction is in complex form. The real and imaginary parts of the data are separated. First, the A*B+C function of the DSPIP is used to calculate the square of the real part. Ports A and B both input the real part of the data, while port C selects either the output data of the next-stage DSPIP or 0. Since this module also performs an accumulation function, when the input data is data from the first column of OFDM symbols to be accumulated, the selector chooses 0 as the input; if it is data from other columns of OFDM symbols within the same time slot, or data from OFDM symbols in subsequent time slots, the output of the second DSPIP is selected. The second DSPIP uses the A*B+C function to calculate the square of the imaginary part and sums it with the square of the real part. Ports A and B both input the imaginary part of the data, while port C selects the output result of the first DSPIP. The output of the second-level DSPIP needs to be selectively processed: if the accumulated value on the same subcarrier of multiple OFDM symbols in the same time slot has been calculated, or the accumulated value on the same subcarrier of multiple OFDM symbols in multiple time slots has been calculated, then the power value is averaged and output; if the accumulation calculation has not been completed, then the calculation result is stored in the FIFO, waiting for the input of data in the next group of OFDM symbols.

[0079] The power delay spectrum window generation module is mainly composed of DIV IPs. The generation method of the numerator and denominator of the power delay spectrum window is as follows: Figure 7 The flowchart for calculating the power delay spectrum window is shown. The noise power is input externally and then compared with the average power in the delay domain obtained on the same subcarrier to obtain the numerator and denominator of the power delay spectrum window. Specifically: if the delay domain power is less than the noise power and the noise power is 0, the denominator of the power delay spectrum window is 1; if the delay domain power is less than the noise power and the noise power is not 0, the denominator of the power delay spectrum window is the noise power; otherwise, the denominator of the power delay spectrum window is the delay domain power; if the delay domain power is not less than the noise power, the numerator of the power delay spectrum window is the delay domain power minus the noise power; otherwise, it is 0. Finally, the division operation is performed using the DIV IP core in the FPGA or ASIC hardware platform, and the power delay spectrum window is output. The rational design of the calculation structure here ensures that the numerator and denominator in the designed soft window are of similar magnitude, allowing the data to be calibrated according to a unified format. This avoids the problem of needing to increase the fixed-point data bit width when the divider result is too large or too small, thus saving hardware implementation resources.

[0080] In the secondary windowing module, the time delay domain LS channel estimation data after the first noise reduction is multiplied by the generated soft window result. This can be implemented through MULT IP in FPGA or ASIC. The module completes secondary noise reduction in the time delay domain.

[0081] like Figure 8The zero-padding module implementation diagram is shown. In this module, the data after secondary windowing needs to be zero-padding before output. Specifically, for the PDSCH channel, assuming the length of each power-of-2 data segment is N, since its pilot is twice as thin in the frequency domain, N zeros need to be padded between the effective data of the front and rear windows, making the total data length 2N. For the PBCH and PDCCH channels, assuming the length of each power-of-2 data segment is N, since its pilot is four times as thin in the frequency domain, 3N zeros need to be padded between the effective data of the front and rear windows, making the total data length 4N. The module outputs the LS channel estimation data after zero-padding in the time delay domain following secondary noise reduction.

[0082] The time-delay domain data after secondary noise reduction is input into the FFT operation module, and the corresponding configuration information, such as the number of operation points for the FFT IP, the flag bit of the last data, and the data validity flag bit, is configured. The number of FFT operation points can be obtained by looking up a table based on the input system configuration information, such as the resource block size.

[0083] The main function of the integrated output module is to integrate and output the segmented frequency domain data. For PDSCH and PDCCH channels, the overlapping portion of the segmented full-frequency domain channel estimates is averaged and output. For PBCH channels, the first 240 points of the frequency domain channel estimates are extracted as the channel estimates for the PBCH frequency domain channel. For the PBCH channel estimates on the incomplete OFDM symbols in the third column of the SSB, the channel estimates can be obtained by averaging or interpolating the channel estimates on the second and fourth columns of the OFDM symbols.

[0084] In the channel estimation device based on power delay spectrum estimation, the top-level module, internal sub-modules, and calling IP all use the unified AXI4-Stream interface protocol, improving module portability. The internal IPs of the modules all adopt a pipelined structure, and data processing employs a parallel processing method, effectively reducing data processing latency.

Claims

1. A channel estimation device based on power delay spectrum estimation, characterized in that, include: The resource particle extraction module is used to extract the resource particles in the frequency domain resource grid that contain pilots for different physical channels; the different physical channels include physical shared channels, physical broadcast channels and physical control channels; The LS channel estimation module is used to generate local pilot sequences and perform LS channel estimation with the pilots extracted by the resource particle extraction module. The IFFT operation module is used to transform the input frequency domain data into a power of 2 number of points by employing two strategies: segmented calculation and inverted edge data, based on different physical channels. The radix-2 IFFT fast algorithm is then used to convert the LS channel estimate at the pilot to the time delay domain. The power delay spectrum estimation and noise reduction module is used to calculate the power delay spectrum window in the time delay domain and to perform noise reduction processing on the channel estimate at the pilot in the time delay domain. The FFT operation module is used to input the time-delay domain channel estimate after noise reduction, and then interpolate it using the radix-2 FFT fast algorithm to obtain the full-frequency domain channel estimate. The integrated output module is used to integrate and output segmented frequency domain data according to different physical channels; In the physical broadcast channel, the reverse edge data strategy is adopted, which reverses the last few data points, fills the total data to the minimum power of 2 points, and then performs IFFT fast operation. In the physical control channel, a segmented calculation strategy is adopted. Based on the configuration information, the input frequency domain data volume is calculated. Then, a table is consulted to find the largest power of 2 point that is less than the input frequency domain data volume. The input data is then segmented according to the table lookup result: the data with the first power of 2 points is the first half, and the data with the second power of 2 points is the second half. The first half is taken from the top of the complete frequency domain data, and the second half is taken from the end of the complete frequency domain data. The two ends of the data overlap in the middle. If the input frequency domain data volume is exactly a power of 2, then both segments of data are the same size as the input frequency domain data itself. Then, IFFT fast calculation is performed on the two segments of data respectively.

2. The channel estimation device based on power delay spectrum estimation according to claim 1, characterized in that, The device is deployed on an FPGA or ASIC hardware platform, with a unified fixed-point data bit width. The top-level module, internal sub-modules, and calling IP all use the unified AXI4-Stream interface protocol. The internal IPs of the modules all adopt a pipelined structure, and data processing adopts a parallel processing method.

3. The channel estimation device based on power delay spectrum estimation according to claim 1, characterized in that, The local pilot is generated according to the protocol and QPSK modulation is performed using the gold sequence. In the physical shared channel, the generation of the gold sequence is related to the sequence number of the time slot in the radio frame, the scrambling ID, the number of OFDM symbols contained in a time slot, and the index of the OFDM symbols placed by the DMRS in a time slot. In the physical broadcast channel, the generation of the gold sequence is related to the SS / PBCH block index, cell ID, and half-frame indication; in the physical control channel, the generation of the gold sequence is related to the slot number in the radio frame, the scrambling ID, the number of OFDM symbols contained in a slot, and the OFDM symbol index placed by the DMRS in a slot.

4. The channel estimation device based on power delay spectrum estimation according to claim 1, characterized in that, In the physical shared channel, a segmented calculation strategy is adopted to support different bandwidth configurations. Based on the configuration information, the input frequency domain data volume is calculated. Then, a table is consulted to find the largest power of 2 point that is less than the input frequency domain data volume. The input data is then segmented according to the table lookup result: the data with the first power of 2 points is the first half, and the data with the second power of 2 points is the second half. The first half is taken from the top of the complete frequency domain data, and the second half is taken from the end of the complete frequency domain data. The two ends of the data overlap in the middle. If the input frequency domain data volume is exactly a power of 2, then both segments of data are the same size as the input frequency domain data itself. Then, IFFT fast calculation is performed on the two segments of data respectively.

5. A channel estimation device based on power delay spectrum estimation according to claim 1, characterized in that, The power delay spectrum estimation includes the following steps: (a) The time delay domain LS channel estimate is truncated and the first noise reduction is performed, wherein the noise reduction window length is configured externally to the module; (b) Calculate the power of the estimated LS channel at the pilot in the time delay domain; (c) Calculate the average value of the estimated power values ​​of the LS channel on the same subcarrier within the same time slot or multiple time slots; (d) Calculate the power spectrum soft window in the time delay domain by combining the noise power. The noise power is input from outside the module and then compared with the average power in the time delay domain obtained on the same subcarrier to obtain the numerator and denominator of the power time delay spectrum window. If the power in the time delay domain is less than the noise power and the noise power is 0, the denominator of the power time delay spectrum window is 1. If the power in the time delay domain is less than the noise power and the noise power is not 0, the denominator of the power time delay spectrum window is the noise power. Otherwise, the denominator of the power time delay spectrum window is the power in the time delay domain. If the power in the time delay domain is not less than the noise power, the numerator of the power time delay spectrum window is the power in the time delay domain minus the noise power. Otherwise, it is 0. (e) Add a soft window to the LS channel estimate at the pilot in the time delay domain for secondary noise reduction.

6. The channel estimation device based on power delay spectrum estimation according to claim 1, characterized in that, In the physical shared channel, the pilots are placed in a double-sparse manner. First, the LS channel estimate after time delay domain noise reduction is padded with zeros so that the amount of data after zero padding is twice the amount of pilot data after segmentation. Then, the corresponding number of FFT calculations are performed to complete the frequency domain interpolation. Finally, the overlapping part of the frequency domain channel estimate obtained by the two interpolations is merged, and the complete frequency domain full channel estimate is output.

7. The channel estimation device based on power delay spectrum estimation according to claim 1, characterized in that, In the physical broadcast channel, the pilots are placed in a four-fold sparse distribution. First, the LS channel estimate after time delay domain noise reduction is zero-padded so that the amount of zero-padded data is four times the amount of pilot data after segmentation. Then, FFT is performed on the corresponding number of points to complete frequency domain interpolation. Finally, the data is truncated to the original number of points. The channel estimate on the third column of OFDM symbols of the SSB block can be obtained by averaging or interpolating the channel estimates on the second and fourth columns of OFDM symbols.

8. A channel estimation device based on power delay spectrum estimation according to claim 1, characterized in that, In the physical control channel, the pilots are placed in a four-fold sparse distribution. First, the LS channel estimate after time delay domain noise reduction is padded with zeros so that the amount of data after zero padding is four times the amount of pilot data after segmentation. Then, the corresponding number of FFT calculations are performed to complete the frequency domain interpolation. Finally, the overlapping part of the frequency domain channel estimate obtained from the two interpolations is merged, and the complete frequency domain full channel estimate is output.

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