Display device and manufacturing method thereof
By integrating drive circuits with Micro LED chips during fabrication, the method addresses the inefficiencies of existing transfer technologies, improving yield and efficiency in Micro LED display production.
Patent Information
- Application Number
- CN202410003008.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-02
- Publication Date
- 2025-07-15
AI Technical Summary
The existing huge transfer technology cannot meet the mass production requirements of Micro LED display devices, and the transfer efficiency is low and the accuracy is insufficient, resulting in the yield failure to reach 99.9999%.
The driving circuit layer is first made on the Micro LED chip, instead of separately making the driving backplane and chip, and the independent epitaxial layer units are formed by etching and forming electrodes and driving circuit layers thereon, simplifying the huge transfer step.
It improves the production yield and efficiency of display devices, reduces the difficulty of mass production, and meets the high yield requirements of Micro LED display devices.
Smart Images
Figure CN120322079A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of display technology, and more specifically, to a display device and a manufacturing method thereof. Background Art
[0002] Light-emitting diode display technology is developing rapidly. Micro LED (Micro Light Emitting Diode) has attracted many scientific and technological workers to invest in research due to its outstanding advantages: small size, low power consumption, high color saturation, fast response speed and long life. However, due to the lack of mature mass transfer technology, Micro LED display devices have been unable to be mass-produced.
[0003] The chip pick-and-place technology used by traditional LEDs can no longer be used to transfer Micro LED chips with a size of less than 50μm from the substrate to the driver backplane, mainly because the vacuum tube can only be about 80um under the physical size limit, and only a few devices can be transferred at a time. Not only is the efficiency low, but the transfer accuracy is also very low, and it cannot be used in the mass production process of Micro LED. In addition, Micro LED display devices have extremely high requirements for transfer, and the yield rate must reach 99.9999%. At present, the yield rate of transfer technology (such as stamp transfer and laser transfer) is usually between 99.9% and 99.99%, which cannot meet the requirements of producing Micro LED display devices using mass transfer. Summary of the invention
[0004] The exemplary embodiments of the present application provide a display device and a method for manufacturing the same, which are used to solve the problem that Micro LED display devices cannot be mass-produced due to mass transfer.
[0005] The technical solutions provided by the embodiments of this application are as follows:
[0006] In a first aspect, the present application provides a method for manufacturing a display device, comprising:
[0007] Providing a substrate having an epitaxial layer and a first base plate, and attaching the first base plate to a side of the epitaxial layer facing away from the substrate;
[0008] Stripping the substrate, and etching the epitaxial layer to form at least two mutually independent epitaxial layer units;
[0009] An electrode is formed on a side of each epitaxial layer unit away from the first substrate, wherein the electrode includes a first electrode and a second electrode, and one epitaxial layer unit and the first electrode and the second electrode corresponding to the epitaxial layer unit constitute a light-emitting diode chip;
[0010] A driving circuit layer is formed on a side of the electrode facing away from the epitaxial layer unit.
[0011] In a second aspect, the present application provides a display device manufactured based on any one of the above manufacturing methods.
[0012] As can be seen from the above technical solutions, for the display device and its manufacturing method provided by the present application, a light-emitting diode chip is first manufactured, and then a driving circuit layer is directly manufactured on the light-emitting diode chip. Compared with separately manufacturing a driving backplane and a light-emitting diode chip, there is no need for the operation step of massive transfer of the light-emitting diode chip, reducing the mass production difficulty brought by massive transfer, and thus being beneficial to improving the production yield and production efficiency of the display device. BRIEF DESCRIPTION OF THE DRAWINGS
[0013] To more clearly illustrate the embodiments of the present application or the implementation manners in the related art, the following will briefly introduce the drawings required for use in the description of the embodiments or the related art. Obviously, the drawings in the following description are some embodiments of the present application, and those of ordinary skill in the art can also obtain other drawings based on these drawings.
[0014] Figure 1 FIG. shows a schematic flow chart of a manufacturing method of a display device in some embodiments;
[0015] Figures 2 - 7 FIG. shows schematic structural diagrams of each step in a manufacturing method of a display device in some embodiments;
[0016] Figure 8 is Figure 1 FIG. shows a refined flow chart of S130 in the manufacturing method of the display device shown;
[0017] Figure 9 is Figure 1 FIG. shows a refined flow chart of S140 in the manufacturing method of the display device shown;
[0018] Figures 10 - 31 FIG. shows schematic structural diagrams of each step in another manufacturing method of a display device in some embodiments. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0019] To make the objectives and implementation manners of the present application clearer, the following will clearly and completely describe the exemplary implementation manners of the present application with reference to the drawings in the exemplary embodiments of the present application. Obviously, the described exemplary embodiments are only a part of the embodiments of the present application, rather than all of the embodiments.
[0020] It should be noted that the brief description of terms in this application is only for the convenience of understanding the embodiments described below, and is not intended to limit the embodiments of this application. Unless otherwise specified, these terms should be understood according to their common and usual meanings.
[0021] The terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover but not exclude inclusion, for example, a product or device comprising a list of components is not necessarily limited to all the components expressly listed but may include other components not expressly listed or inherent to such product or device.
[0022] In some embodiments, Figure 1 As shown, the manufacturing method of the display device includes the following steps:
[0023] S110 , providing a substrate having an epitaxial layer and a first base plate, and attaching the first base plate to a side of the epitaxial layer facing away from the substrate.
[0024] Combination Figure 2 or Figure 10 The epitaxial layer 20 is located on one side of the substrate 1, and the two are stacked. The embodiment of the present application does not limit the type of the substrate 1, and all types of substrates known to those skilled in the art can be used, such as silicon, sapphire, gallium nitride, aluminum nitride, and silicon carbide substrates.
[0025] Combination Figure 3 or Figures 12 - 14 A temporary bonding layer 4 is formed on the surface of the epitaxial layer 20 facing away from the substrate, and a temporary bonding layer 4 is also formed on the surface of one side of the first substrate 51. The two temporary bonding layers 4 are placed opposite to each other to attach the first substrate 51 and the epitaxial layer 20. Exemplarily, the temporary bonding layer 4 includes adhesive or silicon oxide, and the first substrate 51 and the epitaxial layer 20 can be bonded by a thermal compression process.
[0026] The embodiment of the present application does not limit the material of the first substrate 51, and any plate with a flat surface can be used as the first substrate 51, such as a glass plate. The epitaxial layer 20 includes all film layers known to those skilled in the art, such as an undoped layer, a first doped layer, a second doped layer, and a light-emitting layer, which are not limited here.
[0027] S120, peeling off the substrate, etching the epitaxial layer, and forming at least two independent epitaxial layer units.
[0028] Combination Figure 4 Or 15, the epitaxial layer 20 attached with the first substrate 51 is turned over, that is, the substrate 1 is located above the epitaxial layer 20, and the substrate 1 can be peeled off by laser peeling or etching process. Figure 5Or 16, along the direction of the epitaxial layer 20 pointing to the first substrate 51, the epitaxial layer 20 is etched by an etching process, and the entire epitaxial layer 20 is divided into at least two independent epitaxial layer units 25, and there is a gap between adjacent epitaxial layer units 25. The etching process includes but is not limited to dry etching and wet etching, and also includes all processes with a splitting function known to those skilled in the art, and is not limited herein.
[0029] S130. Form electrodes on the side of each epitaxial layer unit facing away from the first substrate.
[0030] Combined Figure 6 , the electrode includes a first electrode 271 and a second electrode 272, and an epitaxial layer unit 25 and the corresponding first electrode 271 and second electrode 272 of the epitaxial layer unit 25 form a light-emitting diode chip 2. The light-emitting diode chip 2 includes but is not limited to a micro light-emitting diode (Micro LED) chip and a mini light-emitting diode (Mini LED).
[0031] In this step, first, a first blind hole and a second blind hole are formed in the epitaxial layer 20 by an etching process, and the depths of the first blind hole and the second blind hole are different, and then a first electrode is fabricated in the first blind hole and a second electrode is fabricated in the second blind hole by a deposition process. Exemplarily, the deposition process includes one of chemical vapor deposition (CVD) and physical vapor deposition (PVD).
[0032] S140. Form a driving circuit layer on the side of the electrode facing away from the epitaxial layer unit.
[0033] Combined Figure 7 , the driving circuit layer 3 is located on the side of the light-emitting diode 2 facing away from the first substrate 51. In this step, processes such as coating, physical vapor deposition, chemical vapor deposition, exposure, and etching can be used to fabricate the driving circuit layer 3. The driving circuit layer includes all types of driving circuit layers known to those skilled in the art, such as a thin film transistor (TFT) driving circuit layer or a complementary metal oxide semiconductor (CMOS) driving circuit layer, and is not limited herein.
[0034] The manufacturing method of the display device provided by the embodiment of the present application first manufactures the light-emitting diode chip 2, and then directly manufactures the driving circuit layer 3 on the light-emitting diode chip 2. Compared with separately manufacturing the driving backplane and the light-emitting diode chip, the operation step of massive transfer of the light-emitting diode chip 2 is not required, reducing the mass production difficulty brought by massive transfer, thereby facilitating the improvement of the production yield and production efficiency of the display device.
[0035] In some embodiments, before "providing a substrate with an epitaxial layer", the manufacturing method further includes the following steps:
[0036] Form an undoped layer on one side of the substrate;
[0037] Form a first doped layer on the side of the undoped layer away from the substrate;
[0038] Form a light-emitting layer on the side of the first doped layer away from the undoped layer;
[0039] Form a second doped layer on the side of the light-emitting layer away from the first doped layer;
[0040] Such as Figures 10 - 11 , Figure 10 is a cross-sectional view of the substrate 1 with the epitaxial layer 20, Figure 11 is Figure 10 The top view of the substrate 1 with the epitaxial layer 20 shown, and the epitaxial layer 20 includes an undoped layer 21, a first doped layer 22, a light-emitting layer 23, and a second doped layer 24 stacked in sequence on one side of the substrate 1.
[0041] In this embodiment, first form an undoped layer 21 on one side of the substrate 1, and the undoped layer 21 is located above the substrate. The undoped layer 21 can be directly grown using the material of the epitaxial layer. For example, the undoped layer can be made of materials such as u-Gallium nitride (u-GaN), etc., and is not limited herein.
[0042] After forming the undoped layer 21, form a first doped layer 22 above the undoped layer 21. The first doped layer 22 can be N-type doped or P-type doped in the original material of the epitaxial layer so that the first doped layer 22 can provide electrons or holes.
[0043] After forming the first doped layer 22, form a light-emitting layer 23 above the first doped layer 22. The light-emitting layer 203 can adopt a multi-quantum well layer to improve the light-emitting efficiency.
[0044] After the light-emitting layer 23 is formed, a second doping layer 24 is formed above the light-emitting layer 23. The first doping layer 22 and the second doping layer 24 are located on both sides of the light-emitting layer 23, and the doping types of the two doping layers are opposite. If the first doping layer 22 is N-type doped, the second doping layer 24 is P-type doped; if the first doping layer 22 is P-type doped, the second doping layer 204 is N-type doped. In specific implementation, the above two structures can both be applied, and are not limited herein.
[0045] In some embodiments, the first electrode includes a first columnar metal and a first pad, and the second electrode includes a second columnar metal and a second pad;
[0046] As Figure 8 shown, "S130. Form electrodes on the side of each epitaxial layer unit facing away from the first substrate" includes the following steps:
[0047] S231. Etch the epitaxial layer unit to form a first blind hole and a second blind hole. The first blind hole exposes the first doping layer, and the second blind hole exposes the second doping layer.
[0048] Combined with Figure 17 , etch the epitaxial layer unit 25 until the first doping layer 22 is exposed to form a first blind hole; etch the epitaxial layer unit 25 until the second doping layer 24 is exposed to form a second blind hole. The depth of the second blind hole is greater than the depth of the first blind hole.
[0049] S232. Form a first columnar metal in the first blind hole and a second columnar metal in the second blind hole. The first columnar metal is electrically connected to the first doping layer and insulated from the undoped layer. The second columnar metal is electrically connected to the second doping layer and insulated from the undoped layer, the first doping layer, and the light-emitting layer.
[0050] In this step, a first columnar metal 2711 is formed in the first blind hole by a deposition process, and the first columnar metal 2711 protrudes from the first blind hole. The first columnar metal 2711 is electrically connected to the first doping layer 22, and there is a gap between the first columnar metal 2711 and the undoped layer 21 exposed on the side wall of the first blind hole, that is, the first columnar metal 2711 is insulated from the undoped layer 21. Similarly, a second columnar metal 2721 is formed in the second blind hole, and the second columnar metal 2721 protrudes from the second blind hole. The second columnar metal 2721 is electrically connected to the second doping layer 24, and there are gaps between the second columnar metal 2721 and the undoped layer 21, the first doping layer 22, and the light-emitting layer 22 exposed on the side wall of the second blind hole, that is, the second columnar metal 2721 is insulated from the undoped layer 21, the first doping layer 22, and the light-emitting layer 22 exposed on the side wall of the second blind hole.
[0051] S233. Form a first dielectric layer on the side of the epitaxial layer unit facing away from the first substrate. The first dielectric layer fills the gaps between the sidewalls of the first columnar metal and the first blind hole, and between the sidewalls of the second columnar metal and the second blind hole, covers the surface of the epitaxial layer unit on the side facing away from the first substrate, and exposes the first columnar metal and the second columnar metal.
[0052] In this step, a first dielectric layer 26 is formed on the side of the epitaxial layer unit 25 facing away from the first substrate 51 by using a deposition process. The first dielectric layer 26 is made of an insulating material, such as silicon dioxide. The first dielectric layer 26 fills the gaps between the sidewalls of the first columnar metal 2711 and the first blind hole, and between the sidewalls of the second columnar metal 2721 and the second blind hole, so that the first columnar metal 2711 is insulated from the undoped layer 21, and the second columnar metal 2721 is insulated from the undoped layer 21, the first doped layer 22, and the light-emitting layer 22 exposed on the sidewall of the second blind hole. The first dielectric layer 26 also wraps the portions of the first columnar metal 2711 protruding from the first blind hole and the second columnar metal 2721 protruding from the second blind hole, and covers the surface of the epitaxial layer unit 25 on the side facing away from the first substrate 51. Then, the first dielectric layer 26 is etched until the first columnar metal 2711 and the second columnar metal 2721 are exposed.
[0053] S234. Form a first pad and a second pad on the side of the first dielectric layer facing away from the epitaxial layer unit. The first pad is electrically connected to the first columnar metal, and the second pad is electrically connected to the second columnar metal.
[0054] In this step, an electrode layer is formed on the side of the first dielectric layer 26 facing away from the epitaxial layer unit 5 by using a deposition process. The electrode layer is etched to form the pattern of the first pad 2712 and the pattern of the second pad 2722. The first pad 2712 is electrically connected to the first columnar metal 2711, and the second pad 2722 is electrically connected to the second columnar metal 2721.
[0055] In some embodiments, as Figure 9 shown, "S140. Form a driving circuit layer on the side of the electrode facing away from the epitaxial layer" includes the following steps:
[0056] S341. Form a first planarization layer on the side of the first pad facing away from the first dielectric layer. The first planarization layer covers the first pad, the second pad, and the first dielectric layer, and also fills the gaps between adjacent epitaxial layer units.
[0057] In this step, in combination with Figure 18, a first flat layer 31 is formed on the side of the first pad 2712 away from the first dielectric layer 26, and the first flat layer 31 is provided as a whole layer, covering the first pad 2712, the second pad 2722 and the surface of the first dielectric layer 26 away from the epitaxial layer unit 25, and also filling the gap between adjacent epitaxial layer units 25. The gap between adjacent epitaxial layer units 25 is formed by etching the epitaxial layer in step S120, and the first flat layer 31 is filled in the gap to prevent optical crosstalk between adjacent light-emitting diode chips.
[0058] S342, forming a patterned source-drain layer on a side of the first planar layer away from the first electrode, the source-drain layer comprising a source electrode and a drain electrode, one of the source electrode and the drain electrode being electrically connected to the second pad through a via hole penetrating the first planar layer.
[0059] In this step, combine Figures 18 - 20 , the first flat layer 31 is etched to form a via hole at the first flat layer 31 corresponding to the first pad 2712 and the second pad 2722, the via hole including a conductive structure, and the form of the conductive structure in the embodiment of the present application is not limited, Figures 19 - 20 The conductive structure is shown as a metal column M1 filled in the via hole by way of example only. The conductive structure may also be set as a metal line located on the side wall of the via hole, which is not limited here.
[0060] The first planar layer 31 includes at least one layer. Figure 20 As shown, the first flat layer 31 includes two layers. After forming the first flat layer 31, a via hole penetrating the first flat layer 31 is made, and then the second first flat layer 31 is formed, and the via holes penetrating the first flat layer 31 are further made. The via holes between the two first flat layers 31 are electrically connected.
[0061] A photoresist layer is coated on the surface of the first flat layer 31 on one side away from the first electrode 271, and a target pattern is obtained by exposure and development, and a source-drain layer 32 is manufactured by physical vapor deposition or chemical vapor deposition. The source-drain layer 32 includes a source electrode and a drain electrode, and there is a gap between the source electrode and the drain electrode. Since the power supply is alternating current, the source electrode and the drain electrode are not distinguished, and one of the source electrode and the drain electrode is electrically connected to the second pad 2722 of the second electrode 272 through a via hole penetrating the first flat layer 31.
[0062] S343, forming a semiconductor layer on a side of the source and drain layer away from the first planar layer, wherein the semiconductor layer covers at least a portion of the source electrode and at least a portion of the drain electrode.
[0063] Combination Figure 21, a semiconductor layer 33 of a whole layer is formed on a side of the source-drain layer 32 facing away from the first flat layer 31 by using a physical vapor deposition or chemical vapor deposition process, and then a target pattern is obtained after exposure and development processes. The semiconductor layer 33 of the target pattern fills a gap between the source electrode and the drain electrode and covers at least part of the source electrode and at least part of the drain electrode to realize the connection between the source electrode and the drain electrode. The semiconductor layer 33 can be made of materials such as amorphous silicon, polycrystalline silicon, and metal oxide, which is not limited herein.
[0064] S344. A second dielectric layer is formed on a side of the semiconductor layer facing away from the source-drain layer. The second dielectric layer covers the semiconductor layer, the source-drain electrodes, and a surface of the first flat layer facing away from the first dielectric layer.
[0065] Combine Figure 22 , a second dielectric layer 34 is formed on a side of the semiconductor layer 33 facing away from the source-drain layer 32 by using a physical vapor deposition or chemical vapor deposition process. The second dielectric layer 34 is provided as a whole layer. The second dielectric layer 34 can be made of materials such as silicon oxide and / or silicon nitride.
[0066] S345. A gate layer and a power supply lead are formed on a side of the second dielectric layer facing away from the semiconductor layer. Along the direction from the epitaxial layer unit to the driving circuit layer, the gate layer is located within the projection of the semiconductor layer. The power supply lead is electrically connected to the first pad through a via hole penetrating the second dielectric layer and the first flat layer.
[0067] Combine Figure 23 , the second dielectric layer 34 and the first flat layer 31 at the position of the first electrode 271 (or the first pad 2712) are etched to form a through hole penetrating the second dielectric layer 34 and the first flat layer 31. A conductive structure is made in the through hole to form a via hole, and the via hole is electrically connected to the first electrode 271 (or the first pad 2712). Then, a power supply lead 35 and a gate layer 36 are made by using a physical vapor deposition or chemical vapor deposition process. The power supply lead 35 is located on a side of the second dielectric layer 34 facing away from the via hole, and the power supply lead 35 is electrically connected to the via hole, so as to lead the first electrode 271 onto the second dielectric layer 34. The gate layer 36 is located on a side of the second dielectric layer 31 facing away from the semiconductor layer 33. Along the direction from the epitaxial layer unit 25 to the driving circuit layer 3, the gate layer 36 is located within the projection of the semiconductor layer 33.
[0068] S346. A second flat layer is formed on a side of the gate layer facing away from the second dielectric layer.
[0069] Combine Figure 24 , the second flat layer 37 covers the gate layer 36, the power supply lead 35, and a surface of the second dielectric layer 34 facing away from the semiconductor layer that is not occupied by the gate layer 36 and the power supply lead 35. The second flat layer 37 can be made of an organic material and is cured and formed by using a UV curing or thermal curing process.
[0070] In some embodiments, after "forming a driving circuit layer on the side of the electrode facing away from the epitaxial layer" in S140, the manufacturing method further includes the following steps:
[0071] Form a support pillar and a first adhesive on the side of the second flat layer facing away from the gate layer. Along the direction from the epitaxial layer unit to the driving circuit layer, the projection of the support pillar at least partially overlaps with the projection of the semiconductor layer, and the first adhesive covers the surface of the second flat layer on the side facing away from the second dielectric layer that is not occupied by the support pillar;
[0072] Provide a second substrate and attach the second substrate to the side of the driving circuit layer facing away from the light-emitting diode chip.
[0073] In this embodiment, in combination with Figure 25 , the support pillar 38 is located directly above the semiconductor layer 33 and is used to provide a supporting force after the wafer transfer operation to protect the structures above it (including the gate layer 36 and the semiconductor layer 33). The support pillar 38 can be prepared from photoresist materials, including RGB glue, BM glue, OC glue, PS glue, and TFT glue, etc. The first adhesive 39 is located on the surface of the second flat layer 37 on the side facing away from the second dielectric layer 34 that is not occupied by the support pillar 38. In combination with Figure 26 , the second substrate 52 is thermocompression bonded to the side of the driving circuit layer 3 facing away from the light-emitting diode layer 2, so that the first substrate is bonded to the first adhesive 39.
[0074] In some embodiments, "attaching the first substrate to the side of the epitaxial layer facing away from the substrate" includes the following steps:
[0075] Form a temporary bonding layer on the side of the first substrate facing the epitaxial layer on the side of the epitaxial layer facing away from the substrate;
[0076] Attach the first substrate to the epitaxial layer using a thermocompression bonding process. The temporary bonding layer includes an adhesive or a silicon oxide layer.
[0077] In this embodiment, in combination with 12-14, a temporary bonding layer 4 is formed on one side surface of the first substrate 51, and a temporary bonding layer 4 is also formed on the side surface of the epitaxial layer 20 facing away from the substrate 1. The two temporary bonding layers 4 are opposed to each other, and the first substrate 51 is attached to the epitaxial layer 20 using a thermocompression bonding process. The temporary bonding layer 4 can be formed by coating an adhesive or by chemical vapor deposition of a silicon oxide layer.
[0078] In some embodiments, the manufacturing method further includes the following steps:
[0079] Remove the first substrate to expose the epitaxial layer unit;
[0080] Provide a cover plate and attach the cover plate to the side of the epitaxial layer unit facing away from the driving circuit layer.
[0081] In this embodiment, first, the structure shown in Figure 26 is flipped upside down. As shown in Figures 27 - 28 , the first substrate 51 is located at the uppermost position. By using laser debonding or chemical etching methods, the first substrate 51 is removed, and then the temporary bonding layer 4 is washed away, exposing the epitaxial layer unit 25 (or the second doping layer 24). When the first substrate 51 is a light-transmissive plate, such as a glass substrate, the first substrate 51 can be removed by laser debonding. When the first substrate 51 is an opaque material, such as a silica substrate or a ceramic substrate, the first substrate 51 can be removed by chemical etching. Exemplarily, a strong acid solution can be used to wash away the temporary bonding layer 4.
[0082] In other embodiments, the first substrate 51 can also be removed by thermal debonding, but the heating temperature needs to be controlled so that the various component structures of the display device fabricated in the previous steps will not be damaged during the heating process.
[0083] Combined with Figure 29 , a second adhesive 6 is coated on the side of the epitaxial layer unit 25 (or the second doping layer 24) facing away from the driving circuit layer 3, and the cover plate 71 is attached to the surface of the side of the epitaxial layer unit 25 (or the second doping layer 24) facing away from the driving circuit layer 3. The second adhesive 6 is colorless and has a high light transmittance, and does not affect the display effect of the display device. The cover plate 71 includes all types of cover plates known to those skilled in the art, such as glass cover plates and liquid crystal cover plates, and is not limited herein.
[0084] In some embodiments, "attaching the cover plate to the side of the epitaxial layer unit facing away from the driving circuit layer" includes the following steps:
[0085] Coat a second adhesive on the side of the epitaxial layer unit facing away from the driving circuit layer;
[0086] Attach the cover plate to the epitaxial layer unit coated with the second adhesive. The surface of the side of the cover plate facing the epitaxial layer unit includes a quantum dot layer, and the quantum dot layer corresponds to the epitaxial layer unit one by one.
[0087] As shown in Figures 29 - 31 , a second adhesive 6 is coated on the side of the epitaxial layer unit 25 (or the second doping layer 24) facing away from the driving circuit layer 3. One side of the cover plate 71 is provided with a quantum dot layer 72. The quantum dot layer 72 is opposed to the second adhesive 6, and the cover plate 71 is attached to the epitaxial layer unit 25 (or the second doping layer 24). The second adhesive 6 has a high light transmittance and does not affect the display effect of the display device. The quantum dot layer 72 corresponds to the epitaxial layer unit 25 one by one, that is, each light-emitting diode chip corresponds to a quantum dot layer.
[0088] Quantum dots are semiconductor materials at the nanoscale. When a certain electric field or light pressure is applied to this nanoscale semiconductor material, they will emit light of a specific frequency, and the frequency of the emitted light will change with the change in the size of this semiconductor. Therefore, by adjusting the size of this nanoscale semiconductor, the color of the light it emits can be controlled. By adjusting the size of the semiconductor in the quantum dot layer 72, the quantum dot layer 72 emits light of the target color. For example, as Figure 30 shown, the quantum dot layer 72 includes three quantum dot layers of RGB, which emit red, green, and blue light respectively, thus realizing the color display of the display device.
[0089] In some embodiments, before "providing the cover plate", the manufacturing method further includes the following steps:
[0090] Using an inkjet printing or spin coating process to form a quantum dot layer and a light isolation layer on the side of the cover plate facing the epitaxial layer unit, and the light isolation layer is located in the gap between adjacent quantum dot layers.
[0091] In this embodiment, as Figure 30 shown, the side of the cover plate 71 facing the epitaxial layer unit 25 (or the second doping layer 24) further includes a light isolation layer 72, and the light isolation layer 72 is located in the gap between adjacent quantum dot layers 72, and is used to prevent optical crosstalk of the light emitted by the quantum dot layer 72. Other methods known to those skilled in the art can also be used to manufacture the quantum dot layer 72 and the light isolation layer 73, such as spraying, flow coating, or scraping, etc., which are not limited herein. The quantum dot layer 72 corresponds to the epitaxial layer unit 25, and the light isolation layer 73 corresponds to the gap between the epitaxial layer units 25.
[0092] It should be noted that the present application embodiment does not limit the preparation sequence of the quantum dot layer 72 and the light isolation layer 73. It can be manufactured one by one from one side edge of the cover plate to the opposite side, or the quantum dot layer 72 can be manufactured first and then the light isolation layer 73, or the light isolation layer 73 can be manufactured first and then the quantum dot layer, or the quantum dot layer 72 and the light isolation layer 73 can be manufactured simultaneously, which are not limited herein.
[0093] In some embodiments, as Figure 29 shown, the second adhesive 6 is no longer provided as a whole layer. The second adhesive 6 corresponds to the epitaxial layer unit 25 one by one, and there is a gap between adjacent second adhesives 6, and this gap corresponds to the gap between the epitaxial layer units 25. A second light isolation layer is provided in the gap between the second adhesives 6. When the light emitted by the light emitting unit 23 passes through the second adhesive 6, the second light isolation layer is used to prevent optical crosstalk.
[0094] Based on the above embodiments, the present application embodiment further provides a display device, which is manufactured based on the manufacturing method of any of the above display devices and has corresponding beneficial effects. To avoid repeated description, it will not be elaborated herein.
[0095] In some embodiments, as Figure 7 shown, the display device includes:
[0096] A light-emitting diode chip 2, including at least two independent epitaxial layer units 25 and electrodes. The electrodes include a first electrode 271 and a second electrode 272. One epitaxial layer unit 25 and the corresponding first electrode 271 and second electrode 272 of this epitaxial layer unit form a light-emitting diode chip 2;
[0097] A driving circuit layer 3, located on the side of the electrode facing away from the epitaxial layer unit 25.
[0098] In some embodiments, as Figure 10 shown, the epitaxial layer unit 25 includes an undoped layer 21, a first doped layer 22, a light-emitting layer 23, and a second doped layer 24 which are stacked.
[0099] In some embodiments, as Figure 17 shown, the first electrode 271 includes a first columnar metal 2711 and a first pad 2712, and the second electrode 272 includes a second columnar metal 2721 and a second pad 2722; each epitaxial layer unit 25 further includes:
[0100] A first blind hole and a second blind hole. The first blind hole exposes the first doped layer, and the second blind hole exposes the second doped layer. The first columnar metal 2711 is located in the first blind hole, electrically connected to the first doped layer 22 and insulated from the undoped layer 21. The second columnar metal 2721 is located in the second blind hole, electrically connected to the second doped layer 24 and insulated from the undoped layer 21, the first doped layer 22, and the light-emitting layer 23;
[0101] A first dielectric layer 26, located on the side of the undoped layer 21 facing away from the first doped layer 22. The first dielectric layer 26 fills the gaps between the first columnar metal 2711 and the side walls of the first blind hole and between the second columnar metal 2721 and the side walls of the second blind hole, covers the surface of the undoped layer 21 on the side facing away from the first doped layer 22 and exposes the first columnar metal 2711 and the second columnar metal 2712;
[0102] Wherein, the first pad 2712 and the second pad 2722 are located on the side of the second dielectric layer 26 facing away from the undoped layer 21. The first pad 2712 is electrically connected to the first columnar metal 2711, and the second pad 2722 is electrically connected to the second columnar metal 2721.
[0103] In some embodiments, as Figures 18 - 24 shown, the driving circuit layer 3 includes:
[0104] The first flat layer 31 is located on the side of the first pad 2712 facing away from the first dielectric layer 26, covering the first pad 2712, the second pad 2722, and the surface of the first dielectric layer 26 on the side facing away from the epitaxial layer unit 25, and also filling the gaps between adjacent epitaxial layer units 25;
[0105] The source-drain layer 32 is located on the side of the first flat layer 31 facing away from the first electrode. The source-drain layer 32 includes a source electrode and a drain electrode, and one of the source electrode and the drain electrode is electrically connected to the second pad 2722 of the second electrode 272 passing through the first flat layer 31;
[0106] The semiconductor layer 33 is located on the side of the source-drain layer 32 facing away from the first flat layer 31. The semiconductor layer 33 fills the gap between the source electrode and the drain electrode and covers at least part of the source electrode and at least part of the drain electrode to realize the connection between the source electrode and the drain electrode;
[0107] The second dielectric layer 34 is located on the side of the semiconductor layer 33 facing away from the source-drain layer 32, covering the surface of the semiconductor layer 33 on the side facing away from the source-drain layer 32, and also covering the surface of the first flat layer 31 on the side facing away from the first dielectric layer 26;
[0108] The power supply lead 35 is located on the side of the second dielectric layer 34 facing away from the first flat layer 31 and is electrically connected to the first pad 2711 of the first electrode 271 through a via hole passing through the second dielectric layer 34 and the first flat layer 31;
[0109] The gate layer 36 is located on the side of the second dielectric layer 34 facing away from the semiconductor layer 33. Along the direction of the epitaxial layer unit 25 pointing to the driving circuit layer 3, the projection of the gate layer 36 is within the projection of the semiconductor layer 33;
[0110] The second flat layer 37 is located on the side of the gate layer facing away from the second dielectric layer, covering the gate layer 36, the power supply lead 35, and the surface of the second dielectric layer 34 on the side facing away from the semiconductor layer that is not occupied by the gate layer 36 and the power supply lead 35.
[0111] In some embodiments, as Figures 25 - 26 shown, the display device further includes:
[0112] The support pillar 38 is located on the side of the second flat layer 37 facing away from the gate layer 36. Along the direction of the epitaxial layer unit 25 pointing to the driving circuit layer 3, the projection of the support pillar 38 overlaps at least part of the projection of the semiconductor layer 33;
[0113] The first adhesive 39 is located on the surface of the second flat layer 37 on the side facing away from the second dielectric layer 34 that is not occupied by the support pillar 38.
[0114] In some embodiments, as Figure 31 shown, the display device further includes:
[0115] The cover plate 71 is located on the side of the epitaxial layer unit 25 away from the driving circuit layer 3.
[0116] In some embodiments, as Figure 31 shown, in this display device, a second adhesive 6 is coated on the side of the epitaxial layer unit 25 away from the driving circuit layer 3, and a quantum dot layer 72 is provided on the side of the cover plate 71 facing the epitaxial layer unit 25, and the quantum dot layers 72 correspond to the epitaxial layer units 25 one by one.
[0117] In some embodiments, as Figure 31 shown, in this display device, a light shielding layer 73 is further provided on the side of the cover plate 71 facing the epitaxial layer unit 25, and the light shielding layer 73 is located in the gap between adjacent quantum dot layers 72.
[0118] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.
[0119] For the sake of convenience of explanation, the above description has been made in conjunction with specific embodiments. However, the above exemplary discussion is not intended to be exhaustive or to limit the embodiments to the specific forms disclosed above. According to the above teachings, various modifications and variations can be obtained. The selection and description of the above embodiments are for the purpose of better explaining the principles and practical applications, so that those skilled in the art can better use the embodiments and various different variations of the embodiments suitable for specific use considerations.
Claims
1. A manufacturing method of a display device, characterized in that, include: Providing a substrate having an epitaxial layer and a first base plate, and attaching the first base plate to a side of the epitaxial layer facing away from the substrate; Stripping the substrate, and etching the epitaxial layer to form at least two mutually independent epitaxial layer units; An electrode is formed on a side of each epitaxial layer unit away from the first substrate, wherein the electrode includes a first electrode and a second electrode, and one epitaxial layer unit and the first electrode and the second electrode corresponding to the epitaxial layer unit constitute a light-emitting diode chip; A driving circuit layer is formed on a side of the electrode away from the epitaxial layer unit.
2. The manufacturing method according to claim 1, wherein, Before providing the substrate having the epitaxial layer, the manufacturing method further includes: forming an undoped layer on one side of the substrate; forming a first doped layer on a side of the undoped layer facing away from the substrate; forming a light-emitting layer on a side of the first doped layer away from the undoped layer; forming a second doping layer on a side of the light-emitting layer away from the first doping layer; The epitaxial layer includes the undoped layer, the first doped layer, the light-emitting layer and the second doped layer which are sequentially stacked on one side of the substrate.
3. The manufacturing method according to claim 2, characterized in that, The first electrode includes a first columnar metal and a first pad, and the second electrode includes a second columnar metal and a second pad; The step of forming an electrode on a side of each epitaxial layer unit away from the first substrate comprises: Etching the epitaxial layer unit to form a first blind hole and a second blind hole, wherein the first blind hole exposes the first doped layer, and the second blind hole exposes the second doped layer; Forming a first columnar metal in the first blind hole, and forming a second columnar metal in the second blind hole, wherein the first columnar metal is electrically connected to the first doped layer and insulated from the undoped layer, and the second columnar metal is electrically connected to the second doped layer and insulated from the undoped layer, the first doped layer and the light-emitting layer; forming a first dielectric layer on a side of the epitaxial layer unit away from the first substrate, the first dielectric layer filling a gap between the first columnar metal and the sidewall of the first blind hole and a gap between the second columnar metal and the sidewall of the second blind hole, covering a surface of the epitaxial layer unit away from the first substrate and exposing the first columnar metal and the second columnar metal; The first pad and the second pad are formed on a side of the first dielectric layer away from the epitaxial layer unit. The first pad is electrically connected to the first columnar metal, and the second pad is electrically connected to the second columnar metal.
4. The manufacturing method according to claim 3, characterized in that, The step of forming a driving circuit layer on a side of the electrode away from the epitaxial layer unit comprises: forming a first planar layer on a side of the first pad facing away from the first dielectric layer, wherein the first planar layer covers the first pad, the second pad and the first dielectric layer, and also fills the gaps between adjacent epitaxial layer units; forming a patterned source-drain layer on a side of the first planar layer away from the first electrode, the source-drain layer comprising a source electrode and a drain electrode, one of the source electrode and the drain electrode being electrically connected to the second pad through a via hole penetrating the first planar layer; A semiconductor layer is formed on a side of the source-drain layer facing away from the first flat layer, and the semiconductor layer covers at least part of the source electrode and at least part of the drain electrode; A second dielectric layer is formed on a side of the semiconductor layer facing away from the source-drain layer, and the second dielectric layer covers the semiconductor layer, the source-drain electrodes, and a surface of the first flat layer facing away from the first dielectric layer; A gate layer and a power lead are formed on a side of the second dielectric layer facing away from the semiconductor layer. Along a direction from the epitaxial layer unit to the driving circuit layer, a projection of the gate layer is within a projection of the semiconductor layer, and the power lead is electrically connected to the first pad through a via hole penetrating through the second dielectric layer and the first flat layer; A second flat layer is formed on a side of the gate layer facing away from the second dielectric layer.
5. The manufacturing method according to claim 4, characterized in that, After forming the driving circuit layer on a side of the electrode facing away from the epitaxial layer, the manufacturing method further includes: A support pillar and a first adhesive are formed on a side of the second flat layer facing away from the gate layer. Along a direction from the epitaxial layer unit to the driving circuit layer, a projection of the support pillar at least partially overlaps a projection of the semiconductor layer, and the first adhesive covers a surface of the second flat layer facing away from the second dielectric layer that is not occupied by the support pillar; Provide a second substrate and attach the second substrate to a side of the driving circuit layer facing away from the light-emitting diode chip.
6. The manufacturing method according to claim 1, wherein It further includes: Remove the first substrate to expose the epitaxial layer unit; Provide a cover plate and attach the cover plate to a side of the epitaxial layer unit facing away from the driving circuit layer.
7. The manufacturing method according to claim 6, characterized in that, The attaching the cover plate to a side of the epitaxial layer unit facing away from the driving circuit layer includes: Coat a second adhesive on a side of the epitaxial layer unit facing away from the driving circuit layer; Attach the cover plate to the epitaxial layer unit coated with the second adhesive. A surface of the cover plate facing the epitaxial layer unit includes a quantum dot layer, and the quantum dot layers correspond to the epitaxial layer units one by one.
8. The manufacturing method according to claim 7, wherein Before providing the cover plate, the manufacturing method further includes: Form the quantum dot layer and a light-blocking layer on a side of the cover plate facing the epitaxial layer unit by an inkjet printing or spin coating process, and the light-blocking layer is in a gap between adjacent quantum dot layers.
9. According to the manufacturing method of any one of claims 1-8, the attaching the first substrate to a side of the epitaxial layer facing away from the substrate includes: Form a temporary bonding layer on a side of the first substrate facing the epitaxial layer with a side of the epitaxial layer facing away from the substrate; Attach the first substrate to the epitaxial layer by a thermal pressing process, and the temporary bonding layer includes an adhesive or a silicon oxide layer.
10. A display device, characterized in that, The display device is manufactured based on the manufacturing method of any one of claims 1-9.