Radar signal processing chip with low power consumption and high performance

Abstract

The invention belongs to the technical field of integrated circuits, particularly relates to a signal processor applied to frequency modulated continuous wave (FMCW) radar target detection, and aims to improve the speed and capability of a radar system for distance measurement, speed measurement and angle measurement of a target. The structure of the processor mainly comprises a fast Fourier transform (FFT) module, a modulo operation module, a constant false alarm rate (CFAR) detection module, a special operation processing unit, a cache module and a high-speed bus. The accelerator can support real-time measurement in a multi-target dynamic scene, and the FFT module is a special hardware accelerator for radar signal processing and adopts a serial pipeline design; the CFAR module adopts a three-dimensional pipeline structure and is used for target detection and false alarm rate reduction; the high-speed cache module and the high-speed bus are used for storing three-dimensional signal processing results and completing calculation of three-dimensional distance measurement, speed measurement and angle measurement together. By optimizing a hardware architecture and an algorithm, the radar signal processor has the advantages of miniaturization, real-time performance, high precision and low power consumption, and is suitable for various radar application scenes such as unmanned aerial vehicles, automobiles, mobile communication and the like.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and particularly relates to a radar signal processor. Background Art

[0002] Radar technology has been widely applied in modern military, civilian, autonomous driving, unmanned aerial vehicles, intelligent transportation and other fields, especially playing a crucial role in functions such as target detection, obstacle avoidance, navigation, and autonomous driving. The radar system can effectively detect and track different types of targets by transmitting electromagnetic waves and receiving reflected signals, and obtain key information such as the distance, speed, and azimuth angle of the target. However, traditional radar signal processing systems are usually relatively large, the processing process is complex and requires a large amount of hardware support, which makes them unsuitable for modern miniaturized and highly integrated radar systems.

[0003] These traditional processors usually rely on general-purpose processors or complex hardware structures, and the processing speed is limited by the hardware architecture, resulting in difficulty in adapting to real-time and dynamic multi-target tracking tasks. In addition, with the development of radar technology, the requirements for measurement accuracy of radar systems are also constantly increasing, especially the ranging, speed measurement, angle measurement accuracy and target tracking ability in a dynamic environment. These challenges require that the radar signal processor not only has high-speed computing capabilities, but also needs to efficiently implement complex signal processing algorithms in order to track targets in real time and accurately measure in complex environments.

[0004] In recent years, in order to solve the above problems, the implementation of radar signal processors has gradually begun to be explored. Some studies have tried to use field programmable gate arrays (FPGAs) or application specific integrated circuits (ASICs) to implement the design of some IPs for hardware acceleration in radar signal processing, but there are still problems such as insufficient speed, high power consumption, and low system integration, and the overall performance is still limited.

[0005] Therefore, designing a dedicated radar signal processing system different from general-purpose processors, by optimizing the hardware architecture and innovative signal processing methods, can overcome the shortcomings of traditional general-purpose processors, improve the performance of radar signal processors while liberating hardware resources. Summary of the Invention

[0006] The purpose of the present invention is to propose a small radar signal processor applied to target detection, and the main solutions are as follows:

[0007] A small radar signal processor for target detection proposed by the present invention, whose circuit structure includes: a fast Fourier transform module (FFT), a modulus operation unit, a constant false alarm detection module (CFAR), a dedicated operation processing unit, a cache module, a high-speed bus, and a control unit. The multi-channel radar echo signals are input into the radar signal processor after being sampled by the ADC, and are allocated to the operation module by the control module through the high-speed bus to complete the signal processing and target detection of three-dimensional ranging, speed measurement, and angle measurement. The cache is used to store the process data.

[0008] In the present invention, the fast Fourier transform module has a serial pipeline structure with configurable number of points. According to the data volume and accuracy requirements of radar signal processing, any structure with the number of points not exceeding 1024 can be configured (the number of FFT points is 2^N); and this module can meet the functions such as three-dimensional FFT calculation and automatic zero-padding.

[0009] In the present invention, the modulus operation unit has a pipeline iterative structure based on the CORDIC algorithm, and the number of iterations can be configured according to the data volume and accuracy requirements of radar signal processing.

[0010] In the present invention, the constant false alarm detection module has a mean value type structure with a configurable sliding window. According to the data volume and accuracy requirements of radar signal processing, the length of the detection unit and the length of the guard unit for constant false alarm detection can be configured; and this module is a three-dimensional structure and can process the calculation results of three-dimensional FFT.

[0011] In the present invention, the main structure of the operation processing unit is a dedicated decimal multiplier and adder, which is used for three-dimensional FFT operation, modulus operation, and CFAR operation in radar signal processing. Description of the Drawings

[0012] Figure 1 It is a schematic diagram of the structure of the radar signal processor of the present invention.

[0013] Figure 2 It is a schematic diagram of the FFT with a pipeline structure having configurable number of points.

[0014] Figure 3 It is a schematic diagram of the modulus structure based on the CORDIC algorithm.

[0015] Figure 4 It is a schematic diagram of the three-dimensional mean value type CFAR structure. Detailed Embodiments

[0016] The present invention will be described in more detail hereinafter with reference to the drawings. In each of the drawings, the same elements are denoted by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown in the figures.

[0017] Many specific details of the present invention are described below, such as the structure, type, and technology of the hardware, the size and bit width of the data, etc., in order to understand the present invention more clearly. However, as those skilled in the art can understand, the present invention can be implemented without these specific details.

[0018] Figure 1 The schematic structural diagram of the small radar signal processor of the present invention is shown.

[0019] As Figure 1 shown, the small radar signal processor 100 in the present invention has a circuit structure including: a fast Fourier transform module (FFT) 101, a modulus operation unit 102, a constant false alarm rate detection module (CFAR) 103, a dedicated operation processing unit 104, a cache module 105, a high-speed bus 106, and a control unit 107. The multi-channel radar echo signals are input into the radar signal processor after being sampled by the ADC, and are allocated to the operation modules (101, 102, 103) by the control module 107 through the high-speed bus 106, and participate in the calculation by calling the dedicated processing unit 104 to complete the signal processing and target detection of three-dimensional ranging, velocity measurement, and angle measurement. The cache 105 is used to store the process data.

[0020] Figure 2 The schematic diagram of the pipelined structure FFT with configurable number of points of the present invention is shown.

[0021] As Figure 2 shown, the pipelined structure FFT (200) with configurable number of points in the present invention can have any structure with the number of points not exceeding 1024 (the number of FFT points is 2^N) according to the data volume and accuracy requirements of radar signal processing; and this module can meet the functions of three-dimensional FFT calculation, automatic zero-padding, etc. The main structure in the figure is the pipelined butterfly operation structure 201, and the reordering module 202 is responsible for reordering the output signals into a sequence convenient for subsequent calculation.

[0022] Figure 3 The schematic structural diagram of the modulus structure based on the CORDIC algorithm of the present invention is shown.

[0023] As Figure 3 shown, the modulus structure 300 based on the CORDIC algorithm in the present invention can configure the number of iterations according to the data volume and accuracy requirements of radar signal processing. In the figure, x and y are the horizontal and vertical coordinates of the vector respectively; the data selector 301 is used to judge the quadrant where the rotated vector is located; the multiplication 302 is used to cancel the scaling in the operation process and restore the true modulus value.

[0024] Figure 4 The schematic structural diagram of the three-dimensional mean type CFAR of the present invention is shown.

[0025] As Figure 4As shown, the CFAR (400) in the present invention is a three-dimensional structure 401 with a configurable sliding window. According to the data volume and accuracy requirements of radar signal processing, the lengths of the detection unit and the guard unit for constant false alarm detection can be configured. After the signal is sampled by the sliding window 402, it is sent to the arithmetic unit to calculate the mean value 403 and the threshold 404. By comparing the detection signal with the threshold 405, the target detection result is output.

[0026] In this document, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a series of elements (such as a process, method, article or device) including those elements not only includes those elements, but also includes other elements not expressly listed. Without further limitation, an element defined by the statement "comprising a..." does not exclude the presence of another identical element in addition to the recited element.

[0027] In the present invention, the embodiments do not describe all the details in detail, nor limit the invention to the specific embodiments described. According to the above description, many changes can be made, such as multipliers, adders, etc. of different structures. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and its modifications. The present invention is only limited by the claims and their full scope and equivalents.

Claims

1. A small radar signal processor applied to target detection, characterized in that The circuit structure includes: a Fast Fourier Transform module (FFT), a modulus operation unit, a Constant False Alarm Rate detection module (CFAR), a dedicated operation processing unit, a cache module, a high-speed bus, and a control unit. The multi-channel radar echo signals are input into the radar signal processor after being sampled by the ADC, and are allocated to the operation module by the control module through the high-speed bus to complete the signal processing and target detection of three-dimensional ranging, velocity measurement, and angle measurement. The cache is used to store the process data.

2. The small radar signal processor applied to target detection according to claim 1, wherein The Fast Fourier Transform module has a configurable-point serial pipeline structure. According to the data volume and accuracy requirements of radar signal processing, any structure with a configurable number of points not exceeding 1024 can be configured (the FFT number of points is 2^N); and this module can meet the functions such as three-dimensional FFT calculation and automatic zero-padding.

3. The small radar signal processor applied to target detection according to claim 2, wherein The modulus operation unit has a pipeline iterative structure based on the CORDIC algorithm, and the number of iterations can be configured according to the data volume and accuracy requirements of radar signal processing.

4. The small radar signal processor applied to target detection according to claim 3, characterized in that, The Constant False Alarm Rate detection module has a mean type structure with a configurable sliding window. According to the data volume and accuracy requirements of radar signal processing, the length of the detection unit and the length of the guard unit for Constant False Alarm Rate detection can be configured; and this module is a three-dimensional structure and can process the calculation results of three-dimensional FFT.

5. The small radar signal processor applied to target detection according to claim 4, characterized in that, The main structure of the operation processing unit is a dedicated fractional multiplier and adder, which is used for various operations in radar signal processing.

Images