DFX design method and device, computer equipment and storage medium

Abstract

The invention provides a DFX design method and device, computer equipment and a storage medium, and belongs to the field of electronic design automation. Running the first design method, and at least outputting a corresponding first netlist hash value and a first PPA index; based on the first netlist hash value and the first PPA index, judging whether the first design method meets the expected requirement of combining the iteration content; when it is judged that the first design method meets the expected requirement for combining the iteration content, the iteration content and the first design method are integrated, and a second design method is obtained; running a second design method, and at least outputting a corresponding second netlist hash value and a second PPA index; determining whether a fault exists or not based on the second netlist hash value and the second PPA index; and when the fault does not exist, outputting the second design method. According to the processing scheme, the reliability is high, the problem positioning efficiency is high, and use is convenient.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic design automation (EDA), and particularly to a DFX design method, device, computer equipment and storage medium. Background Art

[0002] In the existing EDA software design (electronic design automation) process, only the functional and performance requirements of customers for products are considered, without considering the performance and reliability maintenance during the subsequent iteration process of the products. As customer requirements continue to increase and the software becomes more and more complex, it will lead to difficulties in software stability and performance maintenance, and a large amount of time is required to find the changes that cause the software stability to be damaged and the software performance to decline. In addition, due to the complexity of the EDA backend process, R & D needs to spend a lot of energy to determine the reasons for the code not meeting expectations, resulting in a significant reduction in the efficiency of software R & D. Summary of the Invention

[0003] Therefore, in order to overcome the above-mentioned disadvantages of the prior art, the present invention provides a DFX design method, device, computer equipment and storage medium with high reliability, high problem location efficiency and convenient use.

[0004] To achieve the above object, the present invention provides a method for DFX design iteration, including: receiving a design iteration instruction, where the design iteration instruction carries iteration content for a first design method; running the first design method, and at least outputting a corresponding first netlist hash value and a first PPA metric; determining whether the first design method meets the expected requirements for incorporating the iteration content based on the first netlist hash value and the first PPA metric; when it is determined that the first design method meets the expected requirements for incorporating the iteration content, integrating the iteration content and the first design method to obtain a second design method; running the second design method, and at least outputting a corresponding second netlist hash value and a second PPA metric; determining whether there is a fault based on the second netlist hash value and the second PPA metric; when it is determined that there is no fault, outputting the second design method.

[0005] In one embodiment, the method further includes: when it is determined that there is a fault, repairing the faulty location in the second design method to generate a third design method; running the third design method, and at least outputting a corresponding third test netlist hash value and a third test PPA metric; determining whether there is a fault based on the third test netlist hash value and the third test PPA metric; when it is determined that there is no fault, outputting the third design method.

[0006] In one embodiment, determining whether the first design method meets the expected requirements for incorporating iterative content based on the first netlist hash value and the first PPA metric includes: determining whether the first design method meets consistency based on the first netlist hash value; determining a performance change value of the first design method based on the first PPA metric, and determining whether the first design method is stable based on the performance change value; when the first design method meets consistency and is stable, determining that the first design method meets the expected requirements for incorporating iterative content.

[0007] In one embodiment, running the first design method and outputting at least the corresponding first netlist hash value and first PPA metric includes: marking the first design method according to basic algorithm units in a standard library, where each mark corresponds to at least the type and location of a basic algorithm unit in the standard library; generating netlist information according to the marks; calculating the marks in the netlist information using a hash function to generate and output a first netlist hash value; and outputting a first PPA metric according to the netlist information.

[0008] In one embodiment, the marks are stored corresponding to key steps of the first design method.

[0009] In one embodiment, the method further includes: storing the iterative content, the second netlist hash value, and the second PPA metric in correspondence.

[0010] A DFX design device, the device includes: an instruction receiving module, configured to receive a design iteration instruction, where the design iteration instruction carries iterative content for a first design method; a first running module, configured to run the first design method and output at least the corresponding first netlist hash value and first PPA metric; a first fault determination module, configured to determine whether the first design method meets the expected requirements for incorporating iterative content based on the first netlist hash value and the first PPA metric; an integration module, configured to integrate the iterative content and the first design method to obtain a second design method when it is determined that the first design method meets the expected requirements for incorporating the iterative content; a second running module, configured to run the second design method and output at least the corresponding second netlist hash value and second PPA metric; a second fault determination module, configured to determine whether there is a fault based on the second netlist hash value and the second PPA metric; and a storage module, configured to output the second design method when it is determined that there is no fault.

[0011] In one of the embodiments, the first operation module includes: a marking unit, configured to mark the first design method according to the basic algorithm units in the standard library, and each mark corresponds to at least one type and position of the basic algorithm units in the standard library; a netlist information generation unit, configured to generate netlist information according to the marks; a calculation unit, configured to calculate the marks in the netlist information by using a hash function to generate a first netlist hash value; a test unit, configured to output a first PPA metric according to the netlist information.

[0012] A computer device includes a memory and a processor, the memory stores a computer program, and is characterized in that when the processor executes the computer program, the steps of the above method are implemented.

[0013] A computer-readable storage medium stores a computer program thereon, and is characterized in that when the computer program is executed by a processor, the steps of the above method are implemented.

[0014] Compared with the prior art, the advantages of the present invention are as follows: the requirements for the integration of iterative content are specified in the process steps, and the automation judgment of the information output by DFX design ensures that the iterative content does not damage the original stability and performance of the first design method, and proves that the iterative content meets the expectations, ensuring the stability of the software during version iteration from the source. And by testing the netlist hash value and the test PPA metric, it is possible to quickly locate the problems that occur after the integration of the iterative content and the first design method, without the need to modify the iterative content and perform multiple tests to locate the problems, improving the efficiency of problem location. In addition, the method is easy to use: only need to perform corresponding tests according to the process specifications, and the report can be automatically output and the corresponding conclusions can be obtained, and the output content can be subsequently presented in the form of visual tables and charts for easy use. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and those of ordinary skill in the art can obtain other drawings without creative efforts based on these drawings.

[0016] Figure 1 is a schematic flowchart of the DFX design iteration method in the embodiment of the present invention;

[0017] Figure 2 is a schematic diagram of the calculation of the netlist hash value in the embodiment of the present invention;

[0018] Figure 3 is a schematic diagram of the PPA metrics before and after iteration in the embodiment of the present invention;

[0019] Figure 4 is the structural block diagram of the DFX design iteration device in the embodiments of the present invention;

[0020] Figure 5 is the internal structure diagram of the computer device in the embodiments of the present invention. Specific Embodiments

[0021] The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0022] The following uses specific specific examples to illustrate the implementation manners of the present application. Those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without making creative efforts belong to the scope of protection of the present application.

[0023] It should be noted that the following describes various aspects of the embodiments within the protection scope of the present invention. It should be obvious that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is illustrative only. Based on the present application, those skilled in the art should understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspects described herein can be used to implement the device and / or practice the method. In addition, this device and / or this method can be implemented using other structures and / or functions in addition to one or more of the aspects described herein.

[0024] It should also be noted that the diagrams provided in the following embodiments only illustrate the basic concept of the present application in a schematic manner. Only the components related to the present application are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in its actual implementation can be an arbitrary change, and the component layout type may also be more complex.

[0025] In addition, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that the described aspects can be practiced without these specific details.

[0026] Such as Figure 1As shown in the figure, an embodiment of the present application provides a method for DFX design iteration. This method can be applied to a terminal or a server. Among them, the terminal can be, but is not limited to, various personal computers, laptop computers, smart phones, tablet computers, and portable intelligent devices. The server can be implemented by an independent server or a server cluster composed of multiple servers. The DFX design method (Design for Excellence design) closely combines design and manufacturing by considering various factors such as manufacturing, testing, and reliability in advance during the design phase to achieve the design goal of "success in one attempt". The specific contents of DFX design in EDA software include: (1) Design for Manufacturability (DFM), which mainly focuses on whether the PCB design meets the manufacturing process requirements; (2) Design for Testability (DFT). The goal of DFT is to ensure that the product can be tested efficiently and accurately during the production process, reducing the test time and cost; (3) Design for Assembly (DFA). DFA focuses on whether the product assembly process is efficient and convenient; (4) Design for Reliability (DFR). DFR ensures that the product can operate stably in various environments and reduces the failure rate; (5) Design for Cost (DFC). The goal of DFC is to minimize the product cost on the premise of meeting the functions and performance.

[0027] Taking the application of this method to a server as an example for illustration, it includes the following steps:

[0028] Step 101, receive a design iteration instruction, where the design iteration instruction carries iteration content for the first design method.

[0029] The server receives a design iteration instruction, and the design iteration instruction carries iteration content for the first design method. The iteration content can be code that needs to be added to the first design method or other executable methods, etc. The design iteration instruction can directly carry the iteration content or let the server obtain the corresponding content at the acquisition address by carrying the acquisition address of the iteration content.

[0030] Step 102, run the first design method and output at least the corresponding first netlist hash value and the first PPA metric.

[0031] The server can run the first design method and output at least the corresponding first netlist hash value and the first PPA metric. The netlist hash value is calculated from the information of the netlist. The same netlist has the same hash value. The netlist hash value can include the hash value of the cell and the hash value of the wire network. For example Figure 2As shown, the hash value of a cell is calculated from the name, location, and corresponding standard library cell type of each cell. The hash value of a net is calculated from the names of all nets and the connection relationships between the pins they connect to. Through these two hash values, a unique netlist can be identified.

[0032] A cell can correspond to the process, key steps, or operator combinations of the first design method. An operator is a symbol used to perform specific operations, such as arithmetic operators, logical operators, relational operators, etc. Arithmetic operators are symbols such as addition, subtraction, multiplication, and division. Logical operators are symbols such as "AND", "OR", "NOT", etc. Relational operators are symbols such as equal to, greater than, less than, etc. Operator combinations can implement various computational tasks (such as sorting, searching, encryption, etc.). Key steps can contain multiple operator combinations; a process can contain multiple key steps.

[0033] PPA metrics (Power, Performance, Area metrics) are three key metrics for measuring the success of chip design. They represent power consumption (Power), performance (Performance), and area (Area) respectively. PPA metrics can include metrics for measuring chip performance such as worst negative slack (WNS) in placement and routing and optimization, total negative slack (TNS) in placement and routing and optimization, area (Area), power (Power), etc. The server outputs these metrics to analyze the reasons for the improvement or deterioration of the process results.

[0034] In one embodiment, the server can also track optimization actions. Specifically, through pre - setting, the server can track the running status of a certain cell, a certain timing path, or a specific algorithm in the design method and output information accordingly.

[0035] Step 103: Based on the first netlist hash value and the first PPA metric, determine whether the first design method meets the expected requirements for incorporating iterative content.

[0036] The server determines whether the first design method meets the expected requirements for incorporating iterative content based on the first netlist hash value and the first PPA metric. The expected requirements mean that the first design method is in a stable working environment to avoid the collapse of the entire design method (DFX design method) before and after incorporating iterative content.

[0037] The server can determine whether there are software consistency problems through the hash value of the netlist, quickly output the key steps leading to the inconsistency, and improve the efficiency of R & D positioning and repair. The server can quickly analyze the software performance changes through the PPA metrics and judge whether the impact of the incorporated code on software performance is reasonable. By tracking the running status of the algorithm in the process, the server can assist R & D in analyzing the bottlenecks of software performance and improvement methods, thereby improving the efficiency of software performance optimization.

[0038] Step 104, when it is determined that the first design method meets the expected requirements for incorporating iterative content, integrate the iterative content and the first design method to obtain a second design method.

[0039] When it is determined that the first design method meets the expected requirements for incorporating iterative content, the server integrates the iterative content and the first design method to obtain a second design method.

[0040] Step 105, run the second design method and output at least the corresponding second netlist hash value and second PPA metric.

[0041] The server runs the second design method and outputs at least the corresponding second netlist hash value and second PPA metric. The server tests on the second design method incorporating iterative content, and specific information will be output during the test. After the test, the server can automatically generate a test report, which includes the second netlist hash value and the second PPA metric. In some embodiments, the test report may also include the iterative content and / or the incorporation location of the iterative content in the first design method.

[0042] Step 106, based on the second netlist hash value and the second PPA metric, determine whether there is a fault.

[0043] The server determines whether there is a fault based on the second netlist hash value and the second PPA metric. The server first determines whether this integration will cause consistency problems from the second netlist hash value, and judges whether the software performance is damaged from the second PPA metric. If there are no consistency problems and the software performance meets the expectations, the iterative content can be directly integrated; if consistency problems occur or the software performance is damaged, the server can quickly locate the problematic module and steps from the test report, so as to quickly locate the wrong code for repair, and then retest until the final result meets the expectations, so as to ensure the stability and performance of the software from the code incorporation stage.

[0044] Step 107, when it is determined that there is no fault, output the second design method.

[0045] When it is determined that there is no fault, the server outputs the second design method.

[0046] The above method stipulates the requirements for iterative content integration in terms of process steps. The automated judgment of the information output by DFX design ensures that the iterative content does not damage the original stability and performance of the first design method, and proves that the iterative content meets the expectations, guaranteeing the stability of the software during version iteration from the source. Moreover, by testing the netlist hash value and the test PPA metrics, it is possible to quickly locate the problems that occur after the iterative content is integrated with the first design method, without the need to modify the iterative content and conduct multiple tests to locate the problems, improving the efficiency of problem location. Additionally, the method is easy to use: only by performing corresponding tests according to the process specifications, reports can be automatically generated and corresponding conclusions can be obtained, and the output content can be subsequently presented using visual tables and charts for convenient use.

[0047] In one embodiment, the method further includes: when it is determined that there is a fault, repairing the faulty location in the second design method to generate a third design method; running the third design method and outputting at least the corresponding third test netlist hash value and the third test PPA metrics; determining whether there is a fault based on the third test netlist hash value and the third test PPA metrics; when it is determined that there is no fault, outputting the third design method.

[0048] When it is determined that there is a fault, the server determines the faulty location from the second netlist hash value and the second PPA metrics. Then the server repairs the faulty location in the second design method and generates a third design method based on the iterative content and the repaired content. The server runs the third design method and outputs at least the corresponding third test netlist hash value and the third test PPA metrics. The server determines whether there is a fault based on the third test netlist hash value and the third test PPA metrics; when it is determined that there is no fault, outputting the third design method. When the server determines that there is a fault, the server determines the faulty location from the third netlist hash value and the third PPA metrics. Then the server repairs the faulty location in the third design method and retests until the final result meets the expectations, thus ensuring the stability and performance of the design algorithm from the stage of iterative content incorporation.

[0049] In one embodiment, judging whether the first design method meets the expected requirements for incorporating iterative content based on the first netlist hash value and the first PPA metrics includes: judging whether the first design method meets consistency based on the first netlist hash value; determining the performance change value of the first design method based on the first PPA metrics and judging whether the first design method is stable based on this performance change value; when the first design method meets consistency and is stable, determining that the first design method meets the expected requirements for incorporating iterative content.

[0050] The server determines whether the first design method meets the consistency based on the first netlist hash value; determines the performance change value of the first design method based on the first PPA metric, and determines whether the first design method is stable based on the performance change value; when the first design method meets the consistency and is stable, it is determined that the first design method meets the expected requirements for incorporating iterative content.

[0051] The server determines whether the first design method meets the consistency from the first netlist hash value, and determines whether the software performance is stable from the first PPA metric. If there are no consistency problems and the software performance meets the expectations, the server determines that the first design method meets the expected requirements for incorporating iterative content and can directly integrate the iterative content. If a consistency problem occurs or the software performance is unstable, the server can quickly locate the problematic module and steps from the test report, so as to quickly locate the error code for repair, and then retest until the final result meets the expectations, and then incorporate the iterative content.

[0052] In one embodiment, the first design method is run and at least the corresponding first netlist hash value and first PPA metric are output, including: marking the first design method according to the basic algorithm units in the standard library, and each mark corresponds to at least the type and position of a basic algorithm unit in the standard library; generating netlist information according to the marks; calculating the marks in the netlist information by using a hash function to generate and output the first netlist hash value; and outputting the first PPA metric according to the netlist information.

[0053] The server marks the first design method according to the basic algorithm units in the standard library, and each mark corresponds to at least the type and position of a basic algorithm unit in the standard library.

[0054] The server generates netlist information according to the marks. The netlist information can be generated and stored in advance, and the server can directly retrieve the corresponding netlist information from the database without generating it temporarily according to the design iteration instruction.

[0055] The server calculates the marks in the netlist information by using a hash function to generate and output the first netlist hash value. A hash function is a function that converts input data of any length (usually called "message" or "key") into an output of a fixed length through a certain algorithm. The specific function can be selected according to actual needs.

[0056] The server outputs the first PPA metric according to the netlist information.

[0057] The server runs the first design method (the second design method, ···) through a preset script or program, and outputs at least the corresponding first netlist hash value and the first PPA metric (the second netlist hash value and the second PPA metric, ···). The parameter names corresponding to the netlist hash value and the PPA metric in different design methods can be the same or different. However, as Figure 3 shown, the parameter names corresponding to the netlist hash value and the PPA metric in the design methods before and after iteration are both the same, and there may be some differences in the parameter data.

[0058] In one embodiment, tags are stored corresponding to the key steps of the first design method.

[0059] In one embodiment, the method further includes storing the iteration content corresponding to the second netlist hash value and the second PPA metric.

[0060] The above method has high traceability. By saving the iteration content and the information output during version iteration, a corresponding report can be quickly generated through a script later, the accident scene can be traced back, and problems can be analyzed and processed.

[0061] In one embodiment, as Figure 4 shown, a DFX design device is provided. The device includes an instruction receiving module 401, a first running module 402, a first fault judgment module 403, an integration module 404, a second running module 405, a second fault judgment module 406, and a storage module 407.

[0062] The instruction receiving module 401 is configured to receive a design iteration instruction, and the design iteration instruction carries the iteration content for the first design method.

[0063] The first running module 402 is configured to run the first design method and output at least the corresponding first netlist hash value and the first PPA metric.

[0064] The first fault judgment module 403 is configured to judge whether the first design method meets the expected requirements for incorporating the iteration content based on the first netlist hash value and the first PPA metric.

[0065] The integration module 404 is configured to integrate the iteration content and the first design method to obtain a second design method when it is determined that the first design method meets the expected requirements for incorporating the iteration content.

[0066] The second running module 405 is configured to run the second design method and output at least the corresponding second netlist hash value and the second PPA metric.

[0067] The second fault judgment module 406 is configured to determine whether there is a fault based on the second netlist hash value and the second PPA metric.

[0068] A storage module 407, configured to output a second design method when it is determined that there is no fault.

[0069] In one embodiment, the first operation module 402 and the second operation module 405 may be the same operation module or different operation modules. The first fault determination module 403 and the second fault determination module 406 may be the same fault determination module or different fault determination modules.

[0070] In one embodiment, the apparatus further includes:

[0071] A repair module, configured to repair a fault location in the second design method and generate a third design method when it is determined that there is a fault.

[0072] A third operation module, configured to run the third design method and output at least a corresponding third test netlist hash value and third test PPA metrics.

[0073] A third fault determination module, configured to determine whether there is a fault based on the third test netlist hash value and the third test PPA metrics.

[0074] An output module, configured to output the third design method when it is determined that there is no fault.

[0075] In one embodiment, the first fault determination module 403 includes:

[0076] A hash value determination unit, configured to determine whether the first design method conforms to consistency based on the first netlist hash value.

[0077] A PPA metrics determination unit, configured to determine a performance change value of the first design method based on the first PPA metrics and determine whether the first design method is stable based on the performance change value.

[0078] A determination unit, configured to determine that the first design method meets the expected requirements for incorporating iterative content when the first design method conforms to consistency and is stable.

[0079] In one embodiment, the first operation module includes:

[0080] A marking unit, configured to mark the first design method according to basic algorithm units in a standard library, and each mark corresponds to at least a type and a location of a basic algorithm unit in the standard library.

[0081] A netlist information generation unit, configured to generate netlist information according to the marks.

[0082] A calculation unit, configured to calculate the marks in the netlist information by using a hash function to generate a first netlist hash value.

[0083] A test unit for outputting a first PPA metric according to netlist information.

[0084] In one embodiment, the apparatus further includes:

[0085] A storage module for storing the iteration content, the second netlist hash value, and the second PPA metric in a corresponding manner.

[0086] For the specific limitations of the DFX design apparatus, reference can be made to the limitations of the DFX design method in the foregoing text, which will not be elaborated here. Each module in the above DFX design apparatus can be implemented in whole or in part by software, hardware, and their combination. The above modules can be embedded in the processor of the computer device in hardware form or independent of it, or stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to the above modules.

[0087] In one embodiment, a computer device is provided. The computer device can be a server, and its internal structure diagram can be as Figure 5 shown. The computer device includes a processor, a memory, a network interface, and a database connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store data such as the first design method, iteration content, second netlist hash value, and second PPA metric. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, it implements a DFX design method.

[0088] In one embodiment, a computer device is provided, including a memory and a processor. The memory stores a computer program. When the processor executes the computer program, the following steps are implemented: receiving a design iteration instruction, where the design iteration instruction carries iteration content for the first design method; running the first design method and at least outputting a corresponding first netlist hash value and a first PPA metric; determining whether the first design method meets the expected requirements for incorporating the iteration content based on the first netlist hash value and the first PPA metric; when it is determined that the first design method meets the expected requirements for incorporating the iteration content, integrating the iteration content and the first design method to obtain a second design method; running the second design method and at least outputting a corresponding second netlist hash value and a second PPA metric; determining whether there is a fault based on the second netlist hash value and the second PPA metric; when it is determined that there is no fault, outputting the second design method.

[0089] In one embodiment, when the processor executes the computer program, the following steps are further implemented: when it is determined that there is a fault, repair the fault location in the second design method to generate a third design method; run the third design method and output at least the corresponding third test netlist hash value and third test PPA metric; based on the third test netlist hash value and the third test PPA metric, determine whether there is a fault; when it is determined that there is no fault, output the third design method.

[0090] In one embodiment, the determination of whether the first design method meets the expected requirements for incorporating iterative content based on the first netlist hash value and the first PPA metric when the processor executes the computer program includes: determining whether the first design method meets the consistency based on the first netlist hash value; determining the performance change value of the first design method based on the first PPA metric, and determining whether the first design method is stable based on the performance change value; when the first design method meets the consistency and is stable, determine that the first design method meets the expected requirements for incorporating iterative content.

[0091] In one embodiment, the running of the first design method and the output of at least the corresponding first netlist hash value and first PPA metric when the processor executes the computer program include: marking the first design method according to the basic algorithm units in the standard library, where each mark corresponds to at least the type and location of a basic algorithm unit in the standard library; generating netlist information according to the marks; calculating the marks in the netlist information using a hash function to generate and output the first netlist hash value; outputting the first PPA metric according to the netlist information.

[0092] In one embodiment, when the processor executes the computer program, the following steps are further implemented: storing the iterative content in correspondence with the second netlist hash value and the second PPA metric.

[0093] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the following steps are implemented: receiving a design iteration instruction carrying iterative content for the first design method; running the first design method and outputting at least the corresponding first netlist hash value and first PPA metric; determining whether the first design method meets the expected requirements for incorporating iterative content based on the first netlist hash value and the first PPA metric; when it is determined that the first design method meets the expected requirements for incorporating iterative content, integrating the iterative content and the first design method to obtain a second design method; running the second design method and outputting at least the corresponding second netlist hash value and second PPA metric; determining whether there is a fault based on the second netlist hash value and the second PPA metric; when it is determined that there is no fault, outputting the second design method.

[0094] In one embodiment, when the computer program is executed by a processor, the following steps are implemented: when it is determined that there is a fault, repair the fault location in the second design method to generate a third design method; run the third design method and output at least the corresponding third test netlist hash value and third test PPA metric; based on the third test netlist hash value and the third test PPA metric, determine whether there is a fault; when it is determined that there is no fault, output the third design method.

[0095] In one embodiment, determining whether the first design method meets the expected requirements of the incorporated iterative content based on the first netlist hash value and the first PPA metric includes: determining whether the first design method meets consistency based on the first netlist hash value; determining the performance change value of the first design method based on the first PPA metric, and determining whether the first design method is stable based on the performance change value; when the first design method meets consistency and is stable, determine that the first design method meets the expected requirements of the incorporated iterative content.

[0096] In one embodiment, running the first design method and outputting at least the corresponding first netlist hash value and first PPA metric when the computer program is executed by a processor includes: marking the first design method according to the basic algorithm units in the standard library, where each mark corresponds to at least the type and location of a basic algorithm unit in the standard library; generating netlist information according to the marks; calculating the marks in the netlist information using a hash function to generate and output the first netlist hash value; outputting the first PPA metric according to the netlist information.

[0097] In one embodiment, when the computer program is executed by a processor, the following steps are implemented: storing the iterative content in correspondence with the second netlist hash value and the second PPA metric.

[0098] As described above, this is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed in the present application should be covered by the protection scope of the present application.

Claims

1. A method for DFX design iteration, characterized in that, Including: Receiving a design iteration instruction, where the design iteration instruction carries iteration content for a first design method; Running the first design method and at least outputting a corresponding first netlist hash value and first PPA metric; Judging whether the first design method meets the expected requirements for incorporating the iteration content based on the first netlist hash value and the first PPA metric; When it is determined that the first design method meets the expected requirements for incorporating the iteration content, integrating the iteration content and the first design method to obtain a second design method; Running the second design method and at least outputting a corresponding second netlist hash value and second PPA metric; Determining whether there is a fault based on the second netlist hash value and the second PPA metric; When it is determined that there is no fault, outputting the second design method.

2. The method according to claim 1, wherein The method further includes: When it is determined that there is a fault, repairing the faulty location in the second design method to generate a third design method; Running the third design method and at least outputting a corresponding third test netlist hash value and third test PPA metric; Determining whether there is a fault based on the third test netlist hash value and the third test PPA metric; When it is determined that there is no fault, outputting the third design method.

3. The method according to claim 1, wherein The judging whether the first design method meets the expected requirements for incorporating the iteration content based on the first netlist hash value and the first PPA metric includes: Judging whether the first design method meets consistency based on the first netlist hash value; Determining a performance change value of the first design method based on the first PPA metric and judging whether the first design method is stable based on the performance change value; When the first design method meets consistency and is stable, determining that the first design method meets the expected requirements for incorporating the iteration content.

4. The method according to claim 1, wherein Running the first design method and at least outputting a corresponding first netlist hash value and first PPA metric includes: Marking the first design method according to basic algorithm units in a standard library, where each mark corresponds to at least the type and location of a basic algorithm unit in the standard library; Generating netlist information according to the marks; Calculating the marks in the netlist information using a hash function to generate and output a first netlist hash value; Outputting a first PPA metric according to the netlist information.

5. The DFX design method according to claim 4, characterized in that The marks are stored corresponding to the key steps of the first design method.

6. The DFX design method according to claim 1, wherein The method further includes: Storing the iteration content, the second netlist hash value, and the second PPA metric correspondingly.

7. A DFX design device, characterized in that, The apparatus includes: An instruction receiving module for receiving a design iteration instruction, where the design iteration instruction carries iteration content for a first design method; A first running module for running the first design method and at least outputting a corresponding first netlist hash value and first PPA metric; A first fault judging module for judging whether the first design method meets the expected requirements for incorporating the iteration content based on the first netlist hash value and the first PPA metric; An integration module, configured to integrate the iterative content and the first design method to obtain a second design method when it is determined that the first design method meets the expected requirements for incorporating the iterative content; A second running module, configured to run the second design method and at least output a corresponding second netlist hash value and second PPA metrics; A second fault determination module, configured to determine whether there is a fault based on the second netlist hash value and the second PPA metrics; A storage module, configured to output the second design method when it is determined that there is no fault; 8. The DFX design device according to claim 7, wherein The first running module includes: A marking unit, configured to mark the first design method according to the basic algorithm units in the standard library, and each mark corresponds to at least one type and position of the basic algorithm units in the standard library; A netlist information generation unit, configured to generate netlist information according to the marks; A calculation unit, configured to calculate the marks in the netlist information by using a hash function to generate a first netlist hash value; A testing unit, configured to output first PPA metrics according to the netlist information; 9. A computer device, comprising a memory and a processor, the memory storing a computer program, characterized in that, When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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