Implementation method and device for customizing complex operation instruction

Abstract

The invention provides a method and a device for realizing a customized complex operation instruction, which are used for realizing analysis and execution of the customized complex operation instruction based on original continuous operation. The original operation is a set of predetermined operation with multiple implementation modes; the implementation mode comprises independent implementation of a single operation instance, parallel and independent implementation of a plurality of same or different operation instances, and front-back continuous combined implementation of one operation instance and another operation instance. The operation instance is continued before and after the operation instance refers to that the output of one original operation is used as the input of the operation itself or another different original operation. And the analysis of the customized complex operation instruction is realized by the original continuous operation description. The execution of the customized complex operation instruction is to input an analysis result of the customized complex operation instruction, namely the original operation description, into a part capable of implementing the original operation, and the part implementing the operation implements the corresponding original operation according to a mode specified by the original operation description so as to achieve an expected effect.

Description

Technical Field

[0001] The present invention relates to the field of electronic digital data processing, and particularly to an implementation of customizing complex operation instructions. Background Art

[0002] The progress and development of computer technology have led to a rapid increase in the processing power of computing system operation components. However, the computing architecture centered around existing general-purpose processors has reached a bottleneck and it is difficult to achieve revolutionary breakthroughs. A relatively common consensus is to develop computing architectures for specific domains. Domain-specific computing architectures have received increasing attention because they can inherit the flexibility of general computing instruction sets and provide customized instructions that meet the characteristics of specific domains. However, as an extension of the backbone instruction set, the space of the customized instruction set is relatively limited and not as rich as that of the backbone instruction set. Moreover, once the integrated circuit as hardware is designed and determined, it is difficult to change after production and manufacturing. Therefore, the customized instruction set needs to be used sparingly and carefully. There is a contradiction between this implementation limitation and the flexibility required by many possible and changing domain characteristics. On the other hand, in addition to the increase in capacity, the operating speed of the storage component of the computing system has not increased correspondingly due to its own structure, becoming a bottleneck for the operating speed, that is, the performance of the computing system. Moreover, the processing operations for processing data are generally recorded and expressed in the form of instructions (codes), and also need to be accessed and executed through the storage component. Therefore, the computing component is easily limited by the performance of the storage system and cannot well meet the computing requirements of new applications such as artificial intelligence. This performance bottleneck encountered by the computing system is the so-called "memory wall" bottleneck. One way to reduce the negative impact of storage on computing performance is to increase the amount of information contained in the instruction encoding. The more information contained in a given-length encoding, the smaller the amount of memory access required to access this information.

[0003] A technology to address the above limitations and contradictions is to customize complex operation instructions. The so-called customized complex operation is a specific function defined specifically and implemented in the form of an instruction. The customized complex operation instruction adopts a different encoding method from the general instruction and does not explicitly show the specific operation to be implemented. What is stored and accessed is the customized complex operation instruction encoding, and the requirements for the instruction storage and transmission capacity are low. When the instruction needs to be executed, according to the prior agreement, first interpret the specific operation represented by the customized complex operation instruction (encoding), and then implement the corresponding specific operation according to the result of the interpretation, so as to achieve the expected effect of the customized complex operation. In addition, through appropriate agreements and interpretation methods, the meaning of the customized instruction can also be updated, so as to achieve efficient utilization of the instruction space.

[0004] In existing industry practices, the implementation of customized complex operation instructions can be achieved through fixed-function circuits and programmable logic gate arrays (such as FPGAs). The advantage of the fixed-function circuit implementation method is straightforwardness and relatively simple implementation; however, the disadvantage is that once implemented, it cannot be changed, lacking flexibility. The advantage of the programmable logic gate array implementation method is high flexibility, changeability, and good versatility; but the disadvantage is that it requires a large amount of additional storage to store the bit file that guides the operation of the gate array. The implementation of existing general complex instructions is generally completed by the implementation of microcode and micro-operations. Its advantage is that it can provide sufficient flexibility; however, microcode and micro-operations are individual instance operations and need to store other information such as the shared resources they occupy in addition to the identifier of the operation itself, thus increasing the requirements for memory access; furthermore, the use of shared resources will also impose certain restrictions on the parallel implementation of microcode and micro-operations. In addition to the above existing practices, there is also a method of increasing the instruction coding information volume, which is the instruction coding patent CN117707619 that combines the operation context. It combines a group of operations with sequential implementation in pairs for encoding, removes redundant information, and reduces the requirements for access volume; however, this method does not specifically support the independent parallel implementation of multiple operations. Summary of the Invention

[0005] The object of the present invention is to propose a method and device for implementing customized complex operation instructions, which can balance performance, flexibility, and reduce the demand for memory access.

[0006] To achieve the above object, the present invention provides a method for implementing customized complex operation instructions, which realizes the parsing and execution of customized complex operation instructions based on original sequential operations. The original sequential operations are a set of pre-determined operations with multiple implementation modes; its implementation modes include an operation instance being implemented alone, multiple identical or different operation instances being implemented in parallel, and an operation instance being combined with another operation instance in a sequential manner; the sequential connection of operation instances means that the output of an original sequential operation is used as the input of itself or another different original sequential operation.

[0007] The parsing of the customized complex operation instructions is realized by the description of the original sequential operations. The description of the original sequential operations is an information structure composed of one or more description items with a determined relative order. Each description item indicates, in the form of information encoding, a set of current original sequential operations to be executed simultaneously and their (if any) subsequent original sequential operations to be executed, as well as the implementation mode. The current original sequential operation to be executed is the original sequential operation specified by the current description item and will be implemented by the corresponding operation implementation component; the subsequent original sequential operation to be executed is the (subsequent) original sequential operation that uses the output of the current original sequential operation as the input, and its implementation is specified by the description item located after the current description item.

[0008] The execution of the customized complex operation instruction is to input the result of parsing the customized complex operation instruction, that is, the original consecutive operation description, into a component capable of implementing the original consecutive operation. The component implementing the operation implements the corresponding original consecutive operation in the manner specified by the original consecutive operation description to achieve the expected effect of the customized complex operation. The manner specified by the original consecutive operation description is (a certain) implementation mode of the original consecutive operation that conforms to the order of the description items in the original consecutive operation description.

[0009] Optionally, the original consecutive operation may include atomic and indivisible operations, such as integer addition, floating-point multiplication, logical exclusive OR, etc. arithmetic operations, or non-arithmetic operations such as reading and writing memory, data copying, data moving, etc.; it may also include relatively complex operations, such as continuous accumulation operations.

[0010] Optionally, the description items of the original consecutive operation description consist of a description header and a description body.

[0011] Optionally, the description header includes an end description item indicator for indicating whether the description item is the last description item in the original consecutive operation description to which it belongs; the description header also includes an operation type identifier for indicating the type of the original consecutive operation in the description item; the description header also includes an operation repetition mode identifier for indicating the number of instances in which the original consecutive operation in the description item is repeatedly executed in parallel by multiple identical instances, or the number of loops in which the original consecutive operation is repeatedly executed serially by a single instance.

[0012] Optionally, the description body consists of a set of original consecutive operation codes corresponding to the original consecutive operations defined in a pre-determined original consecutive operation set. The original consecutive operation codes are divided into two categories: valid operation codes and invalid operation codes. The original consecutive operation corresponding to the valid operation code needs to be implemented, which is indicated by the validity identifier it contains. It also includes an identifier in the description body of the consecutive pending original operation corresponding to the current pending original operation to be executed, and an input identifier for the consecutive pending original operation to receive the output result of the corresponding current pending original operation. The original consecutive operation corresponding to the invalid operation code does not need to be implemented, which is indicated by the validity identifier it contains.

[0013] Optionally, the ending description item of the description header is indicated by one bit; the operation type is identified by two bits or more than two bits; the operation repetition mode is identified by five bits or more than five bits, where one bit indicates the repetition mode (parallel of multiple identical instances or serial of a single instance), and the remaining bits are the number of repetitions. The original consecutive operation code of the description body is four bits or more than four bits, where one bit is the valid / invalid operation code indication, and the definitions of the other bit positions are different according to the validity of the original consecutive operation code. When the other two bits of the valid operation code are 10, it indicates continuing the left input of the original consecutive operation to be executed; when 01, it indicates continuing the right input of the original consecutive operation to be executed; when 00, it indicates that there is no original consecutive operation to be continued for the current original consecutive operation to be executed, and the result is output to the outside; the remaining part of the valid operation code is the identification in the description body of the original consecutive operation, represented by the binary code of the position sequence number of the original consecutive operation in the (pre-determined) set of original consecutive operations. All the remaining bits of the invalid operation code represent a value: the number of adjacent original consecutive operations that do not need to be implemented and are identified in the description body (the position sequence number of the original consecutive operation in the set).

[0014] The present invention also provides an implementation device for customizing complex operation instructions, including: a parsing control unit, a description providing module, and an original consecutive operation unit.

[0015] The parsing control unit is responsible for controlling the parsing process of the custom complex operation instructions, obtaining the description of the original consecutive operation, and outputting the parsing result; it has an (custom complex operation) instruction input port, a parsing output port, a retrieval request output port, and a retrieval feedback input port.

[0016] The description providing module is responsible for storing and managing the encoding of the custom complex operation instructions for retrieval and the corresponding description of the original consecutive operation; it has a retrieval request input port, a retrieval feedback output port, and a description setting input port.

[0017] The original consecutive operation unit is responsible for implementing the original consecutive operation, and is composed of an operation implementation component and an implementation interconnection mechanism.

[0018] The operation implementation component is composed of a group of independent original consecutive functions that can implement the (pre-determined) original consecutive operation; it has a group of control command input ports, two groups of input data ports, and a group of output data ports. Each of the original consecutive functions occupies one control command input port, two input data ports, and one output data port of the operation implementation component.

[0019] The said implementation interconnection mechanism is responsible for the data transmission required for the implementation of the current to-be-executed original sequence operation and its subsequent to-be-executed original sequence operation (front and back succession); it has a set of input ports connected in one-to-one correspondence with the output data ports of the operation implementation components, and a set of output ports connected in one-to-one correspondence with all the input data ports of the operation implementation components.

[0020] After the parsing control unit obtains the customized complex operation instruction (encoding) to be parsed through its instruction input port, it sends a retrieval request to the description providing module through the retrieval request input port of the description providing module connected to its retrieval request output port. The description providing module then retrieves the stored original sequence operation description corresponding to the encoding of the input customized complex operation instruction, and then sends the retrieval result to the parsing control unit through the retrieval feedback input port of the parsing control unit connected to its retrieval feedback output port. If the retrieval result is successful, the parsing control unit sorts out the obtained retrieval result containing the original sequence operation description corresponding to the current customized complex operation instruction, and outputs it through its parsing output port to complete the parsing of the current customized complex operation instruction; if the retrieval result is failed, the parsing control unit terminates the parsing of the current customized complex operation instruction. The original sequence operation description for the parsing control unit to retrieve is input into the description providing module through the description setting input port of the description providing module before the parsing of the customized complex operation instruction starts.

[0021] The parsing control unit sends all the valid operation codes in the successfully retrieved original sequence operation description to the corresponding original sequence functions of the operation implementation components in the original sequence operation unit through its parsing output port connected to the control command input port of the operation implementation components in the original sequence operation unit. The original sequence functions corresponding to all the valid operation codes independently perform the corresponding original sequence operations on the data input from the input data port to generate corresponding results. For invalid operation codes, the corresponding original sequence operations are not performed and the corresponding original sequence functions do not act. The results after the original sequence functions corresponding to the valid operation codes perform the original sequence operations (if there is no subsequent to-be-executed original sequence operation) will be output from the output data ports of the original sequence functions to the outside of the original sequence operation unit; or are transmitted through the input ports of the implementation interconnection mechanism to the output ports of the implementation interconnection mechanism corresponding to the input of the original sequence function to perform the subsequent to-be-executed original sequence operation specified by the valid operation code, and then reach the input data ports of the original sequence functions of the operation implementation components specified by the valid operation code to participate in the implementation of the (subsequent) original sequence operation.

[0022] Optionally, the description providing module may use a non-rewritable storage device (ROM) or a rewritable storage device (RAM) to implement the storage and management of the original sequential operation description.

[0023] The beneficial effects of the present invention are as follows:

[0024] As described above, the existing custom instruction implementation schemes either lack flexibility, that is, they are basically unchangeable once the instruction definition is determined, or require a large amount of additional storage to store the configuration file. The existing general instruction microcode and micro-operation implementation schemes are difficult to implement in parallel or seamlessly continuously due to the limited resources required for micro-operation implementation. Even if the instruction encoding with context connection is used to increase the unit information amount, the parallel implementation of operations has not been improved.

[0025] The present invention expresses the function of custom complex operations based on the description of original sequential operations. Through an appropriately determined original sequential operation instruction set, any custom complex operation can be implemented by the corresponding original sequential operation with the original sequential operation description. When it is necessary to change the implementation, only the corresponding original sequential operation description stored in the description providing module needs to be changed, without modifying other existing (hardware) implementations, thereby maximizing the flexibility and generality. In addition, the function of the original sequential operation is more complex than that of the logic gate array, the amount of information required for implementation control is less, and correspondingly the requirement for storage is lower, which can minimize the impact of the storage system performance bottleneck. Furthermore, the implementation of the original sequential operation proposed by the present invention supports the (parallel) implementation of one (or more than one) original sequential operation and the sequential implementation of the currently pending original sequential operation and its subsequent pending original sequential operation in the current and subsequent description items, which can effectively solve the performance obstacles caused by data disasters faced by the existing general processor architectures. Description of the Drawings

[0026] By describing the exemplary embodiments of the present invention in more detail in conjunction with the accompanying drawings, the above and other objects, features, and advantages of the present invention will become more obvious. In the exemplary embodiments of the present invention, the same reference numerals generally represent the same components.

[0027] Figure 1 It is a schematic structural diagram of an implementation device for custom complex operation instructions in an embodiment of the present invention. Detailed Embodiments

[0028] The technical solutions of the present invention will be elaborated in detail below in conjunction with the accompanying drawings of the specification and the preferred embodiments. It should be noted that the implementation of the present invention is not limited to the specific structural compositions shown in the following embodiments. Those skilled in the art can achieve various implementation variations through equivalent replacement or adaptive adjustment without departing from the concept of the present invention. The size ratios marked in the drawings are moderately simplified for illustrative purposes only and do not constitute a limitation on the actual product parameters.

[0029] When describing the connection relationship of components, spatial relationship expressions such as "connected to..." should be understood to include two technical solutions: direct contact connection and indirect connection through an intermediate medium. When a limiting expression such as "directly connected to..." appears in the description, it specifically refers to the connection method excluding the intermediate medium.

[0030] Descriptive terms related to directions such as "above", "lower part", "sideways", etc. are understood based on the directions shown in the accompanying drawings of the specification. When there are implementation situations such as structural flipping and position offset in the actual application scenario, the relevant direction descriptions should be adaptively interpreted as the corresponding changed relative position relationships, and such equivalent adjustments should be understood by those skilled in the art to be included within the scope of the claims.

[0031] The purpose of using terms is only to describe specific embodiments and not to limit the present invention. Therefore, singular forms of pronouns such as "the" and "said" should include plural meanings when the technical solution permits and there is no obvious conflict in the context; open-ended expressions such as "comprising" and "including" should be understood to allow the existence of equivalent technical elements not explicitly listed; when the expression "A and / or B" appears, it should include three technical possibilities: A solution, B solution, and the combination of A + B solutions. Embodiment 1

[0032] This embodiment provides a method for implementing a customized complex operation instruction, which realizes the parsing and execution of the customized complex operation instruction based on the original continuous operation. The original continuous operation is a set of pre-determined operations with multiple implementation modes; its implementation modes include a single operation instance implementing alone, multiple identical or different operation instances implementing in parallel, and a combination of a single operation instance and another operation instance implementing sequentially; the sequential connection of operation instances means that the output of one original continuous operation is used as the input of itself or another different original continuous operation.

[0033] The parsing of the customized complex operation instruction is realized by the original continuous operation description. The original continuous operation description is an information structure composed of one or more description items with a determined relative order. Each description item indicates, in the form of information encoding, a set of current original continuous operations to be executed simultaneously and their (if any) subsequent original continuous operations to be executed, as well as the implementation methods. The current original continuous operation to be executed is the original continuous operation specified by the current description item and will be implemented by the corresponding operation implementation component; the subsequent original continuous operation to be executed is the (subsequent) original continuous operation that uses the output of the current original continuous operation as the input, and its implementation is specified by the description item located after the current description item.

[0034] The execution of the customized complex operation instruction is to input the result of parsing the customized complex operation instruction, that is, the original consecutive operation description, into the component capable of implementing the original consecutive operation. The component implementing the operation implements the corresponding original consecutive operation in the manner specified by the original consecutive operation description to achieve the expected effect of the customized complex operation. The manner specified by the original consecutive operation description is (a certain) implementation mode of the original consecutive operation that conforms to the sequence of description items in the original consecutive operation description.

[0035] The original consecutive operation described in this embodiment may include atomic and indivisible operations, such as integer addition, floating-point multiplication, logical exclusive OR and other arithmetic operations, or non-arithmetic operations such as reading and writing memory, data copying, data moving, etc.; it may also include relatively complex operations, such as continuous accumulation operations.

[0036] The description item of the original consecutive operation described in this embodiment consists of a description header and a description body.

[0037] The description header described in this embodiment includes an end description item indicator for indicating whether this description item is the last description item in the original consecutive operation description to which it belongs; the description header also includes an operation type identifier for indicating the type of the original consecutive operation in this description item; the description header also includes an operation repetition mode identifier for indicating the number of instances for the original consecutive operation in this description item to be repeatedly executed in a parallel manner with multiple identical instances, or the number of loops for the original consecutive operation to be repeatedly executed in a serial manner with a single instance.

[0038] The description body described in this embodiment consists of a set of original consecutive operation codes corresponding to the original consecutive operations defined in a pre-determined original consecutive operation set. The original consecutive operation codes are divided into two categories: valid operation codes and invalid operation codes. The original consecutive operation corresponding to the valid operation code needs to be implemented, which is indicated by the validity identifier it contains. It also includes an identifier in the description body of the subsequent consecutive operation to be executed corresponding to the current consecutive operation to be executed, and an input identifier for the subsequent consecutive operation to be executed to receive the output result of the corresponding current consecutive operation to be executed. The original consecutive operation corresponding to the invalid operation code does not need to be implemented, which is indicated by the validity identifier it contains.

[0039] The ending description item of the description header in this embodiment is indicated by one bit; the operation type is identified by two or more than two bits; the operation repetition mode is identified by five or more than five bits, where one bit indicates the repetition mode (parallel of multiple identical instances or serial of a single instance), and the remaining bits are the number of repetitions. The original consecutive operation code of the description body is four or more than four bits, where one bit is the valid / invalid operation code indication, and the definitions of the other bit positions are different according to the validity of the original consecutive operation code. When the other two bits of the valid operation code are 10, it indicates the left input for continuing to execute the original consecutive operation to be executed; when it is 01, it indicates the right input for continuing to execute the original consecutive operation to be executed; when it is 00, it indicates that there is no original consecutive operation to be executed for the current original consecutive operation to be executed, and the result is output to the outside; the remaining part of the valid operation code is the identification in the description body of the original consecutive operation, represented by the binary encoding of the position sequence number of the original consecutive operation in the (pre-determined) set of original consecutive operations. All the remaining bits of the invalid operation code represent a numerical value: the number of consecutive original operations adjacent to the identification in the description body (the position sequence number of the original consecutive operation in the set) that do not need to be implemented.

[0040] Preferably, the style of the description header of the description item is shown in Table 1 (X represents 1 or 0), and the style of the description body is shown in Table 2, which consists of a series of eight-bit original consecutive operation codes.

[0041] Table 1 End description item indicator Operation type identifier Operation repetition mode identifier X 10, 01 or 00 1XXXX or 0XXXX

[0042] Table 2 First original continuous operation code Second original continuous operation code Other original continuous operation codes...... Eight bits Eight bits Eight bits......

[0043] Taking the average value of a data set with a calculation dimension (number of members) of 8 as an example, the original consecutive operation (set) defines four original consecutive operations: read data operation, addition operation, division operation, and retention operation. The corresponding customized complex operation (instruction) is expressed by the following original consecutive operation descriptions, where each line is a description item. It should be noted that the "spaces" and line breaks in the description items are for the convenience of reading; there are no "spaces" in the actual coding, and these description items will be stored continuously in order, rather than line by line. 01000001 11000001 00000011 01000001 10100001 00000011 01000110 11000001 10100001 00000010 01000001 10100010 11000010 00000010 11000001 00000010 10000000 00000001

[0049] The first line is the first description item of the original sequential operation description, expressing the operation of reading the first data. The last description item indicator bit in the description header of the description item is 0; the next two-bit operation type identifier is 10, indicating that the description item is related to arithmetic processing of the original sequential operation; the remaining five bits indicate a single operation. Next is the description body composed of the original sequential operation codes. The first original sequential operation code in the description body of this description item is the valid operation code corresponding to the read data operation, indicated by the first bit being 1; the next two bits of the subsequent original sequential operation input identifier are 10, indicating that the data read by the read data operation is sent to the left input of the subsequent original sequential operation; the remaining five bits are the sequence number of the subsequent original sequential operation; here, 00001 is the identifier in the description body of the addition operation (i.e., the position sequence number of the addition operation of the original sequential operation in the set; the identifier codes in the description bodies of all original sequential operations are, in order, the read data operation 00000 at the zero position, the addition operation 00001 at the first position, the division operation 00010 at the second position, and the reserved operation 00011 at the third position), indicating that the subsequent original sequential operation of the currently to-be-executed read data operation is the addition operation. The second original sequential operation code in the description body of this description item is an invalid operation code, indicated by the first bit being 0, and the remaining seven bits represent the number of consecutive invalid operation (codes); 0000011 is 3 in binary, indicating that the next three original sequential operations in sequence, namely the addition operation, the division operation, and the reserved operation, do not need to be implemented.

[0050] The second line is the second description item of the original sequential operation description, expressing the second read data operation. Except that the subsequent original sequential operation input identifier of the valid operation code of the read data operation in the description body of the description item is 01, indicating that the data read by the read data operation is sent to the right input of the subsequent original sequential operation (addition operation), other meanings are the same as those of the previous description item.

[0051] The third line is the third description item of the original continuous operation description, expressing the operation of accumulation. Among them, the description header's first bit end description item indicator bit is 0; the operation type identifier is 10, indicating that the item in the description is an original continuous operation related to arithmetic processing; the value of the remaining five bits is 6, indicating that the original continuous operation in the description body is repeated 6 times in a serial manner. There are two parallel original continuous operations to be executed represented by valid operation codes in the description body, that is, the read data operation at the zero position in the description body and the addition operation at the first position in the description body. The first bit of the read data operation code is 1, indicating that it is a valid original continuous operation. The next subsequent original continuous operation input identifier is 10, indicating that the data read by the read data operation is sent to the left input of the subsequent original continuous operation; the remaining five bits in the description body of the subsequent original continuous operation indicate that the subsequent original continuous operation is an addition operation. Repeating 6 times corresponds to the operation of reading the third to eighth data. Next, the first bit of the addition operation code is 1, indicating that it is a valid original continuous operation. The next subsequent original continuous operation input identifier is 01, indicating that the implementation result data of the current addition operation is sent to the right input of the subsequent original continuous operation; the remaining five bits in the description body of the subsequent original continuous operation indicate that the subsequent original continuous operation is an addition operation; in this way, by sending the accumulated result of the addition original continuous operation to the right input of the subsequent addition original continuous operation and loading the newly read data to the left input of the subsequent addition original continuous operation, repeating 6 times completes the six addition operations on the first to seventh data. The remaining in this description body are invalid operation codes, indicating that the two consecutive ones behind, corresponding to the division operation at the second position and the reserved operation at the third position in the description body, do not need to be implemented.

[0052] The fourth line is the fourth description item of the original continuation operation description, which completes the last addition operation and the divisor reading operation. Among them, the first bit of the description header ending description item indicator is 0; the operation type identifier is 10, indicating that the item is an original continuation operation related to arithmetic processing; the value of the remaining five bits is 1, indicating that it is a single operation. In the description body, the first bit of the first original continuation operation code is 1, indicating that it is a valid operation code, and the corresponding read data original continuation operation needs to be implemented. The next continuation original continuation operation input identifier is 01, indicating that the data read by the read data operation is sent to the right input of the continuation original continuation operation; the description body of the remaining five bits of the continuation original continuation operation is marked with 00010, indicating that the continuation original continuation operation is a division operation; this operation loads the divisor 8 of the average division into the right input of the division original continuation operation. The first bit of the second original continuation operation code in the description body is 1, indicating that it is a valid operation code, and the corresponding addition operation original continuation operation needs to be implemented; the next continuation original continuation operation input identifier is 10, indicating that the implementation result data of the current addition operation is sent to the left input of the continuation original continuation operation; the description body of the remaining five bits of the continuation original continuation operation is marked with 00010, indicating that the continuation original continuation operation is a division operation; this operation completes the accumulation of the eighth data and the first seven data and sends the result to the left input of the subsequent division original continuation operation as the dividend for the following average division operation; the remaining in this description body are invalid operation codes, indicating that the subsequent two corresponding division operations in the description body at position 2 and the reserved operation at position 3 do not need to be implemented.

[0053] The fifth line is the fifth description item of the original continuation operation description, which completes the last division operation. The first bit of the description header in the description item is the ending description item indicator, which is 1, indicating that this is the last description item of the original continuation operation description, and the description body contains an original continuation operation related to arithmetic processing that does not need to be repeated. The first bit of the first original continuation operation code in the description body is 0, indicating that it is an invalid original continuation operation code. The consecutive invalid operation count 0000010 indicates that the two consecutive original continuation operations starting from the read data operation (i.e., the read data operation and the addition operation) are invalid operations and do not need to be implemented; the first bit of the next original continuation operation code is 1, indicating that it is a valid operation code, and the corresponding division operation needs to be implemented; the continuation original continuation operation input identifier is 00, indicating that this division original continuation operation has no subsequent original continuation operation, and the corresponding description body identifier will be ignored; in this way, the average value obtained by dividing the accumulation of eight data by 8 is output; the remaining in this description body are invalid operation codes, indicating that the corresponding reserved operation does not need to be implemented.

[0054] As can be seen from the above examples, to implement the function of "calculating the average value of a data set with a computational dimension (number of members) of 8", the software coding using existing general instructions involves multiple read and load operations of data and execution of accumulation operation instructions. Even when using the parsing and execution of compression instructions, it is necessary to access more than a dozen bytes of information. However, in the software using this embodiment (assuming that the binary encoding of the customized complex operation instruction defining this function is 00000001), only one or a small number of bytes of encoding are required, thus reducing the requirements for storage and transmission and weakening the impact of the performance bottleneck of the storage system on the computing system. Embodiment 2

[0055] Referring to Figure 1 , this embodiment provides an implementation device for customized complex operation instructions, including: a parsing control unit, a description providing module, and an original and subsequent operation unit.

[0056] The parsing control unit is responsible for controlling the parsing process of the customized complex operation instruction, obtaining the original and subsequent operation description, and outputting the parsing result; it has one (customized complex operation) instruction input port, one parsing output port, one retrieval request output port, and one retrieval feedback input port.

[0057] The description providing module is responsible for storing and managing the encoding of the customized complex operation instruction for retrieval and the corresponding original and subsequent operation description; it has one retrieval request input port, one retrieval feedback output port, and one description setting input port.

[0058] The original and subsequent operation unit is responsible for implementing the original and subsequent operations, and is composed of an operation implementation component and an implementation interconnection mechanism.

[0059] The operation implementation component is composed of a group of independent original and subsequent functions that can implement the (predetermined) original and subsequent operations; it has a group of control command input ports, two groups of input data ports, and one group of output data ports. Each of the original and subsequent functions occupies one control command input port, two input data ports, and one output data port of the operation implementation component.

[0060] The implementation interconnection mechanism is responsible for the data transmission required for the implementation of the current original and subsequent operation to be executed and its subsequent original and subsequent operations to be executed; it has a group of input ports connected in one-to-one correspondence with the output data ports of the operation implementation component, and a group of output ports connected in one-to-one correspondence with all the input data ports of the operation implementation component.

[0061] After the parsing control unit obtains the customized complex operation instruction (encoding) to be parsed through its instruction input port, it sends a retrieval request to the description providing module through the retrieval request input port of the description providing module connected to its retrieval request output port. The description providing module then retrieves the stored original and continued operation description corresponding to the encoding of the input customized complex operation instruction, and then sends the retrieval result to the parsing control unit through the retrieval feedback input port of the parsing control unit connected to its retrieval feedback output port. If the retrieval result is successful, the parsing control unit sorts out the obtained retrieval result containing the original and continued operation description corresponding to the current customized complex operation instruction, and outputs it through its parsing output port to complete the parsing of the current customized complex operation instruction; if the retrieval result is failed, the parsing control unit terminates the parsing of the current customized complex operation instruction. The original and continued operation description for the parsing control unit to retrieve is input into the description providing module through the description setting input port of the description providing module before the parsing of the customized complex operation instruction starts.

[0062] The parsing control unit sends all the valid operation codes in the successfully retrieved original and continued operation description to the corresponding original and continued functions of the operation implementation components in the original and continued operation unit through its parsing output port connected to the control command input port of the operation implementation components in the original and continued operation unit. The original and continued functions corresponding to all valid operation codes independently perform corresponding original and continued operations on the data input from the input data port according to the valid operation codes, generating corresponding results. For invalid operation codes, the corresponding original and continued operations are not performed, and the corresponding original and continued functions do not act. The result after the original and continued functions corresponding to the valid operation codes perform the original and continued operations (if there is no subsequent original and continued operation to be executed) will be output from the output data port of the original and continued function to the outside of the original and continued operation unit; or is transmitted through the input port of the implementation interconnection mechanism to the output port of the implementation interconnection mechanism corresponding to the input of the original and continued function specified by the valid operation code to perform the subsequent original and continued operation, and then reaches the input data port of the original and continued function of the operation implementation component specified by the valid operation code to participate in the implementation of the (subsequent) original and continued operation.

[0063] Preferably, in this embodiment, the description providing module uses a content-rewritable storage device (RAM) to implement the storage and management of the original and continued operation description.

[0064] Specifically, to implement the customized complex operation instruction of "calculating the average value of a data set with a calculation dimension (number of members) of 8" in Embodiment 1, the parsing control unit encodes the obtained customized complex operation instruction (assuming its binary code is 00000001) and retrieves it from the description providing module. When the corresponding original consecutive operation description 010000011100000100000011010000011010000100000011010001101100000110100001000000100100000110100010110000100000001011000001000000101000000000000001 is successfully retrieved by 00000001, the parsing control unit analyzes and processes each description item in the original consecutive operation description one by one according to the encoding order, generates corresponding control commands respectively, and then sends them to the original consecutive operation unit to complete the original consecutive operations such as reading data, addition operation, and division operation (explained item by item in Embodiment 1), and finally achieves the expected effect function of this customized complex operation instruction.

[0065] Existing general-purpose processors use microcode and micro-operations to implement complex instructions. The implementation architectures of microcode and micro-operations, namely arithmetic units, shared cache components (such as registers), and the ratio of the interconnection structures between components, may experience data disasters due to resource competition. For example, the general registers of existing general-purpose processors generally do not exceed thirty-two, but the basic operations they support are at least more than eleven (including operations such as addition, subtraction, multiplication, division, arithmetic left and right shifts, logical left and right shifts, three types of size comparisons, and logical operations such as AND, OR, and NOT). If each basic operation requires two source data registers and one destination data register, more than thirty-three general registers are required for all operations to be implemented in parallel. Therefore, resource shortages will lead to the execution of instructions having to add extra waits or extra design overheads.

[0066] The original consecutive operation unit in this embodiment supports the parallel implementation of multiple original consecutive operations through operation implementation components that can independently and parallelly implement original consecutive operations and an implementation interconnection mechanism for transmitting consecutive operation data, as well as the consecutive implementation of the currently pending original consecutive operation and its subsequent pending original consecutive operations described in the current and subsequent description items, thereby effectively solving the negative impact of data disasters in the existing general-purpose processor architecture on performance.

[0067] The description providing module in this embodiment uses a content rewritable storage device (RAM) to implement the storage and management of the original consecutive operation description. When the instruction definition of the customized complex operation changes, only the corresponding original consecutive operation description needs to be rewritten through the description setting input port, without changing the existing implementation. This improves the flexibility and the usage efficiency of the encoding (space) of the customized complex operation instruction.

[0068] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes or modifications made by those of ordinary skill in the art of the present invention based on the above disclosure fall within the scope of protection of the claims.

Claims

1. A method for implementing customized complex operation instructions, characterized in that, Based on the original-sequence operation, the parsing and execution of customized complex operation instructions are realized. The original-sequence operation is a set of pre-determined operations with multiple implementation modes; Its implementation modes include a single operation instance implementing alone, multiple identical or different operation instances implementing in parallel, and a combination of a single operation instance and another operation instance implementing successively before and after; the successive implementation of operation instances means that the output of an original-sequence operation serves as the input of itself or another different original-sequence operation. The parsing of the customized complex operation instructions is realized by the original-sequence operation description. The original-sequence operation description is an information structure composed of one or more description items with a determined relative order. Each of the description items indicates, in the form of information coding, a set of currently to-be-executed original-sequence operations to be executed simultaneously and their (if any) successive to-be-executed original-sequence operation implementation modes. The currently to-be-executed original-sequence operation is the original-sequence operation specified by the current description item and will be implemented by the corresponding operation implementation component; the successive to-be-executed original-sequence operation is the (subsequent) original-sequence operation that uses the output of the current to-be-executed original-sequence operation as the input, and its implementation is specified by the description item located after the current description item. The execution of the customized complex operation instruction is to input the result of parsing the customized complex operation instruction, that is, the original-sequence operation description, into the component capable of implementing the original-sequence operation. The component implementing the operation implements the corresponding original-sequence operation in the manner specified by the original-sequence operation description to achieve the expected effect of the customized complex operation. The manner specified by the original-sequence operation description is a (certain) implementation mode of the original-sequence operation that conforms to the order of the description items in the original-sequence operation description.

2. The method according to claim 1, wherein the original-sequence operation may include atomic and indivisible arithmetic operations or non-arithmetic operations; it may also include relatively complex arithmetic operations or non-arithmetic operations.

3. The method according to claim 1, wherein the description item of the original-sequence operation description consists of a description header and a description body. The description header includes an end description item indicator for indicating whether this description item is the last description item in the original-sequence operation description to which it belongs; the description header also includes an operation type identifier for indicating the type of the original-sequence operation in this description item; the description header also includes an operation repetition mode identifier for indicating the number of instances when the original-sequence operation in this description item is repeated in parallel with multiple identical instances, or the number of loops when it is repeated serially with a single instance. The description body consists of a set of original-sequence operation codes corresponding to the original-sequence operations defined in the pre-determined original-sequence operation set. The original-sequence operation codes are divided into two categories: valid operation codes and invalid operation codes. The original-sequence operation corresponding to the valid operation code needs to be implemented, which is indicated by the validity identifier it contains. It also includes the identifier in the description body of the successive to-be-executed original-sequence operation corresponding to the current to-be-executed original-sequence operation, and the input identifier for the successive to-be-executed original-sequence operation to receive the output result of the corresponding current to-be-executed original-sequence operation. The original-sequence operation corresponding to the invalid operation code does not need to be implemented, which is indicated by the validity identifier it contains.

4. As claimed in claim 3, the end description item of the described header is indicated by one bit; the operation type is identified by two bits or more than two bits; the operation repetition mode is identified by five bits or more than five bits, where one bit indicates the repetition mode (parallel for multiple identical instances or serial for a single instance), and the remaining bits are the number of repetitions. The original consecutive operation code of the described body is four bits or more than four bits, where one bit is the valid / invalid operation code indicator, and the definitions of the other bit positions are different according to the validity of the original consecutive operation code. When the other two bits of the valid operation code are 10, it represents the left input for continuing to execute the original consecutive operation to be executed; when 01, it represents the right input for continuing to execute the original consecutive operation to be executed; when 00, it represents that there is no original consecutive operation to be executed for the current original consecutive operation to be executed, and the result is output to the outside; the remaining part of the valid operation code is the identification within the described body of the original consecutive operation, represented by the binary encoding of the position number of the original consecutive operation in the (predetermined) set of original consecutive operations. All the remaining bits of the invalid operation code represent a numerical value: the number of original consecutive operations adjacent to the identification within the described body (the position number of the original consecutive operation in the set) that do not need to be implemented.

5. An implementation device for customizing complex operation instructions, characterized in that Comprising: A parsing control unit, a description providing module, and an original consecutive operation unit. The parsing control unit is responsible for controlling the parsing process of the customized complex operation instruction, obtaining the description of the original consecutive operation, and outputting the parsing result; It has an instruction input port for (customized complex operations), a parsing output port, a retrieval request output port, and a retrieval feedback input port. The description providing module is responsible for storing and managing the encoding of the customized complex operation instructions for retrieval and the corresponding descriptions of the original consecutive operations; it has a retrieval request input port, a retrieval feedback output port, and a description setting input port. The original consecutive operation unit is responsible for implementing the original consecutive operation, and is composed of an operation implementation component and an implementation interconnection mechanism. The operation implementation component is composed of a group of independent original consecutive functions capable of implementing the (predetermined) original consecutive operations; it has a group of control command input ports, two groups of input data ports, and a group of output data ports. Each of the original consecutive functions occupies one control command input port, two input data ports, and one output data port of the operation implementation component. The implementation interconnection mechanism is responsible for the data transmission required for the implementation of the current original consecutive operation to be executed and its subsequent original consecutive operation to be executed; it has a group of input ports connected in one-to-one correspondence with the output data ports of the operation implementation component, and a group of output ports connected in one-to-one correspondence with all the input data ports of the operation implementation component.

6. For the apparatus of claim 5, after the parsing control unit obtains the customized complex operation instruction (encoded) to be parsed through its instruction input port, it sends a retrieval request to the description providing module through the retrieval request input port of the description providing module connected to its retrieval request output port. The description providing module then retrieves the stored original and subsequent operation descriptions corresponding to the encoding of the input customized complex operation instruction, and then sends the retrieval result to the parsing control unit through the retrieval feedback input port of the parsing control unit connected to its retrieval feedback output port. If the retrieval result is successful, the parsing control unit sorts out the obtained retrieval result containing the original and subsequent operation descriptions corresponding to the current customized complex operation instruction and outputs it through its parsing output port to complete the parsing of the current customized complex operation instruction; if the retrieval result is failed, the parsing control unit terminates the parsing of the current customized complex operation instruction. The original and subsequent operation descriptions for the parsing control unit to retrieve are input into the description providing module through the description setting input port of the description providing module before the parsing of the customized complex operation instruction starts.

7. For the apparatus of claims 5 - 6, the parsing control unit simultaneously sends all valid operation codes in the successfully retrieved original and subsequent operation descriptions to the corresponding original and subsequent functions of the operation implementation components in the original and subsequent operation unit through its parsing output port connected to the control command input port of the operation implementation components in the original and subsequent operation unit. The corresponding original and subsequent functions of all valid operation codes independently perform corresponding original and subsequent operations on the data input from the input data port according to the valid operation codes to generate corresponding results. For invalid operation codes, the corresponding original and subsequent operations are not performed and the corresponding original and subsequent functions do not act. The result after the corresponding original and subsequent functions of the valid operation codes perform the original and subsequent operations (if there is no subsequent original and subsequent operation to be executed) will be output from the output data port of the original and subsequent functions to the outside of the original and subsequent operation unit; or is transmitted through the input port of the implementation interconnection mechanism to the output port of the implementation interconnection mechanism corresponding to the input of the original and subsequent function to perform the subsequent original and subsequent operation specified by the valid operation code, and then reaches the input data port of the original and subsequent function of the operation implementation component specified by the valid operation code to participate in the implementation of the (subsequent) original and subsequent operations.

8. For the apparatus of claims 5 - 7, the description providing module can use a non - rewritable storage device (ROM) or a rewritable storage device (RAM) to implement the storage and management of the original and subsequent operation descriptions.

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