Flash memory controller, solid-state storage device and method for monitoring link signal quality of solid-state storage device

Abstract

The invention discloses a flash memory controller, a solid-state storage device and a method for monitoring link signal quality of the solid-state storage device. The solid-state storage device is electrically connected to the host through the PCIe bus. The method comprises the following steps: in response to a data transmission error of a PCIe bus, triggering an error notification signal by utilizing a PCIe media access control layer; transmitting a first error counting signal or a second error counting signal to an error counting circuit according to a transmission direction of data transmission by using the link quality monitoring circuit in response to the error notification signal; accumulating a first error count value or a second error count value according to the first error count signal or the second error count signal by using an error count circuit; and reporting the first error count value or the second error count value to the host through the PCIe bus by using the PCIe media access control layer in response to a configuration read packet from the host.

Description

Technical Field

[0001] The present invention relates to integrated circuits, and more particularly to a flash memory controller, a solid state storage device, and a method for monitoring the link signal quality of a solid state storage device. Background Art

[0002] In current computer systems, a host and a solid state storage device can be electrically connected to each other through a Peripheral Component Interconnect Express (PCIe) bus. Although data can be transmitted between the host and the solid state storage device through the PCIe bus, the host cannot know the link quality of the PCIe bus. Often, it is not until the signal of the link in the PCIe bus becomes so bad that a disconnection occurs that the host can detect this abnormal situation and take corresponding processing actions, thus reducing the user experience. Summary of the Invention

[0003] Therefore, the present invention provides a flash memory controller, a solid state storage device, and a method for monitoring the link signal quality of a solid state storage device to solve the above problems.

[0004] The present invention provides a flash memory controller electrically connected to a host through a Peripheral Component Interconnect Express (PCIe) bus. The flash memory controller includes a PCIe media access control layer, a Non-Volatile Memory Express (NVMe) conversion circuit, a flash memory control circuit, a link quality monitoring circuit, and an error counting circuit. The PCIe media access control layer is configured to trigger an error notification signal when an error occurs in data transmission on the PCIe bus. The NVMe conversion circuit is configured to convert a PCIe signal from the PCIe media access control layer into an NVMe signal. The flash memory control circuit is configured to control data access to the flash memory according to the NVMe signal. The link quality monitoring circuit is electrically connected to the flash memory control circuit and the PCIe media access control layer. In response to the error notification signal, the link quality monitoring circuit is configured to generate a first error counting signal or a second error counting signal according to the transmission direction of the data transmission. The error counting circuit is electrically connected to the link quality monitoring circuit, and the error counting circuit is configured to accumulate a first error count value or a second error count value according to the first error counting signal or the second error counting signal. In response to a configuration read packet from the host having a specific address, the error counting circuit is configured to load the first error count value or the second error count value into a first buffer or a second buffer of the PCIe media access control layer, and the PCIe media access control layer reports the first error count value or the second error count value to the host through the PCIe bus.

[0005] The present invention further provides a method for monitoring the link signal quality of a solid-state storage device. The solid-state storage device is electrically connected to a host via a PCIe bus, and the flash memory controller of the solid-state storage device includes a PCIe media access control layer, a flash memory control circuit, a link quality monitoring circuit, and an error counting circuit. The method includes: in response to an error occurring in the data transmission of the PCIe bus between the host and the solid-state storage device, triggering an error notification signal by using the PCIe media access control layer; in response to the error notification signal, transmitting a first error counting signal or a second error counting signal to the error counting circuit by using the link quality monitoring circuit according to the transmission direction of the data transmission; increasing a first error count value or a second error count value by using the error counting circuit according to the first error counting signal or the second error counting signal; and in response to a configuration read packet from the host, reporting the first error count value or the second error count value to the host through the PCIe bus by using the PCIe media access control layer.

[0006] The present invention further provides a solid-state storage device electrically connected to a host via a Peripheral Component Interconnect Express (PCIe) bus. The solid-state storage device includes: a flash memory; and a flash memory controller electrically connected to the flash memory. The flash memory controller includes a PCIe media access control layer, a Non-Volatile Memory Express (NVMe) conversion circuit, a flash memory control circuit, a link quality monitoring circuit, and an error counting circuit. The PCIe media access control layer is configured to trigger an error notification signal when an error occurs in the data transmission on the PCIe bus. The NVMe conversion circuit is configured to convert a PCIe signal from the PCIe media access control layer into an NVMe signal. The flash memory control circuit is configured to control the data access of the flash memory according to the NVMe signal. The link quality monitoring circuit is electrically connected to the flash memory control circuit and the PCIe media access control layer. In response to the error notification signal, the link quality monitoring circuit is configured to generate a first error counting signal or a second error counting signal according to the transmission direction of the data transmission. The error counting circuit is electrically connected to the link quality monitoring circuit, and the error counting circuit is configured to accumulate a first error count value or a second error count value according to the first error counting signal or the second error counting signal. In response to a configuration read packet with a specific address from the host, the error counting circuit is configured to load the first error count value or the second error count value into a first buffer or a second buffer of the PCIe media access control layer, and the PCIe media access control layer reports the first error count value or the second error count value to the host through the PCIe bus. Brief Description of the Drawings

[0007] Figure 1 is a block diagram of a computer system according to an embodiment of the present invention.

[0008] Figure 2 is according to the present invention Figure 1 a state diagram of a state machine in an embodiment.

[0009] Figure 3 is a schematic diagram of a PCIe configuration space of a solid-state storage device according to an embodiment of the present invention.

[0010] Figure 4 is a schematic diagram of a vendor capability structure according to an embodiment of the present invention.

[0011] Figure 5 is a flowchart for triggering an error notification signal and generating an error count signal according to an embodiment of the present invention.

[0012] Figure 6 is a flowchart for a host to obtain TX / RX link quality information according to an embodiment of the present invention.

[0013] Figure 7 is a method for monitoring the link signal quality of a solid-state storage device according to an embodiment of the present invention. Detailed implementation manners

[0014] The following description is a preferred implementation for realizing the invention, aiming to describe the basic spirit of the present invention, but not intended to limit the present invention. The actual content of the invention must refer to the claims hereinafter.

[0015] It must be understood that the words "comprising", "including", etc. used in this specification are used to indicate the existence of specific technical features, numerical values, method steps, operations, components, and / or assemblies, but do not exclude the addition of more technical features, numerical values, method steps, operations, components, assemblies, or any combination of the above.

[0016] The words such as "first", "second", "third", etc. used in the claims are used to modify the components in the claims, not to indicate a priority order, precedence relationship, or that one component precedes another component, or the time sequence when performing method steps, but only to distinguish components with the same name.

[0017] The phrase "configured to" can describe or assert that various units, circuits, or other components are "configured to" perform one or more tasks. In such contexts, the phrase "configured to" is used to imply structure by indicating that the above-mentioned unit / circuit / component includes a structure (e.g., circuitry) that performs those one or more tasks during operation. Thus, even when the specified unit / circuit / component is not currently operating (e.g., not powered on), it can still be said that the above-mentioned unit / circuit / component is configured to perform the above-mentioned tasks. The above-mentioned unit / circuit / component used in conjunction with the phrase "configured to" includes hardware - such as circuits, memory (storing program instructions executable to implement operations), etc. In addition, "configured to" can include a generic structure (e.g., a general-purpose circuitry) that is manipulated by software and / or firmware (e.g., an FPGA or a general-purpose processor executing software) to operate in a manner capable of performing the one or more tasks to be solved. "Configured to" can also include adapting a manufacturing process (e.g., a semiconductor manufacturing device) to manufacture a device (e.g., an integrated circuit) that is adapted to implement or execute one or more tasks.

[0018] Figure 1 FIG. is a block diagram of a computer system according to an embodiment of the present invention.

[0019] As Figure 1 shown, the computer system 1 includes a host 10 and a solid-state storage device 20, and the host 10 is electrically connected to the data storage device 20 through a PCIe bus 15. That is, the host 10 and the solid-state storage device 20 can perform data transmission through links 16 and 17 of the PCIe bus 15, where the link 16 is, for example, from the transmit end TX0 of the host 10 to the receive end RX1 of the solid-state storage device 20, and the link 17 is, for example, from the transmit end TX1 of the solid-state storage device 20 to the receive end RX0 of the host 10.

[0020] In some embodiments, the host 10 includes a processor 110, a memory unit 120, a submission queue 130, a completion queue 140, and a transmission interface 150, and the processor 110, the memory unit 120, the submission queue 130, the completion queue 140, and the transmission interface 150 are electrically connected to each other through a bus 12. The processor 110 includes a central processing unit, a general-purpose processor, a microprocessor, etc., but the present invention is not limited thereto. The memory unit 120 includes a volatile memory and a non-volatile memory. The volatile memory includes, for example, a dynamic random access memory (DRAM) and / or a static random access memory (SRAM), which can be used as a system memory and a data buffer for accessing instructions of the host 10. The non-volatile memory includes, for example, a hard disk drive, a flash memory, a read-only memory, an SD card, a ferroelectric memory (FeRAM), a resistive random access memory (RRAM), etc., but the present invention is not limited thereto.

[0021] The submission queue 130 and the completion queue 140 are volatile memories, which can be implemented by, for example, a static random access memory, a buffer, or a first-in first-out (FIFO) memory, but the present invention is not limited thereto. The submission queue 130 is used to record the access instructions issued by the processor 110, and the completion queue 140 is used to record the status of the solid-state storage device 20 in response to the completed access instructions. The transmission interface 150 is, for example, a high-speed peripheral component interconnect (PCIe) physical layer (PHY), which includes a transmitter TX0 and a receiver RX0.

[0022] In some embodiments, the solid-state storage device 20 includes a flash memory controller 200 and a flash memory 30. The flash memory controller 200 is electrically connected to the flash memory 30 and is configured to control data access to the flash memory 30. The flash memory controller 200 is, for example, an integrated circuit that supports the PCIe protocol and the Non-Volatile Memory Express (NVMe) protocol. The flash memory 30 is, for example, a NAND flash memory. The flash memory controller 200 includes a PCIe media access control layer 210, an NVMe conversion circuit 220, a flash memory control circuit 230, a link quality monitoring circuit, and an error counting circuit 250. The PCIe media access control layer 210 is, for example, a collective term for various circuits and buffers with different functions, which includes a data transmission interface (such as a transmitter TX1 and a receiver RX1) of the PCIe physical layer (not shown) and a state machine 211, a PCIe configuration space 212, and other general control circuits (not shown). The PCIe media access control layer 210 can receive control signals and data from the host 10 through the link 16 and convert them into PCIe signals 21. The NVMe conversion circuit 220 is configured to convert the PCIe signals 21 from the PCIe media access control layer 210 into NVMe signals 22, or convert the NVMe signals 22 from the flash memory control circuit 230 into PCIe signals 21. The flash memory control circuit 230 is configured to generate flash memory interface signals 23 according to the NVMe signals 22 to control data access to the flash memory 30. For the operations of the link quality monitoring circuit 240 and the error counting circuit 250, please refer to Figure 2 the embodiments of.

[0023] Figure 2 in accordance with the present invention Figure 1 The state diagram of the state machine 211 in the embodiments.

[0024] In some embodiments, the state machine 211 is, for example, a Link Training and Status State Machine (LTSSM) defined by the PCIe standard, which is used to perform the initialization and training of the links 16 and 17 of the PCIe bus 15. The state machine 211 can include 11 states, for example: Detect state, Polling state, Configuration state, Recovery state, L0 state, L0s state, L1 state, L2 state, Hot reset state, Loopback state, and Disable state. For the sake of illustration, in Figure 2 the state diagram 200A shown is a simplified state diagram, which only includes the Detect state, Polling state, Configuration state, L0 state, Recovery state, and L1 state.

[0025] Before links 16 and 17 can work properly, link training for links 16 and 17 needs to be performed using state machine 211. The conversion process of the PCIe link training state usually sequentially includes a detection state, a polling state, a setup state, and an L0 state, where the L0 state can be referred to as a normal transmission state, meaning the power state in which links 16 and 17 can transmit data normally. For the solid-state storage device 20, link 17 is, for example, from the transmit end TX1 of the solid-state storage device 20 to the receive end RX0 of the host 10, and it has a first transmission direction. Link 16 is, for example, from the transmit end TX0 of the host 10 to the receive end RX1 of the solid-state storage device 20, and it has a second transmission direction. The data transmission direction between the host 10 and the solid-state storage device 20 is related to the access instruction fetched and executed by the solid-state storage device 20 from the submission queue 130 of the host 10, where the above access instruction can be a write instruction or a read instruction.

[0026] Specifically, when the processor 110 of the host 10 wants to write data to the solid-state storage device 20, the processor 110 will submit the write instruction to the submission queue 130 and store the write data corresponding to the above write instruction in the memory unit 120. When the processor 110 of the host 10 wants to read data from the solid-state storage device 20, the processor 110 will submit the corresponding read instruction to the submission queue 130. The flash memory controller 200 will periodically check the submission status of the submission queue 130 (for example, through a doorbell buffer) to fetch the submitted access instruction from the submission queue 130, so the flash memory controller 200 can know the data transmission direction of the access instruction to be executed. After the flash memory controller 200 finishes executing the access instruction, the flash memory controller 200 will write the instruction completion information of the above access instruction to the completion queue 140 of the host 10 through link 17, so the processor 110 can read the completion queue 140 to know that the above access instruction has been executed by the solid-state storage device 20.

[0027] In some embodiments, when the access instruction fetched by the flash memory controller 200 from the submission queue 130 is a read instruction, when the flash memory controller 200 executes the above read instruction, it will transmit the read data obtained from the flash memory 30 to the host 10 in the first transmission direction through link 17. When the access instruction fetched by the flash memory controller 200 from the submission queue 130 is a write instruction, when the flash memory controller 200 executes the above write instruction, it will transmit the write data stored in the memory unit 120 corresponding to the above write instruction to the flash memory controller 200 in the second transmission direction through link 16. In addition, both the PCIe media access control layer 210 and the flash memory control circuit 230 in the flash memory controller 200 can know the data transmission direction of the access instruction currently executed by the flash memory controller 200.

[0028] In some embodiments, when the above transmission direction is the first transmission direction, signals 216 and 217 transmitted from the PCIe media access control layer 210 to the link quality monitoring circuit 240 are in high logic state and low logic state respectively, for example, and signals 231 and 232 transmitted from the flash memory control circuit 230 to the link quality monitoring circuit 240 are in high logic state and low logic state respectively, for example. When the above transmission direction is the second transmission direction, signals 216 and 217 transmitted from the PCIe media access control layer 210 to the link quality monitoring circuit 240 are in low logic state and high logic state respectively, for example, and signals 231 and 232 transmitted from the flash memory control circuit 230 to the link quality monitoring circuit 240 are in low logic state and high logic state respectively, for example.

[0029] In some embodiments, the process of the flash memory controller 200 triggering the error notification signal and generating the error count signal can refer to Figure 5 process 500. First, the solid-state storage device 20 enters the L0 state to perform data transmission with the host 10 (step 502). The state machine 211 of the PCIe media access control layer 210 continuously detects whether an error occurs in the data transmitted on the link 16 or 17. When the PCIe media access control layer 210 detects that an error occurs in the data transmitted on the link 16 or 17, the solid-state storage device 20 switches from the L0 state to the recovery state. Therefore, the PCIe media access control layer 210 can detect whether the solid-state storage device 20 switches from the L0 state to the recovery state (step 504). If so, the solid-state storage device 20 enters the recovery state (step 506). If not, process 500 returns to step 504.

[0030] After the solid-state storage device 20 switches from the L0 state to the recovery state, the state machine 211 triggers an error notification signal 215 (step 508) and transmits the error notification signal 215 to the link quality monitoring circuit 240, where the error notification signal 215 is, for example, a pulse signal. In some cases, the solid-state storage device 20 will enter the L1 state from the L0 state, where the L1 state is, for example, a low-power state. When the solid-state storage device 20 desires to return from the L1 state to the L0 state, the solid-state storage device 20 will first enter the recovery state from the L1 state. After the PCIe media access control layer 210 completes the re-training of the links 16 and 17 in the recovery state, the solid-state storage device 20 will return from the recovery state to the L0 state to start data transmission via the link 16 or 17. It should be noted that when the solid-state storage device 20 switches from the recovery state to the L0 state, the state machine 211 does not trigger the error notification signal 215. That is to say, when the PCIe media access control layer 210 detects an error in the data packet transmitted on the link 16 or 17, the solid-state storage device 20 will trigger the error notification signal 215 only when it switches from the L0 state to the recovery state, and will not trigger the error notification signal 215 due to other state transition situations.

[0031] In response to the error notification signal 215, the link quality monitoring circuit 240 determines whether the current transmission direction is the first transmission direction or the second transmission direction based on the logic states of the signals 231 and 232 (or the signals 216 and 217) to trigger the first error count signal 241 or the second error count signal 242, where the first error count signal 241 or the second error count signal 242 are, for example, both pulse signals. Specifically, the link quality monitoring circuit 240 can first determine whether the current transmission direction is the first transmission direction (step 510). When the link quality monitoring circuit 240 receives the error notification signal 215, if the signals 231 and 232 are respectively in the high logic state and the low logic state, it means that the flash memory controller 200 transmits the data read from the flash memory 30 to the host 10 in the first transmission direction through the link 17. At this time, the link quality monitoring circuit 240 will trigger the first error count signal 241 (step 512) and transmit the first error count signal 241 to the error counting circuit 250. The error counter 251 (for example, a TX error counter) in the error counting circuit 250 accumulates the first error count value (for example, a TX error count value) based on the above first error count signal 241.

[0032] Next, the link quality monitoring circuit 240 determines again whether the current transmission direction is the second transmission direction (step 514). When the link quality monitoring circuit 240 receives the error notification signal 215, if signals 231 and 232 are in the low logic state and the high logic state respectively, it means that the flash memory controller 200 obtains the write data from the memory unit of the host 10 in the second transmission direction through the link 16. At this time, the link quality monitoring circuit 240 triggers the second error count signal 242 (step 516), and transmits the second error count signal 242 to the error count circuit 250. The error counter 252 (such as the RX error counter) in the error count circuit 250 accumulates the second error count value (such as the RX error count value) according to the above-mentioned second error count signal 242.

[0033] Figure 3 FIG. is a schematic diagram of the PCIe configuration space of the solid-state storage device according to an embodiment of the present invention. Figure 4 FIG. is a schematic diagram of the PCIe capability structure according to an embodiment of the present invention.

[0034] In some embodiments, the PCIe media access control layer 210 of the solid-state storage device 20 has a buffer group (not shown) to store the PCIe configuration space 212, where the PCIe configuration space 212 can be represented by, for example, Figure 3 the PCIe configuration space 300. After the PCIe links 16 and 17 between the host 10 and the solid-state storage device 20 are established, the host 10 reads the settings of its PCIe configuration space 212 from the flash memory controller 200 via the PCIe bus 15 to obtain the capability information about the solid-state storage device 20, such as supported capabilities, device identification, and power management settings. For the sake of illustration, the solid-state storage device 20 supports vendor-specific capabilities, and the host 10 can send a configuration read packet with a specific address to the solid-state storage device 20 through the link 16 to read the first error count value or the second error count value, so as to know the link quality between the host 10 and the solid-state storage device 20, and the details will be described in detail later.

[0035] For example, the PCIe configuration space 300 includes a PCI configuration space 312 and a PCIe extended configuration space 310, as Figure 3 shown. The PCI configuration space 312 includes a configuration space header 302, configuration spaces 304 and 308, and a PCIe Capability Structure 306 that are compatible with the PCI 3.0 standard. It should be noted that in Figure 3The range of each configuration space includes the lower limit value of the address offset, but does not include the upper limit value. For example, the range of the address offset of the PCIe configuration space 300 is between 0 and 0xFFF (represented in hexadecimal). The range of the address offset of the configuration space file header 302 is between 0 and 0x3F.

[0036] When the solid-state storage device 20 supports vendor-specific capabilities, the status register regarding the capability list in the configuration space file header 302 is set to 1, and the capability pointer 3021 in the configuration space file header 302 records the starting address offset of a specific PCIe capability structure (such as the PCIe capability structure 306). The above-mentioned specific PCIe capability structure may also include the next capability pointer to provide the starting address offset of the next specific PCIe capability structure. The PCIe capability structure 306 is, for example, a 12-byte memory space, and its address offset range is between 0x40 and 0xFF. For ease of explanation, the capability pointer 3021 in the configuration space file header 302 points to the PCIe capability structure 306 with a starting address offset of 0xE0, which means the address offset range of the PCIe capability structure 306 is between 0xE0 and 0xEB.

[0037] In some embodiments, the PCIe capability structure 306 can be Figure 4 represented by the PCIe capability structure 400, which includes fields 402 to 412. The fields 402, 404, 406, and 408 respectively represent the Capability ID, Next Capability Pointer, Capability Length, and Type. Specifically, after the host 10 finishes reading the settings of the configuration space file header 302, the host 10 issues a configuration read packet with the address 0xE0 according to the capability pointer 3021 in the configuration space file header 302 to read the double-word length settings starting from 0xE0 in the PCIe capability structure 306, which means it includes the Capability ID, Next Capability Pointer, Capability Length, and Type, as shown in Figure 4 the fields 402, 404, 406, and 408 in the PCIe capability structure 400. In some embodiments, the above-mentioned configuration read packet is, for example, a configuration read transaction layer packet defined by the PCIe protocol, but the present invention is not limited thereto.

[0038] For ease of explanation, the values recorded in fields 402 and 406 are 0x9 and 0x4 respectively. When the value recorded in field 402 is 0x9, it indicates that the solid-state storage device 20 supports vendor-specific capabilities, and at this time, the PCIe capability structure 400 can also be referred to as a vendor-specific capability structure. When the value recorded in field 406 is 0x4, it indicates that the length of the above-mentioned vendor-specific capabilities is 4 bytes. In addition, if the value recorded in field 404 is 0, it means that the PCIe capability structure 400 does not point to other PCIe capability structures. If the set value recorded in field 404 is not 0, it means that the PCIe capability structure 400 will point to the next PCIe capability structure with the value recorded in field 404 as the starting address offset value. Therefore, the host 10 can send a configuration read packet with the address having the above value to the solid-state storage device 20 to read the set value of the next PCIe capability structure.

[0039] Therefore, after the host 10 checks the set values of fields 402, 404, and 406 to confirm that the solid-state storage device 20 supports vendor-specific capabilities and their capability lengths, and whether it points to the next PCIe capability structure, the host 10 will then check the set value of field 408 to determine the type of vendor-specific capabilities supported by the solid-state storage device 20. Here, when the set value of field 408 is equal to a specific value (e.g., 0x1), the host 10 can determine that the vendor-specific capabilities supported by the solid-state storage device 20 carry TX / RX link quality information.

[0040] In some embodiments, the host 10 can know from the set value of the configuration space file header 302 that the starting address offset of the PCIe capability structure 306 is 0xE0, and obtain the double-word length set value starting from the starting address offset value 0xE0 of the PCIe capability structure 306, that is Figure 4 the 4 bytes starting from +000h of Figure 4 (including fields 402 to 408). Among them, the capability identifier of field 402 = 0x9, the capability length of field 406 = 0x4, and the type of field 408 = 0x1. Therefore, the host 10 can know that the solid-state storage device 20 supports vendor-specific capabilities that report TX / RX link quality information, and the PCIe capability structure 306 records the first error count value (e.g., stored in the buffer 2121) and the second error count value (e.g., stored in the buffer 2122) with a length of 4 byte groups. The first error count value is, for example, the double-word length set value starting from 0xE4 (i.e., Figure 4 the 4 bytes starting from +004h of Figure 6 .

[0041] In step 602, the host 10 issues a first configuration read packet with a first address offset value to the solid-state storage device 20. The above-mentioned first address offset value is, for example, 0xE4, which means the starting address offset value of the first error count value in the PCIe capability structure 306.

[0042] In step 604, the solid-state storage device 20 responds to the first configuration read packet to transmit a first data completion packet to the host 10. The above-mentioned first data completion packet is, for example, a completion with data transaction layer packet defined by the PCIe standard. For example, when the solid-state storage device 20 receives the first configuration read packet, the error counting circuit 250 loads the first error count value of the error counter 251 (such as the TX error counter) into the buffer 2121, and the PCIe media access control layer 210 packs the value in the buffer 2121 into the first data completion packet and transmits the first data completion packet to the host 10.

[0043] In step 606, the host 10 issues a second configuration read packet with a second address offset value to the solid-state storage device 20. The above-mentioned second address offset value is, for example, 0xE8, which means the starting address offset value of the second error count value in the PCIe capability structure 306.

[0044] In step 608, the solid-state storage device 20 responds to the second configuration read packet to transmit a second data completion packet to the host 10. The above-mentioned second data completion packet is, for example, a completion with data transaction layer packet defined by the PCIe standard. For example, when the solid-state storage device 20 receives the second configuration read packet, the error counting circuit 250 loads the second error count value of the error counter 252 (such as the RX error counter) into the buffer 2122, and the PCIe media access control layer 210 packs the value in the buffer 2122 into the second data completion packet and transmits the second data completion packet to the host 10.

[0045] Figure 7 It is a method for monitoring the link signal quality of a solid-state storage device according to an embodiment of the present invention. Please refer to Figure 1 and Figure 7 .

[0046] In step 710, in response to an error occurring in the data transmission on the PCIe bus 15 between the host 10 and the solid-state storage device 20, the PCIe media access control layer 210 triggers an error notification signal 215. For example, the error in the above data transmission may occur in the link 16 or 17 of the PCIe bus 15. When the PCIe media access control layer 210 detects an error in the data transmitted on the link 16 or 17, the state machine 211 enters a recovery state from the L0 state. In response to the state machine 211 switching from the L0 state to the recovery state, the state machine 211 triggers an error notification signal 215 (e.g., a pulse signal) and transmits it to the link quality monitoring circuit 240.

[0047] In step 720, in response to the error notification signal 215, the link quality monitoring circuit 240 transmits a first error count signal 241 or a second error count signal 242 to the error count circuit 250 according to the transmission direction of the data transmission. For example, when the link quality monitoring circuit 240 receives the error notification signal 215, if the signals 231 and 232 are in the high logic state and the low logic state respectively, it means that the flash memory controller 200 transmits the data read from the flash memory 30 to the host 10 through the link 17 in the first transmission direction. At this time, the link quality monitoring circuit 240 triggers the first error count signal 241 and transmits the first error count signal 241 to the error count circuit 250. When the link quality monitoring circuit 240 receives the error notification signal 215, if the signals 231 and 232 are in the low logic state and the high logic state respectively, it means that the flash memory controller 200 obtains the write data from the memory unit of the host 10 through the link 16 in the second transmission direction. At this time, the link quality monitoring circuit 240 triggers the second error count signal 242 and transmits the second error count signal 242 to the error count circuit 250.

[0048] In step 730, the error count circuit 250 accumulates a first error count value or a second error count value according to the first error count signal 241 or the second error count signal 242. For example, when the error count circuit 250 receives the first error count signal 241, the error counter 251 (e.g., a TX error counter) in the error count circuit 250 accumulates the first error count value (e.g., a TX error count value) according to the first error count signal 241. When the error count circuit 250 receives the second error count signal 242, the error counter 252 (e.g., an RX error counter) in the error count circuit 250 accumulates the second error count value (e.g., an RX error count value) according to the second error count signal 242.

[0049] In step 740, in response to the configuration read packet from host 10, the first error count value or the second error count value is reported to host 10 via PCIe bus 15 by using PCIe media access control layer 210. For example, when the above-mentioned configuration read packet received by solid-state storage device 20 carries the starting address of the first error count value (such as 0xE4), error counting circuit 250 loads the first error count value of error counter 251 (such as the TX error counter) into buffer 2121, and PCIe media access control layer 210 packs the value in buffer 2121 into the first data completion packet and transmits the first data completion packet to host 10. When the above-mentioned configuration read packet received by solid-state storage device 20 carries the starting address of the second error count value (such as 0xE8), error counting circuit 250 loads the second error count value of error counter 252 (such as the RX error counter) into buffer 2122 and sends the value in buffer 2122 back to host 10 in a data completion packet.

[0050] In summary, the flash memory controller, solid-state storage device, and method for monitoring the link signal quality of a solid-state storage device provided by the present invention can use the PCIe media access control layer in the solid-state storage device to detect errors occurring during data transmission between the host and the solid-state storage device via the PCIe bus, and can calculate the corresponding TX / RX error count values according to different transmission directions. In addition, the solid-state storage device supports the vendor-specific ability to report TX / RX error count values, and the host can actively send a configuration read packet to the solid-state storage device via the PCIe bus to read the TX error count value or the RX error count value, so as to obtain the link signal quality information between the host and the solid-state storage device, such as how many errors have occurred in total on the PCIe link or the number of errors occurring within a specific time interval. Therefore, when the host determines that the link signal quality is poor, it can actively take corresponding link adjustment measures to improve the link signal quality, such as pre-emphasis, de-emphasis, feed-forward equalizer, continuous-time linear equalizer, decision feedback equalizer, and so on.

[0051] Although the present invention is disclosed above with preferred embodiments, it is not intended to limit the scope of the present invention. Any person with ordinary knowledge in the technical field can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to that defined by the appended claims.

[0052] [Symbol Description]

[0053] 1 Computer system

[0054] 10 Host

[0055] 12 Bus

[0056] 15 PCIe Bus

[0057] 16, 17 Link

[0058] 20 Solid - state storage device

[0059] 21 PCIe Signal

[0060] 22 NVMe Signal

[0061] 23 Flash memory interface signal

[0062] 30 Flash memory

[0063] 110 Processor

[0064] 120 Memory unit

[0065] 130 Submission queue

[0066] 140 Completion queue

[0067] 150 Transmission interface

[0068] 200 Flash memory controller

[0069] 200A State diagram

[0070] 210 PCIe Media Access Control layer

[0071] 211 State machine

[0072] 212 PCIe Configuration Space

[0073] 215 Error notification signal

[0074] 216, 217 Signal

[0075] 220 NVMe Protocol conversion circuit

[0076] 230 Flash memory control circuit

[0077] 231, 232 Signal

[0078] 240 Link quality monitoring circuit

[0079] 241 First error count signal

[0080] 242 Second error count signal

[0081] 250 Error Counting Circuit

[0082] 251, 252 Error Counters

[0083] 2121, 2122 Buffers

[0084] 300 PCIe Configuration Space

[0085] 302 Configuration Space File Header

[0086] 304, 308 Configuration Spaces

[0087] 306 PCIe Capability Structure

[0088] 310 PCIe Extended Configuration Space

[0089] 312 PCI Configuration Space

[0090] 3021 Capability Index

[0091] 400 PCIe Capability Structure

[0092] 402 - 412 Fields

[0093] 500 Process

[0094] 502 - 516 Steps

[0095] 600 Process

[0096] 602 - 608 Steps

[0097] 700 Method

[0098] 710 - 740 Steps

[0099] TX0, TX1 Transmitting Ends

[0100] RX0, RX1 Receiving Ends

Claims

1. A flash memory controller is electrically connected to a host through a Peripheral Component Interconnect Express (PCIe) bus. The flash memory controller includes: A PCIe media access control layer configured to trigger an error notification signal when an error occurs in data transmission on the PCIe bus; A Non-Volatile Memory Express (NVMe) conversion circuit configured to convert PCIe signals from the PCIe media access control layer into NVMe signals; A flash memory control circuit configured to control data access to a flash memory according to the NVMe signals; A link quality monitoring circuit electrically connected to the flash memory control circuit and the PCIe media access control layer. In response to the error notification signal, the link quality monitoring circuit is configured to generate a first error count signal or a second error count signal according to the transmission direction of the data transmission; And An error counting circuit electrically connected to the link quality monitoring circuit, configured to accumulate a first error count value or a second error count value according to the first error count signal or the second error count signal, wherein, in response to a configuration read packet from the host having a specific address, the error counting circuit is configured to load the first error count value or the second error count value into a first buffer or a second buffer of the PCIe media access control layer, and the PCIe media access control layer reports the first error count value or the second error count value to the host through the PCIe bus.

2. The flash memory controller according to claim 1, wherein the PCIe bus includes a first link having a first transmission direction and a second link having a second transmission direction. The first transmission direction indicates from the flash memory controller to the host, and the second transmission direction indicates from the host to the flash memory controller.

3. The flash memory controller according to claim 2, wherein: When the access instruction obtained and executed by the flash memory controller from the submission queue of the host is a read instruction, the PCIe media access control layer or the flash memory control circuit determines that the transmission direction is the first transmission direction; And When the access instruction obtained and executed by the flash memory controller from the submission queue of the host is a write instruction, the PCIe media access control layer or the flash memory control circuit determines that the transmission direction is the second transmission direction.

4. The flash memory controller according to claim 3, wherein the first transmission direction and the second transmission direction are respectively represented by a first signal and a second signal generated by the flash memory control circuit, or are respectively represented by a third signal and a fourth signal generated by the PCIe media access control layer.

5. The flash memory controller according to claim 2, wherein the PCIe media access control layer includes a link training state machine. When an error occurs in the data transmission on the first link or the second link, the link training state machine switches from a normal transmission state to a recovery state and triggers the error notification signal.

6. The flash memory controller as claimed in claim 5, wherein in response to the error notification signal: When the transmission direction of the data transmission is the first transmission direction, the link quality monitoring circuit generates the first error count signal; and When the transmission direction of the data transmission is the second transmission direction, the link quality monitoring circuit generates the second error count signal.

7. The flash memory controller as claimed in claim 6, wherein the error counting circuit includes: A first counter, wherein in response to the first error count signal, the first counter accumulates the first error count value; And A second counter, wherein in response to the second error count signal, the second counter accumulates the second error count value.

8. The flash memory controller as claimed in claim 2, wherein the PCIe configuration space in the PCIe media access control layer includes a PCIe capability structure, the PCIe capability structure defines a vendor-specific capability of the flash memory controller to support reporting the first error count value and the second error count value, and the PCIe capability structure includes the first buffer and the second buffer.

9. The flash memory controller as claimed in claim 8, wherein when the specific address of the configuration read packet points to the first buffer, the error counting circuit loads the first error count value into the first buffer, and the PCIe media access control layer packages the first error count value stored in the first buffer into a first data completion packet and reports the first data completion packet to the host via the PCIe bus, wherein when the specific address of the configuration read packet points to the second buffer, the error counting circuit loads the second error count value into the second buffer, and the PCIe media access control layer packages the second error count value stored in the second buffer into a second data completion packet and reports the second data completion packet to the host via the PCIe bus.

10. The flash memory controller as claimed in claim 9, wherein the configuration read packet is a configuration read exchange layer packet of the PCIe protocol, and the first data completion packet and the second data completion packet are data completion exchange layer packets of the PCIe protocol.

11. A method for monitoring the link signal quality of a solid-state storage device, wherein the solid-state storage device is electrically connected to a host via a PCIe bus, and the flash memory controller of the solid-state storage device includes a PCIe media access control layer, a flash memory control circuit, a link quality monitoring circuit, and an error counting circuit, the method comprising: In response to an error occurring in the data transmission of the PCIe bus between the host and the solid-state storage device, triggering an error notification signal by using the PCIe media access control layer; In response to the error notification signal, transmitting a first error count signal or a second error count signal to the error counting circuit by using the link quality monitoring circuit according to the transmission direction of the data transmission; Utilize the error counting circuit to accumulate a first error count value or a second error count value according to the first error counting signal or the second error counting signal; and In response to a configuration read packet from the host, utilize the PCIe media access control layer to report the first error count value or the second error count value to the host via the PCIe bus.

12. The method according to claim 11, wherein the PCIe bus includes a first link having a first transmission direction and a second link having a second transmission direction, the first transmission direction indicates from the flash memory controller to the host, and the second transmission direction indicates from the host to the flash memory controller.

13. The method according to claim 12, further comprising: When the access instruction obtained and executed by the flash memory controller from the submission queue of the host is a read instruction, utilize the PCIe media access control layer or the flash memory control circuit to determine that the transmission direction is the first transmission direction; and When the access instruction obtained and executed by the flash memory controller from the submission queue of the host is a write instruction, utilize the PCIe media access control layer or the flash memory control circuit to determine that the transmission direction is the second transmission direction.

14. The method according to claim 13, wherein the first transmission direction and the second transmission direction are respectively represented by a first signal and a second signal generated by the flash memory control circuit, or are respectively represented by a third signal and a fourth signal generated by the PCIe media access control layer.

15. The method according to claim 12, wherein the PCIe media access control layer includes a link training state machine, and when an error occurs in the data transmission on the first link or the second link, the method further includes: Switch the link training state machine from the normal transmission state to the recovery state, and trigger the error notification signal.

16. The method according to claim 15, further comprising: In response to the error notification signal: When the transmission direction of the data transmission is the first transmission direction, utilize the link quality monitoring circuit to generate the first error counting signal; and When the transmission direction of the data transmission is the second transmission direction, utilize the link quality monitoring circuit to generate the second error counting signal.

17. The method according to claim 12, wherein in the PCIe configuration space of the PCIe media access control layer, there is a PCIe capability structure, the PCIe capability structure defines the vendor-specific capability of the solid-state storage device to support reporting the first error count value and the second error count value, and the PCIe capability structure includes the first buffer and the second buffer.

18. The method according to claim 17, further comprising: When the specific address of the configuration read packet points to the first buffer, utilize the error counting circuit to load the first error count value into the first buffer, utilize the PCIe media access control layer to package the first error count value stored in the first buffer into a first data completion packet, and report the first data completion packet to the host via the PCIe bus; and When the specific address of the configuration read packet points to the second buffer, the error counting circuit is utilized to load the second error count value into the first buffer, and the PCIe media access control layer is utilized to wrap the second error count value stored in the second buffer into a second data completion packet, and the second data completion packet is reported to the host via the PCIe bus.

19. The method according to claim 18, wherein the configuration read packet is a configuration read exchange layer packet of the PCIe protocol, and the first data completion packet and the second data completion packet are data completion exchange layer packets of the PCIe protocol.

20. A solid-state storage device electrically connected to a host through a Peripheral Component Interconnect Express (PCIe) bus, the solid-state storage device comprising: a flash memory; and a flash memory controller electrically connected to the flash memory, wherein the flash memory controller comprises: a PCIe media access control layer configured to trigger an error notification signal when an error occurs in data transmission on the PCIe bus; a Non-Volatile Memory Express (NVMe) conversion circuit configured to convert PCIe signals from the PCIe media access control layer into NVMe signals; a flash memory control circuit configured to control data access of the flash memory according to the NVMe signals; a link quality monitoring circuit electrically connected to the flash memory control circuit and the PCIe media access control layer, wherein in response to the error notification signal, the link quality monitoring circuit is configured to generate a first error count signal or a second error count signal according to the transmission direction of the data transmission; and an error counting circuit electrically connected to the link quality monitoring circuit, wherein the error counting circuit is configured to accumulate a first error count value or a second error count value according to the first error count signal or the second error count signal, wherein, in response to a configuration read packet with a specific address from the host, the error counting circuit is configured to load the first error count value or the second error count value into a first buffer or a second buffer, and report the first error count value or the second error count value to the host via the PCIe bus.

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