Method and system for evaluating chip removal effect in drilling process based on chip capacity ratio

Abstract

The invention provides a drilling process chip removal effect evaluation method and system based on a chip capacity ratio, relates to the technical field of chip removal effect evaluation, and constructs a closed-loop evaluation system of a drilling chip removal effect through multi-dimensional feature fusion and an intelligent decision mechanism. Firstly, the cutting spiral form, the winding state and the fracture uniformity are innovatively incorporated into a unified evaluation model, and the accuracy of chip blockage risk prediction and the process diagnosis precision are remarkably improved; secondly, a dynamic weight adjusting mechanism is established, limitation of traditional static threshold evaluation is broken through, and the system can adapt to different material characteristics and tool working conditions; meanwhile, a technological parameter intelligent mapping model is developed, real-time optimization compensation of key parameters such as the feeding amount and the rotating speed is achieved, the chip removal failure rate is effectively reduced, and the service life of a tool is prolonged.

Description

Technical Field

[0001] The present invention relates to the technical field of chip removal effect evaluation, and specifically provides an evaluation method and system for the chip removal effect in the drilling process based on the chip volume ratio. Background Art

[0002] In the field of precision drilling, the chip removal effect directly affects the machining quality and tool life. Especially in complex working conditions such as deep hole machining and micro-hole drilling, problems such as chip entanglement and abnormal fracture frequently occur. Traditional methods rely on manual experience observation or single physical quantity monitoring, and there are three technical bottlenecks: First, the quantitative relationship between the dynamic evolution of the chip spiral shape and the chip removal resistance has not been established, resulting in a lack of theoretical basis for process parameter adjustment; second, the evaluation of chip breaking uniformity is missing, making it difficult to identify design defects of chip breakers or cooling parameter mismatches in a timely manner; third, the existing evaluation systems cannot achieve a dynamic closed-loop between the machining state and the optimization strategy, which is particularly prominent when dealing with difficult-to-machine materials such as superalloys and composite materials. These problems seriously restrict the product qualification rate and production efficiency in high-end manufacturing fields such as aerospace precision components and automotive engine core components.

[0003] In the prior art, the publication number CN114662876A discloses a method for evaluating the quality of broaching surfaces based on measuring the bending degree of chips. The process of this evaluation method is as follows: First, collect the chips during the broaching process and perform edge extraction to obtain the edge feature curve of the chips. Second, extract multiple feature points on the edge feature curve obtained in the first step. Third, measure the distance L from each feature point to the starting point of the edge feature curve and the curve length S. Fourth, perform quadratic function fitting on the measured distance L and curve length S corresponding to each feature point to obtain the chip shape feature curve. Fifth, take the distance corresponding to the highest point of the chip shape feature curve as the feature height h. Substitute the feature height h into the pre-fitted surface roughness-feature height relationship function to obtain the surface roughness on the broaching surface when this cutting is performed. However, this solution only evaluates the surface quality relying on a single index of chip bending height, lacks a multi-parameter dynamic coupling mechanism, and cannot comprehensively reflect the correlation between chip shape and machining state, and has low applicability in terms of evaluation dimensions and working condition adaptability.

[0004] The above information disclosed in the background art section is only used to enhance the understanding of the background of the present disclosure, and therefore it may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0005] The purpose of the present invention is to provide an evaluation method and system for the chip removal effect in the drilling process based on the chip volume ratio to solve the problems raised in the above background art.

[0006] To achieve the above purpose, the present invention provides the following technical solutions:

[0007] An evaluation method for chip evacuation effect in the drilling process based on the chip volume ratio, the specific steps include:

[0008] S1: Optically scan the chips generated during the cutting process and collect the three-dimensional morphological data of the chips;

[0009] S2: Calculate the chip volume ratio and the chip fracture coefficient based on the three-dimensional morphological data of the chips, and generate the final effect evaluation coefficient according to the chip volume ratio and the chip fracture coefficient;

[0010] S3: Generate the chip evacuation effect level based on the final effect evaluation coefficient, and give the corresponding optimization suggestions according to the chip evacuation effect level.

[0011] Preferably, the three-dimensional morphological data of the chips includes the spiral outer diameter, the pitch, and the spiral axis angle. The logic for collecting the three-dimensional morphological data of the chips in step S1 is:

[0012] Collect the surface morphology of the chips through a line laser three-dimensional scanner to generate a high-density point cloud data set composed of three-dimensional coordinate points (x, y, z). Then, align the data coordinate system by fitting the spiral axis based on the RANSAC algorithm, and control the axis angle deviation within ±0.1°.

[0013] Preferably, the calculation methods for the spiral outer diameter and the pitch are:

[0014] Perform spatial pose matching between the point cloud data set and a preset theoretical spiral model, calculate the measured values of the spiral outer diameter 2r and the pitch P through the least squares method, and use the error rate between the measured value and the theoretical value as the parameter credibility index. When the error rate is less than the preset error threshold, the parameter is considered credible, where r represents the spiral radius.

[0015] Preferably, the calculation method for the chip volume ratio is:

[0016]

[0017] In the formula, R v represents the chip volume ratio, V c , V m respectively represent the chip volume and the material removal volume, k1 to k3 all represent preset adjustment coefficients, k1 to k3 are all greater than 0, and k1 + k2 + k3 = 1, L cw represents the winding length coefficient, D cw represents the winding tightness coefficient, represents the average chip fracture coefficient;

[0018] Among them, the calculation methods for the chip volume and the material removal volume are respectively:

[0019] V c = πr2 Pn

[0020] V m = fπ 2 n

[0021] Where n represents the number of spiral turns of the chip, and f represents the drilling feed rate.

[0022] Preferably, when calculating the winding length coefficient and the winding tightness coefficient, collect all chip groups that are wound around each other pairwise. Designate the longer chip as chip A and the shorter chip as chip B, and calculate the average length and average pitch of chip A and chip B in all chip groups respectively;

[0023] The calculation methods of the winding length coefficient and the winding tightness coefficient are respectively:

[0024]

[0025] Where l A , l B represent the average lengths of chip A and chip B respectively, P A,i , P B,i represent the average pitches of the i-th turn of chip A and chip B respectively. The subscript i represents the index of the number of turns, and i ∈ [1, n].

[0026] Preferably, when calculating the chip fracture coefficient, collect all chips with breakage points, divide them into several fracture segments according to the breakage points of the chips, and calculate the chip fracture coefficient of each fractured chip;

[0027] The calculation method of the chip fracture coefficient is:

[0028]

[0029] Where l ′ j represents the length of the j-th fracture segment of the chip. The subscript j represents the index of the fracture segment, and m represents the total number of fracture segments. The smaller the chip fracture coefficient, the better the fracture morphology of the chip;

[0030] Finally, take the average value of the chip fracture coefficients of all fractured chips to obtain the average chip fracture coefficient

[0031] Preferably, the calculation method of the effect evaluation coefficient is:

[0032] E s = a × R v + β × τ

[0033] Where E sDenote the effect evaluation coefficient, α and β respectively denote the preset weight coefficients, both of which are greater than 0, and α + β = 1. τ represents an intermediate parameter, and its calculation method is:

[0034]

[0035] In the formula, C y denotes the fracture threshold, and C y ∈[0.45, 0.65].

[0036] Preferably, the logic for optimizing suggestions according to the effect evaluation coefficient is as follows: Train an LSTM prediction model based on historical processing data, establish a mapping relationship library between the effect evaluation coefficient and processing parameters. When it is detected that the value of the effect evaluation coefficient deviates from the target interval, call the mapping relationship library to generate a dynamic parameter compensation instruction, where the processing parameters include drilling feed rate, spindle speed, and geometric parameters of the chip breaker.

[0037] Preferably, when the effect evaluation coefficient E s ≥0.9, it is determined as excellent chip evacuation, and an optimization suggestion to maintain the current parameters is generated;

[0038] When the effect evaluation coefficient 0.7 ≤ E s <0.9, it is determined as good chip evacuation, and an optimization suggestion to reduce the feed rate by 5% - 10% is generated;

[0039] When the effect evaluation coefficient 0.5 ≤ E s <0.7, it is determined as critical chip evacuation, and an optimization suggestion to increase the spindle speed by 10% - 15% is generated;

[0040] When the effect evaluation coefficient E s <0.5, it is determined as abnormal chip evacuation, and an optimization suggestion to replace the tool or adjust the geometric parameters of the chip breaker is generated.

[0041] An evaluation system for the chip evacuation effect in the drilling process based on the chip volume ratio, the evaluation system is used to execute the evaluation method described in any one of claims 1 - 9, and specifically includes:

[0042] A three - dimensional scanning module, used to perform non - contact optical scanning of the chip surface morphology and generate point cloud data;

[0043] A data processing module, used to calculate the chip volume ratio and chip fracture coefficient, as well as the final effect evaluation coefficient;

[0044] An effect evaluation module, used to generate the chip evacuation effect level and corresponding optimization suggestions according to the effect evaluation coefficient.

[0045] Compared with the prior art, the beneficial effects of the present invention are:

[0046] Through multi-dimensional feature fusion and intelligent decision-making mechanisms, the present invention constructs a closed-loop evaluation system for the chip removal effect in drilling. First, innovatively, the helical shape, winding state, and fracture uniformity of the chips are incorporated into a unified evaluation model, significantly improving the accuracy of chip jamming risk prediction and the precision of process diagnosis. Second, a dynamic weight adjustment mechanism is established to break through the limitations of traditional static threshold evaluation, enabling the system to adapt to different material characteristics and tool working conditions. At the same time, an intelligent mapping model for process parameters is developed to achieve real-time optimization and compensation of key parameters such as feed rate and rotational speed, effectively reducing the chip removal failure rate and extending the tool life. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 is a schematic diagram of the overall method flow of the present invention;

[0048] Figure 2 is a schematic diagram of the module structure of the present invention;

[0049] Figure 3 is a schematic diagram of the structure of a single-segment chip of the present invention;

[0050] Figure 4 is a schematic diagram of the winding condition of a double-segment chip of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0051] To make the objectives, technical solutions, and advantages of the present invention clearer and more understandable, the following further details the present invention in conjunction with specific embodiments.

[0052] It should be noted that unless otherwise defined, the technical terms or scientific terms used in the present invention should have the ordinary meanings understood by those of ordinary skill in the field to which the present invention pertains. The "first", "second", and similar terms used in the present invention do not denote any order, quantity, or importance, but are only used to distinguish different components. The terms "including" or "comprising" and the like mean that the elements or items appearing before this word cover the elements or items listed after this word and their equivalents, without excluding other elements or items. The terms "connected" or "coupled" and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right", etc. are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0053] Embodiment:

[0054] Please refer to Figures 1 to 4 , the present invention provides a technical solution:

[0055] An evaluation method for the chip removal effect in the drilling process based on the chip volume ratio, the specific steps include:

[0056] S1: Conduct optical scanning on the chips generated during the cutting process to collect the three-dimensional morphological data of the chips.

[0057] The three-dimensional morphological data of the chips includes the spiral outer diameter, pitch, and spiral axis angle. The logic for collecting the three-dimensional morphological data of the chips in step S1 is as follows:

[0058] Collect the surface morphology of the chips through a line laser three-dimensional scanner to generate a high-density point cloud data set composed of three-dimensional coordinate points (x, y, z). Then, align the data coordinate system by fitting the spiral axis based on the RANSAC algorithm, and control the axis angle deviation within ±0.1°.

[0059] The calculation methods for the spiral outer diameter and pitch are as follows:

[0060] Perform spatial pose matching between the point cloud data set and a preset theoretical spiral model, calculate the measured values of the spiral outer diameter 2r and pitch P through the least squares method, and use the error rate between the measured value and the theoretical value as the parameter credibility index. When the error rate is less than the preset error threshold, the parameter is considered credible, where r represents the spiral radius.

[0061] In this step, a non-contact optical scanning technology is used to obtain the surface topology information of the chips and generate a high-density point cloud data set. Then, align the measured point cloud with the theoretical spiral model through a spatial pose matching algorithm, which can eliminate the coordinate system deviation. At the same time, during the spiral axis calibration process, the optimal axis equation is fitted based on the point cloud distribution characteristics, which can ensure the accuracy of subsequent parameter extraction, thereby providing standardized geometric input data for the calculation of various subsequent coefficients.

[0062] S2: Calculate the chip space ratio and chip fracture coefficient based on the three-dimensional morphological data of the chips, and generate a final effect evaluation coefficient according to the chip space ratio and chip fracture coefficient.

[0063] The calculation method for the chip space ratio is as follows:

[0064]

[0065] In the formula, R v represents the chip space ratio, V c , V m respectively represent the chip volume and material removal volume, k1 to k3 all represent preset adjustment coefficients, k1 to k3 are all greater than 0, and k1 + k2 + k3 = 1, L cw represents the winding length coefficient, D cw represents the winding tightness coefficient, C b represents the average chip fracture coefficient.

[0066] The chip volume ratio calculation formula here can comprehensively reflect the proportional relationship between the chip volume and the material removal amount, and quantify the chip evacuation resistance through three correction terms: the winding length coefficient, the winding tightness coefficient, and the chip fracture coefficient. The winding length coefficient reflects the length difference between adjacent chip segments. The smaller the difference, the more continuous the chip flow; the winding tightness coefficient is used to evaluate the uniformity of the chip pitch. The smaller the value, the more stable the chip winding structure; the chip fracture coefficient is used to measure the length dispersion of the chip fracture segments. A low dispersion indicates excellent fracture morphology uniformity.

[0067] The calculation methods of the chip volume and the material removal volume are as follows:

[0068] V c = πr 2 Pn

[0069] V m = fπr 2 n

[0070] In the formula, n represents the number of helical turns of the chip, and f represents the drilling feed rate.

[0071] When calculating the winding length coefficient and the winding tightness coefficient, collect all pairs of mutually wound chip groups. Label the longer chip in each group as chip A and the shorter chip as chip B, and calculate the average length and average pitch of chip A and chip B in all chip groups respectively;

[0072] The calculation methods of the winding length coefficient and the winding tightness coefficient are as follows:

[0073]

[0074] In the formula, l A 、l B represent the average lengths of chip A and chip B respectively, and P A,i 、P B,i represent the average pitches of the i-th turn of chip A and chip B respectively. The subscript i represents the index of the turn number, and i ∈ [1, n].

[0075] The total length of the mutual overlap and winding of adjacent helical chips along the helical axis direction. The longer the winding length, the more chip winding, the greater the chip evacuation resistance, and it is easy to cause chip evacuation groove blockage. Based on the winding length, the chip evacuation effect under different cutting conditions can be quantitatively analyzed. Therefore, the winding length coefficient here can reflect the difference in the lengths of adjacent chips. The closer it is to 1, the smaller the length of the chips that are wound. When it is equal to 0, there is no winding.

[0076] When calculating the chip breakage coefficient, all chips with breakage points are collected, divided into several fracture segments according to the breakage points of the chips, and the chip breakage coefficient of each fractured chip is calculated. Specifically, chips with damaged parts but not completely broken are collected. Assuming the chip has one breakage point, it is divided into two fracture segments. If it has two different breakage points, it is divided into three fracture segments, and so on.

[0077] The calculation method of the chip breakage coefficient is as follows:

[0078]

[0079] In the formula, l ′ j represents the length of the j-th fracture segment of the chip, the subscript j represents the index of the fracture segment, m represents the total number of fracture segments. The smaller the chip breakage coefficient, the better the fracture morphology of the chip;

[0080] Finally, the average value of the chip breakage coefficients of all fractured chips is calculated to obtain the average chip breakage coefficient.

[0081] Here, the detection of the fracture segment can be carried out by the curvature mutation characteristics of adjacent fracture points. The chip breakage coefficient quantifies the consistency of the fracture morphology by calculating the relative deviation of the length of each fracture segment from the average length. This coefficient is strongly correlated with the geometric parameters of the chip breaker groove. When it approaches 0, it indicates that the chip fracture length is highly uniform and the chip evacuation resistance is significantly reduced.

[0082] In this step, by constructing a dynamic chip accommodation ratio calculation formula and introducing a multi-dimensional correction mechanism on the basis of the traditional volume ratio, a refined evaluation of the chip evacuation effect is realized, which can better evaluate the basic relationship between the chip generation efficiency and the material removal amount, the length difference between adjacent chip segments, the uniformity of the chip pitch, and the length dispersion of the chip fracture segments. Thus, the complex chip morphology characteristics are transformed into quantifiable engineering indicators, eliminating the subjective deviation of manual evaluation and being applicable to the standardized process design of different material-tool combinations.

[0083] S3: Generate a chip evacuation effect level based on the final effect evaluation coefficient, and give corresponding optimization suggestions according to the chip evacuation effect level.

[0084] The calculation method of the effect evaluation coefficient is as follows:

[0085] E s = a × R v + β × τ

[0086] In the formula, E sDenote the effect evaluation coefficient, α and β respectively denote the preset weight coefficients, both of which are greater than 0, and α + β = 1. τ represents an intermediate parameter, and its calculation method is as follows:

[0087]

[0088] In the formula, C y denotes the fracture threshold, and C y ∈ [0.45, 0.65].

[0089] Here, the two groups of preset weight coefficients can be adjusted according to expert experience or actual use, and respectively represent the weighing degrees in two directions of the direct influence of the chip removal groove load and the promotion of chip removal by uniform fracture. By setting an intermediate parameter, this item can be set to zero when the chip fracture coefficient is too large to shield abnormal fracture interference.

[0090] Based on historical processing data, train the LSTM prediction model to establish a mapping relationship library between the effect evaluation coefficient and processing parameters. When it is detected that the value of the effect evaluation coefficient deviates from the target interval, call the mapping relationship library to generate a dynamic parameter compensation instruction, where the processing parameters include drilling feed rate, spindle speed, and geometric parameters of the chip breaker groove.

[0091] When the effect evaluation coefficient E s ≥ 0.9, it is determined as excellent chip removal, and an optimization suggestion to maintain the current parameters is generated;

[0092] When the effect evaluation coefficient 0.7 ≤ E s < 0.9, it is determined as good chip removal, and an optimization suggestion to reduce the feed rate by 5% - 10% is generated;

[0093] When the effect evaluation coefficient 0.5 ≤ E s < 0.7, it is determined as critical chip removal, and an optimization suggestion to increase the spindle speed by 10% - 15% is generated;

[0094] When the effect evaluation coefficient E s < 0.5, it is determined as abnormal chip removal, and an optimization suggestion to replace the tool or adjust the geometric parameters of the chip breaker groove is generated.

[0095] In this step, the interactive influence between the chip accommodation state and the fracture morphology is incorporated into a unified evaluation system, which improves the accuracy of chip removal effect evaluation. At the same time, quantitative analysis of the effect evaluation coefficient can be realized, and a corresponding intelligent decision-making mechanism can be obtained, so as to upgrade the chip removal effect evaluation from "passive monitoring" to "active regulation", playing a role in improving the stability and economy of the drilling process and providing core technical support for process optimization in the intelligent manufacturing scenario

[0096] An evaluation system for chip removal effect in the drilling process based on the chip accommodation ratio, which is used to execute the above evaluation method, specifically includes:

[0097] A three-dimensional scanning module for performing non-contact optical scanning of the chip surface morphology and generating point cloud data;

[0098] A data processing module for calculating the chip accommodation ratio, chip fracture coefficient, and the final effect evaluation coefficient;

[0099] An effect evaluation module for generating a chip evacuation effect level and corresponding optimization suggestions according to the effect evaluation coefficient.

[0100] In summary, the present invention constructs a closed-loop evaluation system for drilling chip evacuation effect through multi-dimensional feature fusion and intelligent decision-making mechanism. First, innovatively incorporates the chip spiral morphology, winding state, and fracture uniformity into a unified evaluation model, significantly improving the accuracy of chip jamming risk prediction and the precision of process diagnosis; second, establishes a dynamic weight adjustment mechanism, breaking through the limitations of traditional static threshold evaluation, enabling the system to adapt to different material characteristics and tool working conditions; at the same time, develops an intelligent mapping model for process parameters, realizing real-time optimization compensation of key parameters such as feed rate and rotational speed, effectively reducing the chip evacuation failure rate and extending the tool service life.

[0101] The above formulas are all dimensionless and take their numerical values for calculation. The formulas are obtained by collecting a large amount of data for software simulation to obtain a formula closest to the actual situation. The preset parameters in the formulas are set by those skilled in the art according to the actual situation.

[0102] The above embodiments can be implemented in whole or in part by software, hardware, firmware, or any other combination. When implemented using software, the above embodiments can be implemented in whole or in part in the form of a computer program product. Those skilled in the art can realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed by hardware or software methods depends on the specific application and design constraints of the technical solution.

[0103] The units described as separate components may or may not be physically separated. The components shown as units may or may not be physical units, and may be located in one place, or may be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0104] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present application, and all should be covered by the protection scope of the present application.

Claims

1. An evaluation method for the chip removal effect in the drilling process based on the chip volume ratio, characterized in that, The specific steps include: S1: Optically scan the chips generated during the cutting process to collect three-dimensional shape data of the chips; S2: Calculate the chip volume ratio and chip fracture coefficient based on the three-dimensional shape data of the chips, and generate the final effect evaluation coefficient according to the chip volume ratio and chip fracture coefficient; S3: Generate a chip evacuation effect level based on the final effect evaluation coefficient, and give corresponding optimization suggestions according to the chip evacuation effect level.

2. The evaluation method for the chip removal effect during the drilling process based on the chip volume ratio according to claim 1, wherein: The three-dimensional shape data of the chips includes the spiral outer diameter, pitch, and spiral axis angle. The logic for collecting the three-dimensional shape data of the chips in step S1 is as follows: Collect the surface shape of the chips through a line laser three-dimensional scanner to generate a high-density point cloud data set composed of three-dimensional coordinate points (x, y, z). Then, align the data coordinate system by fitting the spiral axis based on the RANSAC algorithm, and control the axis angle deviation within ±0.1°.

3. The evaluation method for the chip removal effect in the drilling process based on the chip volume ratio according to claim 2, wherein: The calculation methods for the spiral outer diameter and pitch are as follows: Perform spatial pose matching between the point cloud data set and a preset theoretical spiral model, calculate the measured values of the spiral outer diameter 2r and pitch P by the least squares method, and use the error rate between the measured value and the theoretical value as the parameter credibility index. When the error rate is less than the preset error threshold, the parameter is considered credible, where r represents the spiral radius.

4. The evaluation method for the chip removal effect in the drilling process based on the chip volume ratio according to claim 3, characterized in that: The calculation method for the chip volume ratio is as follows: where R v represents the chip volume ratio, V c , V m respectively represent the chip volume and the material removal volume, k1 to k3 all represent preset adjustment coefficients, k1 to k3 are all greater than 0, and k1 + k2 + k3 = 1, L cw represents the winding length coefficient, D cw represents the winding tightness coefficient, represents the average chip fracture coefficient; The calculation methods for the chip volume and material removal volume are as follows: V c = πr 2 Pn V m = fπr 2 n In the formula, n represents the number of spiral turns of the chips, and f represents the drilling feed rate.

5. The evaluation method for the chip removal effect in the drilling process based on the chip volume ratio according to claim 4, wherein: When calculating the winding length coefficient and winding tightness coefficient, collect all pairs of mutually wound chip groups, label the longer chips as chip A and the shorter chips as chip B, and calculate the average length and average pitch of chip A and chip B in all chip groups respectively; The calculation methods for the winding length coefficient and winding tightness coefficient are as follows: where \(l\) A and \(l\) B represent the average lengths of chip A and chip B respectively, \(P\) A,i and \(P\) B,i represent the average pitches of the \(i\)-th turn of chip A and chip B respectively, the subscript \(i\) represents the index of the number of turns, and \(i\in[1,n]\).

6. The evaluation method for chip evacuation effect during drilling based on chip volume ratio according to claim 5, wherein: When calculating the chip fracture coefficient, collect all chips with breakage points, divide them into several groups of fracture segments according to the breakage points of the chips, and calculate the chip fracture coefficient of each fractured chip; The calculation method for the chip fracture coefficient is as follows: where l ′ j represents the length of the j-th broken segment of the chip, the subscript j represents the index of the broken segment, m represents the total number of broken segments, and the smaller the chip fracture coefficient, the better the fracture morphology of the chip; Finally, calculate the mean value of the chip breakage coefficients of all the broken chips to obtain the average chip breakage coefficient 7. An evaluation method for the chip removal effect in the drilling process based on the chip volume ratio according to claim 6, characterized in that: The calculation method for the effect evaluation coefficient is as follows: E s = a × R v + β × τ where E s represents the effect evaluation coefficient, a and β respectively represent the preset weight coefficients, both of which are greater than 0, and a + β = 1, τ represents the intermediate parameter, and its calculation method is as follows: where C y represents the fracture threshold, and C y ∈[0.45, 0.65].

8. The evaluation method for the chip evacuation effect in the drilling process based on the chip volume ratio according to claim 7, wherein: The logic for the optimization suggestions based on the effect evaluation coefficient is as follows: Train an LSTM prediction model based on historical processing data, establish an effect evaluation coefficient - processing parameter mapping relationship library. When it is detected that the value of the effect evaluation coefficient deviates from the target interval, call the mapping relationship library to generate a dynamic parameter compensation instruction, where the processing parameters include the drilling feed rate, spindle speed, and geometric parameters of the chip breaker groove.

9. The evaluation method for the chip evacuation effect in the drilling process based on the chip volume ratio according to claim 7, wherein: When the effect evaluation coefficient E s ≥ 0.9, it is determined as excellent chip removal, and an optimization suggestion to maintain the current parameters is generated; When the effect evaluation coefficient 0.7 ≤ E s <0.9, it is determined as good chip evacuation, and an optimization suggestion of reducing the feed rate by 5% - 10% is generated; When the effect evaluation coefficient 0.5 ≤ E s <0.7, it is determined as critical chip evacuation, and an optimization suggestion of increasing the spindle speed by 10% - 15% is generated; When the effect evaluation coefficient E s < 0.5, it is determined that the chip removal is abnormal, and an optimization suggestion for replacing the tool or adjusting the geometric parameters of the chip breaker is generated.

10. An evaluation system for the chip removal effect in the drilling process based on the chip volume ratio, characterized in that: The evaluation system is used to execute the evaluation method described in any one of claims 1-9, and specifically includes: A three-dimensional scanning module for performing non-contact optical scanning of the chip surface shape and generating point cloud data; A data processing module for calculating the chip volume ratio and chip fracture coefficient, as well as the final effect evaluation coefficient; An effect evaluation module for generating a chip evacuation effect level and corresponding optimization suggestions according to the effect evaluation coefficient.

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