A dynamic timing rapid analysis method based on a graph neural network
By adopting a hierarchical two-stage framework based on graph neural networks, the problems of chip performance waste caused by static timing analysis and high computational overhead of dynamic timing analysis are solved, achieving efficient and accurate dynamic timing prediction, which is suitable for circuit optimization and dynamic voltage and frequency adjustment at different process nodes.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI JIAOTONG UNIV
- Filing Date
- 2025-03-10
- Publication Date
- 2026-07-10
AI Technical Summary
Existing static timing analysis methods lead to wasted chip performance, while traditional dynamic timing analysis has huge computational overhead and is difficult to efficiently model dynamic load information. Existing machine learning methods lack model transfer capabilities and have high computational costs in dynamic timing analysis.
A hierarchical two-stage framework based on graph neural networks is adopted, which combines graph representation learning and dynamic temporal prediction. Circuit topology learning and dynamic temporal prediction are performed through graph autoencoders and graph attention networks, and multi-task learning and adaptive learning rate decay optimization models are combined.
It improves the prediction accuracy of dynamic signal arrival time, optimizes chip power consumption and performance, significantly reduces computing costs, is suitable for circuit optimization at different process nodes, supports dynamic voltage and frequency adjustment, and enables fast timing analysis of large-scale circuits.
Smart Images
Figure CN120337835B_ABST
Abstract
Description
[Technical Field]
[0001] This invention relates to the field of integrated circuit design and optimization, particularly timing analysis techniques in electronic design automation (EDA). Specifically, it relates to a dynamic timing analysis method based on graph neural networks (GNNs). This method is applicable to artificial intelligence (AI) accelerators, high-performance computing (HPC) chips, and other computationally intensive circuits. It can effectively predict the dynamic signal arrival times of circuits under different workloads, improving the accuracy of timing analysis and optimizing computational efficiency. [Background Technology]
[0002] In chip design and optimization, timing analysis is a crucial step to ensure correct chip operation. Currently, the mainstream timing analysis methods mainly include static timing analysis (STA) and dynamic timing analysis (DTA).
[0003] Static timing analysis (STA) is a widely used analysis method that calculates the operating frequency of a chip by evaluating the worst-case signal propagation delay. However, STA suffers from the following major problems: overly conservative estimation, as STA is based on worst-case assumptions, leading to lower chip frequency settings and impacting overall performance; failure to consider workload effects, as STA ignores dynamic changes in the input signal and cannot accurately predict timing behavior under real-world operating conditions; and high computational resource consumption, as the computational complexity of STA increases rapidly with chip size, making it difficult to meet the optimization requirements of large-scale AI accelerators.
[0004] Compared to ST (Signal-Based Timing), Dynamic Timing Analysis (DTA) performs timing evaluation under the actual workload of the chip, providing more accurate timing information. More accurate signal arrival time prediction: DTA can capture the behavior of the circuit under real load, reducing over-design issues caused by STA and improving chip utilization; Support for Dynamic Voltage and Frequency Scaling (DVFS): DTA can combine Dynamic Voltage and Frequency Scaling (DVFS) strategies to optimize chip power consumption; Suitable for compute-intensive applications: DTA has broad application prospects in compute-intensive applications such as AI accelerators and deep learning inference hardware.
[0005] However, the main challenges of DTA are: huge computational overhead. Traditional DTA relies on gate-level simulation, which requires a large number of SPICE simulations, resulting in long computation time and high storage requirements; and difficulty in efficiently modeling dynamic load information. DTA needs to consider complex information such as input signal flipping and time arc constraints, and traditional methods cannot guarantee computational efficiency while achieving high-precision prediction.
[0006] In recent years, machine learning methods have been applied to solve many challenging problems in design automation, such as logistic probability prediction, netlist classification, and static timing prediction. However, existing machine learning methods still have the following problems in dynamic timing analysis tasks: lack of modeling of dynamic loads, with most studies focusing only on static circuit structures and ignoring input signal flips and workload changes; limited model generalization ability, as existing methods require separate training of models for different process nodes, resulting in insufficient model transferability; and still high computational cost: although deep learning methods can improve computational efficiency, traditional machine learning methods still struggle to efficiently handle large-scale circuits.
[0007] Graph Neural Networks (GNNs) are powerful machine learning models that excel at handling data with graphical structures. By representing data as a graph (a data structure consisting of nodes and edges) and processing it using neural networks, GNNs enable deep learning of complex data.
[0008] In graph neural networks, each node can be understood as an element or entity in the data, while edges represent the relationships between these elements or entities. By passing the entire graph data through a neural network, graph neural networks are able to capture complex patterns and structures within the data.
[0009] In practical applications, graph neural networks can be applied to various types of data with graph structures, such as social networks, protein-protein interaction networks, and knowledge graphs. Transforming these problems into graph problems helps to better understand and solve them.
[0010] Because graph neural networks (GNNs) have unique advantages over other machine learning methods in processing graph data structures, and circuit structures are very easy to abstract into graph data structures, GNNs have received widespread attention in the field of design automation. However, current methods for timing prediction using GNNs are still mainly limited to static timing information and have not fully integrated the dynamic changes in circuit workload.
[0011] This invention addresses the technical problem of wasted chip performance caused by existing static timing analysis (STA) methods by proposing a dynamic timing analysis method based on graph neural networks (GNN). [Summary of the Invention]
[0012] The purpose of this invention is to provide a dynamic timing analysis method based on graph neural networks (GNNs) to improve the prediction accuracy of dynamic signal arrival time of circuits at different process nodes (such as 45nm, 7nm, etc.), optimize chip power consumption and performance, and significantly improve computational efficiency.
[0013] This invention constructs a hierarchical two-stage framework, combining graph representation learning and dynamic timing prediction, to achieve rapid timing analysis of AI accelerators, computationally intensive chips, and other digital circuits, including the following steps:
[0014] S1. Circuit diagram modeling: Represent the topology and workload characteristics of the target circuit as a graph data structure with nodes and edges. Nodes represent the circuit's input / output pins (I / O Pins) and standard cells (Standard Cells). Edges represent the circuit's connection relationships and timing arcs, including timing parameters such as minimum / maximum rise delay and minimum / maximum fall delay.
[0015] S2. The pre-trained graph representation learning model uses a graph autoencoder (GAE) for unsupervised learning of the circuit topology to learn the structural features of the circuit. Combined with supervised learning tasks, it predicts the pin flip states of the circuit to improve the adaptability of the GNN model to dynamic timing changes. After training, the global circuit embedding vector of the circuit is obtained as the input of the timing prediction model.
[0016] S3. Dynamic timing prediction based on graph neural networks (GNN): Construct a timing prediction model based on graph attention network (GAT); combine pre-trained circuit embedding information and dynamic load features to predict signal arrival time under different workloads through regression learning; adopt the edge feature enhancement strategy and combine the constraint information of timing arcs to optimize the GNN model's ability to model circuit timing.
[0017] S4. Joint Fine-tuning optimization: A multi-task learning strategy is adopted to jointly optimize the pre-trained GNN model and the time series prediction model; the mean squared error (MSE) loss function is used to optimize the dynamic time series prediction task and improve the prediction accuracy; and adaptive learning rate decay is combined to improve the convergence speed of the model.
[0018] S5. Test the trained graph neural network-based machine learning model on different test datasets, and use the graph neural network-based machine learning model to quickly predict the dynamic delay of circuits of different sizes and under different load conditions.
[0019] Preferably, the circuit diagram data structure further includes node weights and edge weights, wherein: node weights include the logic type of circuit pins, input / output characteristics, etc.; edge weights include timing parameters such as minimum / maximum rise delay and minimum / maximum fall delay, so as to enhance the expressive power of circuit topology information.
[0020] Preferably, the pre-trained graph representation learning model combines graph autoencoder (GAE) with multi-task learning, wherein: unsupervised learning is used to reconstruct the circuit topology to improve the generalization ability of the GNN model; and supervised classification tasks are used to predict the input pin flip state to enhance the accuracy of dynamic timing prediction.
[0021] Preferably, the dynamic temporal prediction model adopts a graph attention network (GAT)-based structure and incorporates the following optimization strategies: Edge Feature Enhancement: Utilizing temporal constraint information to optimize the signal propagation modeling capability; Global Circuit Embedding: Combining the global features output by the pre-trained GNN model to improve prediction stability.
[0022] Preferably, the dynamic time-series prediction task employs an adaptive learning rate decay strategy, wherein: a larger learning rate is used in the early stage of training to accelerate convergence; and an exponential decay strategy is used in the later stage of training to improve the final prediction accuracy and reduce the risk of overfitting.
[0023] Preferably, the method is applicable to different process nodes, including but not limited to: 45nm process: suitable for chip optimization of mature process nodes; 7nm process: suitable for AI accelerator optimization of advanced processes; other advanced processes: suitable for timing optimization of future high-performance computing chips.
[0024] Preferably, the method can be applied to a variety of computationally intensive functional units, including but not limited to: multiplier units (MULs): used for digital signal processing and AI accelerator computation; multiply-accumulate units (MACs): suitable for deep learning computations such as convolutional neural networks (CNNs); matrix multiplication units (MMUs): used for large neural networks and high-performance computing tasks.
[0025] Preferably, the method can be further combined with a dynamic voltage and frequency scaling (DVFS) strategy to optimize the chip's power consumption and computing performance, wherein: by combining dynamic timing prediction, the circuit operating frequency is automatically adjusted to improve the energy efficiency ratio; and the voltage and frequency are reduced under low load conditions to reduce power consumption and improve chip lifespan.
[0026] Preferably, the method supports parallel inference optimization to improve computational efficiency, wherein: batch inference is used to process multiple workloads simultaneously, thereby improving the throughput of timing prediction; and GPU acceleration is combined to achieve fast dynamic timing analysis of large-scale circuits.
[0027] This invention provides an efficient and accurate dynamic timing analysis method, which is of significant value in computationally intensive applications such as AI accelerators and high-performance computing chips. Its main technical advantages include: 1. Improved timing prediction accuracy: Combining graph neural networks (GNNs) allows for the capture of circuit structural information and dynamic load changes, improving prediction accuracy and reducing over-design issues compared to traditional static timing analysis (STA); 2. Support for different process nodes: Applicable to 45nm, 7nm, and more advanced semiconductor process nodes, improving cross-process migration capabilities; 3. Significantly reduced computational costs: Compared to traditional methods that obtain dynamic delays through gate-level simulation, this method achieves a 50-fold computational speedup on AI accelerator circuits, meeting the needs of large-scale circuit optimization; 4. Enhanced model generalization ability: Employing an unsupervised + supervised multi-task learning strategy improves the model's adaptability to different circuit topologies and load conditions, reducing the risk of overfitting; 5. Optimization of chip power consumption and performance: Combined with dynamic timing prediction, it can be further applied to dynamic voltage and frequency regulation (DVFS) strategies to optimize chip power consumption and improve computational efficiency. This invention combines graph representation learning with dynamic timing analysis to provide an efficient and accurate timing prediction method, which has broad application prospects in the design and optimization of future high-performance chips. [Attached Image Description]
[0028] Figure 1 This is a flowchart of a dynamic time series fast analysis method based on graph neural networks.
[0029] Figure 2 This is an example structure diagram of a graph neural network machine learning model.
Detailed Implementation Methods
[0030] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.
[0031] Example
[0032] This embodiment implements a dynamic time series fast analysis method based on graph neural networks for the time series analysis of functional units in AI accelerators. By learning graph representations and dynamic time series prediction, it improves the accuracy of signal arrival time prediction and optimizes computational overhead.
[0033] Figure 1 This is a flowchart of a dynamic time series fast analysis method based on graph neural networks. (Example:) Figure 1 As shown, the implementation process includes: generating training and testing datasets, constructing a graph data structure, model pre-training, joint fine-tuning, and model validation; specifically, it includes the following steps:
[0034] S1. Generation of the dataset:
[0035] S1.1 Functional Unit Selection: Select typical functional units in the AI accelerator (such as multipliers (MULs), multiply-accumulate units (MACs), and matrix multiplication units (MMUs)).
[0036] S1.2 Process Node Coverage: Standard cell libraries for 45nm and 7nm process nodes are used, representing mature and advanced processes respectively, to ensure that the model can adapt to the timing characteristics differences (such as latency, power consumption, and noise margin) of different process nodes. 。
[0037] S1.3 Logic Synthesis (Cadence Genus) and Place & Route (Cadence Innovus):
[0038] Logic synthesis: converting a high-level description of a circuit (such as Verilog code) into a gate-level netlist to determine the connections between logic gates;
[0039] Placement and routing: Based on physical design rules, determine the physical location of logic gates on the chip and the path of metal interconnects, and generate real timing path information (such as interconnect delays);
[0040] S1.4 Generates Standard Delayed Format (SDF):
[0041] Timing parameters are extracted using static timing analysis (STA) to generate a standard delay format (SDF) file, which contains key information such as the minimum / maximum rise delay and minimum / maximum fall delay for each timing path in the circuit.
[0042] S1.5 gate-level simulation (Synopsys VCS):
[0043] Input a randomly generated workload signal (such as a sequence of input pin level toggles) to simulate the actual operating scenario of the circuit;
[0044] Dynamic delay data is obtained through simulation, which is the actual time it takes for a signal to propagate from the input pin to the output pin (related to the load and input state).
[0045] S1.6 Dataset Construction:
[0046] The input pin flip information and the corresponding circuit dynamic delay are randomly generated to cover different load scenario datasets for subsequent model training.
[0047] S2. Graph Data Structure Construction: The node information of the graph structure includes input / output pins (I / O pins), standard cell logic gates (Gates), and encodes the gate type and its functional attributes; the edge information includes the minimum / maximum rise delay and minimum / maximum fall delay extracted from the SDF file, and forms directed timing arcs; in addition, the input signal state and internal pin toggle information of different workloads at time steps t and t-1 are recorded.
[0048] S3. Pre-trained Graph Representation Learning Model: First, a graph representation learning model based on GAE is constructed, using unsupervised learning to reconstruct the circuit topology and improve the model's generalization ability. Next, supervised learning is used to predict the input pin toggle states, enhancing adaptability to dynamic load changes. Finally, after training, a global circuit embedding vector is generated for timing prediction tasks. When building the model, a graph convolutional neural network (GCN) is used as the encoder for graph embedding computation. Throughout the pre-training process, three weighted loss functions are used: topology reconstruction loss L... adj The circuit structure reconstruction error is calculated based on binary cross-entropy; the pin flipping classification loss L... pin Cross-entropy loss is used to improve the accuracy of flipped state classification; workload reconstruction loss L workload Binary cross-entropy loss is used to optimize the input state reconstruction effect; the loss function for the entire pre-training phase is L. pretrained =L adj +L pin +λL workload In the formula, Lpretrained L represents the overall loss of the pre-trained model. adj L represents the topology reconstruction loss. pin L represents the pin-to-pin classification loss. workload Let λ be the workload reconstruction loss, and λ be a hyperparameter used to adjust the weight of the workload reconstruction loss in the overall loss function.
[0049] S4. Training of a Dynamic Timing Prediction Model Based on Graph Neural Networks: First, we use a Graph Attention Network (GAT) for feature extraction and employ an edge feature enhancement strategy, combining circuit topology and timing constraint information to optimize signal propagation modeling capabilities. Simultaneously, we calculate the attention coefficients of the adjacency matrix for weighted aggregation of node information. During dynamic timing prediction, the input is a combination of the global circuit embedding and workload features obtained from the pre-trained model. The output is the predicted signal arrival time. To improve the overall prediction accuracy, as an auxiliary prediction task, we simultaneously predict the pin flipping status within the circuit network and calculate the loss function for this part. Finally, in the joint tuning phase, we add a certain weight multiplied by the loss function of the pre-trained model. The loss function in the entire joint fine-tuning process is L. total =L arrival +L inc_pin +βL pretrained In the formula, L total L represents the loss function during the entire joint fine-tuning process. arrival L represents the prediction loss for signal arrival time under dynamic excitation. inc_pin L represents the loss for predicting the switching of each pin within the circuit. pretrained β is the loss of the pre-trained model, and β is a hyperparameter used to adjust the weight of the pre-trained model's loss in the overall loss.
[0050] S5. After complete pre-training and joint fine-tuning, the trained model is tested and used on the test dataset.
[0051] In particular, to ensure the accuracy of the circuit topology during the construction of the S2 graph data structure, this invention further refines the characteristics of nodes and edges when constructing the graph data structure:
[0052] S21. Node characteristics include input / output pins (I / O Pins) and standard cells, with information such as logic gate type, input drive capability, and load capability for each standard cell, and the cell type is represented by a 9-bit binary encoding method; edge characteristics include the timing constraints of the circuit, including information such as minimum / maximum rise delay and minimum / maximum fall delay extracted from the standard delay format (SDF) file; dynamic load characteristics include recording the load state at time t and time t-1 for input pins, using 0 or 1 to represent the current working load state, while this characteristic of non-input nodes is set to -1 to ensure the rationality of dynamic characteristics.
[0053] Specifically, in the process of pre-training the S3 graph representation learning model, this invention further optimizes the model's learning objective and loss function when constructing the pre-trained model based on graph autoencoders (GAE):
[0054] S31. Topology Reconstruction Task Optimization: Based on GAE, an edge prediction task is introduced to enhance the model's ability to understand circuit topology relationships. The adjacency matrix reconstruction error L is calculated. adj At the same time, binary cross-entropy loss is used to enable the model to more accurately recover the circuit structure; pin flipping classification optimization: a three-class supervised task is used to identify three cases: 0→1 flipping, 1→0 flipping, and no flipping, and the loss L is calculated. pin A weighted cross-entropy strategy is employed to address class imbalance in the training data. Input load reconstruction task optimization: For workload reconstruction of input pins, a masking mechanism is introduced, calculating the binary cross-entropy loss L only for the actual input nodes. workload This prevents features from non-input nodes from affecting model learning.
[0055] In particular, during the training of the S4 dynamic time-series prediction model based on graph neural networks, this invention performs specific optimizations on the graph attention network (GAT) to improve the prediction accuracy of signal arrival time:
[0056] S41. Introduction of Edge Feature Enhancement Mechanism: When calculating attention coefficients, not only node features are used, but also the temporal constraint information of edges is combined. Edge-Enhanced GAT (EGAT) is used to calculate attention weights, enabling the model to better capture the timing characteristics of the circuit; Multi-scale graph feature fusion: By stacking multiple GAT layers, the model learns the circuit topology at different scales, and finally obtains the global circuit embedding vector. Combined with the temporal constraint information, the stability of timing prediction is improved.
[0057] Specifically, during the training of the S4 graph neural network-based dynamic time-series prediction model, this invention employs a multi-task learning strategy to achieve joint optimization of the pre-trained model and downstream tasks:
[0058] S42. Joint Optimization Strategy: While optimizing the downstream dynamic timing prediction task, the pre-trained graph representation learning model is simultaneously fine-tuned to fully utilize circuit embedding features and improve the accuracy of signal arrival time prediction. Incremental Pin Flip Classification Task: Based on the original pre-trained pin flip prediction, an incremental correction task is introduced. That is, in the fine-tuning stage, the flip state classification is re-optimized by combining real workload data, so that the model can adapt to the actual circuit application environment. Adaptive Learning Rate Decay: To improve training stability, an exponential decay strategy is adopted, gradually reducing the learning rate in the later stages of training to prevent overfitting and improve the model's generalization ability.
[0059] Model training: The dynamic time series analysis method based on graph neural networks proposed in this invention adopts a phased training approach, including a pre-training phase and a joint fine-tuning phase.
[0060] 1) Pre-training stage: To improve the learning ability of circuit topology features, this invention uses a graph autoencoder (GAE) for pre-training, enabling the model to learn circuit structure information unsupervised. Simultaneously, supervised learning is used to optimize pin toggle state prediction, improving the model's generalization ability. First, ten AI accelerator benchmark circuits (MULs, MACs, MMUs) at the 45nm GPDK045 and 7nm ASAP7 process nodes are used. Then, logic synthesis (Cadence Genus), placement and routing (Cadence Innovus), static timing analysis (Synopsys PrimeTime), SDF annotation, and gate-level simulation (Synopsys VCS) are performed. Finally, 100,000 random input signals with different loads are generated, input pin toggle information is extracted, and converted into a graph data structure.
[0061] For the pre-trained network structure, a 7-layer Graph Convolutional Neural Network (GCN) is used for the encoder, with hidden layer dimensions of [256, 128, 128, 64, 64, 64, 32], ultimately mapping the circuit to a 32-dimensional latent space. For the decoder, the topology reconstruction decoder calculates the binary cross-entropy loss based on the circuit's adjacency matrix; the pin-flipping classification decoder uses a 3-layer MLP for flipping classification and calculates the weighted cross-entropy loss; and the input load reconstruction decoder reconstructs the input signal state using a single-layer MLP and calculates the loss. The hyperparameter λ in the pre-trained joint loss function is set to 0.1.
[0062] During the pre-training phase, the Adam optimizer was used with an initial learning rate of 0.001 and a batch size of 32. Training was performed for 200 epochs, and exponential learning rate decay was used, decreasing by a factor of 0.1 every 50 epochs.
[0063] 2) Joint fine-tuning stage: After the pre-training stage is completed, this invention further combines the pre-trained graph embedding vectors (Global Circuit Embedding) with the dynamic temporal prediction task to improve the prediction accuracy of the model through joint fine-tuning.
[0064] First, downstream task data is prepared by expanding the graph data structure and adding timing arc features, including edge features: minimum / maximum rise delay, minimum / maximum fall delay, and dynamic load information of input nodes, to enhance the model's adaptability to different workloads.
[0065] Next, during joint fine-tuning training, for the feature extractor, a 4-layer edge-enhanced graph attention network (Edge-enhanced GAT, EGAT) is used for feature extraction to improve the model's ability to model dynamic load changes. For dynamic time series regression prediction, a single-layer MLP regression is used to calculate the signal arrival time, and the mean squared error (MSE) loss function is used for training optimization.
[0066] Finally, for the entire joint fine-tuning, the weight hyperparameter β of the loss function for the pre-trained model was set to 0.1. The entire fine-tuning process still used the Adam optimizer, with an initial learning rate of 0.001, a batch size of 32, and a total training duration of 200 epochs. Exponential decay was employed, with the learning rate decreasing by a factor of 0.1 every 50 epochs.
[0067] Model testing: The present invention was tested on 10 benchmark circuits at 7nm and 45nm process nodes to evaluate its generalization ability. The test data included circuit structures of different sizes, from 4-bit MAC to 32-bit MMU and 10K unseen random input loads to ensure the model's generalization ability under different workloads.
[0068] At 45nm process technology, the mean square error (MSE) of the predicted dynamic delay in this invention is reduced by 25.49% compared to the multilayer perceptron (MLP) method and by 23.37% compared to the random forest (RF) method. At 7nm process technology, the MSE of the predicted dynamic delay in this invention is reduced by 31.92% compared to the MLP method and by 13.57% compared to the random forest (RF) method. In gate-level simulation, the computation time for analyzing one circuit is approximately 560.37 seconds.
[0069] Under the same conditions, this invention requires only 11.24 seconds, achieving a 50-fold speedup, which can meet the timing analysis requirements of large-scale circuits.
[0070] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM).
[0071] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and additions without departing from the principle of the present invention, and these improvements and additions should also be considered within the scope of protection of the present invention.
Claims
1. A dynamic time series analysis method based on graph neural networks, characterized in that, Includes the following steps: S1. Acquire dynamic time-series data covering different processes and load scenarios; S2. Circuit diagram modeling: Model the topology and workload characteristics of the target circuit and represent it as a graph data structure with nodes and edges. Nodes represent the functional units and input / output pins of the circuit, and edges represent the circuit connection relationships and timing arc information, combined with dynamic load information. S3. Graph Representation Learning: Unsupervised learning of the static topology of the circuit is performed through a pre-trained model based on graph autoencoder (GAE), and supervised learning of the dynamic load is combined to generate a global circuit embedding vector. S4. Use the trained graph neural network (GNN) to extract circuit structure features and combine them with dynamic workload information to generate a unified global circuit embedding vector; S4. Training and fine-tuning of dynamic temporal prediction model: The edge feature-enhanced graph attention network (EGAT) is used to combine the pre-trained global circuit embedding vector and temporal arc constraint information, and the arrival time of dynamic signals is predicted through regression learning. A multi-task learning strategy is used to jointly optimize the pre-trained model and downstream tasks. S5: Model Optimization and Application: Input the dynamic time series data into the trained model, use the optimized graph neural network (GNN) for dynamic time series analysis, and optimize the training process through an adaptive learning rate decay strategy to achieve dynamic time series analysis across process nodes.
2. The method according to claim 1, characterized in that, The node types of the graph data structure include: input / output pins (I / O pins), used to represent circuit input and output signals; standard cell logic gates, which represent different types of logic cells through multi-bit encoding; and signal toggle states, used to indicate changes in signal state at a specific time step.
3. The method according to claim 2, characterized in that, The circuit connection relationship is used to define the circuit topology; the timing arc information includes the minimum rise delay, maximum rise delay, minimum fall delay, and maximum fall delay; the signal propagation direction is used to indicate the direction in which the signal propagates along the timing arc.
4. The method according to claim 1, characterized in that... The pre-trained graph representation learning model The tasks include: a topology reconstruction task, which reconstructs the circuit topology based on a graph autoencoder (GAE); a pin flip classification task, which predicts the flip state of input pins through supervised learning, including rising flip 0→1, falling flip 1→0, and no flip; and an input signal reconstruction task, which uses a binary cross-entropy loss function to reconstruct the input load and improve the feature representation capability.
5. The method according to claim 1, characterized in that, The dynamic time-series prediction model is based on a graph attention network (GAT) and incorporates the following optimization strategies: edge feature enhancement, which improves the prediction ability of signal arrival time by fusing features of the temporal constraint information of edges; global embedding, which embeds the global circuit representation of the pre-trained model into the time-series prediction model to improve generalization ability; and supervised learning optimization, which uses the mean squared error loss function (MSE) for regression learning to optimize the prediction accuracy of signal arrival time.
6. The method according to claim 1, characterized in that, Dynamic timing prediction is a regression problem that aims to predict the worst-case signal arrival time on the critical path of a circuit.