Display panel and display device

Abstract

The invention provides a display panel and a display device, and relates to the technical field of display. A shift register in a gate drive circuit comprises a level transmission unit and a gating unit; a first control unit in the level transmission unit is configured to control a signal of a first node and a signal of a second node, and a first output unit is configured to output a level transmission signal; a level transmission signal of the ith-level shift register is used as an input signal of the jth-level shift register, 1 < = i < = N, 1 < = j < = N, and i is not equal to j; the gating unit is configured to output a gate driving signal at least according to a stage transmission signal and a frequency control signal; the display panel comprises a first voltage signal line and a second voltage signal line, the first voltage signal line is used for transmitting a first voltage signal, and the second voltage signal line is used for transmitting a third voltage signal; the first voltage signal and the third voltage signal have the same potential type. Therefore, the accuracy of the gate driving signal output by the driving circuit is improved, and the display accuracy of the display panel is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0002] With the continuous development of science and technology, more and more display products, such as mobile phones, tablet computers, laptop computers, and smart wearable devices, etc., are widely used in people's daily life and work, bringing great convenience to people's daily life and work, and becoming an indispensable important tool for people today.

[0003] In a display product, a gate driving circuit is usually used to perform a row-by-row scan on a pixel circuit. The gate driving signal output by the gate driving circuit is affected by many node signals. How to improve the accuracy of the gate driving signal output by the gate driving circuit has become one of the technical problems to be solved urgently at present. Summary of the Invention

[0004] In order to solve the above technical problems, the present disclosure provides a display panel and a display device, aiming to improve the accuracy of the gate driving signal output by the driving circuit, thereby improving the display accuracy of the display panel.

[0005] In a first aspect, the present disclosure provides a display panel, including:

[0006] A gate driving circuit, the gate driving circuit includes N cascaded shift registers, N≥2, and N is an integer;

[0007] The shift register includes a stage transmission unit and a selection unit connected to the stage transmission unit. The stage transmission unit includes a first control unit and a first output unit;

[0008] The first control unit is configured to control the signals of a first node and a second node at least according to a first voltage signal, a second voltage signal, a first clock signal, and a second clock signal;

[0009] The first output unit is configured to output a stage transmission signal at least according to the signal of the first node, the signal of the second node, a third voltage signal, and a fourth voltage signal; the stage transmission signal of the i-th stage shift register serves as the input signal of the j-th stage shift register, 1≤i≤N, 1≤j≤N, i≠j, and both i and j are integers;

[0010] The selection unit is configured to output a gate driving signal at least according to the stage transmission signal and a frequency control signal;

[0011] The display panel includes voltage signal lines, which include a first voltage signal line and a second voltage signal line. The first voltage signal line is used to transmit the first voltage signal, and the second voltage signal line is used to transmit the third voltage signal; the first voltage signal and the third voltage signal have the same potential type.

[0012] In a second aspect, based on the same inventive concept, the present disclosure provides a display device including the display panel provided in the first aspect of the present disclosure.

[0013] The technical solutions provided in the embodiments of the present disclosure have the following advantages compared with the prior art:

[0014] In the display panel and the display device provided in the embodiments of the present disclosure, the first voltage signal corresponding to the first control unit in the shift register is transmitted by the first voltage signal line, and the third voltage signal corresponding to the first output unit is transmitted by the second voltage signal line. The first voltage signal and the third voltage signal have the same potential type, that is, both are high potential signals or both are low potential signals, but the two are transmitted by different voltage signal lines. When the coupling of the clock signal affects the first voltage signal, since the third voltage signal is transmitted by the second signal line, the third voltage signal will not be affected by the coupling of the clock signal. When the stage transmission signal output by the first output unit is the third voltage signal, the third voltage signal is a stable voltage signal transmitted by the second signal line, which can accurately control the selection unit. Therefore, the way of introducing different voltage signal lines for the first control unit and the first output unit to transmit the first voltage signal and the third voltage signal with the same potential type in the embodiments of the present disclosure is beneficial to improving the transmission accuracy of the stage transmission signal, and further beneficial to improving the accuracy of the gate driving signal output by the gate driving circuit. Description of the Drawings

[0015] The drawings here are incorporated into the specification and form a part of this specification, showing the embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure.

[0016] To more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0017] Figure 1 Shown is a planar structure diagram of the display panel provided in the embodiments of the present disclosure;

[0018] Figure 2 Shown is another planar structure diagram of the display panel provided in the embodiments of the present disclosure;

[0019] Figure 3 The figure shows a schematic connection diagram of a shift register in a gate driving circuit provided by an embodiment of the present disclosure;

[0020] Figure 4 The figure shows a schematic structural diagram of a shift register in a gate driving circuit provided by an embodiment of the present disclosure;

[0021] Figure 5 The figure shows a schematic circuit diagram of a pixel driving circuit provided by an embodiment of the present disclosure;

[0022] Figure 6 The figure shows another schematic circuit diagram of a pixel driving circuit provided by an embodiment of the present disclosure;

[0023] Figure 7 The figure shows Figure 5 a timing diagram of the pixel driving circuit in

[0024] Figure 8 The figure shows a simulation schematic diagram of a first voltage signal and a third voltage signal;

[0025] Figure 9 The figure shows a schematic circuit diagram of a first control unit and a first output unit in a shift register provided by an embodiment of the present disclosure;

[0026] Figure 10 The figure shows a schematic circuit diagram of a strobe unit in a display panel provided by an embodiment of the present disclosure;

[0027] Figure 11 The figure shows Figure 9 an intermediate transmission unit and Figure 10 a driving timing diagram of the strobe unit in

[0028] Figure 12 The figure shows a schematic connection diagram of a shift register and a voltage signal line;

[0029] Figure 13 The figure shows a schematic connection diagram of a voltage signal line and a fan-out line in a display panel provided by an embodiment of the present disclosure;

[0030] Figure 14 The figure shows a schematic structural diagram of a display panel provided by an embodiment of the present disclosure after being bent through a bending region;

[0031] Figure 15 The figure shows a schematic film layer diagram of a display panel provided in an embodiment of the present disclosure;

[0032] Figure 16 The figure shows Figure 13 an AA-direction cross-sectional view of

[0033] Figure 17 Shown is a schematic diagram of a film layer in which a first voltage signal line and a second voltage signal line are connected through a first connection portion;

[0034] Figure 18 Shown is Figure 13 a schematic diagram of a film layer of a first fan-out line and a second fan-out line in;

[0035] Figure 19 Shown is Figure 13 a cross-sectional view taken along the BB direction of;

[0036] Figure 20 Shown is Figure 13 another cross-sectional view taken along the BB direction of;

[0037] Figure 21 Shown is another connection schematic diagram of a voltage signal line and a fan-out line in the display panel provided by the embodiment of the present disclosure;

[0038] Figure 22 Shown is Figure 21 a cross-sectional view taken along the CC direction of;

[0039] Figure 23 Shown is a layout schematic diagram of some signal lines in a fan-out area and a bending area;

[0040] Figure 24 Shown is a structural schematic diagram of a display device provided by the embodiment of the present disclosure. Detailed implementation manners

[0041] In order to more clearly understand the above objects, features and advantages of the present disclosure, the solutions of the present disclosure will be further described below. It should be noted that, without conflict, the embodiments of the present disclosure and the features in the embodiments may be combined with each other.

[0042] In the following description, many specific details are set forth in order to fully understand the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only a part of the embodiments of the present disclosure, rather than all the embodiments.

[0043] Figure 1 Shown is a planar structure diagram of a display panel 100 provided by the embodiment of the present disclosure. It should be noted that, Figure 1For illustration purposes, only a display panel with a rectangular structure is taken as an example, and the actual shape of the display panel is not limited. In some other embodiments of the present disclosure, the display panel may also be embodied in other feasible shapes such as circular or rounded rectangular. Optionally, the display panel provided in this embodiment may be an organic light-emitting display panel, and the corresponding light-emitting element is an organic light-emitting element. Of course, in some other embodiments of the present disclosure, the display panel may also adopt a display panel using inorganic light-emitting diode display technology, such as a Micro LED display panel, or a Mini LED display panel, etc. The present disclosure does not limit this.

[0044] Optionally, the display panel 100 includes a plurality of pixel driving circuits P0. Figure 1 Only a rectangular structure is used to illustrate the pixel driving circuit, and the number and arrangement of the pixel driving circuits are not limited. In addition, Figure 1 The position of the gate driving circuit 00 in the display panel is only for illustration purposes, and only an example of introducing a set of gate driving circuits 00 in the display panel and setting the gate driving circuit 00 on the non-display area on one side of the display area AA is taken for illustration, but the present disclosure is not limited thereto. In some other embodiments of the present disclosure, two or more sets of gate driving circuits 00 may also be provided in the display panel. When two sets of gate driving circuits 00 are provided in the display panel, the gate driving circuits 00 may also be respectively arranged on both sides of the display area AA. For example, please refer to Figure 2 , Figure 2 Shown is another planar structure diagram of the display panel provided by the embodiment of the present disclosure. The gate driving circuit 00 mentioned in the embodiment of the present disclosure is configured to provide a gate driving signal to the pixel driving circuit. The method of driving the pixel driving circuit by two sets of gate driving circuits 00 is beneficial to improving the transmission efficiency and reliability of the gate driving circuit 00. It should be noted that in some other embodiments of the present disclosure, the gate driving circuit 00 may also be arranged in the display area to achieve an extremely narrow border or borderless design of the display panel. The specific position of the gate driving circuit of the present disclosure is not limited.

[0045] Figure 3 Shown is a connection schematic diagram of the shift register 01 in the gate driving circuit 00 provided by the embodiment of the present disclosure. Figure 4 Shown is a structural schematic diagram of the shift register 01 in the gate driving circuit 00 provided by the embodiment of the present disclosure. Please refer to Figures 1 to 4 , the display panel 100 provided by the embodiment of the present disclosure includes:

[0046] The gate driving circuit 00 includes N cascaded shift registers 01, where N≥2 and N is an integer. The shift register 01 includes a stage transmission unit 03 and a gating unit 30 connected to the stage transmission unit 03. The stage transmission unit 03 includes a first control unit 10 and a first output unit 20. The first control unit 10 is configured to control the signals of the first node N1 and the second node N2 at least according to the first voltage signal VGHA, the second voltage signal VGLA, the first clock signal CK, and the second clock signal XCK. The first output unit 20 is configured to output a stage transmission signal NEXT at least according to the signals of the first node N1, the second node N2, the third voltage signal VGHD, and the fourth voltage signal VLGA’. The stage transmission signal NEXT of the i-th stage shift register 01 serves as the input signal of the j-th stage shift register 01, where 1≤i≤N, 1≤j≤N, i≠j, and both i and j are integers. The gating unit 30 is configured to output a gate driving signal SN_OUT at least according to the stage transmission signal NEXT and the frequency control signal CTRL.

[0047] The display panel 100 includes a voltage signal line 60, and the voltage signal line 60 includes a first voltage signal line 51 and a second voltage signal line 52. The first voltage signal line 51 is used to transmit the first voltage signal VGHA, and the second voltage signal line 52 is used to transmit the third voltage signal VGHD. The potential types of the first voltage signal VGHA and the third voltage signal VGHD are the same. It should be noted that the same potential type of the two voltage signals mentioned in the embodiments of the present disclosure means that both of these two signals are high-potential signals or both are low-potential signals, but does not limit whether the voltage values of the two signals are the same.

[0048] Among them, the first control unit 10 is also electrically connected to the input signal terminal IN. The first control unit 10 is used to receive the input signal IN, the first voltage signal VGHA, the second voltage signal VGLA, the first clock signal CK, and the second clock signal XCK to control the signals of the first node N1 and the second node N2. For example, when controlling the signal of the first node N1 to be an effective level, the signal of the second node N2 can be controlled to be an invalid level; or when controlling the signal of the second node N2 to be an effective level, the signal of the first node N1 can be controlled to be an invalid level. Among them, the first voltage signal VGHA and the second voltage signal VGLA are two signals with different potential types. One of the first voltage signal VGHA and the second voltage signal VGLA can be a high-potential signal, and the other can be a low-potential signal.

[0049] The first output unit 20 is connected to at least the first node N1 and the second node N2, and receives a third voltage signal VGHD and a fourth voltage signal VGLA' to control the stage transfer signal NEXT. For example, when the signal of the first node N1 is at an effective level, the third voltage signal VGHD will be output as the shift signal NEXT, that is, the shift signal NEXT is consistent with the third voltage signal VGHD; when the signal of the second node N2 is at an effective level, the fourth voltage signal VGLA' will be output as the shift signal, that is, the shift signal NEXT is consistent with the fourth voltage signal VGLA'. Among them, the third voltage signal VGHD and the fourth voltage signal VGLA' are two signals with different potential types. One of the third voltage signal VGHD and the fourth voltage signal VGLA' can be a high-potential signal, and the other can be a low-potential signal, so that one of the third voltage signal VGHD and the fourth voltage signal VGLA' can be used as the effective level of the stage transfer signal, and the other can be used as the invalid level of the stage transfer signal.

[0050] The gating unit 30 receives at least the stage transfer signal NEXT, the frequency control signal CTRL, the signal of the first node N1, and the signal of the second node N2 to control the gate driving signal SN_OUT according to the stage transfer signal NEXT, the frequency control signal CTRL, the signal of the first node N1, and the signal of the second node N2. For example, when the signal of the second node N2 is an effective level signal, the gate driving signal SN_OUT output by the gating unit 30 can be controlled to be consistent with the sixth voltage signal VGLB. When the signal of the fifth node N5 is an effective level signal, the gate driving signal SN_OUT output by the gating unit 30 can be controlled to be consistent with the fifth voltage signal VGHB or the seventh voltage signal VGHC. The working timings of the stage transfer unit 03 and the gating unit 30 will be described in subsequent embodiments.

[0051] Please continue to refer to Figure 1 and Figure 2 In the display panel provided by the embodiments of the present disclosure, the output end of the shift register 01 is connected to the scan line S, and the scan line S is further electrically connected to the pixel driving circuit P0. The shift register 01 provides a gate driving signal to the pixel driving circuit P0 through the scan line S. The gate driving signal includes, for example, a reset control signal, a data writing control signal, a light emitting control signal, etc. to control the operation of the pixel driving circuit. Optionally, at least two different control signals correspond to different gate driving circuits. For example, the gate driving circuit for sending the reset control signal and the gate driving circuit for sending the light emitting control signal are two independent gate driving circuits.

[0052] Figure 5 The following shows a circuit schematic diagram of the pixel driving circuit provided by the embodiments of the present disclosure for Figure 5For example, the pixel driving circuit P0 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, and a capacitor C. Among them, the third transistor M3 is a driving transistor for providing a driving current to the light-emitting element D0. The gate, the first pole, and the second pole of the driving transistor are respectively connected to the first sub-node N01, the third sub-node N03, and the second sub-node N02. The first pole and the second pole of the fifth transistor M5 are respectively connected to the first reset signal terminal Vref1 and the first sub-node N01, and the gate is connected to the first control signal terminal S1N for receiving a reset control signal. The fifth transistor M5 is used to provide the first reset signal Vref1 to the first sub-node N01. The first pole and the second pole of the second transistor M2 are respectively connected to the data voltage signal terminal Vdata and the second sub-node N02, and the gate receives the control signal SP. The second transistor M2 is used to transmit the data voltage signal Vdata to the second sub-node N02. It should be noted that in the embodiments of the present disclosure, the signal terminals and the signals transmitted by the signal terminals are represented by the same reference numerals. The first pole and the second pole of the fourth transistor M4 are respectively connected to the third sub-node N03 and the first sub-node N01, and the gate is connected to the second control signal terminal S2N for receiving the control signal S2N. The fourth transistor M4 is used to perform threshold compensation on the third transistor M3. The first pole and the second pole of the seventh transistor M7 are respectively connected to the second reset signal terminal Vref2 and the first pole of the light-emitting element D0, and the gate is connected to the control signal terminal SPX. The seventh transistor M7 is used to reset the first pole of the light-emitting element D0. The first pole and the second pole of the eighth transistor M8 are respectively connected to the bias adjustment signal terminal DVH and the second sub-node N02, and the gate is connected to the control signal terminal SPX. The first pole and the second pole of the first transistor M1 are respectively connected to the first power signal terminal PVDD and the second sub-node N02, and the gate is connected to the light-emitting control signal terminal Emit. The first pole and the second pole of the sixth transistor M6 are respectively connected to the third sub-node N03 and the first pole of the light-emitting element D0, and the gate is connected to the light-emitting control signal terminal Emit for transmitting the driving current to the light-emitting element D0. The second pole of the light-emitting element D0 receives the second power signal PVEE. It should be noted that the embodiments of the present disclosure are only described by taking the gates of the seventh transistor M7 and the eighth transistor M8 as being both connected to the control signal terminal SPX as an example, but the present disclosure is not limited thereto. It should also be noted that, Figure 5 the pixel driving circuit in it is only for illustration, and the present disclosure does not limit the specific structure of the pixel driving circuit, Figure 5In the embodiment, the fourth transistor M4 and the fifth transistor M5 connected to the first sub-node N01 are N-type transistors. The N-type transistor can be an oxide transistor. The signals for controlling the conduction of the fourth transistor M4 and the fifth transistor M5 are high-potential signals, and the other transistors are all P-type transistors. In this embodiment, when the fourth transistor M4 and the fifth transistor M5 are N-type transistors and the N-type transistor is an oxide transistor, it is beneficial to reduce the leakage current of the fourth transistor M4 and the fifth transistor M5 to the first sub-node N01, thereby facilitating the maintenance of the stability of the potential of the gate of the driving transistor connected to the first sub-node N01. In some other embodiments, the pixel driving circuit may also be embodied in other structures. For example, please refer to Figure 6 , Figure 6 which shows another circuit schematic diagram of the pixel driving circuit provided by the embodiment of the present disclosure. The connection relationship and working principle are the same as those of Figure 5 , and the difference from Figure 5 is only that the fourth transistor M4 and the fifth transistor M5 are P-type transistors, and the P-type transistors are turned on under the control of a low-potential signal. Figure 6 When all the transistors in the embodiment shown are P-type transistors, it is beneficial to simplify the manufacturing process of the pixel driving circuit.

[0053] Figure 5 and Figure 6 In the pixel driving circuits shown, the first control signal terminal S1N, the second control signal terminal S2N, the light emission control signal terminal Emit, and the control signal terminals SP and SPX are all connected to the gate driving circuit. Optionally, the first control signal terminal S1N and the second control signal terminal S2N can correspond to the same group of gate driving circuits, and the light emission control signal terminal Emit, the control signal terminals SP and SPX can respectively correspond to other different gate driving circuits. Of course, in some other embodiments of the present disclosure, the first control signal terminal S1N and the second control signal terminal S2N can also respectively correspond to different gate driving circuits. It should be noted that in this embodiment, only the structure of the gate driving circuit corresponding to the case where the first control signal S1N and the second control signal S2N correspond to the same group of gate driving circuits is described, and the structure of other gate driving circuits in the display panel is not limited.

[0054] The following will describe the working principle with reference to Figure 7 , and Figure 5 The working principle of the pixel driving circuit in Figure 6 can be referred to this embodiment. Figure 7 Shown in Figure 5 is a timing diagram of the pixel driving circuit in Figure 5 and Figure 7 , the specific working process of the pixel driving circuit P0 includes an initialization stage t1, a data writing and threshold compensation stage t2, a bias stage t3, and a light emission stage t4.

[0055] In the initialization stage t1, the high-potential signal of the first control signal S1N controls the fifth transistor M5 to conduct, and transmits the first reset signal Vref1 to the control terminal of the third transistor M3 for initialization, so as to eliminate the residual charge of the previous frame of image, thereby improving the display effect of the display panel. In the present disclosure, in a partial time period of the initialization stage t1, there is an overlapping time of the effective levels of the first control signal S1N and the second control signal S2N, which is beneficial to improving the hysteresis problem of the driving transistor during the initialization stage.

[0056] In the data writing and threshold compensation stage t2, the fifth transistor M5 is turned off, the control signal SP controls the second transistor M2 to conduct, the second control signal S2N controls the fourth transistor M4 to conduct, the data voltage signal Vdata is written into the third transistor M3 through the second transistor M2, and the fourth transistor M4 is connected between the gate and the first pole of the third transistor M3, and can capture the threshold voltage of the third transistor M3 to the gate of the third transistor M3, realizing the compensation of the threshold voltage and self-compensating the deviation of the threshold voltage of the driving transistor.

[0057] In the bias stage t3, the control signal SPX controls the eighth transistor M8 to conduct, and the bias adjustment signal DVH is transmitted to the second pole (i.e., the second sub-node N02) of the driving transistor through the eighth transistor M8 to adjust the bias state of the driving transistor. At the same time, the control signal SPX controls the seventh transistor M7 to conduct, and the second reset signal Vref2 is transmitted to the anode of the light-emitting element D0 through the seventh transistor M7 to reset the light-emitting element D0.

[0058] In the light-emitting stage t4, the second transistor M2, the fourth transistor M4, the fifth transistor M5, and the seventh transistor M7 are all turned off, the first transistor M1, the third transistor M3, and the sixth transistor M6 are all turned on, and the driving current is transmitted to the first pole of the light-emitting element D0, and the light-emitting element D0 emits light. It should be noted that Figure 7 The timing diagram of

[0059] Optionally, the first control signal S1N and the second control signal S2N received by the above pixel driving circuit are provided by two different gate driving circuits. In an alternative embodiment of the present disclosure, the gate driving signal SN_OUT output by the gate driving circuit 00 mentioned in the present disclosure can be used as the first control signal S1N provided to the pixel driving circuit, and the second control signal S2N is provided by another gate driving circuit. At this time, the gate driving circuit provided by the present disclosure is configured to provide the first control signal S1N to the fifth transistor M5 at least during the initialization stage t1, turn on the fifth transistor M5, and transmit the first reset signal Vref1 to the third transistor M3, so that the potential of the first sub-node N01 becomes low.

[0060] When the display panel needs to implement zoned refreshing, in two adjacent display areas, the pixel driving circuit in one display area needs to be refreshed (the first control signal terminal S1N needs to receive the valid level signal in the gate driving signal), while the pixel driving circuit in the other display area does not need to be refreshed (the first control signal terminal S1N needs to receive the invalid level signal in the gate driving signal). Therefore, the accuracy of the gate driving signal output by the gate driving circuit 00 in the embodiment of the present disclosure directly determines whether the pixel driving circuit can control the corresponding light-emitting element to emit light correctly.

[0061] In another embodiment of the present disclosure, the gate driving signal SN_OUT output by the gate driving circuit 00 mentioned in the present disclosure can be used as the second control signal S2N provided to the pixel driving circuit, and the first control signal S1N is provided by another gate driving circuit. At this time, the gate driving circuit provided by the present disclosure is configured to provide the second control signal S2N to the fourth transistor during the data writing and threshold compensation stage t2 to achieve threshold voltage compensation.

[0062] Of course, in some other embodiments of the present disclosure, the gate driving circuit that transmits the first control signal S1N and the second control signal S2N to the pixel driving circuit can also be the same gate driving circuit, that is, the gate driving circuit provided in the embodiment of the present disclosure can be configured to transmit the above first control signal S1N and second control signal S2N to the pixel driving circuit. For example, in the gate driving circuit provided by the present disclosure, the output of the local shift register can provide the first control signal S1N and the second control signal S2N to the pixel driving circuits of different rows respectively. For this, reference can be made to the content of related technologies, and the present disclosure does not make specific limitations in this regard.

[0063] Please continue to refer to Figure 4, for the first control unit 10 in the shift register 01, it controls the signals of the first node N1 and the second node N2 according to the input signal IN, the first clock signal CK, the second clock signal XCK, the first voltage signal VGHA, and the second voltage signal VGLA. For the first output unit 20, it controls the output of the stage transmission signal NEXT according to the third voltage signal VGHD, the fourth voltage signal VGLA’, and the signals of the first node N1 and the second node N2. In the related art, in the first control unit 10, due to the circuit logic itself, the first clock signal CK or the second clock signal XCK will cause coupling interference to the first voltage signal VGHA, causing the originally constant first voltage signal VGHA to appear as a sawtooth with high and low level jumps. For example, please refer to Figure 8 , Figure 8 The figure shows a simulation diagram of the first voltage signal VGHA and the third voltage signal VGHD. The first voltage signal VGHA will appear as a sawtooth due to the coupling effect of the clock signal. When the present disclosure separately introduces the second voltage signal line 52 for the first output unit 20 to transmit the third voltage signal VGHD, the third voltage signal VGHD is not affected or hardly affected by the coupling effect of the clock signal. If the third voltage signal VGHD in the first output unit 20 and the first voltage signal VGHA in the first control unit 10 are the same signal transmitted by the same signal line, the third voltage signal VGHD will also be affected by the clock signal and generate a sawtooth with high and low level jumps. When the third voltage signal VGHD is output as the stage transmission signal, the stage transmission signal will also generate a sawtooth with high and low level jumps, thereby affecting the control of the selection unit 30 and causing the selection unit 30 to output an error, affecting the control of the pixel driving circuit.

[0064] To solve the above problems, in the embodiments of the present disclosure, the first voltage signal VGHA corresponding to the first control unit 10 is transmitted by the first voltage signal line 51, and the third voltage signal VGHD corresponding to the first output unit 20 is transmitted by the second voltage signal line 52. The potential types of the first voltage signal VGHA and the third voltage signal VGHD are the same, that is, both are high-potential signals or both are low-potential signals, but they are transmitted by different voltage signal lines. When the coupling of the clock signal affects the first voltage signal VGHA, since the third voltage signal VGHD is transmitted by the second voltage signal line 52, the third voltage signal VGHD will not be affected by the coupling of the clock signal. When the stage transmission signal NEXT output by the first output unit 20 is the third voltage signal VGHD, the third voltage signal VGHD is a stable voltage signal transmitted by the second voltage signal line 52, which can accurately control the gating unit 30. Therefore, the embodiments of the present disclosure introduce different voltage signal lines for the first control unit 10 and the first output unit 20 to transmit the first voltage signal VGHA and the third voltage signal VGHD with the same potential type, which is beneficial to improving the transmission accuracy of the stage transmission signal NEXT, and further beneficial to improving the accuracy of the gate driving signal output by the gate driving circuit 00.

[0065] In some embodiments, the third voltage signal VGHD corresponds to the valid level signal in the stage transmission signal. Or rather, the third voltage signal VGHD is output as the valid level signal in the stage transmission signal. Since the valid level of the stage transmission signal is a signal related to the valid level of the gate driving signal, and the valid level of the gate driving signal directly affects the conduction state of the corresponding transistor, using a separate second voltage signal line 52 to transmit the third voltage signal VGHD can ensure the stability of the output of the third voltage signal VGHD. In addition, the stage transmission signal of the current-stage shift register is transmitted to the next-stage shift register as the input signal of the next-stage shift register. Therefore, using a separate second voltage signal line 52 to transmit the third voltage signal VGHD can also ensure the stability of the valid level of the input signal of the subsequent shift register, so that the valid levels of the input signals of the subsequent stages of shift registers remain constant and are not affected by other signals.

[0066] The working principle and related technical effects of the gate driving circuit 00 in the embodiments of the present disclosure will be further described below in conjunction with specific circuit structures.

[0067] Figure 9The following is a schematic circuit diagram of a first control unit 10 and a first output unit 20 in a shift register 01 provided by an embodiment of the present disclosure. Exemplarily, the first control unit 10 includes a first control module 11 and a second control module 12. The first control module 11 is configured to receive an input signal IN and control signals of a third node N3 and a fourth node N4 in response to a first clock signal CK. The signal of the third node N3 is connected to a second node N2. The second control module 12 is configured to receive a first voltage signal VGHA and a second voltage signal VGLA, and control signals of a first node N1 and a second node N2 in response to signals of the third node N3, signals of the fourth node N4, the first clock signal CK, and a second clock signal XCK. Among them, the voltage signal VGHA is provided by a first voltage signal line.

[0068] Exemplarily, the first control module 11 includes a transistor T13 and a transistor T14. A first pole of the transistor 13 is connected to an input signal terminal IN, a second pole is connected to the fourth node N4, and a gate is connected to the first clock signal CK; a first pole of the transistor T14 is connected to the input signal terminal IN, a second pole is connected to the third node N3, and a gate receives the first clock signal CK.

[0069] Exemplarily, the second control module 12 includes transistors T15 to T25, capacitor C3, capacitor C4, and capacitor C5. The first pole of transistor T15 receives the second voltage signal VGLA, the gate receives the first clock signal CK, and the second pole is connected to node N0; the gate of transistor T16 is connected to the third node N3, the first pole receives the first clock signal CK, and the second pole is connected to node N0; the first pole of transistor T17 is connected to node N0, the gate receives the second voltage signal VGLA, and the second pole is connected to the first plate of capacitor C4, and the second plate of capacitor C4 is connected to node N6; the first pole of transistor T18 receives the second clock signal XCK, the gate is connected to the first plate of capacitor C4, and the second pole is connected to node N6. The first pole of transistor T19 is connected to node N6, the second pole of transistor T19 is connected to the first node N1, and the gate receives the second clock signal XCK; the first pole of transistor T20 receives the first voltage signal VGHA, the second pole is connected to the first node N1, and the gate is connected to the third node N3; the two plates of capacitor C3 respectively receive the first voltage signal VGHA and the signal of the first node N1. The first pole of transistor T21 is connected to the third node N3, the second pole is connected to the second node N2, and the gate receives the second voltage signal VGLA; the first pole of transistor T22 is connected to the fourth node N4, the second pole is connected to the first pole of transistor T23, and the gate receives the second voltage signal VGLA; the first pole and the gate of transistor T23 are connected to the second pole of transistor T22, and the second pole of transistor T23 is connected to the second node N2; the first plate of capacitor C5 is connected to the gate of transistor T23, and the second plate is connected to the second poles of transistors T24 and T25; the first pole of transistor T24 receives the first voltage signal VGHA, and the gate is connected to node N0; the first pole of transistor T25 receives the second clock signal XCK, and the gate is connected to the gate of transistor T23.

[0070] Exemplarily, the first output unit 20 includes a first output module 21 and a second output module 22. The first output module 21 includes transistor T11, and the second output module 22 includes transistor T12. The gate of transistor T11 is connected to the first node N1, the first pole receives the third voltage signal VGHD, and the second pole outputs the transfer signal NEXT; the gate of transistor T12 is connected to the second node N2, the first pole receives the fourth voltage signal VGLA’, and the second pole outputs the transfer signal NEXT.

[0071] It should be noted that Figure 9The circuit structures of the illustrated first control unit 10 and first output unit 20 are only schematic and do not specifically limit the specific structures of the first control unit 10 and first output unit 20. In some other embodiments of the present disclosure, the first control unit 10 and first output unit 20 may also adopt other feasible circuit structures. The transistors in the first control unit 10 and first output unit 20 are also only schematic. In some other embodiments of the present disclosure, the structures of at least some of the transistors may also be changed to dual-gate structures.

[0072] Figure 10 The figure shows a schematic circuit diagram of a strobe unit 30 in a display panel provided by an embodiment of the present disclosure. Optionally, the strobe unit 30 includes a second control unit 31 and a second output unit 32. The second control unit 31 is configured to control the signal of a fifth node N5 at least according to the signal of a first node N1, a first voltage signal VGHA, a stage transmission signal NEXT, and a frequency control signal CTRL. The second output unit 32 is configured to output a gate driving signal at least according to the signals of the fifth node N5 and a second node N2.

[0073] Please refer to Figure 4 and Figure 10 , for example, the second control unit 31 in the strobe unit 30 includes an isolation protection unit 301 and an output control unit 302, and the second output unit 32 includes a third output module 311 and a fourth output module 312. The control end of the isolation protection unit 301 receives the stage transmission signal NEXT, the input end of the isolation protection unit 301 receives the frequency control signal CTRL, the output end of the isolation protection unit 301 is connected to the control end of the output control unit 302, and the isolation protection unit 301 can control the signal output to the control end of the output control unit 302 according to the stage transmission signal NEXT and the frequency control signal CTRL. The output control unit 302 receives the signal of the first node N1 and the first voltage signal VGHA, and the output end is connected to the control end of the third output module 311 through the fifth node N5. For example, when the stage transmission signal NEXT can control the isolation protection unit 301 to conduct, the isolation protection unit 301 can transmit the frequency control signal CTRL to the control end of the output control unit 302, and when the stage transmission signal NEXT controls the isolation protection unit 301 to cut off, the output of the frequency control signal CTRL to the control end of the output control unit 302 can be stopped. The output control unit 302 can control the signal of the fifth node N5 at least according to the signal of the first node N1 and the first voltage signal VGHA.

[0074] Optionally, the isolation protection unit 301 includes a transistor T3, the output control unit 302 includes transistors T4 and T5. The gate of the transistor T3 receives the stage transmission signal NEXT, the first pole receives the frequency control signal CTRL, the second pole is connected to the gate of the transistor T4. The first pole of the transistor T4 is connected to the first node N1, and the second pole is connected to the fifth node N5. The gate of the transistor T5 is connected to the first node N1, the first pole receives the first voltage signal VGHA, and the second pole is connected to the fifth node N5. The third output module 311 includes a transistor T1, and the fourth output module 312 includes a transistor T2. The gate of the transistor T1 is connected to the fifth node N5, the first pole receives the fifth voltage signal VGHB or the seventh voltage signal VGHC, and the second pole is connected to the output end SN_OUT of the gating unit 30. The gate of the transistor T2 is connected to the second node N2, the first pole receives the sixth voltage signal VGLB, and the second pole is connected to the output end SN_OUT of the gating unit 30.

[0075] Figure 11 As shown Figure 9 The intermediate transmission unit 03 and Figure 10 A driving timing diagram of the intermediate gating unit 30 will be combined with the following Figure 9 、 Figure 10 and Figure 11 to introduce the working principle and process of the shift register:

[0076] In the Ta stage, the input signal IN is at a high level and the first clock signal CK is at a low level. At this time, the transistors T13, T14, and T15 are turned on. The input signal IN is transmitted to the third node N3 and the fourth node N4 through the transistors T13 and T14 respectively, making both the third node N3 and the fourth node N4 at a high level, and the transistors T16 and T20 are turned off. At the same time, the second voltage signal VGLA is transmitted to the node N0 through the transistor T15, the node N0 is at a low level, and the transistor T17 is always on. The low-level signal is transmitted to the gate of the transistor T18, the transistor T18 is turned on, the second clock signal XCK is at a high level, the transistor T19 is turned off, the first node N1 maintains the high level of the previous stage, the transistor T11 is turned off, and the stage transmission signal NEXT maintains the low level of the previous stage.

[0077] In the Tb stage, the input signal IN is at a high level and the first clock signal CK is at a high level. At this time, the transistors T13, T14, and T15 are turned off, the third node N3 and the fourth node N4 remain at a high level, the transistors T16 and T20 are turned off, the node N0 remains at a low level, the transistor T18 is turned on, the second clock signal XCK is at a low level, and is transmitted to the sixth node N6 through the transistor T18, making the sixth node N6 at a low level. The transistor T19 is turned on, the signal of the sixth node N6 is transmitted to the first node N1, the transistor T11 is turned on, and the third voltage signal VGHD is transmitted to the output terminal, making the stage transmission signal NEXT at a high level.

[0078] In the Tc stage, the input signal IN is at a high level and the first clock signal CK is at a low level. At this time, the transistors T13, T14, and T15 are turned on, and the input signal IN is transmitted to the third node N3 and the fourth node N4 through the transistors T13 and T14 respectively, making both the third node N3 and the fourth node N4 at a high level. The transistors T16 and T20 are turned off; at the same time, the second voltage signal VGLA is transmitted to the node N0 through the transistor T15, the node N0 is at a low level, and the transistor T17 is always on, so the second pole of the transistor T17 is at a low level, the transistor T18 is turned on, the second clock signal XCK is at a high level, the sixth node N6 remains at a high level, the transistor T19 is turned off, the first node N1 remains at a low level, the transistor T11 is turned on, and the third voltage signal VGHD is transmitted to the output terminal, making the stage transmission signal NEXT at a high level.

[0079] In the Td stage, the input signal IN is at a low level and the first clock signal CK is at a high level. The transistors T13, T14, and T15 are all turned off, the third node N3 and the fourth node N4 both remain at a high level, and the transistors T16 and T20 are both turned off; the node N0 remains at a low level, and the transistor T17 is always on, the second pole of the transistor T17 is at a low level, the transistor T18 is turned on, the second clock signal XCK is at a low level, and the second clock signal XCK is transmitted to the sixth node N6 through the transistor T18, making the sixth node N6 at a low level; at the same time, the transistor T19 is turned on, the signal of the sixth node N6 is transmitted to the first node N1 and is at a low level, the transistor T11 is turned on, and the third voltage signal VGHD is transmitted to the output terminal, making the stage transmission signal NEXT at a high level.

[0080] In the Te stage, the input signal IN is at a low level, the first clock signal CK is at a low level, transistors T13, T14, and T15 are turned on. The input signal IN is transmitted to the third node N3 and the fourth node N4 through transistors T13 and T14 respectively, making both the third node N3 and the fourth node N4 at a low level, and transistors T16 and T20 are turned on. At the same time, transistor T15 is turned on, and the second voltage signal VGLA is transmitted to node N0 through transistor T15. Node N0 is at a low level, and transistor T17 is always on, so the second pole of transistor T17 is at a low level, transistor T18 is turned on, the second clock signal XCK is at a high level, the sixth node N6 remains at a high level, and transistor T19 is turned off. Transistor T20 is turned on, and the first voltage signal VGHA is transmitted to the first node N1 through transistor T20, making the first node N1 at a high level, and transistor T11 is turned off. At the same time, transistors T21 and T22 are always on, and the signal of the third node N3 is transmitted to the second node N2, making the second node N2 at a low level, transistor T12 is turned on, and the fourth voltage signal VGLA’ is transmitted to the output terminal, making the stage transmission signal NEXT at a low level.

[0081] Optionally, in this embodiment, the fourth voltage signal VGLA’ received by the first output unit 20 and the second voltage signal VGLA received by the first control unit 10 are signals with the same voltage value. However, the present disclosure is not limited thereto. In some other embodiments of the present disclosure, the two may also be signals with the same potential type but different voltage values.

[0082] Please refer to Figure 4 , Figures 9 to 11 , in the same shift register, when the shift signal NEXT output by the first output unit 20 controls transistor T3 to turn on, the frequency control signal CTRL will be transmitted to the seventh node N7. At this time, if the frequency control signal NEXT is a valid level signal, the signal of the seventh node N7 will also be a valid level signal. If the frequency control signal NEXT is an invalid level signal, the signal of the seventh node N7 will also be an invalid level signal. When the signal of the seventh node N7 is a valid level signal, transistor T4 can be controlled to turn on, and the signal of the first node N1 will be able to be transmitted to the fifth node N5, making the signal of the fifth node N5 consistent with the signal of the first node N1. At this time, the shift signal NEXT output by the first output unit 20 can be controlled to be consistent with the gate drive signal output by the second output unit 32, that is, when the shift signal NEXT is a valid level signal, the gate drive signal will also be a valid level signal. When the signal of the seventh node N7 is an invalid level signal, transistor T4 cannot be controlled to turn on, and the signal of the first node N1 cannot be transmitted to the fifth node N5, making the gate drive signal unable to be synchronized with the shift signal NEXT to remain at a valid level signal.

[0083] In this embodiment, by making the frequency control signal CTRL include an active level signal and an inactive level signal, during a partial time period (such as the frame display time F1), when the shift signal NEXT is controlled to be an active level signal and the frequency control signal CTRL remains at the active level (in this embodiment, the low level signal is taken as the active level signal of the frequency control signal CTRL for illustration), the seventh node N7 is at the active level, so that the shift register outputs the active level of the gate driving signal during this time period, enabling the pixel driving circuit electrically connected to the shift register to perform signal refreshing. In another partial time period (such as the frame display time F2), when the shift signal NEXT is controlled to be at the active level, the frequency control signal CTRL is at the inactive level. At this time, the signal of the seventh node N7 is at the inactive level, so that the shift register cannot output the active level of the gate driving signal. That is, during this time period, the gate driving signal output by the shift register is at the inactive level, making the pixel driving circuit connected to the shift register unable to perform signal refreshing. In this way, different display areas can be controlled to be refreshed at different refresh frequencies.

[0084] Please refer to Figure 4 , Figure 9 , Figure 10 and Figure 11, at a certain moment state of the circuit, for example, when the input signal IN is at a high level and the first clock signal CK is at a low level, the transistor T15 is turned on, the transistor T17 is always on, and the low-level signal VGL will be transmitted to the gate of the transistor T18 through the transistor T15 and the transistor T17, causing the transistor T18 to be turned on. At the moment when the second clock signal XCK jumps from a high level to a low level, the low-level signal of the second clock signal XCK will be transmitted to the gate of the transistor T19, causing the transistor T19 to be turned on, and the low-level signal at the first pole of the transistor T18 will be transmitted to the first node N1. When the second clock signal XCK is at a low level, the transistor T19 is turned on. Since the second pole of the transistor T19 and the second pole of the transistor T20 are connected together, considering the circuit coupling effect, the low-potential signal of the second clock signal XCK will cause a certain coupling to the first voltage signal VGHA received by the transistor T20, causing a low-level glitch phenomenon in the first voltage signal VGHA. If the first pole of the transistor T11 in the first output unit 20 and the first pole of the transistor T20 in the first control unit 10 are connected to the same voltage signal line, the voltage signal received by the transistor T11 will also have a low-level glitch phenomenon. When the transistor T11 is turned on, the stage transmission signal originally output through the transistor T11 should be a stable high-potential signal, but due to the coupling interference of the low-potential signal of the second clock signal XCK, a low-level glitch will also appear in the stage transmission signal output through the transistor T11. Considering that the gating unit 30 needs to output a gate driving signal according to the aforementioned stage transmission signal NEXT and the frequency control signal CTRL, if there is a low-level glitch in the stage transmission signal, it will affect the gate driving signal output by the gating unit 30. For example, when the stage transmission signal NEXT is a constant high-level signal, it cannot control the isolation protection unit 301 in the gating unit 30 to be turned on. And if an unexpected low-level glitch appears in the stage transmission signal NEXT, the low-level glitch will cause the isolation protection unit 301 to be turned on accidentally. At this time, when the frequency control signal CTRL jumps from a high level to a low level, the low-level frequency control signal will be transmitted to the output control unit 302, causing the output control unit 302 to be turned on abnormally, and the low-level signal at the first node N1 will cause the transistor T1 in the second output unit 32 to be turned on, resulting in the shift register 01 outputting a high-level signal abnormally. But when the shift register 01 outputs a high-level signal, it will cause the corresponding pixel driving circuit to drive the light-emitting element to emit light abnormally, most likely causing the corresponding light-emitting element to be burned and abnormal dark lines to appear on the display screen, affecting the display effect.Therefore, the first voltage signal VGHA corresponding to the first control unit 10 in the embodiments of the present disclosure is transmitted by the first voltage signal line, and the third voltage signal VGHD corresponding to the first output unit 20 is transmitted by the second voltage signal line. The potential types of the first voltage signal VGHA and the third voltage signal VGHD are the same, that is, both are high-potential signals or both are low-potential signals (in this embodiment, high-potential signals are taken as an example for illustration). However, they are transmitted by different voltage signal lines. When the coupling of the clock signal affects the first voltage signal, since the third voltage signal VGHD is transmitted by the second signal line, the third voltage signal VGHD will not be affected by the coupling of the clock signal. When the stage transmission signal output by the first output unit 20 is the third voltage signal VGHD, the third voltage signal VGHD is a stable voltage signal transmitted by the second signal line and will not affect the accuracy of the stage transmission signal. Therefore, the way of introducing different voltage signal lines for the first control unit 10 and the first output unit 20 to transmit the first voltage signal VGHA and the third voltage signal VGHD with the same potential type in the present disclosure is beneficial to improving the transmission accuracy of the stage transmission signal, and further beneficial to improving the accuracy of the gate driving signal output by the gate driving circuit 00, avoiding the problem that the light-emitting element is burned and abnormal dark lines appear due to abnormal output of the gate driving signal, so it is beneficial to improve the overall display effect of the display panel.

[0085] Figure 12 Shown is a schematic connection diagram of the shift register 01 and the voltage signal line. Please refer to Figure 12 In an alternative embodiment of the present disclosure, among the N-stage shift registers 01 connected in cascade, the first control units 10 in different shift registers 01 are connected to the same first voltage signal line 51.

[0086] Please refer to Figure 11 、 Figure 10 and Figure 12 Optionally, the strobe unit 30 includes a second control unit 31 and a second output unit 32. The second control unit 31 is configured to control the signal of the fifth node N5 at least according to the stage transmission signal NEXT, the frequency control signal CTRL, and the first voltage signal VGHA. The second output unit 32 controls the output of the gate driving signal at least according to the signal of the fifth node N5 and the signal of the second node N2. It should be noted that, for clearly showing the connection relationship between the shift register 01 and the voltage signal line 60, Figure 12Only the connection relationships between the first control unit 10, the first output unit 20, the second control unit 31, and the second output unit 32 in the three - level shift register 01 and the voltage signal line 60 are illustrated, and other signal lines are not shown. The number of shift registers 01 actually included in the gate driving circuit is not limited. In the same gate driving circuit, the connection relationships between other shift registers 01 and the voltage signal line 60 can be referred to Figure 12 。

[0087] The first voltage signal line 51 is used to transmit the first voltage signal VGHA to the first control unit 10 in the shift register 01. In this embodiment, when the first control units 10 in different shift registers 01 are connected to the same first voltage signal line 51, there is no need to introduce different voltage signal lines for different shift registers 01 to transmit the first voltage signal VGHA. It is sufficient to use the same first voltage signal line 51 to transmit the first voltage signal VGHA to different shift registers 01. Therefore, it is beneficial to reduce the number of voltage signal lines corresponding to the entire gate driving circuit 00 and simplify the wiring of the display panel.

[0088] Optionally, in this embodiment, taking the example that the first control unit 10 and the second control unit 31 in the gating unit 30 in the same shift register 01 are connected to the same first voltage signal line 51 for illustration, in this way, the first control units 10 and the second control units 31 in different shift registers 01 can correspond to the same first voltage signal line. Therefore, it is beneficial to further reduce the number of voltage signal lines corresponding to the gate driving circuit 00 and also beneficial to simplify the wiring of the display panel.

[0089] Please continue to refer to Figure 12 , in an alternative embodiment of the present disclosure, in the cascaded shift registers 01, the first output units 20 in different shift registers 01 are connected to the same second voltage signal line 52.

[0090] To avoid the coupling effect of the clock signal on the voltage signal received by the first output unit 20, a second voltage signal line 52 is introduced in the embodiments of the present disclosure. The second voltage signal line 52 is used to provide a third voltage signal VGHD to the first output unit 20 in the shift register 01. When different shift registers 01 in the same gate driving circuit 00 correspond to the same second voltage signal line 52 and the third voltage signal VGHD is transmitted to the first output units 20 in different shift registers 01 through the same second voltage signal line 52, there is no need to introduce different voltage signal lines for different shift registers 01 to transmit the third voltage signal VGHD. Therefore, it is beneficial to reduce the number of voltage signal lines corresponding to the gate driving circuit 00 and also beneficial to simplify the wiring of the display panel.

[0091] In the embodiments of the present disclosure, the first control unit 10 receives at least a first voltage signal VGHA to control the signals of the first node N1 and the second node N2, and the first output unit 20 controls the stage transmission signal at least according to the signals of the first node N1, the signals of the second node N2, and a third voltage signal VGHD. When the first voltage signal line 51 and the second voltage signal line 52 are respectively introduced in the embodiments of the present disclosure to transmit the foregoing first voltage signal VGHA and the third voltage signal VGHD, the first voltage signal VGHA and the third voltage signal VGHD are signals of the same potential type, that is, both of them are high potential signals or both are low potential signals. On this basis, in an optional embodiment of the present disclosure, the voltage values of the first voltage signal VGHA and the third voltage signal VGHD are the same. The voltage signals on the display panel are usually provided by a chip. For example, bonding pads can be provided on the display panel to bond the chip or the flexible circuit board, and the voltage signals are transmitted to the voltage signal lines through the bonding pads, and then further transmitted to the gate driving circuit 00 or the pixel driving circuit in the panel, etc. When the voltage values of the first voltage signal VGHA corresponding to the first control unit 10 and the third voltage signal VGHD corresponding to the first output unit 20 in the gate driving circuit 00 are the same, the first voltage signal line 51 for transmitting the first voltage signal VGHA and the second voltage signal line 52 for transmitting the third voltage signal VGHD can be connected to the same bonding pad, which is beneficial to reducing the number of bonding pads and the number of pads on the chip, so it is beneficial to simplify the chip design.

[0092] Of course, in some other embodiments of the present disclosure, when the voltage values of the first voltage signal VGHA and the third voltage signal VGHD are the same, the first voltage signal line 51 and the second voltage signal line 52 can also be connected to different bonding pads, and the voltage values of the voltage signals transmitted by the different bonding pads are the same. The present disclosure does not specifically limit this.

[0093] It should be noted that the same voltage values of the first voltage signal VGHA and the third voltage signal VGHD mentioned in the embodiments of the present disclosure mean that the voltage values of the two are the same when the first voltage signal is not affected by the coupling of the clock signal, or the voltage values are the same as the voltage signals transmitted by the bonding pads to which the first voltage signal line 51 and the second voltage signal line 52 are connected.

[0094] Please continue to refer to Figure 12 , in an optional embodiment of the present disclosure, the second voltage signal VGLA and the fourth voltage signal VGLA' are signals with the same voltage value and are provided by the same voltage signal line 60, and the voltage signal line 60 here is the fifth voltage signal line 55.

[0095] In this embodiment, the second voltage signal VGLA is a low-potential signal provided to the first control unit 10, and the fourth voltage signal VGLA' is a low-potential signal provided to the first output unit 20. When the second voltage signal VGLA and the fourth voltage signal VGLA' are set to signals with the same voltage value provided by the same voltage signal line 60, there is no need to separately introduce different voltage signal lines for the first control unit 10 and the first output unit 20 to transmit the low-potential signal. Therefore, it is beneficial to simplify the number of voltage signal lines corresponding to the gate driving circuit 00.

[0096] In some embodiments, the fourth voltage signal VGLA' corresponds to the invalid level signal in the stage transmission signal. Or rather, the fourth voltage signal VGLA' is output as the invalid level signal in the stage transmission signal.

[0097] Optionally, in the same gate driving circuit 00, the first control units 10 and the first output units 20 of different cascaded shift registers 01 are both connected to the same fifth voltage signal line 55. Through this fifth voltage signal line 55, the second voltage signal VGLA and the fourth voltage signal VGLA' with the same voltage value can be provided to different shift registers 01. There is no need to separately introduce different voltage signal lines for different shift registers 01, which is beneficial to reducing the number of voltage signal lines connected to the gate driving circuit and beneficial to simplifying the wiring of the display panel.

[0098] It should be noted that in some other embodiments of the present disclosure, the second voltage signal VGLA and the fourth voltage signal VGLA' can also be signals with the same potential type but different voltage values; or, the second voltage signal VGLA and the fourth voltage signal VGLA' can also be reflected as signals with the same voltage value provided by different voltage signal lines. The present disclosure does not specifically limit this.

[0099] Optionally, in the embodiments of the present disclosure, the first voltage signal and the third voltage signal are both high-potential signals, and the second voltage signal and the fourth voltage signal are both low-potential signals as an example for illustration. However, the present disclosure is not limited thereto. In some other embodiments of the present disclosure, the first voltage signal and the third voltage signal can also be reflected as low-potential signals, and the second voltage signal and the fourth voltage signal can also be reflected as high-potential signals.

[0100] Figure 13 Shown is a schematic connection diagram of the voltage signal line and the fan-out line in the display panel provided by the embodiments of the present disclosure. It should be noted that Figure 13 Only the connection relationship between the voltage signal line connected to the gate driving circuit 00 and the fan-out line is shown, and the connection relationship between other traces in the display panel and the fan-out line is not shown. For the connection relationship between other traces such as the data line and the fan-out line, reference can be made to the related art, and the present disclosure does not limit this. Please refer to Figure 1 andFigure 13 , in an alternative embodiment of the present disclosure, the display panel 100 includes a display area AA and a first non-display area A1 located on one side of the display area along the first direction D1. The first non-display area includes a fan-out area Q1 and a bending area Q2. The fan-out area Q1 is located between the bending area Q2 and the display area AA; the fan-out area Q1 includes a first fan-out line 91 and a second fan-out line 92. The first fan-out line 91 is electrically connected to the first voltage signal line 51, and the second fan-out line 92 is electrically connected to the second voltage signal line 52; the bending area Q2 includes a first lead 81, and the first fan-out line 91 and the second fan-out line 92 are electrically connected to the same first lead 81.

[0101] Optionally, the display panel provided by the embodiment of the present disclosure is a flexible display panel. The flexible display panel can be bent through the bending area Q2 to bend at least some components to the backlight surface of the display panel, so as to reduce the border width of the display panel. Figure 13 The non-bent area of the display panel is schematically shown. For the structural diagram of the bent display panel, reference can be made to Figure 14 , where Figure 14 FIG. shows a schematic structural diagram of the display panel provided by the embodiment of the present disclosure after being bent through the bending area Q2. Optionally, a pad area Q4 is provided on the side of the bending area Q2 away from the fan-out area Q1. The pad area Q4 is used for bonding with the control chip IC or for bonding with the flexible circuit board. In this way, the pad area Q4 will not occupy the space on the light-emitting surface side of the display panel, so it is beneficial to realize the narrow border design of the display panel.

[0102] Please continue to refer to Figure 13 and Figure 14 , in the first non-display area, the fan-out area Q1 is adjacent to the display area in the display panel. The bending area Q2 is located on the side of the fan-out area Q1 away from the display area. The display panel can be bent through the bending area Q2. The pad area Q4 is located on the side of the bending area Q2 away from the fan-out area Q1. The pad area Q4 includes a plurality of bonding pads P. After the control chip IC is bonded to the pad area Q4, the control chip IC can provide signals such as power signals and data signals through the bonding pads P. It should be noted that Figure 13Only the bonding pads connected to some of the voltage signal lines are schematically shown, and other bonding pads are not shown. In fact, there are other bonding pads in the pad region Q4. To realize the connection between the first voltage signal line 51 and the second voltage signal line 52 and the bonding pad P, in this embodiment, a first fan-out line 91 connected to the first voltage signal line 51 and a second fan-out line 92 connected to the second voltage signal line 52 are introduced in the pad region Q4. Considering that the extension direction of the fan-out lines in the fan-out region Q1 is not unique, and most of them show a trend of converging from both sides of the fan-out region Q1 to the middle region, bending the fan-out region Q1 may cause the risk of broken wires. Therefore, in the embodiment of the present disclosure, a bending region Q2 is further introduced, and a first lead 81 is introduced in the bending region Q2. Through this first lead 81, the fan-out line is electrically connected to the bonding pad P in the pad region Q4. Optionally, the first lead 81 extends along the first direction D1, conforming to the bending trend of the bending region Q2, which is beneficial to avoiding the problem of broken wires due to bending.

[0103] In this embodiment, the first voltage signal line 51 is electrically connected to the first fan-out line 91, and the second voltage signal line 52 is electrically connected to the second fan-out line 92. The first fan-out line 91 and the second fan-out line 92 are electrically connected to the same first lead 81 in the bending region Q2. In this way, voltage signals with the same voltage value can be respectively transmitted to the first fan-out line 91 and the second fan-out line 92 through the first lead 81, and further transmitted to the first voltage signal line 51 and the second voltage signal line 52. The voltage signal transmitted through the first voltage signal line 51 is the first voltage signal VGHA mentioned in the foregoing embodiment, and the voltage signal transmitted through the second voltage signal line 52 is the third voltage signal VGHD mentioned in the foregoing embodiment. Since the first voltage signal line 51 and the second voltage signal line 52 are connected to the same first lead 81, the voltage value of the first voltage signal VGHA is the same as the voltage value of the third voltage signal VGHD. The connection method of connecting to the same first lead 81 can also reduce the number of leads in the bending region Q2 and simplify the wiring structure of the bending region Q2.

[0104] Please continue to refer to Figure 13, in an alternative embodiment of the present disclosure, the ends of the first fan-out line 91 and the second fan-out line 92 away from the display area are electrically connected through a first connection part 71, and the first connection part 71 is located in the fan-out area Q1. Since the first fan-out line 91 and the second fan-out line 92 are electrically connected to the same first lead 81 in the bending area Q2, before being electrically connected to the first lead 81, the first fan-out line 91 and the second fan-out line 92 can be electrically connected first. In this embodiment, the solution of electrically connecting the ends of the first fan-out line 91 and the second fan-out line 92 close to the bending area Q2 through the first connection part 71 is described. The first connection part 71 is located in the fan-out area Q1. Considering that the extending direction of the first connection part 71 for connecting the first fan-out line 91 and the second fan-out line 92 is not the first direction D1, there may be a risk of wire breakage if the first connection part 71 is arranged in the bending area Q2. Therefore, in this embodiment, arranging the first connection part 71 in the non-bending fan-out area Q1 is beneficial to reducing the risk of wire breakage in the bending area Q2. In addition, if the first fan-out line 91 and the second fan-out line 92 are not located in the same metal layer, when electrically connecting the first fan-out line 91 and the second fan-out line 92 through the first connection part 71, the electrical connection needs to be achieved through a via connection method. Therefore, when the first connection part 71 is located in the fan-out area Q1, the corresponding via holes will also be located in the fan-out area Q1, which is also beneficial to avoiding the risk of via hole breakage caused by arranging the via holes in the bending area Q2.

[0105] It should be noted that in some other embodiments of the present disclosure, if there is sufficient space in the display panel, two leads can also be arranged in the bending area to be electrically connected to the first fan-out line 91 and the second fan-out line 92 respectively, and the present disclosure does not specifically limit this.

[0106] Figure 15 The figure shows a film layer schematic diagram of a display panel provided in an embodiment of the present disclosure. This embodiment schematically shows a feasible film layer structure of the driving functional layer on the display panel, but does not limit this. Please refer to Figure 15, optionally, the driving functional layer includes a first active layer L1, a first metal layer M1, a capacitive metal layer MC, a second active layer L2, a gate metal layer MG, a second metal layer M2, and a third metal layer M3 disposed on the same side of the substrate 00. In some other embodiments of the present disclosure, the display panel may further include a fourth metal layer disposed on the side of the third metal layer M3 facing away from the substrate. Optionally, the display panel includes a P-type transistor T-1 and an N-type transistor T-2. The material of the first active layer L1 of the P-type transistor T-1 is polysilicon, and the material of the second active layer L2 of the N-type transistor T-2 is a metal oxide, such as IGZO, IZO, etc. The gate of the P-type transistor T-1 may be located in the first metal layer M1, and the source and drain may be located in the second metal layer M2 and / or the third metal layer M3, for example. The gate of the N-type transistor T-2 may be located in the gate metal layer MG, and the source and drain may be located in the second metal layer M2 and / or the third metal layer M3, for example. In the display panel, the first metal layer M1, the gate metal layer MG, and the second metal layer M2 may also be provided with a plurality of signal lines. Similarly, signal lines can be arranged on both the third metal layer M3 and the capacitive metal layer MC. The capacitive metal layer MC is also used to overlap with the second metal layer M2 or the first metal layer M1 to form a storage capacitor in the pixel driving circuit.

[0107] Please continue to refer to Figure 13 and Figure 15 , signal lines can be arranged in the above-mentioned metal film layers in the display panel. Since signal lines such as voltage signal lines and data lines in the display panel need to be connected to the bonding pads through the fan-out lines in the fan-out area Q1, the number of fan-out lines in the fan-out area Q1 will be relatively large. In an alternative embodiment of the present disclosure, the first fan-out line 91 connected to the first voltage signal line 51 and the second fan-out line 92 connected to the second voltage signal line 52 are located in different film layers. The first voltage signal line 51 and the second voltage signal line 52 connected to the same gate driving circuit 00 may be arranged adjacent to each other in the display panel. Thus, in the fan-out area Q1, the first fan-out line 91 and the second fan-out line 92 will also be arranged adjacent to each other. Considering that there are many fan-out lines in the fan-out area Q1 and the space is limited, the first fan-out line 91 and the second fan-out line 92 can be respectively arranged in different metal layers to avoid the problem of short circuit due to the close distance between the first fan-out line 91 and the second fan-out line 92. Therefore, it is beneficial to improve the stability of the signals transmitted by the first fan-out line 91 and the second fan-out line 92.

[0108] Figure 16 As shown in Figure 13 is an AA cross-sectional view of, which schematically shows the film layer relationship of the first fan-out line 91, the first connection portion 71, and the second fan-out line 92. Please refer to Figure 16, in an alternative embodiment of the present disclosure, the first fan-out line 91 includes a first sub-line 911 and a second sub-line 912 that are electrically connected, and the first sub-line 911 and the second sub-line 912 are arranged on different layers.

[0109] Figure 16 The illustrated embodiment is described by taking the first sub-line 911 located in the first metal layer M1 and the second sub-line 912 located in the capacitor metal layer MC as an example, but the present disclosure is not limited thereto. In some other embodiments of the present disclosure, the first sub-line 911 and the second sub-line 912 may also be located in other metal layers on the display panel. When the first fan-out line 91 is arranged in a double-layer wiring manner using the first sub-line 911 and the second sub-line 912, the first sub-line 911 and the second sub-line 912 can be connected in parallel, which is beneficial to reducing the overall impedance of the first fan-out line 91 and improving the signal transmission efficiency on the first fan-out line 91.

[0110] Please refer to Figure 4 and Figure 13 , both the first control unit 10 and the second control unit 31 in the shift register 01 are electrically connected to the first voltage signal line 51, and obtain the first voltage signal VGHA through the first voltage signal line 51. Therefore, the load corresponding to the first voltage signal line 51 is relatively large. When the first fan-out line 91 electrically connected to the first voltage signal line 51 is wired in a double-layer wiring manner, it is beneficial to reduce the impedance of the first fan-out line 91, improve the transmission efficiency of the first voltage signal VGHA on the first fan-out line 91, and is beneficial to reducing the difference in the first voltage signal VGHA received by different shift registers 01, thereby being beneficial to improving the operating stability of different shift registers 01. In some other embodiments of the present disclosure, if there is sufficient space on the display panel, the first fan-out line 91 can also be wired in a triple-layer wiring manner, and the present disclosure does not specifically limit this.

[0111] Please refer to Figure 13 and Figure 16, optionally, considering that the second voltage signal line 52 is a voltage signal line separately introduced for the first output unit 20 in the shift register 01, the second voltage signal line 52 can be electrically connected only to the first output unit 20 in the shift register 01. Therefore, the load of the second voltage signal line 52 is relatively small. Further considering the limited space in the fan-out region Q1, the second fan-out line 92 corresponding to the second voltage signal line 52 can be routed in a single-layer routing manner. This embodiment shows a solution of setting the second fan-out line 92 on the gate metal layer MG, but the present disclosure is not limited thereto. In some other embodiments of the present disclosure, the second fan-out line 92 can also be set on other metal layers. Of course, if the routing space in the fan-out region Q1 is sufficient, the second fan-out line 92 can be routed in a double-layer routing or triple-layer routing manner to reduce the overall impedance of the second fan-out line 92 and improve the stability of the third voltage signal transmitted by the second fan-out line 92.

[0112] Figure 17 The following is a schematic diagram of a film layer showing the connection of the first voltage signal line 51 and the second voltage signal line 52 through the first connection portion 71. Please refer to Figure 13 and Figure 17 , when the first sub-line 911 and the second sub-line 912 in the first fan-out line 91 are located on the first metal layer M1 and the capacitor metal layer MC respectively, and the second fan-out line 92 is located on the gate metal layer MG, the first connection portion 71 connecting the first fan-out line 91 and the second fan-out line 92 can be set on the capacitor metal layer MC, directly connected to the second sub-line 912 in the first fan-out line 91, and electrically connected to the second fan-out line 92 through a via hole, which is beneficial to reducing the connection difficulty between the first fan-out line 91 and the second fan-out line 92. However, the present disclosure is not limited thereto. In some other embodiments of the present disclosure, the first connection portion 71 can also be set on other feasible metal layers according to actual requirements, for example, it can be located on the first metal layer M1.

[0113] Figure 16 and Figure 17 The embodiment shown shows a solution in which the first fan-out line 91 and the second fan-out line 92 do not overlap in a direction perpendicular to the plane of the substrate 00. However, the present disclosure is not limited thereto. In some other embodiments of the present disclosure, in a direction perpendicular to the plane of the substrate 00, the first fan-out line 91 and the second fan-out line 92 can also overlap. For example, please refer to Figure 18 , Figure 18 The following shows Figure 13A schematic diagram of a film layer of the first fan-out line 91 and the second fan-out line 92. Considering that the first fan-out line 91 is electrically connected to the first voltage signal line 51, and the second fan-out line 92 is electrically connected to the second voltage signal line 52, and the first voltage signal VGHA and the third voltage signal VGHD respectively transmitted by the first voltage signal line 51 and the second voltage signal line 52 are signals of the same potential type. Optionally, the voltage values of the first voltage signal VGHA and the third voltage signal VGHD are the same. Therefore, when the first fan-out line 91 and the second fan-out line 92 are set to overlap, the signals transmitted by the first fan-out line 91 and the second fan-out line 92 will not cause mutual coupling interference. At the same time, the overlapping setting method of the two is also beneficial to reduce the actual occupied space width of the first fan-out line 91 and the second fan-out line 92 in the fan-out area (specifically referring to the space width parallel to the plane where the substrate 00 is located), thereby facilitating the realization of a narrow border width of the display panel.

[0114] Please continue to refer to Figure 13 , in an optional implementation manner of the present disclosure, the first non-display area includes a pad area Q4, the pad area Q4 is located on the side of the bending area Q2 away from the display area, the pad area Q4 includes a plurality of bonding pads P, and the bonding pad P includes a first bonding pad P1; the first lead 81 is electrically connected to the first bonding pad P1. The bonding pads P in the pad area Q4 are used to be electrically connected to a control chip or a flexible circuit board. In this way, the control chip can transmit signals to the signal lines in the display panel through the bonding pads. In this embodiment, the first voltage signal line 51 and the second voltage signal line 52 are respectively electrically connected to the first fan-out line 91 and the second fan-out line 92 in the fan-out area Q1, and the first fan-out line 91 and the second fan-out line 92 are also electrically connected to the same first lead 81 in the bending area Q2, and the first lead 81 is electrically connected to the first bonding pad P1. In this way, the electrical connection between the first bonding pad P1 and the first voltage signal line 51 and the second voltage signal line 52 is realized, and the corresponding voltage signals can be transmitted to the first voltage signal line 51 and the second voltage signal line 52 through one first bonding pad P1, so that the voltage values of the first voltage signal VGHA transmitted by the first voltage signal line 51 and the third voltage signal VGHD transmitted by the second voltage signal line 52 are the same. Therefore, it is not necessary to introduce different bonding pads for the first voltage signal line 51 and the second voltage signal line 52, which is beneficial to reducing the number of bonding pads in the pad area Q4, reducing the number of pads in the control chip bonded in the bonding area, and thus is beneficial to simplifying the chip structure and reducing the production cost.

[0115] Please combine Figure 4 and Figure 10, in an alternative embodiment of the present disclosure, the gating unit 30 includes a second control unit 31 and a second output unit 32. The second control unit 31 is configured to control the signal of the fifth node N5 at least according to the first voltage signal VGHA, the signal of the first node N1, the stage transmission signal NEXT, and the frequency control signal CTRL. The second output unit 32 is configured to output a gate driving signal at least according to the signals of the fifth node N5 and the second node N2.

[0116] In this embodiment, the second control unit 31 in the gating unit 30 receives the first voltage signal VGHA and can be connected to the same first voltage signal line 51 as the first control unit 10. There is no need to separately introduce a voltage signal line for transmitting the high-voltage signal for the second control unit 31, which is beneficial to reducing the number of voltage signal lines connected to the gate driving circuit 00 and simplifying the wiring difficulty of the display panel.

[0117] It should be noted that when the space of the display panel is sufficient, a voltage signal line for transmitting the high-voltage signal can also be introduced for the second control unit 31, so as to avoid the mutual influence of the high-voltage signals received by different units in the shift register 01 and improve the accuracy of the signals of each unit in the shift register 01.

[0118] Please refer to Figure 4 and Figure 12 , in an alternative embodiment of the present disclosure, N cascaded shift registers 01 include a first shift register 011 and a second shift register 012. The second output unit 32 of the first shift register 011 is configured to output a gate driving signal according to the fifth voltage signal VGHB, the sixth voltage signal VGLB, and the signal of the second node N2. The second output unit 32 of the second shift register 012 is configured to output a gate driving signal according to the seventh voltage signal VGHC, the sixth voltage signal VGLB, and the signal of the second node N2. The fifth voltage signal VGHB, the seventh voltage signal VGHC, and the third voltage signal VGHD are signals of the same potential type. The sixth voltage signal VGLB, the fourth voltage signal VGLA’, and the second voltage signal VGLA are signals of the same potential type.

[0119] Please continue to refer to Figure 12 , the cascaded N shift registers 01 include a first shift register 011 and a second shift register 012. Optionally, the first shift register 011 is located at an odd stage, and the second shift register 012 is located at an even stage; or, the first shift register 011 is located at an even stage, and the second shift register 012 is located at an odd stage. This embodiment is described only by taking the first shift register 011 located at an odd stage and the second shift register 012 located at an even stage as an example.

[0120] For each first shift register 01 in the same gate driving circuit 00, its second output unit 32 is connected to the same third voltage signal line 53 for transmitting a fifth voltage signal VGHB to the second output unit 32. For each second shift register 01 in the same gate driving circuit 00, its second output unit 32 is connected to the same fourth voltage signal line 54 for transmitting a seventh voltage signal VGHC to the second output unit 32. When the first shift register 01 needs to transmit an effective level signal in the gate driving signal to the corresponding scan line, the fifth voltage signal VGHB will be able to be transmitted to the output end of the shift register 01 and output as the gate driving signal. When the second shift register 01 needs to transmit an effective level signal in the gate driving signal to the corresponding scan line, the seventh voltage signal VGHC will be able to be transmitted to the output end of the shift register 01 and output as the gate driving signal. If the third output modules 311 of the odd-level and even-level shift registers 01 are connected to the same voltage signal line, considering that during the process of the gate driving signal output by the shift register 01 jumping from a high level to a low level, due to the coupling effect of the signal, the voltage signal on the voltage signal line connected to the third output module 311 in the selection unit 30 will be affected, resulting in ripples or glitches on the signal of this voltage signal line. Since the gate driving signal output by each stage of the shift register 01 will have a corresponding coupling effect during the process of jumping from a high level to a low level, the voltage signal on the aforementioned voltage signal line will repeatedly appear ripples or glitches. Therefore, the present disclosure introduces a third voltage signal line 53 and a fourth voltage signal line 54 for the first shift register 01 and the second shift register 01 respectively to transmit the fifth voltage signal VGHB and the seventh voltage signal VGHC respectively. The ripples or glitches generated on the third voltage signal line 53 due to the coupling effect will be halved, and the ripples or glitches generated on the fourth voltage signal line 53 due to the coupling effect will also be halved. Thus, the influence on the signals on the third voltage signal line 53 and the fourth voltage signal line 54 will also be reduced. Moreover, for adjacent odd-level and even-level shift registers, since their third output modules 311 are connected to different voltage signal lines, their signals will not affect each other. Therefore, it is beneficial to improve the stability of the gate driving signal output by the selection unit 30.

[0121] In the present disclosure, the fifth voltage signal VGHB, the seventh voltage signal VGHC, and the third voltage signal VGHD are signals of the same potential type. Optionally, the fifth voltage signal VGHB, the seventh voltage signal VGHC, the third voltage signal VGHD, and the first voltage signal VGHA are high-potential signals. The sixth voltage signal VGLB, the fourth voltage signal VGLA', and the second voltage signal VGLA are signals of the same potential type. Optionally, the sixth voltage signal VGLB, the fourth voltage signal VGLA', and the second voltage signal VGLA are low-potential signals. By setting the fifth voltage signal VGHB, the seventh voltage signal VGHC, the third voltage signal VGHD, and the first voltage signal VGHA as high-potential signals, and setting the sixth voltage signal VGLB, the fourth voltage signal VGLA', and the second voltage signal VGLA as low-potential signals, the control of the gate driving signal output by the shift register 01 is achieved. Of course, in some other embodiments of the present disclosure, the fifth voltage signal VGHB, the seventh voltage signal VGHC, the third voltage signal VGHD, and the first voltage signal VGHA may also be embodied as low-potential signals, and the sixth voltage signal VGLB, the fourth voltage signal VGLA', and the second voltage signal VGLA may also be embodied as high-potential signals. The present disclosure does not make specific limitations thereto.

[0122] Please continue to refer to Figure 13 , in an optional implementation manner of the present disclosure, the voltage signal lines 60 in the display panel further include a third voltage signal line 53 and a fourth voltage signal line 54. The third voltage signal line 53 is used to transmit the fifth voltage signal VGHB, and the fourth voltage signal line 54 is used to transmit the seventh voltage signal VGHC. The method of introducing different voltage signal lines for the odd-stage shift register and the even-stage shift register to transmit the fifth voltage signal VGHB and the seventh voltage signal VGHC of the same potential type is beneficial to avoiding the mutual influence of the signals received by the odd-stage shift register and the even-stage shift register, and thus is beneficial to improving the accuracy of the gate driving signal output by the shift register.

[0123] Please refer to Figure 13 , in an optional implementation manner of the present disclosure, the voltage values of the fifth voltage signal VGHB, the seventh voltage signal VGHC, the third voltage signal VGHD, and the first voltage signal VGHA are the same; and / or, the voltage values of the sixth voltage signal VGLB, the fourth voltage signal VGLA', and the second voltage signal VGLA are the same.

[0124] When the voltage values of the fifth voltage signal VGHB, the seventh voltage signal VGHC, the third voltage signal VGHD, and the first voltage signal VGHA are set to be the same, the voltage signal lines corresponding to these voltage signals can be connected to the same bonding pad through fan-out lines, and these voltage signals can be transmitted to the shift register 01 through the same bonding pad, which helps to reduce the number of bonding pads included in the pad area Q4, simplifies the chip structure, and reduces the chip production cost.

[0125] Optionally, the fifth voltage signal VGHB, the seventh voltage signal VGHC, the third voltage signal VGHD, and the first voltage signal VGHA are high-potential signals, and these high-potential signals with the same voltage value can be transmitted to the shift register 01 through the same bonding pad, which helps to achieve unified control of the high-potential signals.

[0126] It should be noted that in some alternative embodiments of the present disclosure, when the fifth voltage signal VGHB, the seventh voltage signal VGHC, the third voltage signal VGHD, and the first voltage signal VGHA are all high-potential signals, the voltage values of these voltage signals can be set to be not completely the same, or different from each other. At this time, the voltage signals with different voltage values can be transmitted by different bonding pads, and the present disclosure does not make specific limitations on this.

[0127] Similarly, when the voltage values of the sixth voltage signal VGLB, the fourth voltage signal VGLA', and the second voltage signal VGLA are set to be the same, the voltage signal lines corresponding to these voltage signals can be connected to the same bonding pad through fan-out lines, and these voltage signals can be transmitted to the shift register 01 through the same bonding pad, which also helps to reduce the number of bonding pads included in the pad area Q4, simplifies the chip structure, and reduces the chip production cost.

[0128] Optionally, the sixth voltage signal VGLB, the fourth voltage signal VGLA', and the second voltage signal VGLA are low-potential signals, and these low-potential signals with the same voltage value can be transmitted to the shift register 01 through the same bonding pad, which helps to achieve unified control of the high-potential signals.

[0129] It should be noted that when the sixth voltage signal VGLB, the fourth voltage signal VGLA', and the second voltage signal VGLA are all low-potential signals, the voltage values of these voltage signals can be set to be not completely the same, or different from each other. At this time, the voltage signals with different voltage values can be transmitted by different bonding pads, and the present disclosure does not make specific limitations on this.

[0130] Please continue to refer to Figure 1 and Figure 13, in an alternative embodiment of the present disclosure, the display panel includes a display area AA and a first non-display area A1 located on one side of the display area AA along the first direction D1. The first non-display area A1 includes a fan-out area Q1 and a bending area Q2. The fan-out area Q1 is located between the bending area Q2 and the display area; the fan-out area Q1 includes a third fan-out line 93 and a fourth fan-out line 94. The third fan-out line 93 is electrically connected to the third voltage signal line 53, and the fourth fan-out line 94 is electrically connected to the fourth voltage signal line 54; the bending area Q2 includes a second lead 82 and a third lead 83. The second lead 82 is electrically connected to the third fan-out line 93, and the third lead 83 is electrically connected to the fourth fan-out line 94.

[0131] The third voltage signal line 53 is used to provide a voltage signal to the second output unit 32 in the odd-stage shift register 01, and the fourth voltage signal line 54 is used to provide a voltage signal to the second output unit 32 in the even-stage shift register 01. The third voltage signal line 53 is electrically connected to the second lead 82 through the third fan-out line 93, and the fourth voltage signal line 54 is electrically connected to the third lead 83 through the fourth fan-out line 94. That is to say, the fan-out lines corresponding to the third voltage signal line 53 and the fourth voltage signal line 54 are separately routed, and the leads corresponding to the bending area Q2 are also separately routed. This is beneficial to improving the stability and accuracy of the voltage signals transmitted to the third voltage signal line 53 and the fourth voltage signal line 54.

[0132] Figure 19 Shown as Figure 13 a cross-sectional view taken along the BB direction of Figure 20 Shown as Figure 13 another cross-sectional view taken along the BB direction of Figure 15 , Figure 19 and Figure 20 , in an alternative embodiment of the present disclosure, the third fan-out line 93 includes at least two sub-fan-out lines 930 located in different metal layers and electrically connected, and the fourth fan-out line 94 includes at least two sub-fan-out lines 940 located in different metal layers and electrically connected.

[0133] Please refer to Figure 15 , in the display panel, signal lines can be arranged on metal film layers such as the gate metal layer MG, the first metal layer M1, the capacitor metal layer MC, the second metal layer M2, and the third metal layer M3. In the fan-out area, the fan-out lines can be arranged on at least one of the gate metal layer MG, the capacitor metal layer MC, and the first metal layer M1. Figure 19 The shown embodiment shows a structure in which both the third fan-out line 93 and the fourth fan-out line 94 are double-layer routed. Figure 20 The shown embodiment shows a structure in which both the third fan-out line 93 and the fourth fan-out line 94 are triple-layer routed. Figure 19In the embodiment shown, the third fan-out line 93 and the fourth fan-out line 94 are respectively connected in parallel in the gate metal layer MG and the first metal layer M1 as an example for explanation. Figure 20 The illustrated embodiment is described by taking the wiring method of the third fan-out line 93 and the fourth fan-out line 94 in the gate metal layer MG, the capacitor metal layer MC and the first metal layer M1 respectively as an example, but the present disclosure is not limited to this. When the third fan-out line 93 and the fourth fan-out line 94 adopt double-layer wiring or triple-layer wiring, the corresponding routing can also be set in other film layers.

[0134] In this embodiment, the third fan-out line 93 and the fourth fan-out line 94 adopt a double-layer metal parallel routing method or a three-layer metal parallel routing method, which is beneficial to reducing the impedance of the third fan-out line 93 and the fourth fan-out line 94, thereby facilitating the improvement of the transmission efficiency of the voltage signal on the third fan-out line 93 and the fourth fan-out line 94, so as to reduce the difference in the fifth voltage signal received by different first shift registers 01, and at the same time, it is beneficial to reduce the difference in the seventh voltage signal received by different second shift registers 01, and is beneficial to improving the working stability and consistency of different shift registers 01.

[0135] Considering that the third fan-out line 93 and the fourth fan-out line 94 are electrically connected to the third voltage signal line 53 and the fourth voltage signal line 54 respectively, and the signals transmitted by the third voltage signal line 53 and the fourth voltage signal line 54 can be output to the pixel driving circuit as gate drive signals, when the third fan-out line 93 and the fourth fan-out line 94 correspond to three sub-fan-out lines respectively, it is beneficial to reduce the impedance of the third voltage signal line 53 and the fourth voltage signal line 54, and improve the transmission stability and accuracy of the corresponding voltage signals. At this time, the three sub-fan-out lines corresponding to the third voltage signal line 53 and the fourth voltage signal line 54 can be distributed in the first metal layer M1, the capacitor metal layer MC and the gate metal layer MG. Please combine Figure 13 , Figure 18 and Figure 20 Optionally, along the direction perpendicular to the substrate 00, the first fan-out line 91 and the second fan-out line 92 overlap in the orthographic projection of the plane where the substrate 00 is located, and the sub-fan-out line corresponding to the first fan-out line is distributed in the capacitor metal layer MC and the first metal layer M1, and the second fan-out line 92 is distributed in the gate metal layer MG, that is, the first fan-out line 91 and the second fan-out line 92 are distributed as a whole in the first metal layer M1, the capacitor metal layer MC and the gate metal layer MG. This is conducive to the rational use of the space in the fan-out area to set the first fan-out line 91, the second fan-out line 92, the third fan-out line 93 and the fourth fan-out line 94, which ensures the reliable transmission of the signals on the fan-out line and is conducive to the realization of the narrow frame design of the display panel.

[0136] Please continue to refer to Figure 13, in an alternative embodiment of the present disclosure, the first non-display area includes a pad area Q4, the pad area Q4 is located on the side of the bending area Q2 away from the display area, the pad area Q4 includes a plurality of bonding pads P, the bonding pad P includes a second bonding pad P2, and the second lead 82 and the third lead 83 are electrically connected to the same second bonding pad P2.

[0137] Optionally, a connection line area Q3 is further included between the bending area Q2 and the pad area Q4. The connection line area Q3 is provided with connection lines for electrically connecting the bonding pads P to the leads in the bending area Q2. The second lead 82 and the third lead 83 can correspond to different connection lines in the connection line area. After the connection lines corresponding to the second lead 82 and the third lead 83 are electrically connected in the wiring area Q3, they are then electrically connected to the second bonding pad P2. By transmitting voltage signals to the third voltage signal line 53 and the fourth voltage signal line 54 respectively through one second bonding pad P2, it is not necessary to introduce different bonding pads for the third voltage signal line 53 and the fourth voltage signal line 54 respectively. Thus, it is beneficial to reduce the number of bonding pads in the pad area Q4, and further beneficial to reduce the number of pads in the control chip bonded to the pad area Q4, which is beneficial to simplify the chip structure and reduce the chip production cost. The method of separately routing the third fan-out line 93 and the fourth fan-out line 94 corresponding to the third voltage signal line 53 and the fourth voltage signal line 54, and separately routing the corresponding second lead 82 and the third lead 83 is beneficial to improving the stability and accuracy of the voltage signals transmitted to the third voltage signal line 53 and the fourth voltage signal line 54, and avoiding signal interference in the odd-stage shift register and the even-stage shift register.

[0138] Figure 13 The illustrated embodiment shows a solution where the first bonding pad P1 and the second bonding pad P2 are two independent pads. At this time, different high-potential signals can be transmitted through the first bonding pad P1 and the second bonding pad P2 respectively, but the present disclosure is not limited thereto. In some other embodiments of the present disclosure, the first bonding pad P1 and the second bonding pad P2 can also be electrically connected. For example, please refer to Figure 21 , Figure 21 Shown is another connection schematic diagram of the voltage signal line and the fan-out line in the display panel provided by the embodiment of the present disclosure. In this embodiment, the first bonding pad P1 and the second bonding pad P2 are electrically connected through a signal line, and they are at the same potential. Thus, voltage signals with the same voltage value can be provided to the first voltage signal line 51, the second voltage signal line 52, the third voltage signal line 53, and the fourth voltage signal line 54 respectively through the first bonding pad P1 and the second bonding pad P2.

[0139] Please continue to refer to Figure 4 and Figure 21, in an alternative embodiment of the present disclosure, the gating unit 30 is configured to output a gate driving signal at least according to the stage transmission signal NEXT, the frequency control signal CTRL, and the sixth voltage signal VGLB. The sixth voltage signal VGLB and the second voltage signal VGLA are signals of the same potential type, and / or the sixth voltage signal VGLB and the fourth voltage signal VGLA' are signals of the same potential type. The display panel voltage signal line 60 further includes a fifth voltage signal line 55 and a sixth voltage signal line 56. The fifth voltage signal line 55 is used to transmit at least one of the second voltage signal VGLA and the fourth voltage signal VGLA', and the sixth voltage signal line 56 is used to transmit the sixth voltage signal VGLB.

[0140] In the embodiment of the present disclosure, the sixth voltage signal VGLB and the fourth voltage signal VGLA' have the same potential type, and / or the sixth voltage signal VGLB and the second voltage signal VGLA have the same potential type. Optionally, the sixth voltage signal VGLB, the fourth voltage signal VGLA', and the second voltage signal VGLA are all low potential signals, and the first voltage signal VGHA, the third voltage signal VGHD, the fifth voltage signal VGHB, and the seventh voltage signal VGHC are all high potential signals. In the embodiment of the present disclosure, a fifth voltage signal line 55 is introduced in the display panel to transmit the second voltage signal VGLA or the fourth voltage signal VGLA', and a sixth voltage signal line 56 is introduced to transmit the sixth voltage signal VGLB. In this embodiment, the low potential signals corresponding to the first control unit 10 and the first output unit 20 are transmitted by the fifth voltage signal line 55, and the low potential signals corresponding to the second control unit 31 and the second output unit 32 are transmitted by the sixth voltage signal line 56 as an example for illustration. The method of separately arranging the fifth voltage signal line 55 and the sixth voltage signal line 56 is beneficial to avoiding the influence of the low potential signals in the gating unit 30 by the low potential signals of the first control unit 10 and the first output unit 20, thereby being beneficial to improving the accuracy of the gate driving signal output by the gating unit.

[0141] Please continue to refer to Figure 1 and Figure 21 , in an alternative embodiment of the present disclosure, the display panel includes a display area AA and a first non-display area A1 located on one side of the display area AA along the first direction D1. The first non-display area A1 includes a fan-out area Q1 and a bending area Q2. The fan-out area Q1 is located between the bending area Q2 and the display area. The fan-out area Q1 includes a fifth fan-out line 95, and the bending area Q2 includes a fourth lead 84. The fifth voltage signal line 55 and the sixth voltage signal line 56 are connected to the same fifth fan-out line 95, and the fifth fan-out line 95 is electrically connected to the fourth lead 84.

[0142] Optionally, the second voltage signal VGLA, the fourth voltage signal VGLA', and the sixth voltage signal VGLB have the same potential type and the same voltage value. To achieve the electrical connection between the fifth voltage signal line 55 and the sixth voltage signal line 56 and the bonding pad P3 in the pad region Q4, in this embodiment, a fifth fan-out line 95 is introduced in the fan-out region Q1, and a fourth lead 84 is introduced in the bending region Q2. The fifth voltage signal line 55 and the sixth voltage signal line 56 are electrically connected to a fourth lead 84 through the same fifth fan-out line 95, and then the electrical connection with the same third bonding pad P3 can be achieved through the fourth lead 84. In this way, the number of fan-out lines and the number of leads corresponding to the fifth voltage signal line 55 and the sixth voltage signal line 56 can be reduced, which is beneficial to simplifying the wiring difficulty of the display panel while realizing the effective transmission of the voltage signal.

[0143] Please continue to refer to Figure 13 , in an alternative embodiment of the present disclosure, the fifth voltage signal line 55 and the sixth voltage signal line 56 are electrically connected through a second connection portion 72, and the second connection portion 72 is located on a side of the fan-out region Q1 away from the bending region Q2.

[0144] During actual wiring, the fifth voltage signal line 55 and the sixth voltage signal line 56 are connected to different units in the shift register 01. For example, the fifth voltage signal line 55 is used to be electrically connected to the first control unit 10 and the first output unit 20 in the shift register 01, while the sixth voltage signal line 56 is electrically connected to the second control unit 31 and the second output unit 32 in the strobe unit 30 of the shift register 01. To achieve the near connection of the fifth voltage signal line 55 with the first control unit 10 and the first output unit 20, the fifth voltage signal line 55 can be arranged between the first control unit 10 and the first output unit 20. To achieve the near connection of the sixth voltage signal line 56 with the strobe unit 30, the sixth voltage signal line 56 can be arranged on a side of the strobe unit 30 away from the first output unit 20, or between the second control unit 31 and the second output unit 32. In this way, the fifth voltage signal line 55 and the sixth voltage signal line 56 are not adjacent, and there is at least the first output unit 20 between them. To achieve the electrical connection between the fifth voltage signal line 55 and the sixth voltage signal line 56 and the same fifth fan-out line 95, the ends of the fifth voltage signal line 55 and the sixth voltage signal line 56 close to the fan-out region Q1 can be electrically connected through the second connection portion 72 first, and then electrically connected to the fifth fan-out line 95 through the second connection portion 72. At this time, the second connection portion 72 can be located on a side of the fan-out region Q1 away from the bending region Q2, without occupying the space of the fan-out region Q1, so as not to affect the original wiring in the fan-out region Q1, and also not increase the number of fan-out wirings in the fan-out region Q1.

[0145] Optionally, if there is sufficient space in the display panel, different fan-out lines and lead lines can also be introduced for the fifth voltage signal line 55 and the sixth voltage signal line 56 respectively. After electrically connecting the two lead lines in the wiring area Q4, they are then connected to the bonding pad P3 to improve the stability of the signals transmitted to the fifth voltage signal line 55 and the sixth voltage signal line 56.

[0146] Figure 22 As shown Figure 21 is a cross-sectional view in the CC direction. Please refer to Figure 22 , in an alternative embodiment of the present disclosure, the fifth fan-out line 95 includes at least two sub-fan-out lines 950 located in different metal layers and electrically connected. Figure 22 The embodiment is described by taking the sub-fan-out lines 950 of the fifth fan-out line 95 located in three metal layers as an example, but the number of sub-fan-out lines 950 included in the fifth fan-out line 95 is not limited. In some other embodiments of the present disclosure, the fifth fan-out line 95 may also include two sub-fan-out lines or more than three sub-fan-out lines. When the fifth fan-out line 95 includes at least two sub-fan-out lines 950 located in different metal layers, the at least two sub-fan-out lines 950 are in a parallel structure. In this way, the overall impedance of the fifth fan-out line 95 can be reduced, which is beneficial to improving the rate of the voltage signals transmitted on the fifth sub-fan-out line.

[0147] It should be noted that Figure 22 the embodiment shown is described by taking the three sub-fan-out lines 950 in the fifth fan-out line being located in the gate metal layer MG, the capacitor metal layer MC, and the first metal layer M1 respectively as an example, but the present disclosure is not limited thereto. In some other embodiments of the present disclosure, the sub-fan-out lines 950 in the fifth fan-out line 95 can also be arranged in other feasible metal film layers.

[0148] Please continue to refer to Figure 1 , Figure 4 and Figure 13 , in an alternative embodiment of the present disclosure, the voltage signal lines 60 in the display panel include a first type of voltage signal line 61 and a second type of voltage signal line 62. Among them, the first type of voltage signal line 61 is electrically connected to at least the stage transmission unit 03, and the second type of voltage signal line 62 is electrically connected to the selection unit 30. In this embodiment, the first type of voltage signal line 61 includes the aforementioned first voltage signal line 51, second voltage signal line 52, and fifth voltage signal line 55; the second type of voltage signal line 62 includes the aforementioned third voltage signal line 53, fourth voltage signal line 54, and sixth voltage signal line 56.

[0149] The display panel includes a display area AA and a first non-display area A1 located on one side of the display area AA along the first direction D1. The first non-display area A1 includes a fan-out area Q1. The fan-out area Q1 includes first-type fan-out lines S01 and second-type fan-out lines S02. The first-type fan-out lines S01 are electrically connected to first-type voltage signal lines 61, and the second-type fan-out lines S02 are electrically connected to second-type voltage signal lines 62. In this embodiment, the first-type fan-out lines S01 include a first fan-out line 91 and a second fan-out line 92, and the second-type fan-out lines S02 include a third fan-out line 93, a fourth fan-out line 94, and a fifth fan-out line 95.

[0150] The number of film layers occupied by at least one first-type fan-out line S01 in the display panel is n1, and the number of film layers occupied by at least one second-type fan-out line S02 in the display panel is n2, where n1 ≤ n2. The film layers occupied by the fan-out lines in the display panel refer to the wiring film layers of the fan-out lines in the display panel. For example, the fan-out lines can be Figure 15 wired on the metal film layer shown in the illustrated embodiment. Exemplarily, they can be distributed in at least one of the first metal layer M1, the capacitor metal layer MC, and the gate metal layer MG.

[0151] Considering that the second-type voltage signal lines 62 corresponding to the second-type fan-out lines S02 are connected to the gating unit 30, and the gating unit 30 is the unit that finally outputs the gate driving signal in the display panel, and it outputs the gate driving signal at least according to the voltage signals transmitted on the second-type voltage signal lines 62. Therefore, the stability of the voltage signals transmitted on the second-type voltage signal lines 62 directly determines the stability of the finally output gate driving signal. In this embodiment, when the number of film layers occupied by the second-type fan-out lines S02 corresponding to the second-type voltage signal lines 62 in the display panel is set to be relatively large, the impedance of the second-type fan-out lines S02 is reduced by the multi-layer parallel wiring method, which is beneficial to reducing the overall impedance of the second-type voltage signal lines 62 and the second-type fan-out lines S02, thereby making the voltage signals transmitted on the second-type fan-out lines S02 and the second-type voltage signal lines 62 more stable. Therefore, it is beneficial to improve the stability of the gate driving signal output by the gating unit 30. Since the first-type voltage signal lines 61 are connected to the stage transmission unit, the signals thereon do not directly affect the stability of the gate driving signal. Therefore, the number of film layers occupied by the first-type fan-out lines S01 corresponding to the first-type voltage signal lines 61 can be less to save the wiring space.

[0152] In the embodiment of the present disclosure, the number of film layers occupied by at least one second fan-out line S02 corresponding to the second-type voltage signal lines 62 connected to the second output unit 32 of the gating unit 30 is n2, and the number of film layers occupied by at least one first fan-out line S01 corresponding to the first-type voltage signal lines 61 connected to the stage transmission unit 03 is n1, where n1 ≤ n2.

[0153] Please combine with Figure 4 and Figure 13 In an alternative embodiment of the present disclosure, the gating unit 30 includes a second control unit 31 and a second output unit 32. The second control unit 31 is configured to control the signal of the fifth node N5 at least according to the first voltage signal VGHA, the signal of the first node N1, the stage transmission signal NEXT, and the frequency control signal CTRL. The second output unit 32 is configured to output a gate driving signal at least according to the signal of the fifth node N5, the signal of the second node N2, and according to the fifth voltage signal VGHB or the seventh voltage signal VGHC. The fifth voltage signal VGHB, the seventh voltage signal VGHC, and the first voltage signal VGHA are signals of the same potential type. The first type of voltage signal line 61 includes a first voltage signal line 51 and a second voltage signal line 52. The second type of voltage signal line 62 includes a third voltage signal line 53 and a fourth voltage signal line 54. The third voltage signal line 53 is used to transmit the fifth voltage signal VGHB, and the fourth voltage signal line 54 is used to transmit the seventh voltage signal VGHC. The first type of fan-out line S01 includes a first fan-out line 91 and a second fan-out line 92. The second type of fan-out line S02 includes a third fan-out line 93 and a fourth fan-out line 94. The first fan-out line 91 is electrically connected to the first voltage signal line 51, the second fan-out line 92 is electrically connected to the second voltage signal line 52, the third fan-out line 93 is electrically connected to the third voltage signal line 53, and the fourth fan-out line 94 is electrically connected to the fourth voltage signal line 54.

[0154] Please combine with Figure 16 、 Figure 19 and Figure 20 The number of film layers occupied by the first fan-out line 91 in the display panel is n11, the number of film layers occupied by the second fan-out line 92 in the display panel is n12, the number of film layers occupied by the third fan-out line 93 in the display panel is n21, and the number of film layers occupied by the fourth fan-out line 94 in the display panel is n22. Wherein, n11 < n21, n11 < n22, and / or, n12 < n21, n12 < n22. Figure 16 The illustrated embodiment is described by taking n11 = 2 and n12 = 1 as an example, Figure 19 is described by taking n21 = n22 = 2 as an example, Figure 20 is described by taking n21 = n22 = 3 as an example.

[0155] In the present disclosure, the first voltage signal line 51 and the second voltage signal line 52 transmit voltage signals to the cells inside the shift register and do not transmit signals to the pixel driving circuit. The third voltage signal line 53 and the fourth voltage signal line 54 are voltage signal lines connected to the second output cell 32 in the shift register. When the third output module 311 in the second output cell 32 is turned on, the voltage signal in the third voltage signal line 53 or the fourth voltage signal line 54 will be output as a gate driving signal from the output terminal SN_OUT of the gating unit. Therefore, the stability of the voltage signals on the third voltage signal line 53 and the fourth voltage signal line 54 directly determines the stability of the gate driving signal transmitted to the pixel driving circuit. Thus, in this embodiment, when the number of film layers occupied by the third fan-out line 93 and the fourth fan-out line 94 corresponding to the third voltage signal line 53 and / or the fourth voltage signal line 54 is set to be greater than the number of film layers occupied by the first fan-out line 91 and the second fan-out line 92, it is beneficial to reduce the impedance of the third fan-out line 93 and / or the fourth fan-out line 94, thereby facilitating the reduction of the total impedance of the third fan-out line 93 and the third voltage signal line 53, and / or, reducing the total impedance of the fourth fan-out line 94 and the fourth voltage signal line 54. Therefore, it is beneficial to improve the stability of the voltage signals transmitted by the third voltage signal line 53 and the fourth voltage signal line 54, and is beneficial to improve the stability of the gate driving signal output by the shift register.

[0156] It should be noted that in the fan-out region, for fan-out lines with the same or approximately the same extending direction, the interval between adjacent fan-out lines can be set to be the same to simplify the wiring difficulty of the fan-out lines in the fan-out region.

[0157] In some other embodiments of the present disclosure, the intervals between at least some different fan-out lines can also be designed differently. For example, Figure 23 Shown is a layout schematic diagram of some signal lines in the fan-out region and the bending region. Please refer to Figure 23, optionally, the third fan-out line 93 and the fifth fan-out line 05 are respectively located on both sides of the fourth fan-out line 94 and are adjacent to the fourth fan-out line 94, and the interval width D01 between the third fan-out line 93 and the fourth fan-out line 94 is less than the interval width D02 between the fourth fan-out line 94 and the fifth fan-out line 95. Since the potential types of the voltage signals transmitted by the third fan-out line 93 and the fourth fan-out line 94 are the same, for example, both are high-potential signals, while the potential type of the voltage signal transmitted by the fifth fan-out line 95 is different from that of the fourth fan-out line 94. For example, the voltage signal transmitted by the fifth fan-out line 95 is a low-potential signal or an alternating current signal, while the voltage signal transmitted by the fourth fan-out line 94 is a high-potential signal. Therefore, in the present disclosure, when the third fan-out line 93 and the fourth fan-out line 94 are set to be relatively close, the signals between them will not affect each other, and when the fifth fan-out line 95 is set to be relatively far from the fourth fan-out line 94, it is beneficial to avoid the mutual coupling effect of their signals. A similar design is adopted for the interval relationship between the second lead 82, the third lead 83, and the fourth lead 84. The interval width D22 between the second lead 82 and the third lead 83 is less than the interval width D21 between the fourth lead 84 and the third lead 83, which is also beneficial to reducing the mutual coupling effect between different types of signals.

[0158] In the fan-out region Q1, the interval widths between at least some of the fan-out lines transmitting the same signal are the same. For example, the potential types and voltage values of the voltage signals transmitted by the first fan-out line 91, the second fan-out line 92, the third fan-out line 93, and the fourth fan-out line 94 are the same, for example, all are high-potential signals. At this time, the interval width D11 between the first fan-out line 91 and the second fan-out line 92 can be set to be equal to the interval width D01 between the third fan-out line 93 and the fourth fan-out line 94. Optionally, if the second fan-out line 92 is located between the first fan-out line 91 and the third fan-out line 93 and no other fan-out lines are provided between the second fan-out line 92 and the third fan-out line 93, assuming the interval width between the second fan-out line 92 and the third fan-out line 93 is D12, D12 = D11 = D01 can be further set. In this way, the fan-out lines transmitting the same signal can be arranged using the same interval standard, which is beneficial to simplifying the wiring difficulty in the fan-out region.

[0159] In the bending region Q2, the interval widths between at least some of the leads transmitting the same signal are the same. For example, the potential types and voltage values of the voltage signals transmitted by the first lead 81, the second lead 82, and the third lead 83 are the same, for example, all are high-potential. Then, the interval width D23 between the first lead 81 and the second lead 82 can be set to be equal to the interval width D22 between the second lead 82 and the third lead 83, which is also beneficial to simplifying the wiring difficulty in the bending region.

[0160] Based on the same inventive concept, the present disclosure also provides a display device. Figure 24The following is a schematic structural diagram of a display device 200 provided by an embodiment of the present disclosure. Please refer to Figure 24 , the display device 200 includes the display panel 100 in any of the above embodiments. The display device 200 provided by the embodiment of the present disclosure may be any electronic device with a display function, such as a touch display screen, a mobile phone, a tablet computer, a notebook computer, an e-reader, or a television. The display device 200 provided by the embodiment of the present disclosure has the beneficial effects of the display panel provided by the embodiment of the present disclosure. For specific descriptions of the display panel, reference may be made to the above embodiments, and details are not described herein again.

[0161] It can be understood that Figure 24 , only a rounded rectangle structure is taken as an example to illustrate a shape of the display device 200. In some other embodiments of the present disclosure, the display device 200 may also be embodied as a circular shape, an oval shape, or any other feasible shape, and the present disclosure does not specifically limit this.

[0162] In summary, the technical solutions provided by the embodiments of the present disclosure have the following advantages:

[0163] In the display panel and the display device provided by the embodiments of the present disclosure, the first voltage signal corresponding to the first control unit in the shift register is transmitted by the first voltage signal line, and the third voltage signal corresponding to the first output unit is transmitted by the second voltage signal line. The potential types of the first voltage signal and the third voltage signal are the same, that is, both are high-potential signals or both are low-potential signals, but they are transmitted by different voltage signal lines. When the coupling of the clock signal affects the first voltage signal, since the third voltage signal is transmitted by the second signal line, the third voltage signal will not be affected by the coupling of the clock signal. When the stage transmission signal output by the first output unit is the third voltage signal, the third voltage signal is a stable voltage signal transmitted by the second signal line, which can accurately control the selection unit. Therefore, the embodiment of the present disclosure introduces different voltage signal lines for the first control unit and the first output unit to transmit the first voltage signal and the third voltage signal with the same potential type, which is beneficial to improving the transmission accuracy of the stage transmission signal, and further beneficial to improving the accuracy of the gate driving signal output by the gate driving circuit.

[0164] It should be noted that in this document, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variation thereof is intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the said element.

[0165] The above are only specific embodiments of the present disclosure, enabling those skilled in the art to understand or implement the present disclosure. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments described herein, but rather to the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that, Comprising: A gate driving circuit, the gate driving circuit including N cascaded shift registers, N≥2 and N being an integer; The shift register includes a stage transmission unit and a gating unit connected to the stage transmission unit, the stage transmission unit including a first control unit and a first output unit; The first control unit is configured to control the signals of a first node and a second node at least according to a first voltage signal, a second voltage signal, a first clock signal, and a second clock signal; The first output unit is configured to output a stage transmission signal at least according to the signal of the first node, the signal of the second node, a third voltage signal, and a fourth voltage signal; the stage transmission signal of the i-th stage shift register serves as an input signal of the j-th stage shift register, 1≤i≤N, 1≤j≤N, i≠j, and both i and j are integers; The gating unit is configured to output a gate driving signal at least according to the stage transmission signal and a frequency control signal; The display panel includes voltage signal lines, the voltage signal lines including a first voltage signal line and a second voltage signal line, the first voltage signal line being used for transmitting the first voltage signal, and the second voltage signal line being used for transmitting the third voltage signal; the potential types of the first voltage signal and the third voltage signal are the same.

2. The display panel according to claim 1, wherein Among the N cascaded shift registers, the first control units in different shift registers are connected to the same first voltage signal line.

3. The display panel according to claim 1, characterized in that, Among the cascaded shift registers, the first output units in different shift registers are connected to the same second voltage signal line.

4. The display panel according to claim 1, wherein The voltage values of the first voltage signal and the third voltage signal are the same.

5. The display panel according to claim 1, characterized in that, The second voltage signal and the fourth voltage signal are signals with the same voltage value and are provided by the same voltage signal line.

6. The display panel according to claim 1, wherein The display panel includes a display area and a first non-display area located on one side of the display area along a first direction, the first non-display area including a fan-out area and a bending area, the fan-out area being located between the bending area and the display area; The fan-out area includes a first fan-out line and a second fan-out line, the first fan-out line being electrically connected to the first voltage signal line, and the second fan-out line being electrically connected to the second voltage signal line; the bending area includes a first lead, and the first fan-out line and the second fan-out line are electrically connected to the same first lead.

7. The display panel according to claim 6, wherein The ends of the first fan-out line and the second fan-out line far from the display area are electrically connected through a first connection portion, and the first connection portion is located in the fan-out area.

8. The display panel according to claim 6, wherein The first fan-out line and the second fan-out line are located in different film layers.

9. The display panel according to claim 8, wherein, The first fan-out line includes a first sub-line and a second sub-line that are electrically connected, and the first sub-line and the second sub-line are arranged in different layers.

10. The display panel according to claim 6, wherein The first non-display area includes a pad area, the pad area being located on the side of the bending area far from the display area, the pad area including a plurality of bonding pads, the bonding pads including a first bonding pad; the first lead is electrically connected to the first bonding pad.

11. The display panel according to claim 1, wherein, The gating unit includes a second control unit and a second output unit. The second control unit is configured to control the signal of a fifth node at least based on the first voltage signal, the signal of the first node, the stage transmission signal, and the frequency control signal. The second output unit is configured to output the gate driving signal at least based on the signals of the fifth node and the second node.

12. The display panel according to claim 11, wherein The N cascaded shift registers include a first shift register and a second shift register. The second output unit of the first shift register is configured to output the gate driving signal based on a fifth voltage signal, a sixth voltage signal, and the signal of the second node. The second output unit of the second shift register is configured to output the gate driving signal based on a seventh voltage signal, the sixth voltage signal, and the signal of the second node. The fifth voltage signal, the seventh voltage signal, and the third voltage signal are signals of the same potential type. The sixth voltage signal, the fourth voltage signal, and the second voltage signal are signals of the same potential type.

13. The display panel according to claim 12, wherein The voltage values of the fifth voltage signal, the seventh voltage signal, the third voltage signal, and the first voltage signal are the same; and / or, the voltage values of the sixth voltage signal, the fourth voltage signal, and the second voltage signal are the same.

14. The display panel according to claim 12, wherein The fifth voltage signal, the seventh voltage signal, the third voltage signal, and the first voltage signal are high-potential signals.

15. The display panel according to claim 12, characterized in that, The sixth voltage signal, the fourth voltage signal, and the second voltage signal are low-potential signals.

16. The display panel according to claim 12, wherein The first shift register is located at an odd stage, and the second shift register is located at an even stage; or, the first shift register is located at an even stage, and the second shift register is located at an odd stage.

17. The display panel according to claim 12, wherein The voltage signal line further includes a third voltage signal line and a fourth voltage signal line. The third voltage signal line is used to transmit the fifth voltage signal, and the fourth voltage signal line is used to transmit the seventh voltage signal.

18. The display panel according to claim 17, wherein The display panel includes a display area and a first non-display area located on one side of the display area along a first direction. The first non-display area includes a fan-out area and a bending area. The fan-out area is located between the bending area and the display area. The fan-out area includes a third fan-out line and a fourth fan-out line. The third fan-out line is electrically connected to the third voltage signal line, and the fourth fan-out line is electrically connected to the fourth voltage signal line. The bending area includes a second lead and a third lead. The second lead is electrically connected to the third fan-out line, and the third lead is electrically connected to the fourth fan-out line.

19. The display panel according to claim 18, characterized in that, The third fan-out line includes at least two sub-fan-out lines located in different metal layers and electrically connected. The fourth fan-out line includes at least two sub-fan-out lines located in different metal layers and electrically connected.

20. The display panel according to claim 18, wherein, The first non-display area includes a pad area. The pad area is located on the side of the bending area away from the display area. The pad area includes a plurality of bonding pads. The bonding pads include a second bonding pad. The second lead and the third lead are electrically connected to the same second bonding pad.

21. The display panel according to claim 1, wherein The gating unit is configured to output the gate driving signal at least according to the stage transmission signal, the frequency control signal, and a sixth voltage signal, where the sixth voltage signal and the second voltage signal are signals of the same potential type, and / or the sixth voltage signal and the fourth voltage signal are signals of the same potential type; The voltage signal lines further include a fifth voltage signal line and a sixth voltage signal line. The fifth voltage signal line is configured to transmit at least one of the second voltage signal and the fourth voltage signal, and the sixth voltage signal line is configured to transmit the sixth voltage signal.

22. The display panel according to claim 21, wherein The display panel includes a display area and a first non-display area located on one side of the display area along a first direction. The first non-display area includes a fan-out area and a bending area, and the fan-out area is located between the bending area and the display area; The fan-out area includes a fifth fan-out line, and the bending area includes a fourth lead. The fifth voltage signal line and the sixth voltage signal line are connected to the same fifth fan-out line, and the fifth fan-out line is electrically connected to the fourth lead.

23. The display panel according to claim 22, wherein, The fifth voltage signal line and the sixth voltage signal line are electrically connected through a second connection portion, and the second connection portion is located on a side of the fan-out area away from the bending area.

24. The display panel according to claim 22, wherein The fifth fan-out line includes at least two sub-fan-out lines located in different metal layers and electrically connected.

25. The display panel according to claim 1, wherein, The voltage signal lines include a first type of voltage signal line and a second type of voltage signal line. The first type of voltage signal line is electrically connected to at least the stage transmission unit, and the second type of voltage signal line is electrically connected to the gating unit; The display panel includes a display area and a first non-display area located on one side of the display area along a first direction. The first non-display area includes a fan-out area; the fan-out area includes a first type of fan-out line and a second type of fan-out line. The first type of fan-out line is electrically connected to the first type of voltage signal line, and the second type of fan-out line is electrically connected to the second type of voltage signal line; The number of film layers occupied by at least one of the first type of fan-out lines in the display panel is n1, and the number of film layers occupied by at least one of the second type of fan-out lines in the display panel is n2, where n1 ≤ n2.

26. The display panel according to claim 25, wherein The gating unit includes a second control unit and a second output unit. The second control unit is configured to control the signal of a fifth node at least according to the first voltage signal, the signal of the first node, the stage transmission signal, and the frequency control signal. The second output unit is configured to output the gate driving signal at least according to the fifth node, the signal of the second node, and according to the fifth voltage signal or the seventh voltage signal; the fifth voltage signal, the seventh voltage signal, and the first voltage signal are signals of the same potential type; The first type of voltage signal line includes the first voltage signal line and the second voltage signal line. The second type of voltage signal line includes a third voltage signal line and a fourth voltage signal line. The third voltage signal line is configured to transmit the fifth voltage signal, and the fourth voltage signal line is configured to transmit the seventh voltage signal; The first type of fan-out lines includes a first fan-out line and a second fan-out line, the second type of fan-out lines includes a third fan-out line and a fourth fan-out line, the first fan-out line is electrically connected to the first voltage signal line, the second fan-out line is electrically connected to the second voltage signal line, the third fan-out line is electrically connected to the third voltage signal line, and the fourth fan-out line is electrically connected to the fourth voltage signal line; The number of film layers occupied by the first fan-out line in the display panel is n11, the number of film layers occupied by the second fan-out line in the display panel is n12, the number of film layers occupied by the third fan-out line in the display panel is n21, and the number of film layers occupied by the fourth fan-out line in the display panel is n22, where n11 < n21, n11 < n22, and / or n12 < n21, n12 < n22.

27. A display device, characterized in that, A display panel according to any one of claims 1 to 26.

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