Wafer-level inductor packaging structure and preparation method thereof

Abstract

The invention provides a wafer level inductor packaging structure and a preparation method thereof, the packaging structure comprises an intermediate layer, an electromagnetic bump, plastic packaging bodies, a plastic packaging part and a third functional chip, the number of the plastic packaging bodies is two, and the plastic packaging bodies are vertically arranged on the front surface of the intermediate layer after rotating by 90 degrees and are symmetrically arranged on the two sides of the electromagnetic bump; enabling the first left side wall metal layer and the second left side wall metal layer to face the front surface of the interposer, wherein the first left side wall metal layer and the second left side wall metal layer in the plastic package body are electrically connected with the electromagnetic bump through the interposer; the plastic package part wraps the two plastic package bodies and the electromagnetic bump; and the third functional chip is integrated on the surfaces of the first right side wall metal layer and the second right side wall metal layer. According to the wafer-level inductor packaging structure provided by the invention, high-density integration of six chips in a limited space is realized, the packaging size is remarkably reduced, and the preparation method is simple.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and more particularly to a wafer-level inductor packaging structure and a preparation method thereof. Background Art

[0002] In the current semiconductor industry, electronic packaging technology has become an indispensable and important aspect driving the development of the entire industry. After decades of continuous evolution, packaging technology has made great progress, making the requirements for high-density and high-performance packaging gradually become the mainstream development trend in the packaging field.

[0003] Fan-out wafer-level packaging technology, as an embedded packaging form realized in the wafer-level processing process, not only represents a major innovation in packaging technology, but also is a main advanced packaging process with a high I / O number and excellent integration flexibility. With its unique technical advantages, it is playing an increasingly important role in meeting the requirements of modern electronic products for high performance and miniaturization.

[0004] In the current packaging technology field, in order to achieve high-level system integration and high-density interconnection, thereby meeting the increasingly complex functional requirements of semiconductor electronic products, improving product performance, increasing packaging density, and enhancing the electrical performance transmission efficiency have become the most critical and influential technical solutions for high-end semiconductor products. These technical solutions not only represent the latest development achievements of semiconductor packaging technology, but also are the technical difficulties that current semiconductor manufacturers are competing to invest in research and development resources to overcome. They lead the direction of contemporary semiconductor research and provide a powerful driving force for the continuous progress and innovation of the semiconductor industry.

[0005] Existing wafer-level inductor packages are mostly planar inductor structures, where planar spiral coils are fabricated on the wafer through wafer-level lithography and electroplating processes, or high magnetic permeability materials are used between layers. This method and structure are limited by area, and it is difficult to increase the inductance and dissipate heat. Summary of the Invention

[0006] To solve the above problems, the present invention provides a high-density wafer-level inductor packaging structure and a preparation method thereof, which is a wafer-level inductor packaging structure capable of increasing the inductance and having excellent heat dissipation performance.

[0007] In a first aspect, the present invention discloses a wafer-level inductor packaging structure, which includes: An interposer, having a front surface and a back surface, for support and electrical connection; Electromagnetic bumps, disposed on the front surface of the interposer; Plastic package body, having a substrate wafer, a first functional chip disposed on the front surface of the substrate wafer, and a second functional chip disposed on the back surface of the substrate wafer. A plurality of through-silicon vias are provided in the substrate wafer, and the first functional chip and the second functional chip are connected through the through-silicon vias. The first functional chip has a first left-side wall metal layer and a first right-side wall metal layer for external electrical connection, and the second functional chip has a second left-side wall metal layer and a second right-side wall metal layer for external electrical connection. There are two plastic package bodies, which are vertically disposed on the front surface of the interposer after being rotated 90 degrees and are symmetrically arranged on both sides of the electromagnetic bump, so that the first left-side wall metal layer and the second left-side wall metal layer face the front surface of the interposer, and the first left-side wall metal layer and the second left-side wall metal layer in the plastic package body are electrically connected to the electromagnetic bump through the interposer; Plastic encapsulation part, formed on the front surface of the interposer, covering two plastic package bodies and the electromagnetic bump, and the surfaces of the first right-side wall metal layer and the second right-side wall metal layer of the two plastic package bodies are exposed; a second redistribution metal layer is formed on the surfaces of the first right-side wall metal layer and the second right-side wall metal layer; A third functional chip, integrated on the surfaces of the first right-side wall metal layer and the second right-side wall metal layer of the two plastic package bodies, is electrically connected to the first right-side wall metal layer and the second right-side wall metal layer through the second redistribution metal layer, forming a wafer-level inductance package structure.

[0008] Preferably, solder balls are provided on the back surface of the interposer for electrical connection with an external circuit.

[0009] Preferably, the interposer is a structure of a mixture of an organic dielectric and a redistribution metal layer.

[0010] Preferably, the electromagnetic bump is made of NiFe material with electromagnetic properties.

[0011] Preferably, the first functional chip and the second functional chip are memory chips with a storage function; the third functional chip is a chip with an SOC processor.

[0012] In a second aspect, the present invention also provides a preparation method of the above wafer-level inductance package structure, which includes the following steps: S1. Provide an interposer, which has a front surface and a back surface, and the front surface of the interposer has a first redistribution metal layer for electrical connection; S2. Electroplate NiFe material with electromagnetic properties on the surface of the first redistribution metal layer to form an electromagnetic bump; S3. Provide two plastic package bodies with the same structure, which are vertically disposed on the first redistribution metal layer on the front surface of the interposer after being rotated 90 degrees and are symmetrically arranged on both sides of the electromagnetic bump; the preparation method of the plastic package body is as follows: A. Provide a substrate wafer having a plurality of through-silicon vias, connect a first functional chip to the front surface of the substrate wafer, and connect a second functional chip to the back surface of the substrate wafer; B. On both side walls of the first functional chip, a first left side wall metal layer and a first right side wall metal layer for external electrical connection are formed, and on both side walls of the second functional chip, a second left side wall metal layer and a second right side wall metal layer for external electrical connection are formed; Among them, after the plastic package rotates 90 degrees, the first left side wall metal layer and the second left side wall metal layer in the plastic package face the front of the interposer, and the first left side wall metal layer and the second left side wall metal layer are electrically connected to the electromagnetic bumps through the first redistribution metal layer; S4. Plastic package the front of the interposer, and the plastic encapsulation material covers the two plastic packages and the electromagnetic bumps to form a plastic encapsulation part. Grind the top of the plastic encapsulation part to expose the surfaces of the first right side wall metal layer and the second right side wall metal layer of the plastic package; S5. Form a second redistribution metal layer on the surfaces of the first right side wall metal layer and the second right side wall metal layer, connect a third functional chip on the surface of the second redistribution metal layer, and perform a ball mounting process on the back of the interposer to form solder balls, thus completing the preparation of the wafer-level inductance packaging structure.

[0013] Preferably, an introduction to the first functional chip / the second functional chip / the third functional chip.

[0014] Preferably, the plastic encapsulation material is an epoxy plastic encapsulation material.

[0015] Preferably, the interposer is a glass interposer or a silicon interposer.

[0016] Compared with the prior art, the beneficial effects of the present invention are: 1. In the plastic package of the present invention, dual-sided functional chip integration is realized, with high integration degree, making the packaging volume and floor area smaller; the first functional chip and the second functional chip are directly interconnected through the through-silicon vias of the substrate wafer, reducing the interconnection length, significantly reducing the transmission delay of signals between the first functional chip and the second functional chip, and improving the connection stability; 2. After rotating the plastic package 90 degrees, it is vertically arranged on the front of the interposer, and together with the third functional chip on the top around the electromagnetic bumps, a vertical chip inductive 3D packaging structure is realized, enhancing the performance of the inductive packaging structure; 3. The wafer-level inductive packaging structure provided by the present invention realizes the high-density integration of 6 chips in a limited space, significantly reducing the packaging size, and the preparation method is simple; 4. Compared with the traditional planar inductor, the three-dimensional inductor structure provided by the present invention increases the effective magnetic flux linkage by expanding the vertical dimension of the magnetic flux path, thereby increasing the inductance; 5. In the wafer-level inductive packaging structure provided by the present invention, each functional chip can achieve effective heat dissipation. Description of the Drawings

[0017] Figure 1 Schematic diagram of the wafer-level inductance packaging structure in Embodiment 1 of the present invention; Figure 2 Schematic diagram of the structure of the glass interposer in Embodiment 2 of the present invention; Figure 3 For Figure 2 Schematic diagram of the structure with electromagnetic bumps electroplated in the structure shown; Figure 4 Schematic diagram of the structure of the plastic package in Embodiment 2 of the present invention; Figure 5 Schematic diagram of the structure of the substrate wafer in Embodiment 2 of the present invention; Figure 6 For Figure 5 Schematic diagram of bonding the first functional chip in the structure shown; Figure 7 For Figure 3 Schematic diagram of the structure with the plastic package rotated 90 degrees connected in the structure shown; Figure 8 For Figure 7 Schematic diagram of the structure after plastic packaging the structure shown.

[0018] Label description: Interposer - 1; Front side - 101; Back side - 102; First redistribution metal layer - 103; Glass wafer - 104; Electromagnetic bump - 2; Plastic package - 3; Substrate wafer - 31; Through-silicon via - 310; First functional chip - 32; Second functional chip - 33; First left sidewall metal layer - 320; First right sidewall metal layer - 321; Second left sidewall metal layer - 330; Second right sidewall metal layer - 331; Plastic packaging part - 4; Second redistribution metal layer - 5; Third functional chip - 6; Solder ball - 7. Detailed implementation manners

[0019] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments.

[0020] Embodiment 1 As Figure 1 shown, this embodiment discloses a wafer-level inductance packaging structure, which includes: An interposer 1, having a front side 101 and a back side 102, for support and electrical connection; An electromagnetic bump 2, disposed on the front side 101 of the interposer 1; The plastic package body 3 has a substrate wafer 31, a first functional chip 32 disposed on the front surface of the substrate wafer 31, and a second functional chip 33 disposed on the back surface of the substrate wafer 31. A plurality of through-silicon vias 310 are provided in the substrate wafer 31, and the first functional chip 32 and the second functional chip 33 are connected through the through-silicon vias 310. The first functional chip 32 further has a first left-side wall metal layer 320 and a first right-side wall metal layer 321 for external electrical connection, and the second functional chip 33 has a second left-side wall metal layer 330 and a second right-side wall metal layer 331 for external electrical connection. There are two plastic package bodies 3, which are vertically disposed on the front surface 101 of the interposer 1 after being rotated 90 degrees and symmetrically arranged on both sides of the electromagnetic bump 2, so that the first left-side wall metal layer 320 and the second left-side wall metal layer 330 face the front surface 101 of the interposer 1, and the first left-side wall metal layer 320 and the second left-side wall metal layer 330 in the plastic package body 3 are electrically connected to the electromagnetic bump 2 through the interposer 1; The plastic encapsulation part 4 is formed on the front surface 101 of the interposer 1, covering the two plastic package bodies 3 and the electromagnetic bump 2, and the surfaces of the first right-side wall metal layer 321 and the second right-side wall metal layer 331 of the two plastic package bodies 3 are exposed; a second redistribution metal layer 5 is formed on the surfaces of the first right-side wall metal layer 321 and the second right-side wall metal layer 331; The third functional chip 6 is integrated on the surfaces of the first right-side wall metal layer 321 and the second right-side wall metal layer 331 of the two plastic package bodies 3 and is electrically connected to the first right-side wall metal layer 321 and the second right-side wall metal layer 331 through the second redistribution metal layer 5. Solder balls 7 are provided on the back surface 102 of the interposer 1, forming a wafer-level inductance package structure.

[0021] Among them, the interposer 1 has a structure of a mixture of an organic medium and a redistribution metal layer. This structure is a PI / RDL structure, where PI is polyimide and RDL refers to the redistribution metal layer. The PI / RDL structure in this embodiment can be a multi-layer interposer 1 structure formed by alternating one layer of PI and one layer of metal. The advantage of the PI / RDL structure is small size and good performance. For the detailed PI / RDL structure, refer to the relevant records in the prior art, and it will not be specifically elaborated in this embodiment.

[0022] In this embodiment, the first functional chip 32 and the second functional chip 33 are memory chips with a storage function; the third functional chip 6 is a chip with an SOC processor.

[0023] During specific implementation, the distance between the plastic package body 3 and the electromagnetic bump 2 is greater than 100 microns.

[0024] During specific implementation, each of the two plastic package bodies 3 can be connected to a third functional chip 6, or they can be commonly connected to a third functional chip 6, which is not limited herein.

[0025] In this embodiment, through the solder balls 7 on the back surface 102 of the interposer 1, other circuits can be connected. The wafer-level inductance packaging structure provided by the present invention realizes the high-density integration of 6 chips in a limited space, significantly reducing the packaging size.

[0026] In this embodiment, after rotating the plastic package 3 by 90 degrees, it is vertically arranged on the front surface 101 of the interposer 1, and together with the third functional chip 6 at the top, around the electromagnetic bump 2, a vertical-chip inductance 3D packaging structure is realized, enhancing the performance of the inductance packaging structure.

[0027] Embodiment 2 This embodiment provides a preparation method for the wafer-level inductance packaging structure described in Embodiment 1, which includes the following steps: S1. Provide an interposer 1, the interposer 1 has a front surface 101 and a back surface 102, and the front surface 101 of the interposer 1 has a first redistribution metal layer 103 for electrical connection.

[0028] S2. Electroplate a NiFe material with electromagnetic properties on the surface of the first redistribution metal layer 103 to form an electromagnetic bump 2; the electromagnetic bump 2 is used to form an inductance structure subsequently.

[0029] S3. Provide two plastic packages 3 with the same structure. After rotating the plastic package 3 by 90 degrees, it is vertically arranged on the first redistribution metal layer 103 of the front surface 101 of the interposer 1 and symmetrically arranged on both sides of the electromagnetic bump 2; Among them, after rotating the plastic package 3 by 90 degrees, the first left-side wall metal layer 320 and the second left-side wall metal layer 330 in the plastic package 3 face the front surface 101 of the interposer 1, and the first left-side wall metal layer 320 and the second left-side wall metal layer 330 are electrically connected to the electromagnetic bump 2 through the first redistribution metal layer 103; forming a structure as Figure 7 shown. In this step, creatively, part of the I / O interfaces of the first functional chip and the second functional chip are set to the side walls at both ends of the chip through redistribution.

[0030] S4. Plastic package the front surface 101 of the interposer 1, and the plastic packaging material covers the two plastic packages 3 and the electromagnetic bump 2 to form a plastic packaging part 4, forming a structure as Figure 8 shown; the plastic packaging part 4 can protect each chip from the external environment and can also ensure reliable electrical connection between each chip and the interposer 1. The plastic packaging material is an epoxy plastic packaging material.

[0031] S5. Grind the top of the plastic encapsulation part 4 to expose the surfaces of the first right-side wall metal layer 321 and the second right-side wall metal layer 331 of the plastic encapsulation body 3. Form a second redistribution metal layer 5 on the surfaces of the first right-side wall metal layer 321 and the second right-side wall metal layer 331, and connect the third functional chip 6 on the surface of the second redistribution metal layer 5. Grind the glass wafer 104 of the interposer 1 to expose the bottom surface of the first redistribution metal layer 103, and perform a ball mounting process on the back surface 102 of the interposer 1 (i.e., the bottom surface of the first redistribution metal layer 103) to form solder balls 7, obtaining the Figure 1 wafer-level inductance packaging structure shown.

[0032] In step S1, the interposer 1 can be a glass interposer or a silicon interposer. In this embodiment, taking the glass interposer as an example, apply a release layer glue (bonding glue) on the glass wafer 104 shown in Figure 2 , and then form the first redistribution metal layer 103 through processes such as sputtering, photolithography, electroplating, and cleaning, which is used to connect the vertical plastic encapsulation body 3 and the electromagnetic bump 2.

[0033] The structure of the electromagnetic bump 2 electroplated on the surface of the first redistribution metal layer 103 is as shown in Figure 3 .

[0034] In step S3, the structure of the plastic encapsulation body 3 is as shown in Figure 4 , which needs to be prepared in advance. The preparation method is as follows: A. Provide a substrate wafer 31 with multiple through-silicon vias 310 TSVs, and perform a CopperReveal (copper exposure process) on the substrate wafer 31, such as fine steps like Si Etch (silicon etching), PECVD (plasma-enhanced chemical vapor deposition), CMP (chemical mechanical polishing), etc., to expose the silicon surface. Immerse the processed wafer in an electroplating solution containing copper, nickel, gold, etc. ions. Under the action of current, copper ions are reduced to metallic copper and deposited on specific areas of the wafer to form metal bumps, and then perform plasma cleaning to remove the residual electroplating solution and impurities on the surface, forming the structure shown in Figure 5 ; Under high temperature and high pressure conditions, bond multiple first functional chips 32 to the front surface of the substrate wafer 31 through metal bumps to form the structure shown in Figure 6The structure shown uses a single first functional chip 32 as an example in the figure. During the bonding process, the temperature and pressure need to be precisely controlled to ensure the bonding quality and efficiency. After bonding, visual inspection and solder joint testing are required to ensure the bonding quality. Preheating and baking the first functional chip 32 can facilitate the fluidity of the underfill. Use a dispensing machine to apply the bottom underfill to the designated position of the first functional chip 32 according to the setting. Utilize the capillary effect to make the bottom underfill naturally spread and fill the gap between the first functional chip 32 and the substrate wafer 31, and ensure uniform filling without omission. Place the filled first functional chip 32 into a heating device for high-temperature baking to accelerate the glue curing process. Using the same method, connect the second functional chip 33 to the back of the substrate wafer 31; finally, use a dicing machine to cut it into single pieces to form the plastic package body 3 structure as shown in Figure 4 shown.

[0035] B. On both side walls at the two ends of the cut first functional chip 32, a first left side wall metal layer 320 and a first right side wall metal layer 321 for external electrical connection are formed. On both side walls at the two ends of the second functional chip 33, a second left side wall metal layer 330 and a second right side wall metal layer 331 for external electrical connection are formed; among them, when designing the RDL for the first functional chip 32 and the second functional chip 33, it will be made beyond the chip boundary on the dicing channel, and when diced into single pieces, chips with metal side walls will be formed. Other technical solutions that can form metal layers on the side walls are also acceptable.

[0036] Place two plastic package bodies 3 with the same structure. After rotating the plastic package body 3 by 90 degrees, vertically set it on the first redistribution metal layer 103 on the front side 101 of the interposer 1, and symmetrically set it on both sides of the electromagnetic bump 2; After rotating the plastic package body 3 by 90 degrees, the first left side wall metal layer 320 and the second left side wall metal layer 330 in the plastic package body 3 face the front side 101 of the interposer 1, and the first left side wall metal layer 320 and the second left side wall metal layer 330 are electrically connected to the electromagnetic bump 2 through the first redistribution metal layer 103.

[0037] The plastic package body 3 in this embodiment realizes the integration of double-sided functional chips, has a high integration degree, makes the package volume and floor area smaller; the first functional chip 32 and the second functional chip 33 are directly interconnected through the through-silicon vias 310 of the substrate wafer 31, reducing the interconnection length, significantly reducing the transmission delay of signals between the first functional chip 32 and the second functional chip 33, and improving the connection stability.

[0038] The above are only some embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the creative concept of the present invention, other deformations and improvements can still be made, and these all belong to the protection scope of the present invention.

Claims

1. A wafer-level inductive packaging structure, characterized in that Comprising: An interposer layer having a front side and a back side for support and electrical connection; Electromagnetic bumps disposed on the front side of the interposer layer; Two molding bodies, each having a substrate wafer, a first functional chip disposed on the front side of the substrate wafer, and a second functional chip disposed on the back side of the substrate wafer. A plurality of through-silicon vias are provided in the substrate wafer, and the first functional chip and the second functional chip are connected through the through-silicon vias. The first functional chip has a first left sidewall metal layer and a first right sidewall metal layer for external electrical connection, and the second functional chip has a second left sidewall metal layer and a second right sidewall metal layer for external electrical connection. The two molding bodies are rotated 90 degrees and vertically disposed on the front side of the interposer layer and symmetrically arranged on both sides of the electromagnetic bumps, so that the first left sidewall metal layer and the second left sidewall metal layer face the front side of the interposer layer. The first left sidewall metal layer and the second left sidewall metal layer in the molding bodies are electrically connected to the electromagnetic bumps through the interposer layer; A molding portion formed on the front side of the interposer layer to cover the two molding bodies and the electromagnetic bumps, and the surfaces of the first right sidewall metal layer and the second right sidewall metal layer of the two molding bodies are exposed; Form a second redistribution metal layer on the surfaces of the first right sidewall metal layer and the second right sidewall metal layer; A third functional chip integrated on the surfaces of the first right sidewall metal layer and the second right sidewall metal layer of the two molding bodies and electrically connected to the first right sidewall metal layer and the second right sidewall metal layer through the second redistribution metal layer, forming a wafer-level inductance packaging structure.

2. The wafer-level inductive packaging structure according to claim 1, wherein, Solder balls are provided on the back side of the interposer layer for electrical connection with an external circuit.

3. The wafer-level inductive packaging structure according to claim 2, wherein The interposer layer has a structure of a mixture of an organic dielectric and a redistribution metal layer.

4. The wafer-level inductive packaging structure according to claim 3, characterized in that, The electromagnetic bumps are made of NiFe material with electromagnetic properties.

5. The wafer-level inductive packaging structure according to claim 4, wherein, The first functional chip and the second functional chip are memory chips with a storage function; the third functional chip is a chip with an SOC processor.

6. The manufacturing method of the wafer-level inductance packaging structure according to any one of claims 1-5, characterized in that, Including the following steps: S1. Provide an interposer layer having a front side and a back side. The front side of the interposer layer has a first redistribution metal layer for electrical connection; S2. Electroplate NiFe material with electromagnetic properties on the surface of the first redistribution metal layer to form electromagnetic bumps; S3. Provide two identical molding bodies. The molding bodies are rotated 90 degrees and vertically disposed on the first redistribution metal layer on the front side of the interposer layer and symmetrically arranged on both sides of the electromagnetic bumps. The preparation method of the molding bodies is as follows: A. Provide a substrate wafer having a plurality of through-silicon vias, connect a first functional chip to the front side of the substrate wafer, and connect a second functional chip to the back side of the substrate wafer; B. Form a first left sidewall metal layer and a first right sidewall metal layer for external electrical connection on both sidewalls of the first functional chip, and form a second left sidewall metal layer and a second right sidewall metal layer for external electrical connection on both sidewalls of the second functional chip; Wherein, after the molding body is rotated 90 degrees, the first left sidewall metal layer and the second left sidewall metal layer in the molding body face the front side of the interposer layer, and the first left sidewall metal layer and the second left sidewall metal layer are electrically connected to the electromagnetic bumps through the first redistribution metal layer; S4. On the front side of the encapsulation interposer, encapsulation material wraps two encapsulation bodies and electromagnetic bumps to form an encapsulation part, and the top of the encapsulation part is ground to expose the surfaces of the metal layers on the first right side wall and the second right side wall of the encapsulation body; S5. A second redistribution metal layer is formed on the surfaces of the metal layers on the first right side wall and the second right side wall, a third functional chip is connected to the surface of the second redistribution metal layer, and a ball mounting process is performed on the back side of the interposer to form solder balls, completing the preparation of the wafer-level inductor packaging structure.

7. The preparation method according to claim 6, characterized in that, Introduction of the first functional chip / second functional chip / third functional chip.

8. The preparation method according to claim 7, characterized in that, The encapsulation material is epoxy encapsulation material.

9. The preparation method according to claim 8, characterized in that, The interposer is a glass interposer or a silicon interposer.

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