Memory, manufacturing method thereof and memory system

Abstract

The invention provides a memory, a manufacturing method thereof and a memory system. The manufacturing method of the memory comprises the following steps: forming an active column array in a virtual region and a memory region; the active column array comprises a plurality of active columns which are arranged in an array along a first direction and a second direction; the virtual area and the storage area are arranged along a first direction, and the active column extends along a third direction; the first direction and the second direction intersect and are perpendicular to the third direction; forming a plurality of first conductive parts in the virtual region and the storage region; the plurality of first conductive parts are arranged along a first direction, extend along a second direction and are positioned between the adjacent active columns along the first direction; forming a second conductive part and a first conductive shielding structure in each of the virtual region and the storage region; the second conductive parts and the first conductive shielding structures extend in the first direction and are alternately arranged in the second direction, the second conductive parts are connected with one ends of the active columns, and the first conductive parts in the virtual regions are connected with the first conductive shielding structures.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, for example, to a memory, a manufacturing method thereof, and a memory system. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a common storage device, which has the characteristics of high integration, fast read / write speed, low cost, etc., and is widely used in various consumer electronic products, such as computers, mobile phones, set-top boxes, etc.

[0003] However, there are still many problems to be solved in dynamic random access memory. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a memory, a manufacturing method thereof, and a memory system to solve at least one problem existing in the prior art.

[0005] In a first aspect, an embodiment of the present disclosure provides a manufacturing method of a memory, including:

[0006] Forming an active pillar array in a virtual area and a storage area; the active pillar array includes a plurality of active pillars arranged in an array along a first direction and a second direction; the virtual area and the storage area are arranged along the first direction, and the active pillars extend along a third direction; the first direction intersects with the second direction and is perpendicular to the third direction;

[0007] Forming a plurality of first conductive parts in the virtual area and the storage area; the plurality of first conductive parts are arranged along the first direction, and the first conductive parts extend along the second direction and are located between adjacent active pillars along the first direction;

[0008] Forming a second conductive part and a first conductive shielding structure in both the virtual area and the storage area; the second conductive part and the first conductive shielding structure both extend along the first direction and are alternately arranged along the second direction, the second conductive part is connected to one end of the active pillar, and the first conductive part in the virtual area is connected to the first conductive shielding structure.

[0009] In an optional embodiment, the forming of the active pillar array includes:

[0010] Providing a substrate;

[0011] Etching the substrate to form a plurality of first trenches arranged at intervals along the second direction; the first trenches extend along the first direction and the bottom is located in the substrate;

[0012] Forming a first dielectric layer in the first trenches;

[0013] Etch the substrate and the first dielectric layer to form second trenches and third trenches arranged alternately along the first direction; wherein, both the second trenches and the third trenches extend along the second direction and the bottoms are located in the substrate, and the depths of the second trenches and the third trenches are less than the depth of the first trench; the first trench, the second trench, and the third trench divide the substrate into a plurality of the active columns.

[0014] In an optional implementation manner, the method further includes:

[0015] Form a second conductive shielding structure in the second trench; the second conductive shielding structure located in the virtual region is connected to the first conductive shielding structure.

[0016] In an optional implementation manner, the forming the second conductive shielding structure in the second trench includes:

[0017] Form a second conductive shielding material layer covering the sidewalls of the second trench in the second trench from the first side of the active column;

[0018] Etch the second conductive shielding material layer in the storage region from the second side of the active column to form a second conductive shielding structure; the first side and the second side are two opposite sides of the active column along the third direction; the size of the second conductive shielding structure in the storage region along the third direction is less than the size of the second conductive shielding structure in the virtual region along the third direction.

[0019] In an optional implementation manner, the method further includes:

[0020] Etch the second conductive shielding structure from the second side of the active column to form a plurality of second conductive shielding lines arranged along the second direction;

[0021] Form a first contact structure; the first contact structure includes a first sub-contact structure and a second sub-contact structure, the first sub-contact structure is connected to the second conductive shielding line in the virtual region, and the second sub-contact structure is connected to the second conductive shielding line in the storage region.

[0022] In an optional implementation manner, the method further includes:

[0023] Thin the substrate from the second side of the active column to expose the first dielectric layer, and the remaining substrate constitutes a plurality of semiconductor structures and a plurality of the active columns;

[0024] The forming the second conductive portion includes:

[0025] Form a first conductive material layer on the semiconductor structure;

[0026] Perform heat treatment on the semiconductor structure and the first conductive material layer to form the second conductive portion.

[0027] In an alternative embodiment, the forming of the first conductive portion includes:

[0028] Form a second conductive material layer on the sidewalls and the bottom wall of the third trench from the first side of the active pillar;

[0029] Remove a portion of the second conductive material layer of the storage region from the second side of the active pillar to form a first filling region; the remaining second conductive material layer constitutes the first conductive portion, and the dimension of the first conductive portion of the storage region along the third direction is smaller than the dimension of the first conductive portion of the virtual region along the third direction.

[0030] In an alternative embodiment, the forming of the first conductive shielding structure includes:

[0031] When removing a portion of the second conductive material layer of the storage region from the second side of the active pillar, remove the first dielectric layer located between adjacent semiconductor structures in the storage region to form a second filling region;

[0032] Form a second dielectric layer in the first filling region, and form the second dielectric layer and a third conductive material layer in the second filling region; the second dielectric layer in the second filling region is located between the third conductive material layer and the semiconductor structure;

[0033] Remove the third conductive material layer to form a third filling region;

[0034] Form a third dielectric layer and a fourth conductive material layer in the third filling region; the third dielectric layer is located between the fourth conductive material layer and the second dielectric layer, and the fourth conductive material layer constitutes the portion of the first conductive shielding structure located in the storage region.

[0035] In an alternative embodiment, the forming of the first conductive portion and the first conductive shielding structure includes:

[0036] After forming the second dielectric layer and the third conductive material layer in the second filling region, remove the first dielectric layer located between adjacent semiconductor structures in the virtual region to form a fourth filling region;

[0037] Form a fifth conductive material layer in the fourth filling region;

[0038] When removing the third conductive material layer, the fifth conductive material layer and the second conductive material layer in the virtual region are removed to form a fifth filling region;

[0039] When forming a third dielectric layer and a fourth conductive material layer in the third filling region, the fourth conductive material layer and the third dielectric layer are formed in the fifth filling region; the third dielectric layer in the virtual region is at least located between the fourth conductive material layer and the semiconductor structure; the fourth conductive material layer between adjacent semiconductor structures in the virtual region constitutes a part of the first conductive shielding structure in the virtual region, and the remaining fourth conductive material layers in the virtual region constitute a first conductive part of the virtual region.

[0040] In an alternative embodiment, the method further includes:

[0041] Before forming the first filling region and the second filling region, a protective layer covering the virtual region is formed from the second side of the active pillar;

[0042] After forming a second dielectric layer in the first filling region and the second dielectric layer and the third conductive material layer in the second filling region, the protective layer is removed.

[0043] In an alternative embodiment, the method further includes:

[0044] Etching the first conductive part from the second side of the active pillar to form a plurality of first conductive lines arranged along the second direction;

[0045] Forming a second contact structure from the second side of the active pillar; the second contact structure includes a third sub-contact structure and a fourth sub-contact structure, the third sub-contact structure is connected to the first conductive line in the storage region, and the fourth sub-contact structure is connected to the first conductive line in the virtual region.

[0046] In a second aspect, an embodiment of the present disclosure provides a memory,

[0047] The memory includes a storage chip, the storage chip includes a storage region and a virtual region arranged along a first direction, and both the storage region and the virtual region include:

[0048] An active pillar array; the active pillar array includes a plurality of active pillars arranged in an array along the first direction and the second direction, and the active pillars extend along a third direction; the first direction intersects with the second direction and is perpendicular to the third direction;

[0049] A plurality of first conductive lines; the plurality of first conductive lines are arranged along the first direction, and the first conductive lines extend along the second direction and are located between adjacent active pillars along the first direction;

[0050] A plurality of first conductive shield lines and a plurality of second conductive lines; the second conductive lines and the first conductive shield lines both extend along the first direction and are alternately arranged along the second direction, one end of the second conductive lines is connected to the active pillar, and the first conductive line in the virtual region is connected to the first conductive shield line.

[0051] In an alternative embodiment, the storage region and the virtual region further include:

[0052] A plurality of second conductive shield lines; the second conductive shield lines extend along the second direction and are located between adjacent first conductive lines; the second conductive shield lines in the virtual region are connected to the first conductive shield lines.

[0053] In an alternative embodiment, the size of the second conductive shield line in the storage region along the third direction is smaller than the size of the second conductive shield line in the virtual region along the third direction.

[0054] In an alternative embodiment, the memory further includes a first contact structure; the first contact structure includes a first sub-contact structure and a second sub-contact structure, the first contact structure is located on the second side of the active pillar, and the first sub-contact structure is connected to the second conductive shield line in the virtual region, and the second sub-contact structure is connected to the second conductive shield line in the storage region.

[0055] In an alternative embodiment, the memory further includes a second contact structure; the second contact structure includes a third sub-contact structure and a fourth sub-contact structure, the second contact structure is located on the second side of the active pillar, and the third sub-contact structure is connected to the first conductive line in the storage region, and the fourth sub-contact structure is connected to the first conductive line in the virtual region.

[0056] In an alternative embodiment, the size of the first conductive line in the storage region along the third direction is smaller than the size of the first conductive line in the virtual region along the third direction.

[0057] In an alternative embodiment, the storage region further includes: a second dielectric layer; the second dielectric layer is located between the first conductive line and the first conductive shield line, between the first conductive shield line and the second conductive line, and between the first conductive line and the second conductive line.

[0058] In an alternative embodiment, the storage area and the virtual area further include: a third dielectric layer; wherein, the third dielectric layer in the virtual area is located between the second conductive line and the first conductive shielding line in the virtual area, and between the second conductive line and the first conductive line in the virtual area; the third dielectric layer in the storage area is located between the first conductive shielding line and the second dielectric layer in the storage area.

[0059] In a third aspect, an embodiment of the present disclosure provides a memory system, including:

[0060] One or more memories as described in any one of the above embodiments;

[0061] A memory controller, coupled to the memory and configured to control the memory.

[0062] In the embodiment of the present disclosure, the first conductive line in the virtual area is connected to the first shielding structure, so that the first shielding structure can be led out by using the first conductive line in the virtual area, without forming an additional contact structure for the first shielding structure. Therefore, the process burden of the area for forming the contact structure can be greatly reduced, the process difficulty and cost can be reduced, the process window can be expanded, and since the density of the finally formed contact structure is reduced, the performance of the memory can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] Figure 1 FIG. is a schematic circuit connection diagram of an architecture adopting 1T1C provided by an embodiment of the present disclosure;

[0064] Figure 2 FIG. is a schematic flowchart of a method for manufacturing a memory provided by an embodiment of the present disclosure;

[0065] Figures 3 to 31 FIG. is a schematic process diagram of a method for manufacturing a memory provided by an embodiment of the present disclosure;

[0066] Figures 32 to 34 FIG. is a schematic structural diagram of a memory provided by an embodiment of the present disclosure;

[0067] Figure 35 FIG. is a schematic block diagram of a composition of an electronic device provided by an embodiment of the present disclosure;

[0068] Figures 36 to 37 FIG. is a schematic block diagram of a composition of a memory system provided by an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0069] To make the technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the present disclosure will be further elaborated in detail below in conjunction with the drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation manners described herein. On the contrary, these implementation manners are provided to enable a more thorough understanding of the present disclosure and to be able to fully convey the scope of the present disclosure to those skilled in the art.

[0070] The present disclosure will be described more specifically by way of example in the following paragraphs with reference to the drawings. The advantages and features of the present disclosure will be clearer according to the following description and claims. It should be noted that the drawings are all in very simplified forms and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the purpose of the embodiments of the present disclosure.

[0071] It can be understood that the meanings of "on", "above", and "over" in the present disclosure should be interpreted in the broadest manner, so that "on" not only means "on" something without any intervening features or layers therebetween (i.e., directly on something), but also includes the meaning of having intervening features or layers on something.

[0072] In addition, for the convenience of description, spatial relative terms such as "on", "above", "over", "upper", etc. may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. Except for the orientation depicted in the drawings, the spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptors used herein can be interpreted accordingly.

[0073] In the embodiments of the present disclosure, the term "substrate" refers to a material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials, such as silicon, silicon germanium, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials, such as glass, plastic, or sapphire wafers.

[0074] In the embodiments of the present disclosure, the term "layer" refers to a portion of a material that includes a region having a thickness. The layer may extend over the entirety of a structure below or above, or may have a scope that is less than the scope of the structure below or above. Additionally, the layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure, or the layer may be between any horizontal planes at the top and bottom surfaces of the continuous structure. The layer may extend horizontally, vertically, and / or along an inclined surface. The layer may include a plurality of sub-layers. For example, an interconnect layer may include one or more conductor and contact sub-layers (wherein interconnect lines and / or via contacts are formed), and one or more dielectric sub-layers.

[0075] In the embodiments of the present disclosure, the terms "first", "second", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0076] With the development of dynamic random access memory technology, the size of memory cells is getting smaller and smaller, and its array architecture changes from 8F 2 to 6F 2 and then to 4F 2 ; in addition, based on the requirements for ions and leakage current in dynamic random access memory, the architecture of the memory changes from a planar array transistor to a recess gate array transistor, then from a recess gate array transistor to a buried saddle Fin array transistor, and then from a buried saddle Fin array transistor to a vertical gate transistor.

[0077] In some embodiments, whether it is a planar transistor, a recess gate array transistor, a buried transistor, or a vertical gate transistor, a dynamic random access memory is composed of a plurality of memory cell structures. Each memory cell structure is mainly composed of a transistor and a memory structure (memory capacitor) controlled by the transistor, that is, the dynamic random access memory includes an architecture of 1 transistor (T, Transistor) and 1 capacitor (C, Capacitance) (1T1C); its main principle of operation is to use the amount of charge stored in the capacitor to represent whether a binary bit (bit) is 1 or 0.

[0078] Figure 1 A schematic diagram of a circuit connection adopting the 1T1C architecture provided in the embodiments of the present disclosure is shown in Figure 1As shown, the drain of the transistor T is connected to the bit line (BL, Bite Line), the source of the transistor T is connected to one electrode plate of the capacitor C, the other electrode plate of the capacitor C is grounded through the ground terminal (GND, Ground), and the gate of the transistor T is connected to the word line (WL, Word Line); a voltage is applied through the word line WL to control the conduction or cut-off of the transistor T, and the bit line BL is used to perform a read or write operation on the transistor T when the transistor T is conducting.

[0079] With the continuous increase in the storage density requirements for dynamic random access memories, the process difficulty in the manufacturing process of memories is becoming increasingly large. How to reduce the process difficulty, reduce the process cost, and improve the performance of memories has become an urgent problem to be solved.

[0080] Based on one or more of the above problems, embodiments of the present disclosure provide a method for manufacturing a memory. Figure 2 It is a schematic flowchart of a method for manufacturing a memory provided by an embodiment of the present disclosure. As Figure 2 shown, the method for manufacturing a memory provided by an embodiment of the present disclosure includes the following steps:

[0081] Step 1001: Form an active pillar array in the virtual area and the storage area; the active pillar array includes a plurality of active pillars arranged in an array along a first direction and a second direction; the virtual area and the storage area are arranged along the first direction, and the active pillars extend along a third direction; the first direction intersects with the second direction and is perpendicular to the third direction;

[0082] Step 1002: Form a plurality of first conductive parts in the virtual area and the storage area; the plurality of first conductive parts are arranged along the first direction, and the first conductive parts extend along the second direction and are located between adjacent active pillars along the first direction;

[0083] Step 1003: Form a second conductive part and a first conductive shielding structure in both the virtual area and the storage area; the second conductive part and the first conductive shielding structure both extend along the first direction and are alternately arranged along the second direction, the second conductive part is connected to one end of the two ends of the active pillar opposite along the third direction, and the first conductive part in the virtual area is connected to the first conductive shielding structure.

[0084] Figures 3 to 31 It is a schematic diagram of the process of a method for manufacturing a memory provided by an embodiment of the present disclosure. It should be understood that Figure 2 the steps shown are not exclusive, and other steps may be performed before, after, or between any of the shown operations; Figure 2 the steps shown can be adjusted in order according to actual needs. The following combinationFigure 2 , Figures 3 to 31 A detailed description is given of the manufacturing method of the memory provided in the embodiments of the present disclosure.

[0085] In some embodiments, as Figures 3 to 8 shown, an active pillar array 161 is formed, including: providing a substrate 156; etching the substrate 156 to form a plurality of first trenches 157 arranged at intervals along the second direction; the first trenches 157 extend along the first direction and the bottoms are located in the substrate 156; forming a first dielectric layer 106 in the first trenches 157; etching the substrate 156 and the first dielectric layer 106 to form second trenches 159 and third trenches 160 arranged alternately along the first direction; wherein, both the second trenches 159 and the third trenches 160 extend along the second direction and the bottoms are located in the substrate 156, and the depths of the second trenches 159 and the third trenches 160 are less than the depth of the first trenches 157; the first trenches 157, the second trenches 159, and the third trenches 160 divide the substrate 156 into a plurality of the active pillars 102.

[0086] Here, Figure 4 cross-sectional views along dd', ee', and cc' in Figure 3 are respectively shown, and only part of the structure is shown in the top view of Figure 3 , and there is still some substrate material at the bottom of the first trenches 157; Figure 6 cross-sectional views along dd', ee', and cc' in Figure 5 are respectively shown; Figure 8 cross-sectional views along dd', ee', and cc' in Figure 7 are respectively shown, and only part of the structure is shown in the top view of Figure 7 , and there is still some substrate material at the bottoms of the second trenches 159 and the third trenches 160; Figure 10 cross-sectional views along dd', ee', and cc' in Figure 9 are respectively shown.

[0087] In some specific examples, the depth of the first trenches 157 is h1 as Figure 4 shown, and the depths of the second trenches 159 and the third trenches 160 are h3 and h2 respectively as Figure 8 shown, where h2 = h3 < h1. In some other specific examples, h3 and h2 may also not be equal.

[0088] In some specific examples, the substrate 156 may include a single-element semiconductor material substrate (such as a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a compound semiconductor material substrate (such as a silicon-germanium (SiGe) substrate, etc.), a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. Exemplarily, the substrate is a silicon substrate.

[0089] In some specific examples, the methods for forming the first trench 157, the second trench 159, and the third trench 160 include but are not limited to dry etching, for example, a plasma etching process or a reactive ion etching process.

[0090] In some specific examples, the material of the first dielectric layer 106 includes but is not limited to silicon oxide and silicon nitride.

[0091] The first direction intersects with the second direction here. In some specific examples, the first direction is perpendicular to the second direction. The embodiments of the present disclosure are described by taking the first direction and the second direction being perpendicular as an example.

[0092] The first direction here may be the Y-axis direction in the accompanying drawings of the present disclosure, the second direction may be the X-axis direction in the accompanying drawings of the present disclosure, and the third direction may be the Z-axis direction in the accompanying drawings of the present disclosure.

[0093] As Figure 11 and Figure 12 shown, the memory in the embodiments of the present disclosure includes a virtual area 100 and a storage area 101. It can be understood that the memory includes a plurality of memory chips, and each memory chip can be powered on and off independently to perform independent read and write operations. Each memory chip includes a virtual area 100 and a storage area 101. The virtual area 100 is located in the edge area of the memory chip, and the finally formed transistors and storage structures in the virtual area 100 may not be used for storage functions. And the embodiments of the present disclosure only exemplarily show that the virtual area 100 in the memory chip is located on one side of the opposite sides of the storage area 101 along the first direction. In some specific examples, the virtual area 100 in the memory chip may be located on the opposite sides of the memory chip along the first direction. In other specific examples, the virtual area is located on the opposite sides of the storage area along the first direction and on the opposite sides of the storage area along the second direction. Figures 3 to 29 The virtual area in the shown embodiments refers to the virtual area distributed on one side or both sides of the opposite sides of the storage area along the first direction. And Figures 3 to 29 in the shown embodiments, the virtual areas corresponding to two adjacent memory chips along the second direction are in contact.

[0094] Here Figure 11 is a top view, Figure 12 which respectively shows along Figure 11The cross-sectional view along the aa' direction is a cross-sectional view of the virtual area 100 along the second direction, the cross-sectional view along the bb' direction is a cross-sectional view of the storage area 101 along the second direction, and the cross-sectional view along the cc' direction is a cross-sectional view of the virtual area 100 and the storage area 101 along the first direction.

[0095] In some embodiments, Figure 9 as well as Figure 10 As shown, the method includes: forming a second conductive shielding material layer 144 in the second trench 159 from the first side of the active pillar 102 to cover the sidewall of the second trench 159 .

[0096] In some specific examples, the method further includes: forming a fourth dielectric layer 135 on the sidewalls and the bottom wall of the second trench 159 , and filling the second conductive shielding material layer 144 in the second trench 159 formed with the fourth dielectric layer 135 .

[0097] Here, the material of the second conductive shielding material layer 144 includes a conductive material, and illustratively includes metal tungsten. The material of the fourth dielectric layer 135 includes, but is not limited to, silicon nitride and silicon oxide.

[0098] In some embodiments, the forming of the first conductive portion includes: forming a second conductive material layer 111 on the sidewall and bottom wall of the third trench from the first side of the active pillar.

[0099] In some specific examples, the method also includes: before forming the second conductive material layer 111, forming a gate oxide layer 149 on the side walls and bottom walls of the third trench 160 from the first side of the active pillar; forming the second conductive material layer 111 covering the side walls and bottom walls of the third trench 160 in the third trench 160 in which the gate oxide layer 149 is formed; and forming a fifth dielectric layer 136 in the third trench 160, wherein the fifth dielectric layer 136 covers the second conductive material layer 111.

[0100] Here, the material of the fifth dielectric layer 136 includes but is not limited to silicon nitride and silicon oxide; the material of the second conductive material layer 111 includes but is not limited to conductive metal or conductive alloy, and the conductive metal may include tungsten or copper, etc.; the material of the gate oxide layer 149 includes but is not limited to silicon oxide.

[0101] In some specific examples, the active pillar 102 includes a first doped region, a channel region, and a second doped region arranged along a third direction. The first doped region may be one of a source and a drain of a transistor, and the second doped region may be the other of the source and the drain of the transistor.

[0102] In some specific examples, the fifth dielectric layer 136, the second conductive material layer, and the gate oxide layer 149 can be etched back from the first side of the active column 102, so that the remaining fifth dielectric layer 136, the second conductive material layer 111, and the gate oxide layer 149 cover the sidewalls of the second doped region and the channel region of the active column 102. And a sixth dielectric layer is filled in the filling region formed after etching back the fifth dielectric layer 136, the second conductive material layer 111, and the gate oxide layer 149. The material of the sixth dielectric layer includes, but is not limited to, silicon oxide and silicon nitride.

[0103] In some specific examples, the method further includes: forming a stacked structure 138 covering the active column from the first side of the active column, and forming a storage structure ( Figure 12 not shown in the figure) in the stacked structure 138. The storage structure is connected to the other end of the two opposite ends of the active column 102 along the third direction, specifically, it can be connected to the first doped region of the active column.

[0104] In some specific examples, the memory includes a dynamic random access memory, and the storage structure includes a storage capacitor. The storage capacitor can have various structures. Exemplarily, the storage capacitor includes a cup-shaped, cylindrical, or pillar-shaped capacitor.

[0105] In some specific examples, the methods for forming the fourth dielectric layer 135, the fifth dielectric layer 136, the sixth dielectric layer, and the stacked structure 138 include, but are not limited to, physical vapor deposition (PVD, Physical Vapor Deposition) process, chemical vapor deposition (CVD, Chemical Vapor Deposition) process, atomic layer deposition (ALD, Atomic Layer Deposition), and other processes.

[0106] Next, as Figure 13 shown, a carrier wafer 142 is formed on the stacked structure 138 from the first side of the active column, and the above-mentioned substrate 156 is flipped so that the second side of the active column faces upward. Here, the carrier wafer 142 can be used to carry the substrate during subsequent processings from the second side of the active column and protect the related structures formed on the first side of the active column.

[0107] The above embodiments are processings from the first side of the active column. Next, the processings from the second side of the active column will be specifically introduced. Here, the first side and the second side are the two opposite sides of the active column along the third direction.

[0108] In some embodiments, the method further includes: thinning the substrate from a second side of the active pillar to expose the first dielectric layer, and the remaining substrate forms a plurality of semiconductor structures and a plurality of the active pillars; the forming of the second conductive portion includes: forming a first conductive material layer on the semiconductor structure; performing a heat treatment on the semiconductor structure and the first conductive material layer to form the second conductive portion.

[0109] The plurality of semiconductor structures are arranged along a second direction here, and each semiconductor structure extends along a first direction, and the semiconductor structure is connected to a second doped region of a plurality of active pillars arranged along the first direction.

[0110] In some embodiments, the forming of the first conductive portion includes: removing a part of the second conductive material layer of the storage region from a second side of the active pillar to form a first filling region; the remaining second conductive material layer forms the first conductive portion, and the size of the first conductive portion of the storage region along the third direction is smaller than the size of the first conductive portion of the virtual region along the third direction.

[0111] In some embodiments, the forming of the first conductive shielding structure includes: when removing a part of the second conductive material layer of the storage region from a second side of the active pillar, removing the first dielectric layer of the storage region located between adjacent semiconductor structures to form a second filling region; forming a second dielectric layer in the first filling region, and forming the second dielectric layer and a third conductive material layer in the second filling region; the second dielectric layer in the second filling region is located between the third conductive material layer and the semiconductor structure; removing the third conductive material layer to form a third filling region; forming a third dielectric layer and a fourth conductive material layer in the third filling region; the third dielectric layer is located between the fourth conductive material layer and the second dielectric layer, and the fourth conductive material layer forms the part of the first conductive shielding structure located in the storage region.

[0112] In some embodiments, forming the first conductive portion and the first conductive shielding structure includes: after forming the second dielectric layer and the third conductive material layer in the second filling region, removing the first dielectric layer of the virtual region located between adjacent semiconductor structures to form a fourth filling region; forming a fifth conductive material layer in the fourth filling region; when removing the third conductive material layer, removing the fifth conductive material layer and the second conductive material layer of the virtual region to form a fifth filling region; when forming the third dielectric layer and the fourth conductive material layer in the third filling region, forming the fourth conductive material layer and the third dielectric layer in the fifth filling region; the third dielectric layer in the virtual region is at least located between the fourth conductive material layer and the semiconductor structure; the fourth conductive material layer between adjacent semiconductor structures in the virtual region constitutes the portion of the first conductive shielding structure located in the virtual region, and the remaining fourth conductive material layer in the virtual region constitutes the first conductive portion of the virtual region.

[0113] In some embodiments, the method further includes: before forming the first filling region and the second filling region, forming a protective layer covering the virtual region from the second side of the active pillar; after forming the second dielectric layer in the first filling region and forming the second dielectric layer and the third conductive material layer in the second filling region, removing the protective layer.

[0114] In some embodiments, the method further includes: forming a second contact structure from the second side of the active pillar; the second contact structure includes a third sub-contact structure and a fourth sub-contact structure, the third sub-contact structure is connected to the first conductive wire of the storage region, and the fourth sub-contact structure is connected to the first conductive wire of the virtual region.

[0115] In some embodiments, the method further includes: forming a second conductive shielding structure in the second trench; the second conductive shielding structure located in the virtual region is connected to the first conductive shielding structure.

[0116] In some embodiments, forming the second conductive shielding structure in the second trench includes: etching the second conductive shielding material layer in the storage region from the second side of the active pillar to form the second conductive shielding structure; the first side and the second side are opposite sides of the active pillar along the third direction; the size of the second conductive shielding structure in the storage region along the third direction is smaller than the size of the second conductive shielding structure in the virtual region along the third direction.

[0117] In some embodiments, the method further includes: forming a first contact structure; the first contact structure includes a first sub-contact structure and a second sub-contact structure, the first sub-contact structure is connected to the second conductive shielding line of the virtual region, and the second sub-contact structure is connected to the second conductive shielding line of the storage region.

[0118] Next, a specific description will be given of the process treatment performed on the second side of the active column in conjunction with Figures 13 to 31 the following.

[0119] As Figure 13 shown, the substrate 156 is thinned from the second side of the active column, such that the first dielectric layer 106 and the semiconductor structure 110 are exposed.

[0120] Next, as Figure 14 shown, a protective layer 122 covering the virtual region 100 is formed from the second side of the active column; the first dielectric layer 106 located between adjacent semiconductor structures 110 in the storage region 101 is removed to form a second filling region 113; a portion of the second conductive material layer 111 in the storage region 101 is removed to form a first filling region 112. The first filling region 112 and the second filling region 113 are in communication here. The remaining second conductive material layer 111 in the storage region 101 constitutes the first conductive portion 103 of the storage region 101. The first conductive portion 103 includes a first sub-conductive portion 147 and a second sub-conductive portion 148, and the first sub-conductive portion 147 and the second sub-conductive portion 148 are arranged along a first direction and both extend along a second direction.

[0121] In some specific examples, as Figure 14 shown, the method further includes: removing a portion of the gate oxide layer 149 in the storage region 101, such that the remaining gate oxide layer 149 and the remaining second conductive material layer 111 in the storage region 101 cover the sidewalls of the channel region of the active column.

[0122] In some specific examples, as Figure 14 shown, the method further includes: removing a portion of the fourth dielectric layer 135 and a portion of the second conductive shielding material layer 144 in the storage region 101 to form a sixth filling region 133. The remaining second conductive shielding material layer 144 in the storage region 101 constitutes the second conductive shielding structure 107 in the storage region, and the second conductive shielding structure 107 in the storage region covers the sidewalls of the channel region of the active column.

[0123] In the embodiments of the present disclosure, the second conductive shielding material layer 144 in the virtual region 100 is not etched back on the second side of the active column, and the second conductive shielding structure in the virtual region covers the sidewalls of the channel region of the active column and the sidewalls of the second doping region, such that the second conductive shielding structure finally formed in the virtual region is connected to the first conductive shielding structure.

[0124] In some specific examples, the material of the protective layer 122 includes but is not limited to metallic aluminum.

[0125] In some embodiments, as Figure 13 shown, an adhesion layer 143 is further formed between the second conductive material layer 111 and the gate oxide layer 149. The material of the adhesion layer 143 includes but is not limited to titanium nitride. When removing a part of the second conductive material layer 111 in the storage area 101 to form the first filling area 112, the method further includes removing a part of the adhesion layer 143 in the storage area 101.

[0126] Figures 16 to 18 respectively show cross-sectional views along Figure 15 aa', bb', and cc' in

[0127] Next, as Figures 15 to 18 shown, a second dielectric layer 114 is formed in the first filling area 112, and the second dielectric layer 114 and a third conductive material layer 115 are formed in the second filling area 113. In some specific examples, first, as Figure 16 shown, a second initial dielectric layer 145 and a third initial conductive material layer 146 are formed. The second initial dielectric layer 145 and the third initial conductive material layer 146 are also formed on the semiconductor structure 110. A planarization process can be used to remove a part of the second initial dielectric layer 145 and a part of the third initial conductive material layer 146, so that the top surfaces of the formed second dielectric layer 114 and the third conductive material layer 115 are flush with the top surface of the semiconductor structure 110.

[0128] Next, as Figures 17 to 18 shown, the protective layer 122 is removed, so as to expose a part of the semiconductor structure 110 in the virtual area 100 and the first dielectric layer 106 in the virtual area; the first dielectric layer 106 in the virtual area 100 located between adjacent semiconductor structures 110 is removed to form a fourth filling area 119; a fifth conductive material layer 120 is formed in the fourth filling area 119.

[0129] In some embodiments, next, as Figure 19 shown, a first conductive material layer is formed on the semiconductor structure 110, and the semiconductor structure 110 and the first conductive material layer are heat-treated to form a second conductive portion 104. The second conductive portion 104 extends along the Y-axis direction. In subsequent processes, the second conductive portion 104 is etched to form a plurality of second conductive wires arranged along the Y-axis direction.

[0130] Figure 21 and Figure 22 respectively show along Figure 20Cross-sectional views of aa', bb', and cc' in

[0131] As shown in Figure 20 and Figure 21 In the virtual region 100 and the storage region 101, an eighth dielectric layer 139 is formed. The eighth dielectric layer 139 covers the semiconductor structure 110, the third conductive material layer 115, and the fifth conductive material layer 120. The material of the eighth dielectric layer 139 includes, but is not limited to, silicon nitride and silicon oxide. The eighth dielectric layer 139 is etched to expose a part of the semiconductor structure 110 and the third conductive material layer 115.

[0132] Next, as shown in Figure 22 The second dielectric layer 114, the third conductive material layer 115, and the first conductive portion 103 are etched to form a first conductive wire 123 and a seventh filling region 134.

[0133] In some specific examples, the method further includes: etching the second conductive portion, the first conductive shielding structure 105, and the second conductive shielding structure 107 to form a second conductive wire 126, a first conductive shielding wire 125, and a second conductive shielding wire 108, and forming a seventh filling region 134.

[0134] In some specific examples, the second conductive shielding structure 107 in the virtual region 100 and the first conductive portion in the virtual region 100 may not be etched, so that in the finally formed memory, the second conductive shielding structures in the virtual regions 100 of two adjacent memory cells along the second direction are connected, and the first conductive wires 123 in the virtual regions 100 of two adjacent memory cells along the second direction are connected.

[0135] In some specific examples, the above first conductive wire 123 may be a word line, and the second conductive wire 126 may be a bit line.

[0136] Figure 24 and Figure 25 respectively show cross-sectional views of aa', bb', and cc' along Figure 23 in

[0137] Next, as shown in Figure 23 and Figure 24 A ninth dielectric layer 140 is filled in the seventh filling region 134. The material of the ninth dielectric layer 140 includes, but is not limited to, silicon nitride and silicon oxide.

[0138] Next, as shown in Figure 25As shown, a first conductive material layer is formed on the semiconductor structure 110, and the semiconductor structure 110 and the first conductive material layer are heat-treated to form a second conductive wire 126; the third conductive material layer 115 is removed to form a third filling region 116; and when the third conductive material layer 115 is removed, the fifth conductive material layer 120 and the second conductive material layer 111 of the virtual region 100 are removed to form a fifth filling region 121.

[0139] In some specific examples, the material of the second conductive wire 126 includes, but is not limited to, nickel silicide.

[0140] Figure 27 and Figure 28 respectively show cross-sectional views along Figure 26 aa', bb', and cc' in

[0141] Next, as Figure 26 and Figure 27 shown, a third dielectric layer 117 and a fourth conductive material layer 118 are formed in the third filling region 116; and when the third dielectric layer 117 and the fourth conductive material layer 118 are formed in the third filling region 116, the fourth conductive material layer 118 and the third dielectric layer 117 are formed in the fifth filling region 121. The third dielectric layer 117 in the virtual region 100 is at least located between the fourth conductive material layer 118 and the semiconductor structure 110; the fourth conductive material layer 118 located between adjacent semiconductor structures 110 in the virtual region 100 constitutes a part of the first conductive shielding structure in the virtual region 100, and the remaining fourth conductive material layer 118 in the virtual region 100 constitutes the first conductive part 103 of the virtual region 100.

[0142] Next, as Figure 28 shown, a tenth dielectric layer 141 is formed from the second side of the active pillar, and the tenth dielectric layer 141 is etched to form a third contact structure 127 in the tenth dielectric layer 141, and the third contact structure 127 is connected to the second conductive wire 126.

[0143] In some specific examples, as Figure 26 shown, the method further includes: forming a second contact structure 124 from the second side of the active pillar; the second contact structure 124 includes a third sub-contact structure 164 and a fourth sub-contact structure 165, the third sub-contact structure 164 is connected to the first conductive wire 123 of the storage region 101, and the fourth sub-contact structure 165 is connected to the first conductive wire 123 of the virtual region 100.

[0144] In some specific examples, as Figure 28As shown, the method further includes: further etching the first conductive shielding line to narrow the width of the first conductive shielding line at the edge of the memory chip, so as to facilitate the formation of the third sub-contact structure 164.

[0145] In some specific examples, as Figure 26 As shown, the memory chip in the embodiment of the present disclosure further includes a first contact area 167. The first contact area 167 is located on both sides of the memory area along the second direction. An array of memory cells with storage functions can be formed in the memory area. The memory cells can include a 1T1C structure. The first contact area 167 is mainly used to form contact structures. The second sub-contact structure and the third sub-contact structure in the embodiment of the present disclosure can be formed in the first contact area 167, and the first sub-contact structure and the fourth sub-contact structure can be formed in the virtual areas 100 on opposite sides of the memory area 101 along the first direction.

[0146] As Figure 26 As shown, the memory chip in the embodiment of the present disclosure further includes a second contact area 166. It should be noted that in the embodiment of the present disclosure, only one side of the two opposite sides of the memory chip 153 along the first direction is exemplarily shown to have a virtual area. In some specific examples, each memory chip can include virtual areas located on opposite sides of the memory area along the first direction. The virtual areas of adjacent memory chips along the first direction are separated by the second contact area 166, and the second contact area 166 is located between the virtual areas of adjacent memory chips 153 along the first direction. The third contact structure in the embodiment of the present disclosure can be formed in the second contact area 166. The first conductive line and the second conductive shielding line in the embodiment of the present disclosure can extend to the first contact area 167, and the second conductive line and the first conductive shielding line can extend to the second contact area 166.

[0147] In some specific examples, as Figure 26 As shown, the first conductive line 123 includes a first sub-conductive line 131 and a second sub-conductive line 132. The first sub-conductive line 131 and the second sub-conductive line 132 are arranged along the first direction and both extend along the second direction. The first sub-conductive line 131 covers the side walls of the channel regions of multiple active pillars 102 in the first row of active pillars 150, and the second sub-conductive line 132 covers the side walls of the channel regions of multiple active pillars 102 in the second row of active pillars 151. The adjacent first row of active pillars 150 and the second row of active pillars 151 form a row of active pillar group 152, and the second conductive shielding structure 107 is located between adjacent rows of active pillar groups 152. The third sub-contact structure 164 includes a fifth sub-contact structure 129 and a sixth sub-contact structure 130. The fifth sub-contact structure 129 is connected to the first sub-conductive line 131, and the sixth sub-contact structure 130 is connected to the second sub-conductive line 132.

[0148] In some specific examples, as Figure 26As shown, the second contact structure 124 in the virtual region can be a whole, which can increase the contact area between the second contact structure 124 in the virtual region and the first conductive line 123, and increase the contact area between the second contact structure 124 in the virtual region and the upper metal layer.

[0149] It can be understood that in the embodiments of the present disclosure, the first conductive line 123 in the virtual region 100 is connected to the first conductive shielding line 125, and the first conductive lines 123 in the virtual region and in the storage region are both led out. In this way, the first conductive shielding line 125 can be led out by using the first conductive line 123 in the virtual region 100, that is, multiple first conductive shielding lines 125 in the memory chip can be led out by using a single first conductive line 123 in the virtual region through the second contact structure 124, without the need to additionally form a contact structure for the first conductive shielding line 125. Therefore, the process burden of the region where the contact structure is formed can be greatly reduced, the process difficulty and cost can be reduced, the process window can be expanded, and since the density of the finally formed contact structure is reduced, the performance of the memory can be improved.

[0150] In the embodiments of the present disclosure, as Figure 29 shown, the method further includes: forming a first contact structure 109; the first contact structure 109 includes a first sub-contact structure 162 and a second sub-contact structure 163, the first sub-contact structure 162 is connected to the second conductive shielding line 108 in the virtual region 100, and the second sub-contact structure 163 is connected to the second conductive shielding line 108 in the storage region 101.

[0151] It can be understood that in the embodiments of the present disclosure, while performing special processing on the first conductive part 103 in the virtual region 100, similar processing is also performed on the formation of the second conductive shielding structure 107 in the virtual region 100, so that the second conductive shielding line 108 in the virtual region 100 is connected to the first conductive shielding line 125, and the second conductive shielding lines 108 in the virtual region and in the storage region are both led out. In this way, the first conductive shielding line 125 can be led out by using the contact structure of the second conductive shielding line 108 in the virtual region, that is, multiple first conductive shielding lines 125 in the memory chip can be led out by using a single second conductive shielding line 108 in the virtual region through the first contact structure 109, so that the contact structure for the first conductive shielding line 125 does not need to be additionally formed. Therefore, the process burden of the region where the contact structure is formed can be greatly reduced, the process difficulty and cost can be reduced, the process window can be expanded, and since the density of the finally formed contact structure is reduced, the performance of the memory can be improved.

[0152] Based on a similar concept to the above embodiments, the embodiments of the present disclosure also provide the following technical solutions:

[0153] In some embodiments, as Figure 30 shown, a method for fabricating a memory includes: forming an active pillar array in a virtual region 100 and a storage region 101; the active pillar array includes a plurality of active pillars 102 arranged in an array along a first direction and a second direction; the virtual region 100 and the storage region 101 are arranged along the second direction, and the active pillars 102 extend along a third direction; the first direction intersects with the second direction and both are perpendicular to the third direction; forming a plurality of second conductive shielding structures 107 in the virtual region 100 and the storage region 101; the plurality of second conductive shielding structures 107 are arranged along the first direction, and the second conductive shielding structures 107 extend along the second direction and are located between adjacent active pillars 102 along the first direction; forming a second conductive portion 104 and a first conductive shielding structure 105 in both the virtual region 100 and the storage region 101; the second conductive portion 104 and the first conductive shielding structure 105 both extend along the first direction and are alternately arranged along the second direction, one end of the second conductive portion 104 is connected to one of the two opposite ends of the active pillar 102 along the third direction, and the first conductive shielding structure 105 in the virtual region 100 is connected to the second conductive shielding structure 107.

[0154] In some embodiments, as Figure 31 shown, the method further includes: etching the first conductive shielding structure 105 from the second side of the active pillar 102 to form a plurality of first conductive shielding lines 125 arranged along the first direction; forming a fourth contact structure 128 in both the virtual region and the storage region 101, and the fourth contact structure 128 is connected to the first conductive shielding line 125.

[0155] It can be understood that in the above embodiments, the first conductive shielding structure 105 in the virtual region 100 is connected to the second conductive shielding structure 107, and the first conductive shielding structures 105 in the virtual region and the storage region are both led out. In this way, the second conductive shielding structure 107 can be led out by using the contact structure of the first conductive shielding structure 105 in the virtual region 100, so that there is no need to additionally form a contact structure for the second conductive shielding structure 107. Therefore, the process burden of the region for forming the contact structure can be greatly reduced, the process difficulty and cost can be reduced, the process window can be expanded, and since the density of the finally formed contact structure is reduced, the performance of the memory can be improved.

[0156] It should be noted that in some specific examples, the virtual region is located on both sides of the storage region along the first direction and on both sides of the storage region along the second direction. Figures 30 to 31In the illustrated embodiments, the virtual regions refer to the virtual regions distributed on one or both sides of the storage region that are opposite to each other along the second direction.

[0157] Based on the above method for manufacturing a memory, embodiments of the present disclosure further provide a memory, as Figure 32 and Figure 33 shown, the memory includes a memory chip 153, the memory chip 153 includes a storage region 101 and virtual regions 100 arranged along a first direction, both the storage region 101 and the virtual regions 100 include: an active column array; the active column array includes a plurality of active columns 102 arranged in an array along the first direction and the second direction, the active columns 102 extend along a third direction; the first direction intersects with the second direction and both are perpendicular to the third direction; a plurality of first conductive lines 123; the plurality of first conductive lines 123 are arranged along the first direction, the first conductive lines 123 extend along the second direction and are located between adjacent active columns 102 along the first direction; a plurality of first conductive shielding lines 125 and a plurality of second conductive lines 126; the second conductive lines 126 and the first conductive shielding lines 125 both extend along the first direction and are alternately arranged along the second direction, the second conductive lines 126 are connected to one end of the active columns 102, and the first conductive lines 123 in the virtual regions 100 are connected to the first conductive shielding lines 125.

[0158] In some specific examples, the memory includes a plurality of memory chips 153, adjacent memory chips 153 are separated by a dielectric layer, and each memory chip 153 can perform independent read and write operations.

[0159] In some specific examples, the memory further includes a storage structure, the storage structure is located on a first side of the active columns 102, the second conductive lines 126 are located on a second side of the active columns 102, and the first side and the second side are opposite sides of the active columns 102 along the third direction. In some specific examples, the memory includes a dynamic random access memory, and the storage structure includes a storage capacitor. The storage capacitor can have various structures. Exemplarily, the storage capacitor includes a cup-shaped, cylindrical, or pillar-shaped capacitor. The active columns 102 include a first doped region, a channel region, and a second doped region arranged along the third direction, the second conductive lines 126 are connected to the second doped region, and the storage structure is connected to the first doped region. The first doped region can be one of the source and the drain, and the second doped region can be the other of the source and the drain.

[0160] In some specific examples, the first conductive lines 123 can be word lines, and the second conductive lines 126 can be bit lines. The material of the first conductive lines 123 includes but is not limited to polysilicon, conductive metal, or conductive alloy, and the conductive metal can include metal tungsten or metal copper, etc. The material of the second conductive lines 126 includes but is not limited to nickel silicide.

[0161] In some embodiments, such as Figure 32 shown, the memory further includes a second contact structure 124; the second contact structure 124 includes a third sub-contact structure 164 and a fourth sub-contact structure 165. The second contact structure 124 is located on the second side of the active pillar, and the third sub-contact structure 164 is connected to the first conductive line 123 of the storage area 101, and the fourth sub-contact structure 165 is connected to the first conductive line of the virtual area 100 123.

[0162] In some specific examples, such as Figure 32 shown, the memory chip in the embodiments of the present disclosure further includes a first contact area 167. The first contact area 167 is located on both sides of the storage area along the second direction. An array of storage units with storage functions can be formed in the storage area. The storage units can include a 1T1C structure. The first contact area 167 is mainly used to form contact structures. The second sub-contact structure and the third sub-contact structure in the embodiments of the present disclosure can be formed in the first contact area 167, and the first sub-contact structure and the fourth sub-contact structure can be formed in the virtual areas 100 on the opposite sides of the storage area 101 along the first direction.

[0163] Such as Figure 32 shown, the memory chip in the embodiments of the present disclosure further includes a second contact area 166. It should be noted that in the embodiments of the present disclosure, only one side of the two opposite sides of the memory chip 153 along the first direction is exemplarily shown to have a virtual area. In some specific examples, each memory chip can include virtual areas located on the opposite sides of the storage area along the first direction. The virtual areas of adjacent memory chips along the first direction are separated by the second contact area 166. The second contact area 166 is located between the virtual areas of adjacent memory chips 153 along the first direction. The third contact structure in the embodiments of the present disclosure can be formed in the second contact area 166. The first conductive line and the second conductive shielding line in the embodiments of the present disclosure can extend to the first contact area 167, and the second conductive line and the first conductive shielding line can extend to the second contact area 166.

[0164] It can be understood that in the embodiments of the present disclosure, since the first conductive line 123 in the virtual area 100 is connected to the first conductive shielding line 125, both the first conductive line 123 in the virtual area and the first conductive line 123 in the storage area are led out. The contact structure of the first conductive shielding line 125 can be led out by using the contact structure of the first conductive line 123 in the virtual area 100, eliminating the contact structure of the first conductive shielding line 125. This can reduce the burden on the formation area of the contact structure, lower the process difficulty, reduce the process cost, expand the process window, and since the density of the finally formed contact structure is reduced, the performance of the memory can be improved.

[0165] In some embodiments, the storage area 101 and the virtual area 100 further include: a plurality of second conductive shielding lines 108; the second conductive shielding lines 108 extend along the second direction and are located between adjacent first conductive lines 123; the second conductive shielding lines 108 located in the virtual area 100 are connected to the first conductive shielding line 125.

[0166] In some embodiments, as Figure 29 shown, the memory further includes a first contact structure 109; the first contact structure 109 includes a first sub-contact structure 162 and a second sub-contact structure 163, the first contact structure 109 is located on the second side of the active column, and the first sub-contact structure 162 is connected to the second conductive shielding line 108 of the virtual area 100, and the second sub-contact structure 163 is connected to the second conductive shielding line 108 of the storage area 101.

[0167] It can be understood that in the embodiments of the present disclosure, since the second conductive shielding line 108 in the virtual area 100 is connected to the first conductive shielding line 125, the second conductive shielding lines 108 in the virtual area and the second conductive shielding lines 108 in the storage area are both led out, and the first conductive shielding line 125 can be led out by using the contact structure of the second conductive shielding line 108 in the virtual area 100, eliminating the contact structure of the first conductive shielding line 125. This can reduce the burden on the formation area of the contact structure, reduce the process difficulty, reduce the process cost, expand the process window, and since the density of the finally formed contact structure is reduced, the performance of the memory can be improved.

[0168] In some specific examples, the active column array includes a first row of active columns 150 and a second row of active columns 151 arranged alternately along the first direction. Adjacent first row of active columns 150 and second row of active columns 151 form a row of active column groups 152. The first conductive line 123 is located between the first row of active columns and the second row of active columns in the row of active column groups 152, and the second conductive shielding line 108 is located between adjacent row of active column groups 152.

[0169] In some specific examples, the first conductive line 123 includes a first sub-conductive line 131 and a second sub-conductive line 132. The first sub-conductive line 131 and the second sub-conductive line 132 are arranged along the first direction and both extend along the second direction. The first sub-conductive line 131 covers the side walls of the channel regions of a plurality of active columns in the first row of active columns, and the second sub-conductive line 132 covers the side walls of the channel regions of a plurality of active columns in the second row of active columns. The third sub-contact structure 164 includes a fifth sub-contact structure 129 and a sixth sub-contact structure 130. The fifth sub-contact structure 129 is connected to the first sub-conductive line 131, and the sixth sub-contact structure 130 is connected to the second sub-conductive line 132.

[0170] In some specific examples, a gate oxide layer is also formed between the first sub-conductive wire 131 and the first row of active pillars, and between the second sub-conductive wire 132 and the second row of active pillars. The material of the gate oxide layer includes but is not limited to silicon oxide.

[0171] In some embodiments, the size of the second conductive shield wire 108 in the storage area 101 along the third direction is smaller than the size of the second conductive shield wire 108 in the virtual area 100 along the third direction.

[0172] In some specific examples, the second conductive shield wire 108 in the storage area 101 covers the sidewalls of the channel regions of the active pillars, while the second conductive shield wire 108 in the virtual area 100 covers the sidewalls of the channel regions of the active pillars and the sidewalls of the second doped regions of the active pillars.

[0173] In some specific examples, the storage chip 153 further includes a third contact structure 127, and the third contact structure 127 is connected to the second conductive wire 126.

[0174] In some specific examples, the materials of the first contact structure 109, the second contact structure 124, and the third contact structure 127 include but are not limited to tungsten.

[0175] In some embodiments, the size of the first conductive wire 123 in the storage area 101 along the third direction is smaller than the size of the first conductive wire 123 in the virtual area 100 along the third direction.

[0176] In some specific examples, the first conductive wire 123 in the storage area 101 covers the sidewalls of the channel regions of the active pillars, while the first conductive wire 123 in the virtual area 100 covers the sidewalls of the channel regions of the active pillars and the sidewalls of the second doped regions of the active pillars.

[0177] In some embodiments, the storage area 101 further includes: a second dielectric layer 114; the second dielectric layer 114 is located between the first conductive wire 123 and the first conductive shield wire 125, between the first conductive shield wire 125 and the second conductive wire 126, and between the first conductive wire 123 and the second conductive wire 126.

[0178] In some specific examples, the material of the second dielectric layer 114 includes but is not limited to silicon oxide and silicon nitride.

[0179] In some embodiments, the storage area 101 and the virtual area 100 further include: a third dielectric layer 117; wherein, the third dielectric layer 117 in the virtual area 100 is located between the second conductive wire 126 and the first conductive shielding wire 125 in the virtual area 100, and between the second conductive wire 126 and the first conductive wire 123 in the virtual area 100; the third dielectric layer 117 in the storage area 101 is located between the first conductive shielding wire 125 and the second dielectric layer 114 in the storage area 101.

[0180] In some specific examples, the material of the third dielectric layer 117 includes, but is not limited to, silicon oxide and silicon nitride.

[0181] In some embodiments, as Figure 34 shown, the memory further includes a first metal wire 154 and a second metal wire 155. Both the first metal wire 154 and the second metal wire 155 extend along a first direction. The first metal wire 154 is connected to the second contact structure 124 in the virtual area 101, and the second metal wire 155 is connected to the second contact structure 124 in the storage area 100. The materials of the first metal wire 154 and the second metal wire 155 include, but are not limited to, copper, tungsten, and aluminum.

[0182] In the above embodiments, the materials of the first conductive shielding wire and the second conductive shielding wire include conductive materials. Exemplarily, it includes metal tungsten. During the read and write operations of the memory, a first voltage can be applied to the first conductive shielding wire, and the first conductive shielding wire can be used to reduce the coupling effect between adjacent second conductive wires. A second voltage can be applied to the second conductive shielding wire, and the second conductive shielding wire can be used to reduce the coupling effect between adjacent transistors along the first direction.

[0183] Embodiments of the present disclosure also provide a memory, as Figure 31As shown, the memory includes a memory chip 153, and the memory chip 153 includes a storage area 101 and a virtual area 100 arranged along a second direction. Both the storage area 101 and the virtual area 100 include: an active column array; the active column array includes a plurality of active columns 102 arranged in an array along a first direction and a second direction, and the active columns 102 extend along a third direction; the first direction intersects with the second direction and is perpendicular to the third direction; a plurality of second conductive shielding lines 108; the plurality of second conductive shielding lines 108 are arranged along the first direction, and the second conductive shielding lines 108 extend along the second direction and are located between adjacent active columns 102 along the first direction; a plurality of first conductive shielding lines 125 and a plurality of second conductive lines 126; the second conductive lines 126 and the first conductive shielding lines 125 both extend along the first direction and are alternately arranged along the second direction, the second conductive lines 126 are connected to one end of the active columns 102, and the first conductive shielding lines 125 in the virtual area 100 are connected to the second conductive shielding lines 108.

[0184] In some embodiments, the memory further includes a fourth contact structure 128 located in the storage area 101 and the virtual area. The fourth contact structure 128 is located on a second side of the active columns 102, and the fourth contact structure 128 is connected to the first conductive shielding lines 125.

[0185] It can be understood that in the above embodiments, the first conductive shielding structure 105 in the virtual area 100 is connected to the second conductive shielding structure 107, so that the second conductive shielding structure 107 can be led out by using the first conductive shielding structure 105 in the virtual area 100, thus eliminating the contact structure of the second conductive shielding structure 107. This can reduce the burden on the formation area of the contact structure, reduce the process difficulty, reduce the process cost, expand the process window, and since the density of the finally formed contact structure is reduced, the performance of the memory can be improved.

[0186] Based on the above memory, an embodiment of the present disclosure further provides a memory system, including: one or more memories as described in any one of the above embodiments; a memory controller coupled to the memory and configured to control the memory.

[0187] In some specific examples, the memory system includes a solid-state drive and a memory. The above memory includes a dynamic random access memory. The memory in the above embodiments can be used as a buffer memory in a solid-state drive, or the memory in the above embodiments can be used as a storage medium in a memory.

[0188] Figure 35A schematic block diagram showing the composition of an exemplary electronic device according to an embodiment of the present application is shown. The electronic device 1 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory. As Figure 35 shown, the electronic device 1 may include a host HOST and a memory system 30, and the memory system 30 includes a memory controller 10 and one or more memory devices 20. The host HOST may be a processor of the electronic device (e.g., a Central Processing Unit (CPU) or a Graphic Processing Unit (GPU)). The host HOST may be configured to send data to or receive data from the memory device 20. The memory controller 10 is coupled to the memory device 20 and the host HOST, and is configured to control the memory device 20. The memory controller 10 may manage the data stored in the memory device 20 and communicate with the host HOST.

[0189] The memory controller 10 may be configured to control the operations of the memory device 20, such as read, erase, write, and refresh operations. In some embodiments, the memory controller 10 is further configured to process an Error Correction Code (ECC) for data read from or written to the memory device 20. The memory controller 10 may also perform any other suitable functions, such as formatting the memory device 20.

[0190] In some specific embodiments, the memory controller 10 and one or more memory devices 20 may be integrated into various types of electronic devices. For example, the memory controller 10 may be integrated into the north bridge of a computer motherboard or directly integrated into the computer CPU, and multiple memory devices 20 may be integrated into a memory module. That is, the memory system 30 may be implemented and packaged into different types of terminal electronic products.

[0191] The memory controller 10 can send data to / receive data from the host HOST, and can send a command CMD and an address ADDR to the memory device 20. The memory controller 10 can include a command generator 11, an address generator 12, a device interface 13, and a host interface 14. The host interface 14 can receive a command CMD and an address ADDR from the host HOST. The command generator 11 can generate an access command, a row hammer refresh command, etc. by decoding the command CMD received from the host HOST, and can provide the access command and the row hammer refresh command to the memory device 20 through the device interface 13. The access command can be a signal instructing the memory device 20 to write or read data by accessing a row of the memory cell array 22 corresponding to the address ADDR. The row hammer refresh command can be a signal commanding the memory device 20 to perform an additional refresh operation on a word line adjacent to the word line that has been intensively accessed within a short period. In other words, an additional refresh operation can be performed on a word line adjacent to the word line that has been accessed multiple times within a short period.

[0192] The address generator 12 in the memory controller 10 can generate a row address and a column address to be accessed in the memory cell array 22 by decoding the address ADDR received from the host interface 14. In addition, the memory device 20 can generate an address of the bank to be accessed when the memory cell array 22 includes multiple banks.

[0193] In addition, the memory controller 10 can control memory operations such as writing and reading by providing various signals to the memory device 20 via the device interface 13. For example, the memory controller 10 can provide a write command to the memory device 20. The write command is used to instruct the memory device 20 to perform a write operation to store data in the memory device 20.

[0194] In some embodiments, the memory device 20 includes a memory cell array 22 and peripheral circuits 21. The memory cell array 22 includes a plurality of banks, each bank includes a plurality of blocks, each block includes a plurality of memory cell rows and a plurality of memory cell columns, each memory cell row is coupled to a corresponding word line, and each memory cell column is coupled to a corresponding bit line. The peripheral circuits 21 can write data to the memory cell array 22 or read data from the memory cell array 22 based on a command CMD and an address ADDR received from the memory controller 10, or can provide a control signal CTRL for refreshing the memory cells included in the memory cell array 22 to a row decoding circuit and a column decoding circuit. In other words, the peripheral circuits 21 can perform all operations to process data in the memory cell array 22. The peripheral circuits 21 can include: control circuits corresponding to each memory block, such as a sensing amplifier (SA) and a word-line driver (WLD), etc., control circuits corresponding to each bank, such as a row decoding circuit, a column decoding circuit, etc., and control circuits corresponding to all banks, such as a command buffer, a command decoder, an address buffer, a data input / output buffer, a mode register, etc.

[0195] The memory device 20 can be a random access memory (RAM), such as a dynamic random access memory (DRAM), a synchronous DRAM (SDRAM), a static RAM (SRAM), a double data rate SDRAM (DDR SDRAM), a DDR2 SDRAM, a DDR3 SDRAM, a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), etc. Hereinafter, only DRAM will be taken as an example for illustration.

[0196] Figure 36 Schematic diagram of the composition block diagram of an exemplary SSD according to an embodiment of the present application. Here, the SSD can be understood as a kind of the foregoing Figure 35 memory system. In this example, the DRAM can be used as a buffer memory.

[0197] As Figure 36As shown, the SSD 30a may include an SSD controller 10a, a buffer memory 20a, and a non-volatile memory 40. The SSD controller 10a may provide a physical connection between the host HOST and the SSD 30a. That is, the SSD controller 10a may provide an interface between the host HOST and the SSD 30a in accordance with the bus format of the host. The SSD controller 10a may decode instructions provided from the host HOST. The SSD controller 10a may access the non-volatile memory 40 based on the decoded result. The buffer memory 20a may temporarily store write data provided from the host HOST or data read from the non-volatile memory 40. When the host HOST issues a read request, if the data present in the non-volatile memory 40 is cached, the buffer memory 20a may support a cache function for directly providing the cached data to the host HOST. The data transfer rate through the bus format of the host (e.g., SATA or SAS) is much higher than the data transfer rate of the memory channel of the SSD 30a. That is, when the interface speed of the host is significantly high, the performance degradation due to the speed difference may be minimized by providing a high-capacity buffer memory 20a. In addition, the buffer memory 20a may store an address mapping table of the non-volatile memory 40. The buffer memory 20a may include, but is not limited to, DRAM. The non-volatile memory 40 is set as the storage medium of the SSD 30a. The non-volatile memory 40 may include, but is not limited to, NAND-type memory.

[0198] Figure 37 Schematic diagram of the composition block diagram of an exemplary memory according to an embodiment of the present application; here, the memory may be understood as a kind of the memory system described above Figure 35 In this example, DRAM may be used as a storage medium.

[0199] As Figure 37 shown, the memory 30b can be easily attached or installed to an electronic device or detached from the electronic device 1 through the illustrated interface. The memory 30b may include a plurality of volatile memories 20b (e.g., DRAM) and a memory controller 10b. The memory module memory 30b can be used to write data, store data, obtain (or read) data, and / or erase data under the control of a controller of a processor of a computer. In some embodiments, the controller memory controller 10b may communicate with the DRAM using at least one communication protocol or technical standard commonly associated with, for example, dual in-line memory modules (DIMMs), registered DIMMs (RDIMMs), low-profile DIMMs (LRDIMMs), unregistered DIMMs (UDIMMs), etc.

[0200] It should be noted that Figure 36 the buffer memory 20a in Figure 37 and the volatile memory 20b inFigure 35 An application scenario of the memory device 20.

[0201] In several embodiments provided by the present disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored, or not executed. In addition, the couplings between the various components shown or discussed are either direct couplings.

[0202] The features disclosed in several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0203] As mentioned above, the above is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A manufacturing method of a memory, characterized in that, Including: Forming an active column array in a virtual region and a storage region; the active column array includes a plurality of active columns arranged in an array along a first direction and a second direction; the virtual region and the storage region are arranged along the first direction, and the active columns extend along a third direction; the first direction intersects with the second direction and is perpendicular to the third direction. Forming a plurality of first conductive parts in the virtual region and the storage region; the plurality of first conductive parts are arranged along the first direction, and the first conductive parts extend along the second direction and are located between adjacent active columns along the first direction. Forming a second conductive part and a first conductive shielding structure in both the virtual region and the storage region; the second conductive part and the first conductive shielding structure both extend along the first direction and are alternately arranged along the second direction, the second conductive part is connected to one end of the active column, and the first conductive part in the virtual region is connected to the first conductive shielding structure.

2. The manufacturing method according to claim 1, characterized in that, The forming of the active column array includes: Providing a substrate. Etching the substrate to form a plurality of first trenches arranged at intervals along the second direction; the first trenches extend along the first direction and the bottoms are located in the substrate. Forming a first dielectric layer in the first trenches. Etching the substrate and the first dielectric layer to form second trenches and third trenches arranged alternately along the first direction; wherein, the second trenches and the third trenches both extend along the second direction and the bottoms are located in the substrate, and the depths of the second trenches and the third trenches are less than the depth of the first trenches; the first trenches, second trenches, and third trenches divide the substrate into a plurality of the active columns.

3. The manufacturing method according to claim 2, characterized in that The method further includes: Forming a second conductive shielding structure in the second trenches; the second conductive shielding structure located in the virtual region is connected to the first conductive shielding structure.

4. The manufacturing method according to claim 3, wherein The forming of the second conductive shielding structure in the second trenches includes: Forming a second conductive shielding material layer covering the sidewalls of the second trenches in the second trenches from a first side of the active column. Etching the second conductive shielding material layer in the storage region from a second side of the active column to form a second conductive shielding structure; the first side and the second side are opposite sides of the active column along the third direction; the size of the second conductive shielding structure in the storage region along the third direction is less than the size of the second conductive shielding structure in the virtual region along the third direction.

5. The manufacturing method according to claim 3, characterized in that, The method further includes: Etching the second conductive shielding structure from the second side of the active column to form a plurality of second conductive shielding lines arranged along the second direction. Forming a first contact structure; the first contact structure includes a first sub-contact structure and a second sub-contact structure, the first sub-contact structure is connected to the second conductive shielding lines in the virtual region, and the second sub-contact structure is connected to the second conductive shielding lines in the storage region.

6. The manufacturing method according to claim 2, characterized in that, The method further includes: Thinning the substrate from the second side of the active column to expose the first dielectric layer, and the remaining substrate constitutes a plurality of semiconductor structures and a plurality of the active columns. The forming of the second conductive part includes: Form a first conductive material layer on the semiconductor structure; Perform a heat treatment on the semiconductor structure and the first conductive material layer to form the second conductive portion.

7. The manufacturing method according to claim 6, characterized in that, The forming of the first conductive portion includes: Form a second conductive material layer on the sidewalls and the bottom wall of the third trench from the first side of the active pillar; Remove a part of the second conductive material layer in the storage area from the second side of the active pillar to form a first filling region; the remaining second conductive material layer constitutes the first conductive portion, and the size of the first conductive portion in the storage area along the third direction is smaller than the size of the first conductive portion in the virtual area along the third direction.

8. The manufacturing method according to claim 7, characterized in that, The forming of the first conductive shielding structure includes: When removing a part of the second conductive material layer in the storage area from the second side of the active pillar, remove the first dielectric layer in the storage area located between adjacent semiconductor structures to form a second filling region; Form a second dielectric layer in the first filling region, and form the second dielectric layer and a third conductive material layer in the second filling region; the second dielectric layer in the second filling region is located between the third conductive material layer and the semiconductor structure; Remove the third conductive material layer to form a third filling region; Form a third dielectric layer and a fourth conductive material layer in the third filling region; the third dielectric layer is located between the fourth conductive material layer and the second dielectric layer, and the fourth conductive material layer constitutes the part of the first conductive shielding structure located in the storage area.

9. The manufacturing method according to claim 8, characterized in that, The forming of the first conductive portion and the first conductive shielding structure includes: After forming the second dielectric layer and the third conductive material layer in the second filling region, remove the first dielectric layer in the virtual area located between adjacent semiconductor structures to form a fourth filling region; Form a fifth conductive material layer in the fourth filling region; When removing the third conductive material layer, remove the fifth conductive material layer and the second conductive material layer in the virtual area to form a fifth filling region; When forming the third dielectric layer and the fourth conductive material layer in the third filling region, form the fourth conductive material layer and the third dielectric layer in the fifth filling region; the third dielectric layer in the virtual area is at least located between the fourth conductive material layer and the semiconductor structure; the fourth conductive material layer located between adjacent semiconductor structures in the virtual area constitutes the part of the first conductive shielding structure located in the virtual area, and the remaining fourth conductive material layer in the virtual area constitutes the first conductive portion of the virtual area.

10. The manufacturing method according to claim 8, wherein, The method further includes: Before forming the first filling region and the second filling region, form a protective layer covering the virtual area from the second side of the active pillar; After forming the second dielectric layer in the first filling region and forming the second dielectric layer and the third conductive material layer in the second filling region, remove the protective layer.

11. The manufacturing method according to claim 1, wherein The method further includes: Etch the first conductive portion from the second side of the active pillar to form a plurality of first conductive wires arranged along the second direction; Form a second contact structure from the second side of the active pillar; the second contact structure includes a third sub-contact structure and a fourth sub-contact structure, the third sub-contact structure is connected to the first conductive wire of the storage area, and the fourth sub-contact structure is connected to the first conductive wire of the virtual area.

12. A memory, characterized in that, The memory includes a memory chip, the memory chip includes a storage area and a virtual area arranged along a first direction, and both the storage area and the virtual area include: An active pillar array; the active pillar array includes a plurality of active pillars arranged in an array along a first direction and a second direction, the active pillars extend along a third direction; the first direction intersects with the second direction and is perpendicular to the third direction; A plurality of first conductive wires; a plurality of the first conductive wires are arranged along the first direction, the first conductive wires extend along the second direction and are located between adjacent active pillars along the first direction; A plurality of first conductive shielding wires and a plurality of second conductive wires; the second conductive wires and the first conductive shielding wires both extend along the first direction and are alternately arranged along the second direction, the second conductive wires are connected to one end of the active pillars, and the first conductive wires in the virtual area are connected to the first conductive shielding wires.

13. The memory according to claim 12, wherein The storage area and the virtual area further include: A plurality of second conductive shielding wires; the second conductive shielding wires extend along the second direction and are located between adjacent first conductive wires; the second conductive shielding wires located in the virtual area are connected to the first conductive shielding wires.

14. The memory according to claim 13, wherein The size of the second conductive shielding wire located in the storage area along the third direction is smaller than the size of the second conductive shielding wire located in the virtual area along the third direction.

15. The memory according to claim 13, wherein The memory further includes a first contact structure; the first contact structure includes a first sub-contact structure and a second sub-contact structure, the first contact structure is located on the second side of the active pillar, and the first sub-contact structure is connected to the second conductive shielding wire of the virtual area, and the second sub-contact structure is connected to the second conductive shielding wire of the storage area.

16. The memory according to claim 12, characterized in that, The memory further includes a second contact structure; the second contact structure includes a third sub-contact structure and a fourth sub-contact structure, the second contact structure is located on the second side of the active pillar, and the third sub-contact structure is connected to the first conductive wire of the storage area, and the fourth sub-contact structure is connected to the first conductive wire of the virtual area.

17. The memory according to claim 12, wherein The size of the first conductive wire located in the storage area along the third direction is smaller than the size of the first conductive wire located in the virtual area along the third direction.

18. The memory according to claim 12, wherein The storage area further includes: a second dielectric layer; the second dielectric layer is located between the first conductive wire and the first conductive shielding wire, between the first conductive shielding wire and the second conductive wire, and between the first conductive wire and the second conductive wire.

19. The memory according to claim 18, wherein The storage area and the virtual area further include: a third dielectric layer; wherein, the third dielectric layer in the virtual area is located between the second conductive line and the first conductive shielding line in the virtual area, and between the second conductive line and the first conductive line in the virtual area; the third dielectric layer in the storage area is located between the first conductive shielding line and the second dielectric layer in the storage area.

20. A memory system, characterized in that, Comprising: One or more memories as claimed in any one of claims 12 to 19; A memory controller coupled to the memory and configured to control the memory.

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