Memory device and method of manufacturing the same

Abstract

The invention provides a memory device and a manufacturing method thereof. The manufacturing method of the memory device includes placing a plurality of first layers and a plurality of second layers in a staggered manner along a first direction; a first hole; forming a first channel structure on one edge of the first hole; forming a first source electrode structure and a first drain electrode structure in the first hole; a first charge trap structure is formed around the first channel structure, wherein the material of the first layer is different from the material of the second layer.

Description

Technical Field

[0001] The present invention relates to a memory technology, and more particularly to a memory device and a method of manufacturing the same. Background Art

[0002] Semiconductor chips can be formed by metal oxide semiconductor field effect transistors (MOSFETs). However, MOSFETs have a relatively high subthreshold swing, resulting in high power consumption. Therefore, how to design to solve the above problems is an important issue in this field. Summary of the Invention

[0003] An embodiment of the present invention includes a method of manufacturing a memory device. The manufacturing method includes: placing a plurality of first layers and a plurality of second layers alternately along a first direction; a first hole; forming a first channel structure at one edge of the first hole; forming a first source structure and a first drain structure in the first hole; and forming a first charge trap structure around the first channel structure, wherein the material of the first layer is different from that of the second layer.

[0004] In some embodiments, the manufacturing method further includes: forming a first intermediate structure at an inner edge of the first channel structure; and forming a first isolation structure at an inner edge of the first intermediate structure, wherein the first isolation structure is located between the first source structure and the first drain structure.

[0005] In some embodiments, the manufacturing method further includes: etching the first intermediate structure to form a second hole; stopping etching the first intermediate structure when the second hole contacts each of the first channel structure and the first isolation structure; and forming a first source structure in the second hole.

[0006] In some embodiments, the manufacturing method further includes: after forming the first source structure, etching the first intermediate structure to form a third hole; stopping etching the first intermediate structure when the third hole contacts each of the first channel structure and the first isolation structure; and forming a first drain structure in the third hole.

[0007] In some embodiments, the manufacturing method further includes: etching the first layer and the second layer to form a second hole separated from the first hole along the first direction; forming a second channel structure at one edge of the second hole; forming a second source structure and a second drain structure in the first hole; and forming a first charge trap structure around the second channel structure.

[0008] In some embodiments, the manufacturing method further includes: removing a first layer; and after removing the first layer, forming a first gate structure between second layers.

[0009] In some embodiments, after forming each of the first source structure and the first drain structure, the first layers are removed.

[0010] In some embodiments, before forming the first gate structure, a first charge trap structure is formed, and multiple gate portions of the first gate structure are located between multiple charge trap portions of the first charge trap structure.

[0011] Embodiments of the present invention include a memory device. The memory device includes a first source structure, a first drain structure, a channel structure surrounding each of the first source structure and the first drain structure, a charge trap structure surrounding the channel structure, and a gate structure surrounding the charge trap structure.

[0012] In some embodiments, the memory device further includes a first isolation structure. The first isolation structure is located between the first source structure and the first drain structure and is used to isolate the first source structure and the first drain structure, wherein the materials of the first source structure, the first drain structure, and the first isolation structure are different from each other.

[0013] In some embodiments, the memory device further includes an oxide layer. The oxide layer is placed between a first gate portion of the gate structure and a second gate portion of the gate structure and surrounds the charge trap structure.

[0014] In some embodiments, the memory device further includes a second source structure, a second drain structure, and a second channel structure separated from the first channel structure and surrounding each of the second source structure and the second drain structure. The charge trap structure surrounds the second channel structure.

[0015] In some embodiments, the first source structure and the first drain structure correspond to multiple transistors of a first memory row, the second source structure and the second drain structure correspond to multiple transistors of a second memory row, each of the transistors of the first memory row is used to receive a first source line signal, and each of the transistors of the second memory row is used to receive a second source line signal different from the first source line signal.

[0016] In some embodiments, a first transistor of the transistors of the first memory row and a second transistor of the transistors of the second memory row share the second gate portion.

[0017] An embodiment of the present invention includes a memory device. The memory device includes a plurality of memory blocks. The memory blocks are used to generate a plurality of bit line signals. Each of the memory blocks includes a plurality of memory rows for storing a plurality of data characters. A first memory block of the memory blocks is used to compare a search character and these data characters to generate these bit line signals. Each of the memory rows includes a plurality of transistors. Each of the plurality of gates of the transistors is used to receive a plurality of word line signals carrying the search character, and the gates surround a plurality of sources and a plurality of drains of these transistors.

[0018] An embodiment of the present invention includes a method for manufacturing a memory device. The manufacturing method includes: forming a first channel structure; forming a first isolation structure surrounded by the first channel structure; forming a first source structure and a first drain structure, wherein the first isolation structure is located between the first source structure and the first drain structure; forming a charge trap structure surrounding the first channel structure; and forming a gate structure surrounding the charge trap structure.

[0019] In some embodiments, the manufacturing method further includes: forming a second channel structure separated from the first channel structure; forming a second isolation structure surrounded by the second channel structure; and forming a second source structure and a second drain structure, wherein the second isolation structure is located between the second source structure and the second drain structure, and the charge trap structure surrounds the second channel structure.

[0020] In some embodiments, the manufacturing method further includes: staggering a plurality of first layers and a plurality of second layers in a first direction; etching the first layers and the second layers to form a first hole extending in the first direction; forming a first channel structure in the first hole; and removing the first layers after the first drain structure is formed.

[0021] In some embodiments, the material of the first isolation structure is the same as the material of the first layers.

[0022] In some embodiments, the manufacturing method further includes: forming an intermediate structure on an inner edge of the first channel structure; and etching the intermediate structure to form a second hole and a third hole separated from each other, wherein the first source structure and the first drain structure are respectively formed in the second hole and the third hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 FIG. is a schematic diagram of a memory system according to some embodiments of the present invention.

[0024] Figures 2A through 2I FIG. is a schematic diagram of process steps for manufacturing a memory device according to some embodiments of the present invention.

[0025] Figure 2JA side view schematic diagram of the process steps for manufacturing a memory device according to some embodiments of the present invention.

[0026] Figure 2K A side view schematic diagram of the process steps for manufacturing a memory device according to some embodiments of the present invention.

[0027] Figure 2L A schematic diagram of the process steps for manufacturing a memory device according to some embodiments of the present invention.

[0028] Figure 2M A top view of a part of a memory device manufactured according to some embodiments of the present invention.

[0029] Figure 3A A schematic diagram of the relationship between the gate voltage signal and the current signal applied to the gate structure according to some embodiments of the present invention.

[0030] Figure 3B A schematic diagram of various scenarios for a search operation of a transistor formed by a channel structure, a charge trap structure, a source structure, and a drain structure in a memory device according to some embodiments of the present invention.

[0031] Figure 4 A schematic diagram of a memory device according to some embodiments of the present invention.

[0032] Explanation of reference numerals:

[0033] 100A: Memory system

[0034] 140: Encoding device

[0035] 150, 159: Memory arrays

[0036] 130, 135: Page buffers

[0037] 191: Combining and sorting device

[0038] 160: Data encoder

[0039] 170: Search encoder

[0040] 110: Data signal

[0041] 111: Encoded data signal

[0042] 171: String selection line signal

[0043] 172: Word line signal

[0044] 180: Bit line signal

[0045] 190: Search Results

[0046] 200, 400: Memory Devices

[0047] OP21~OP212: Process Steps

[0048] 220~224: Oxide Layers

[0049] 211~213: Nitride Layers

[0050] VCH1~VCH6: Holes

[0051] PC1, PC2: Channel Structures

[0052] OX1, OX2: Intermediary Structures

[0053] SN1, SN2: Isolation Structures

[0054] SS1, SS2: Source Structures

[0055] DS1, DS2: Drain Structures

[0056] SP1: Separation Portion

[0057] BK1, BK2, BK(i), BK(i+1): Blocks

[0058] CTS1: Charge Trap Structure

[0059] CTP1~CTP9: Charge Trap Portions

[0060] GS1: Gate Structure

[0061] GP1~GP3: Gate Portions

[0062] I1: Current Signal

[0063] CV1~CV3: Curves

[0064] LVSL, HVSL: Voltage Levels

[0065] IL, IH: Current Levels

[0066] VG: Gate Voltage Signal

[0067] LVT, HVT, MVT: Threshold Voltage Levels

[0068] SLIT(i), SLIT(i+1): Slits

[0069] CL(i)_1, CL(i)_n, CL(i+1)_1, CL(i+1)_n: Memory Rows

[0070] T(i)_1_1, T(i)_1_m+1, T(i)_n_1, T(i)_n_m+1, T(i+1)_n_1, T(i+1)_n_m+1: Transistors

[0071] WL(i)_1, WL(i)_m, WL(i)_m+1, WL(i+1)_m, WL(i+1)_m+1: Word line signals

[0072] BL1, BLn-1, BLn: Bit line signals

[0073] SL1, SLn-1, SLn: Source line signals

[0074] SW1: Search character

[0075] DW1, DWn: Data characters

[0076] X, Y, Z: Directions Detailed implementation manners

[0077] In this document, when an element is referred to as "connected" or "coupled", it may mean "electrically connected" or "electrically coupled". "Connected" or "coupled" can also be used to indicate the cooperative operation or interaction between two or more elements. In addition, although terms such as "first", "second",... are used in this document to describe different elements, these terms are only used to distinguish elements or operations described with the same technical terms. Unless the context clearly indicates otherwise, these terms do not particularly refer to or imply an order or sequence, nor are they used to limit the present invention.

[0078] Unless otherwise defined, all terms used in this document (including technical and scientific terms) have the same meaning as commonly understood by those of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this invention, and will not be interpreted in an idealized or overly formal sense unless clearly defined as such in this document.

[0079] The terms used herein are for the purpose of describing particular embodiments only and are not limiting. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include the plural forms, including "at least one". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It should also be understood that when used in this specification, the terms "comprises" and / or "comprising" specify the presence of the stated features, regions, wholes, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, components, and / or combinations thereof.

[0080] Embodiments of the present invention will be disclosed below with reference to the drawings. For the sake of clarity, many practical details will be described in the following description. However, it should be understood that these practical details are not used to limit the present invention. That is to say, in some embodiments of the present invention, these practical details are not necessary. In addition, for the sake of simplifying the drawings, some conventional structures and elements will be shown in a simple schematic manner in the drawings.

[0081] Figure 1 FIG. is a schematic diagram of a memory system 100A according to some embodiments of the present invention. In some embodiments, the memory system 100A can be implemented by an in-memory search system of a three-dimensional tunneling field effect transistor (3D Tunnel Field Effect Transistor, TFET) memory. As Figure 1 shown, the memory system 100A includes an encoding device 140, memory arrays 150, 159, page buffers 130, 135, and a combined sorting device 191. The encoding device 140 may include a data encoder 160 and a search encoder 170. The memory array 150 may include a plurality of three-dimensionally arranged TFETs.

[0082] In some embodiments, the data encoder 160 is configured to receive a data signal 110 and generate an encoded data signal 111. The search encoder 170 is configured to receive a search signal 120 and generate a string select line (SSL) signal 171 and a word line (WL) signal 172. The memory array 150 is configured to receive the encoded data signal 111, the string select line signal 171, and the word line signal 172 and generate a bit line (BL) signal 180. The page buffer 130 is configured to receive the bit line signal 180 and output it to the combined sorting device 191. The combined sorting device 191 is configured to process the output of the bit line signal 180 to generate a search result 190.

[0083] In some embodiments, the processing of the bit line signal 180 by the combining and sorting device 191 includes AND logic, OR logic, or counting logic processing, and may also include combined processing of the above three logics. Please refer to Figures 2A - 2M AND Figure 4 , the combining and sorting device 191 can receive the sensing results from the memory devices 200 and / or 400, and control sorting (which can be serial or parallel) and combine the sensing results to generate an overall search result as the search result 190.

[0084] In some embodiments, the memory system 100A can be implemented on a single integrated circuit chip, multiple integrated circuits, or as a component of a System-On-a-Chip (SOC). As a specific example, the memory system 100A is implemented on a single integrated circuit chip and is capable of performing search and combined logical operations in the single integrated circuit chip.

[0085] Figure 2A FIG. is a schematic diagram of the process step OP21 for manufacturing the memory device 200 according to some embodiments of the present invention. Please refer to Figure 1 AND Figure 2A , the memory device 200 can be an embodiment of the memory array 150.

[0086] As Figure 2A shown, the memory device 200 includes a plurality of nitride layers 210 and a plurality of oxide layers 220. In Figure 2A the embodiment shown, the nitride layer 210 includes three nitride layers 211 to 213, and the oxide layer 220 includes three oxide layers 221 to 223. However, the embodiments of the present invention are not limited thereto. In various embodiments, the nitride layer 210 and the oxide layer 220 can have various numbers of layers.

[0087] In some embodiments, the nitride layer 210 and the oxide layer 220 are alternately arranged in the Z direction. In other words, in the Z direction, the oxide layer 221, the nitride layer 211, the oxide layer 222, the nitride layer 212, the oxide layer 223, and the nitride layer 213 are arranged in sequence. In some embodiments, the stack of the nitride layer 210 and the oxide layer 220 is referred to as an oxide nitride stack (ON stack). In some embodiments, the material of the nitride layer 210 is silicon nitride. The material of the oxide layer 220 is silicon dioxide.

[0088] In some embodiments, a manufacturing apparatus (not shown in the figures) may perform process step OP21. In process step OP21, the manufacturing apparatus etches the nitride layer 210 and the oxide layer 220 along the Z direction to form holes VCH1 and VCH2. In some embodiments, process step OP21 is referred to as vertical channel hole etching.

[0089] As Figure 2A shown, the holes VCH1 and VCH2 extend through the nitride layer 210 and the oxide layer 220 and are separated from each other. In some embodiments, each of the holes VCH1 and VCH2 generally has the shape of a cylinder.

[0090] Figure 2B FIG. is a schematic diagram of process step OP22 for manufacturing the memory device 200 according to some embodiments of the present invention. In process step OP22, the manufacturing apparatus sequentially fills the holes VCH1 and VCH2 with a channel material, an oxide material, and a nitride material to form channel structures PC1, PC2, intermediate structures OX1, OX2, and isolation structures SN1, SN2.

[0091] Specifically, first, the manufacturing apparatus forms the channel structure PC1 on the inner edge of the hole VCH1 and forms the channel structure PC2 on the inner edge of the hole VCH2. Next, the manufacturing apparatus forms the intermediate structure OX1 on the inner edge of the channel structure PC1 and forms the intermediate structure OX2 on the inner edge of the channel structure PC2. Finally, the manufacturing apparatus forms the isolation structure SN1 on the inner edge of the intermediate structure OX1 and forms the isolation structure SN2 on the inner edge of the intermediate structure OX2. In other words, the intermediate structures OX1 and OX2 respectively surround the isolation structures SN1 and SN2, and the channel structures PC1 and PC2 respectively surround the intermediate structures OX1 and OX2.

[0092] In some embodiments, the materials of the channel structures PC1 and PC2 are intrinsic poly-silicon. The materials of the intermediate structures OX1 and OX2 are oxides, such as silicon dioxide. The materials of the isolation structures SN1 and SN2 are silicon nitride.

[0093] Figure 2C FIG. is a schematic diagram of process step OP23 for manufacturing the memory device 200 according to some embodiments of the present invention. In process step OP23, the manufacturing apparatus performs plug etching on the intermediate structures OX1 and OX2 along the Z direction to generate holes VCH3 and VCH4.

[0094] As Figure 2CAs shown, holes VCH3 and VCH4 respectively extend through intermediate structures OX1 and OX2. Hole VCH3 is located between isolation structure SN1 and channel structure PC1 and is separated from isolation structure SN1 and channel structure PC1. Hole VCH4 is located between isolation structure SN2 and channel structure PC2 and is separated from isolation structure SN2 and channel structure PC2. In some embodiments, each of holes VCH3 and VCH4 generally has the shape of a cylinder.

[0095] Figure 2D FIG. is a schematic diagram of process step OP24 for manufacturing memory device 200 according to some embodiments of the present invention. In process step OP24, the manufacturing apparatus performs a plug pullback process step on holes VCH3 and VCH4.

[0096] Specifically, the manufacturing apparatus can pour hydrofluoric acid into holes VCH3 and VCH4 to etch intermediate structures OX1 and OX2 from holes VCH3 and VCH4, so that the sizes of holes VCH3 and VCH4 increase.

[0097] Next, when hole VCH3 contacts each of the inner edge of channel structure PC1 and isolation structure SN1, and hole VCH4 contacts each of the inner edge of channel structure PC2 and isolation structure SN2, process step OP24 stops.

[0098] Figure 2E FIG. is a schematic diagram of process step OP25 for manufacturing memory device 200 according to some embodiments of the present invention. In process step OP25, the manufacturing apparatus fills source materials into holes VCH3 and VCH4 to form source structures SS1 and SS2.

[0099] In some embodiments, the manufacturing apparatus simultaneously performs chemical vapor deposition (CVD) and doping. Correspondingly, source structures SS1 and SS2 are simultaneously formed and doped with P-type atoms, so that source structures SS1 and SS2 are formed of P-rich materials. In some embodiments, the source materials for forming source structures SS1 and SS2 are P-rich polysilicon.

[0100] In some embodiments, after the source materials are filled into holes VCH3 and VCH4, the manufacturing apparatus further performs chemical-mechanical polishing (CMP) to polish source structures SS1 and SS2 in the Z direction, so that the height of each of source structures SS1 and SS2 is the same as the height of each of channel structures PC1, PC2, intermediate structures OX1, OX2, and isolation structures SN1, SN2.

[0101] Figure 2F A schematic diagram of process step OP26 for manufacturing the memory device 200 according to some embodiments of the present invention. In process step OP26, the manufacturing device performs plug etching on the intermediate structures OX1 and OX2 along the Z direction to generate holes VCH5 and VCH6.

[0102] As Figure 2F shown, the holes VCH5 and VCH6 respectively extend through the intermediate structures OX1 and OX2. The hole VCH5 is located between the isolation structure SN1 and the channel structure PC1 and is separated from the isolation structure SN1 and the channel structure PC1. The hole VCH6 is located between the isolation structure SN2 and the channel structure PC2 and is separated from the isolation structure SN2 and the channel structure PC2. In some embodiments, each of the holes VCH5 and VCH6 generally has the shape of a cylinder.

[0103] Figure 2G A schematic diagram of process step OP27 for manufacturing the memory device 200 according to some embodiments of the present invention. In process step OP27, the manufacturing device performs a plug recession process step on the holes VCH5 and VCH6.

[0104] Specifically, the memory device 200 can pour hydrofluoric acid into the holes VCH5 and VCH6 to etch the intermediate structures OX1 and OX2 from the holes VCH5 and VCH6, so that the sizes of the holes VCH5 and VCH6 increase.

[0105] Next, when the hole VCH5 contacts each of the inner side of the channel structure PC1 and the isolation structure SN1, and the hole VCH6 contacts each of the inner side of the channel structure PC2 and the isolation structure SN2, the process step OP27 stops.

[0106] Figure 2H A schematic diagram of process step OP28 for manufacturing the memory device 200 according to some embodiments of the present invention. In process step OP28, the manufacturing device fills the holes VCH5 and VCH6 with drain material to form drain structures DS1 and DS2.

[0107] In some embodiments, the manufacturing device performs chemical vapor deposition and doping simultaneously. Correspondingly, the drain structures DS1 and DS2 are formed and doped with N-type atoms at the same time, so that the drain structures DS1 and DS2 are formed of N-rich materials. In some embodiments, the drain material for forming the drain structures DS1 and DS2 is N-rich polysilicon.

[0108] In some embodiments, after filling the drain materials into the holes VCH5 and VCH6, the manufacturing apparatus is further configured to perform chemical mechanical polishing to polish the drain structures DS1 and DS2 in the Z direction such that the height of each of the drain structures DS1 and DS2 is the same as the height of each of the channel structures PC1, PC2, the intermediate structures OX1, OX2, and the isolation structures SN1, SN2.

[0109] As Figure 2H shown, in the X direction, the source structure SS1 and the drain structure DS1 are respectively located on opposite sides of the isolation structure SN1. The source structure SS2 and the drain structure DS2 are respectively located on opposite sides of the isolation structure SN2. In some embodiments, the source structures SS1, SS2 and the drain structures DS1, DS2 have the same size. In some embodiments, the sizes of the source structures SS1, SS2 and the drain structures DS1, DS2 are larger than the size of each of the isolation structures SN1 and SN2.

[0110] Figure 2I FIG. is a schematic diagram of a process step OP29 of manufacturing a memory device 200 according to some embodiments of the present invention. In the process step OP29, the manufacturing apparatus performs slit etching on the memory device 200 to form a separation portion SP1.

[0111] As Figure 2I shown, the memory device 200 includes blocks BK1 and BK2. In the X direction, the blocks BK1 and BK2 are separated from each other by the separation portion SP1. In some embodiments, the manufacturing apparatus may form more separation portions to divide the memory device 200 into more blocks.

[0112] Figure 2J FIG. is a side view schematic diagram of a process step OP210 of manufacturing a memory device 200 according to some embodiments of the present invention. In Figure 2J this figure, the Y direction is the direction into the paper. In the process step OP210, the manufacturing apparatus removes the nitride layer 210. At this time, in the Z direction, the oxide layers 221 - 223 are separated from each other, and there is no nitride layer 210 between the two of the oxide layers 221 - 223. In the X direction, the channel structures PC1 and PC2 are separated from each other, and there is no nitride layer 210 between the channel structures PC1 and PC2.

[0113] Figure 2K FIG. is a side view schematic diagram of a process step OP211 of manufacturing a memory device 200 according to some embodiments of the present invention. In Figure 2K this figure, the Y direction is the direction into the paper. In the process step OP211, the manufacturing apparatus forms a charge trap structure CTS1 on the surfaces of the oxide layers 221 - 223 and the channel structures PC1, PC2.

[0114] As Figure 2K shown, the charge trap structure CTS1 includes charge trap portions CTP1 to CTP8. In the Z direction, the charge trap portion CTP2 covers the upper surface of the oxide layer 223, the charge trap portion CTP3 covers the lower surface of the oxide layer 223, the charge trap portion CTP5 covers the upper surface of the oxide layer 222, the charge trap portion CTP6 covers the lower surface of the oxide layer 222, and the charge trap portion CTP8 covers the upper surface of the oxide layer 221.

[0115] On the other hand, the charge trap portion CTP1 is located above the charge trap portion CTP2 and surrounds the channel structures PC1 and PC2. The charge trap portion CTP4 is located between the charge trap portions CTP3 and CTP5 and surrounds the channel structures PC1 and PC2. The charge trap portion CTP7 is located between the charge trap portions CTP6 and CTP8 and surrounds the channel structures PC1 and PC2.

[0116] In some embodiments, the charge trap structure CTS1 can be implemented by an oxide-nitride-oxide (ONO) material. In some embodiments, the process step OP211 is referred to as ONO deposition.

[0117] Figure 2L FIG. is a schematic diagram of the process step OP212 for manufacturing the memory device 200 according to some embodiments of the present invention. In the process step OP212, the manufacturing device forms the gate structure GS1. In Figure 2L the illustrated embodiment, the oxide layer 220 further includes an oxide layer 224, and the charge trap structure CTS1 further includes a charge trap portion CTP9. In the Z direction, the oxide layer 224 is located above the charge trap portion CTP9.

[0118] As Figure 2L shown, the gate structure GS1 includes gate portions GP1 to GP3. The gate portion GP1 is sandwiched between the charge trap portions CTP9 and CTP2 and surrounds the charge trap portion CTP1. The gate portion GP2 is sandwiched between the charge trap portions CTP3 and CTP5 and surrounds the charge trap portion CTP4. The gate portion GP3 is sandwiched between the charge trap portions CTP6 and CTP8 and surrounds the charge trap portion CTP7. In some embodiments, the gate structure GS1 can be implemented by tungsten (W). In some embodiments, the process step OP212 is referred to as tungsten gate deposition.

[0119] Please refer to Figures 2J through 2L, in process steps OP210 to OP212, the nitride layer 210 is replaced by the gate structure GS1 and the charge trap structure CTS1. Correspondingly, process steps OP210 to OP212 can be referred to as gate replacement process steps. In some embodiments, process steps OP21 to OP212 are performed in sequence.

[0120] Figure 2M FIG. 4 is a top view of a part of the manufacturing memory device 200 according to some embodiments of the present invention. In Figure 2M , the Z direction is the direction out of the paper.

[0121] As Figure 2M shown, in the X-Y plane, the gate structure GS1 surrounds the charge trap structure CTS1. The charge trap structure CTS1 surrounds the channel structure PC1. The channel structure PC1 surrounds the intermediate structure OX1, the source structure SS1, the drain structure DS1, and the isolation structure SN1. In the X direction, the isolation structure SN1 is located between the source structure SS1 and the drain structure DS1 to isolate the source structure SS1 and the drain structure DS1 from each other.

[0122] In some embodiments, the gate structure GS1, the source structure SS1, and the drain structure DS1 can respectively operate as the gates, sources, and drains of multiple transistors. Similarly, Figure 2L the gate structure GS2, the source structure SS2, and the drain structure DS2 in

[0123] can also respectively operate as the gates, sources, and drains of multiple transistors.

[0124] In some practices, semiconductor chips can be formed by metal oxide semiconductor field effect transistors (MOSFETs). However, MOSFETs have a relatively high subthreshold swing, resulting in high power consumption.

[0125] In an embodiment of the present invention, compared with the above approach, the memory device 200 is formed by a source structure SS1 and a drain structure DS1. The source structure SS1 has P-type dopants, and the drain structure DS1 has N-type dopants, such that the memory device 200 can operate as a TFET. The TFET has a lower subthreshold swing and a lower off-current, resulting in lower power consumption.

[0126] Figure 3A FIG. 300 is a schematic diagram showing the relationship between the gate voltage signal VG applied to the gate structure GS1 and the current signal I1 according to some embodiments of the present invention. The horizontal axis of FIG. 300 corresponds to the voltage level of the gate voltage signal VG. The vertical axis of FIG. 300 corresponds to the current level of the current signal I1 and is represented in a logarithmic scale.

[0127] As Figure 3A shown, FIG. 300 includes curves CV1 to CV3. The curves CV1 to CV3 respectively represent three states of the transistor through which the current signal I1 flows. In the state corresponding to curve CV1, the transistor is used to store the logic value 0. In the state corresponding to curve CV2, the transistor is used to store the logic value X. In some embodiments, the logic value X represents a don't care logic value. In the state corresponding to curve CV3, the transistor is used to store the logic value 1.

[0128] As Figure 3A shown, when the gate voltage signal VG has a voltage level LVSL, each of the current signals I1 corresponding to curves CV1 and CV2 has a current level IL, and the current signal I1 corresponding to curve CV3 has a current level IH. When the gate voltage signal VG has a voltage level HVSL, each of the current signals I1 corresponding to curves CV3 and CV2 has a current level IL, and the current signal I1 corresponding to curve CV1 has a current level IH. In some embodiments, the voltage level HVSL is greater than the voltage level LVSL, and the current level IH is greater than the current level IL.

[0129] Figure 3B FIG. shows various scenarios of a search operation performed on a transistor formed by a channel structure PC1, a charge trap structure CTS1, a source structure SS1, and a drain structure DS1 in the memory device 200 according to some embodiments of the present invention. During the search operation, the memory device 200 can compare the logic value of the data bit DT1 stored in the transistor with the logic value of the search bit SB1 carried by the gate voltage signal VG to generate a corresponding current signal I1. As Figure 3B shown, the transistor can operate in six scenarios. The six scenarios are arranged in two rows and three columns.

[0130] In the scenario of the first row, the search bit SB1 has a logic value of 0, such that the gate voltage signal VG has a voltage level LVSL. In the scenario of the second row, the search bit SB1 has a logic value of 1, such that the gate voltage signal VG has a voltage level HVSL.

[0131] In the scenario of the first column, the data bit DT1 has a logic value of 0, such that the transistor has a threshold voltage level LVT. In the scenario of the second column, the data bit DT1 has a logic value of 1, such that the transistor has a threshold voltage level HVT. In the scenario of the third column, the data bit DT1 has a logic value of X, such that the transistor has a threshold voltage level MVT. In some embodiments, the threshold voltage level HVT is greater than the threshold voltage level MVT, and the threshold voltage level MVT is greater than the threshold voltage level LVT.

[0132] In some embodiments, the amount of charge in the charge trap structure CTS1 is proportional to the threshold voltage level of the transistor. In other words, in the scenario of the first column, the amount of charge in the charge trap structure CTS1 is the least. In the scenario of the second column, the amount of charge in the charge trap structure CTS1 is the most. In the scenario of the third column, the amount of charge in the charge trap structure CTS1 is between the scenario of the first column and the scenario of the second column.

[0133] As Figure 3B shown, in the scenarios of the first row and the second column and the second row and the first column, in response to the different logic values of the data bit DT1 and the search bit SB1, the current signal I1 has a current level IH. In the other four scenarios, in response to the same logic values of the data bit DT1 and the search bit SB1, the current signal I1 has a current level IL. The logic value X can correspond to the logic value 0 or the logic value 1.

[0134] Figure 4 is a schematic diagram of a memory device 400 illustrated according to some embodiments of the present invention. As Figure 4 shown, the memory device 400 may include a plurality of memory blocks, such as memory blocks BK(i) and BK(i + 1), where i is a positive integer. For simplicity, other memory blocks, such as the memory block BK(i - 1) are not shown in Figure 4 here.

[0135] In some embodiments, the memory device 400 further includes slits SLIT(i) and SLIT(i + 1). The slit SLIT(i) is used to separate the block memory blocks BK(i) and BK(i + 1). The slit SLIT(i + 1) is used to separate the block memory blocks BK(i + 1) and BK(i + 2).

[0136] As Figure 4As shown, memory block BK(i) includes memory rows CL(i)_1 to CL(i)_n, where n is a positive integer. Memory row CL(i)_1 includes transistors T(i)_1_1 to T(i)_1_m+1, where m is a positive integer. Memory row CL(i)_2 includes transistors T(i)_2_1 to T(i)_2_m+1, and so on. Memory row CL(i)_n includes transistors T(i)_n_1 to T(i)_n_m+1.

[0137] Similarly, memory block BK(i+1) includes memory rows CL(i+1)_1 to CL(i+1)_n. Memory row CL(i+1)_1 includes transistors T(i+1)_1_1 to T(i+1)_1_m+1. Memory row CL(i+1)_2 includes transistors T(i+1)_2_1 to T(i+1)_2_m+1, and so on. Memory row CL(i+1)_n includes transistors T(i+1)_n_1 to T(i+1)_n_m+1.

[0138] In some embodiments, each of the gates of transistors T(i)_1_1 to T(i)_n_1 is used to receive word line signal WL(i)_1. Each of the gates of transistors T(i)_1_2 to T(i)_n_2 is used to receive word line signal WL(i)_2, and so on. Each of the gates of transistors T(i)_1_m+1 to T(i)_n_m+1 is used to receive word line signal WL(i)_m+1.

[0139] Similarly, each of the gates of transistors T(i+1)_1_1 to T(i+1)_n_1 is used to receive word line signal WL(i+1)_1. Each of the gates of transistors T(i+1)_1_2 to T(i+1)_n_2 is used to receive word line signal WL(i+1)_2, and so on. Each of the gates of transistors T(i+1)_1_m+1 to T(i+1)_n_m+1 is used to receive word line signal WL(i+1)_m+1. Please refer to Figure 4 and Figure 3A , word line signals WL(i)_1 to WL(i)_m+1 and WL(i+1)_1 to WL(i+1)_m+1 are examples of gate voltage signal VG.

[0140] In some embodiments, the drains of transistors T(i)_1_1 to T(i)_1_m+1 and T(i+1)_1_1 to T(i+1)_1_m+1 are used to output bit line signal BL1. The drains of transistors T(i)_2_1 to T(i)_2_m+1 and T(i+1)_2_1 to T(i+1)_2_m+1 are used to output bit line signal BL2, and so on. The drains of transistors T(i)_n_1 to T(i)_n_m+1 and T(i+1)_n_1 to T(i+1)_n_m+1 are used to output bit line signal BLn.

[0141] In some embodiments, the sources of transistors T(i)_1_1 to T(i)_1_m+1 and T(i+1)_1_1 to T(i+1)_1_m+1 are used to receive source line signal SL1. The sources of transistors T(i)_2_1 to T(i)_2_m+1 and T(i+1)_2_1 to T(i+1)_2_m+1 are used to receive source line signal SL2, and so on. The sources of transistors T(i)_n_1 to T(i)_n_m+1 and T(i+1)_n_1 to T(i+1)_n_m+1 are used to receive source line signal SLn.

[0142] In some embodiments, word line signals WL(i)_1 to WL(i)_m+1 are used to carry search character SW1. Search character SW1 includes search input bits SIB(1) to SIB(m+1). Word line signals WL(i)_1 to WL(i)_m+1 are respectively used to carry search input bits SIB(1) to SIB(m+1).

[0143] In some embodiments, memory rows CL(i)_1 to CL(i)_n are respectively used to store data characters DW1 to DWn. Each transistor in memory rows CL(i)_1 to CL(i)_n is used to store a corresponding data bit in data characters DW1 to DWn.

[0144] During a search operation, memory device 400 is used to compare search character SW1 with data characters DW1 to DWn and generate corresponding bit line signals BL1 to BLn. When there is a high similarity between search character SW1 and one of data characters DW1 to DWn, a corresponding one of bit line signals BL1 to BLn has a low current level. When there is a low similarity between search character SW1 and one of data characters DW1 to DWn, a corresponding one of bit line signals BL1 to BLn has a high current level.

[0145] Please refer to Figure 4 and Figure 2L, in some embodiments, the memory device 400 may be implemented by the memory device 200. For example, the source of the transistor in the memory row CL(i)_n corresponds to the source structure SS1, and the drain of the transistor in the memory row CL(i)_n corresponds to the drain structure DS1. The source of the transistor in the memory row CL(i)_n - 1 corresponds to the source structure SS2, and the drain of the transistor in the memory row CL(i)_n - 1 corresponds to the drain structure DS2. The gate portion GP3 corresponds to the gates of the transistors T(i)_1_1 to T(i)_n_1. The gate portion GP2 corresponds to the gates of the transistors T(i)_1_2 to T(i)_n_2. The gate portion GP1 corresponds to the gates of the transistors T(i)_1_3 to T(i)_n_3.

[0146] In other words, the transistors in the memory row CL(i)_n share the source structure SS1 and the drain structure DS1. The transistors in the memory row CL(i)_n - 1 share the source structure SS2 and the drain structure DS2. The transistors T(i)_1_1 to T(i)_n_1 share the gate portion GP3. The transistors T(i)_1_2 to T(i)_n_2 share the gate portion GP2. The transistors T(i)_1_3 to T(i)_n_3 share the gate portion GP1.

[0147] Although the present disclosure has been disclosed above with embodiments, it is not intended to limit the present disclosure. Those skilled in the art can make some changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be defined by the scope of the appended claims.

Claims

1. A manufacturing method of a memory device, comprising: Placing a plurality of first layers and a plurality of second layers alternately along a first direction; Etching the first layers and the second layers to form a first hole along the first direction; Forming a first channel structure at an edge of the first hole; Forming a first source structure and a first drain structure in the first hole; and Forming a first charge trap structure around the first channel structure, wherein the material of the first layers is different from the material of the second layers.

2. The manufacturing method according to claim 1, further comprising: Forming a first intermediate structure at an inner edge of the first channel structure; and Forming a first isolation structure at an inner edge of the first intermediate structure, wherein the first isolation structure is located between the first source structure and the first drain structure.

3. The manufacturing method according to claim 2, further comprising: Etching the first intermediate structure to form a second hole; Stopping etching the first intermediate structure when the second hole contacts each of the first channel structure and the first isolation structure; and Forming the first source structure in the second hole.

4. The manufacturing method according to claim 3, further comprising: After forming the first source structure, etching the first intermediate structure to form a third hole; Stopping etching the first intermediate structure when the third hole contacts each of the first channel structure and the first isolation structure; and Forming the first drain structure in the third hole.

5. The manufacturing method according to claim 1, further comprising: Etching the first layers and the second layers to form a second hole separated from the first hole along the first direction; Forming a second channel structure at an edge of the second hole; Forming a second source structure and a second drain structure in the first hole; and Forming the first charge trap structure around the second channel structure.

6. The manufacturing method according to claim 1, further comprising: Removing the first layers; and After removing the first layers, forming a first gate structure between the second layers.

7. The manufacturing method according to claim 6, wherein the first layers are removed after forming each of the first source structure and the first drain structure.

8. The manufacturing method according to claim 6, wherein the first charge trap structure is formed before forming the first gate structure, and a plurality of gate portions of the first gate structure are located between a plurality of charge trap portions of the first charge trap structure.

9. A memory device, comprising: A first source structure; A first drain structure; A first channel structure surrounding each of the first source structure and the first drain structure; A charge trap structure surrounding the channel structure; and A gate structure surrounding the charge trap structure.

10. The memory device according to claim 9, further comprising: A first isolation structure, located between the first source structure and the first drain structure and configured to isolate the first source structure and the first drain structure, wherein the materials of the first source structure, the first drain structure, and the first isolation structure are different from each other.

11. The memory device according to claim 9 further comprises: An oxide layer disposed between a first gate portion of the gate structure and a second gate portion of the gate structure and surrounding the charge trap structure.

12. The memory device according to claim 11 further comprises: A second source structure; A second drain structure; and A second channel structure separated from the first channel structure and surrounding each of the second source structure and the second drain structure, wherein the charge trap structure surrounds the second channel structure.

13. The memory device according to claim 12, wherein The first source structure and the first drain structure correspond to a plurality of transistors of a first memory row, The second source structure and the second drain structure correspond to a plurality of transistors of a second memory row, Each of the transistors of the first memory row is configured to receive a first source line signal, and Each of the transistors of the second memory row is configured to receive a second source line signal different from the first source line signal.

14. The memory device according to claim 13, wherein a first transistor of the transistors of the first memory row and a second transistor of the transistors of the second memory row share the second gate portion.

15. A memory device comprising: A plurality of memory blocks configured to generate a plurality of bit line signals, wherein each of the memory blocks comprises a plurality of memory rows configured to store a plurality of data characters, A first memory block of the memory blocks is configured to compare a search character and the data characters to generate the bit line signals, Each of the memory rows comprises a plurality of transistors, Each of the plurality of gates of the transistors is configured to receive a plurality of word line signals carrying the search character, and The gates surround a plurality of sources and a plurality of drains of the transistors.

16. A method of manufacturing a memory device comprising: Forming a first channel structure; Forming a first isolation structure surrounded by the first channel structure; Forming a first source structure and a first drain structure, wherein the first isolation structure is located between the first source structure and the first drain structure; Forming a charge trap structure surrounding the first channel structure; And Forming a gate structure surrounding the charge trap structure.

17. The manufacturing method according to claim 16 further comprises: Forming a second channel structure separated from the first channel structure; Forming a second isolation structure surrounded by the second channel structure; and Forming a second source structure and a second drain structure, wherein the second isolation structure is located between the second source structure and the second drain structure, and The charge trap structure surrounds the second channel structure.

18. The manufacturing method according to claim 16 further comprises: Staggering a plurality of first layers and a plurality of second layers in a first direction; Etching the first layers and the second layers to form a first hole extending in the first direction; Forming a first channel structure in the first hole; And Removing the first layers after forming the first drain structure.

19. The manufacturing method according to claim 18, wherein the material of the first isolation structure is the same as that of these first layers.

20. The manufacturing method according to claim 16, further comprising: forming an intermediate structure on an inner edge of the first channel structure; and etching the intermediate structure to form a second hole and a third hole separated from each other, wherein the first source structure and the first drain structure are respectively formed in the second hole and the third hole.

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