Passivation contact structure and preparation method thereof, solar cell and preparation method and application thereof

Abstract

The invention provides a passivation contact structure and a preparation method thereof, and a solar cell and a preparation method and application thereof. In the stacking direction, the passivation contact structure comprises a first p-type doped polycrystalline silicon layer, a tunneling layer, a second p-type doped polycrystalline silicon layer, a third p-type doped polycrystalline silicon layer and a fourth p-type doped polycrystalline silicon layer which are sequentially arranged, and the doping concentration of the fourth p-type doped polycrystalline silicon layer is larger than that of the third p-type doped polycrystalline silicon layer. When the passivation contact structure is used in a solar cell, the arrangement of the first p-type doped polycrystalline silicon layer can play a role in blocking the internal expansion of doped elements, namely reducing the internal expansion of the doped elements into a silicon substrate, so that the passivation effect is improved; the surface flatness of each film layer can be improved; the fourth p-type doped polycrystalline silicon layer with high doping concentration can improve the contact effect of the passivation contact structure; and a high-low junction is formed between the third p-type doped polycrystalline silicon layer and the fourth p-type doped polycrystalline silicon layer, so that the transmission of carriers and the collection efficiency of the carriers are facilitated.

Description

Technical Field

[0001] The present invention relates to the technical field of crystalline silicon cells, and more specifically, to a passivated contact structure and a preparation method thereof, a solar cell and a preparation method thereof, and an application. Even more specifically, the present invention relates to a passivated contact structure and a preparation method thereof, a solar cell and a preparation method thereof, and a photovoltaic module. Background Art

[0002] Existing photovoltaic cells usually use N-poly (N-type doped polysilicon) and P-poly (P-type doped polysilicon) as the passivation structures at the grid line positions. P-poly uses boron-doped polysilicon to match a relatively thick oxide layer as the passivation structure to provide hole collection for the grid lines. However, the diffusion coefficient and solubility of boron in silicon are relatively low, which will lead to uneven overall distribution. High doping concentration will increase the internal diffusion depth and damage the tunneling structure; if the internal diffusion depth is guaranteed to be low, the surface doping concentration will be too low, affecting the contact effect. Summary of the Invention

[0003] The present invention aims to solve at least one of the technical problems in the related art to some extent. For this purpose, an object of the present invention is to provide a passivated contact structure, which can effectively reduce the internal diffusion of doped impurities or better protect the tunneling layer.

[0004] In one aspect of the present invention, the present invention provides a passivated contact structure. According to an embodiment of the present invention, in the stacking direction, the passivated contact structure includes a first p-type doped polysilicon layer, a tunneling layer, a second p-type doped polysilicon layer, a third p-type doped polysilicon layer, and a fourth p-type doped polysilicon layer arranged in sequence, wherein the doping concentration of the fourth p-type doped polysilicon layer is greater than that of the third p-type doped polysilicon layer. Thus, when the passivated contact structure is used in a solar cell, in the preparation processes of the third p-type doped polysilicon layer and the fourth p-type doped polysilicon layer, the setting of the first p-type doped polysilicon layer can play a role in blocking the internal diffusion of doping elements, that is, reducing the internal diffusion of doping elements into the silicon substrate, thereby improving the passivation effect; the first p-type doped polysilicon layer adheres to the surface of the silicon substrate, which is beneficial to improving its surface flatness and the uniformity of subsequent film layers. The tunneling layer grows on the surface of the first p-type doped polysilicon layer, which can improve the growth efficiency and growth uniformity of the tunneling layer, improve the passivation effect and the carrier transport ability; in addition, the fourth p-type doped polysilicon layer with a high doping concentration is located on the outside, which can further improve the passivation effect and at the same time improve the contact effect of the passivated contact structure; further, a high-low junction is formed between the fourth p-type doped polysilicon layer and the third p-type doped polysilicon layer, which is beneficial to the transport and collection efficiency of carriers, reduces recombination, and is also beneficial to reducing interface defects and suppressing the internal diffusion of doping elements.

[0005] According to an embodiment of the present invention, the doping concentration of the third p-type doped polysilicon layer is greater than that of the second p-type doped polysilicon layer, and / or the doping concentration of the second p-type doped polysilicon layer is greater than that of the first p-type doped polysilicon layer.

[0006] According to an embodiment of the present invention, the thickness of the fourth p-type doped polysilicon layer is 95 nm to 100 nm, and / or the doping concentration is 4×10 19 cm -3 ~5×10 19 cm -3 ; the thickness of the third p-type doped polysilicon layer is 85 nm to 95 nm, and / or the doping concentration is 3×10 19 cm -3 ~4×10 19 cm -3 .

[0007] According to an embodiment of the present invention, at least one of the following conditions is further satisfied: the thickness of the second p-type doped polysilicon layer is 30 nm to 40 nm, and / or the doping concentration is 2×10 19 cm -3 ~3×10 19 cm -3 ; the thickness of the first p-type doped polysilicon layer is 8 nm to 12 nm; the thickness of the tunneling layer is 1 nm to 1.5 nm.

[0008] In another aspect of the present invention, the present invention provides a method for preparing a passivated contact structure. According to an embodiment of the present invention, the method for preparing a passivated contact structure includes: sequentially depositing a first polysilicon layer, a tunneling layer, a second polysilicon layer, a first amorphous silicon layer, and a second amorphous silicon layer on a silicon substrate, wherein the deposition temperature of the second amorphous silicon layer is lower than that of the first amorphous silicon layer; crystallizing the first amorphous silicon layer and the second amorphous silicon layer to obtain a third polysilicon layer and a fourth polysilicon layer; performing p-type impurity diffusion on the first polysilicon layer, the second polysilicon layer, the third polysilicon layer, and the fourth polysilicon layer, and driving it to obtain the first p-type doped polysilicon layer, the second p-type doped polysilicon layer, the third p-type doped polysilicon layer, and the fourth p-type doped polysilicon layer. Thus, in the above process, since the deposition temperature of the second amorphous silicon layer is lower than that of the first amorphous silicon layer, when performing p-type impurity diffusion, a fourth p-type doped polysilicon layer with a high doping concentration and a third p-type doped polysilicon layer with a relatively low doping concentration (i.e., the doping concentration of the fourth p-type doped polysilicon layer is greater than that of the third p-type doped polysilicon layer) will be formed. A high-low junction is formed between the fourth p-type doped polysilicon layer and the third p-type doped polysilicon layer, which is beneficial to the transport of carriers and the collection efficiency of carriers, reduces recombination, and is also beneficial to reducing interface defects and suppressing the inward diffusion of doping elements; moreover, the gradient cooling deposition of the first amorphous silicon layer and the second amorphous silicon layer will not damage the inner layer (such as the second polysilicon layer) structure during the crystallization growth process. When performing the crystallization treatment, the growth amplitude of the first polysilicon layer and the second polysilicon layer is small, and it is not easy to damage the structure of the tunneling layer. And its solid solubility for p-type impurities (such as boron) is lower than that of the third polysilicon layer and the fourth polysilicon layer, which can fully reduce its inward diffusion depth and improve passivation; during the diffusion process, the setting of the first polysilicon layer can play a role in blocking the inward diffusion of doping elements, that is, reducing the inward diffusion of doping elements into the silicon substrate, thereby improving the passivation effect; the fourth p-type doped polysilicon layer with a high doping concentration is located on the outside, which can further improve the passivation effect and at the same time improve the contact effect of the passivated contact structure; further, the first polysilicon layer adheres to the surface of the silicon substrate, which can form a flatter surface. The tunneling layer grows on the surface of the first p-type doped polysilicon layer, which can improve the growth efficiency and growth uniformity of the tunneling layer, improve the passivation effect and the transport ability of carriers.

[0009] According to an embodiment of the present invention, the deposition temperature of the first amorphous silicon layer is 570 °C to 590 °C, and the deposition time is 1000 s to 1200 s; and / or, the deposition temperature of the second amorphous silicon layer is 540 °C to 560 °C, and the deposition time is 1300 s to 1700 s; and / or, the temperature of the crystallization treatment is 930 °C to 970 °C, the crystallization pressure is 150 mtorr to 170 mtorr, and the time is 2000 s to 3000 s.

[0010] According to an embodiment of the present invention, the p-type impurity diffusion is boron diffusion, and the boron diffusion includes a first diffusion and a second diffusion performed in sequence. The temperature of the first diffusion is 835°C to 845°C, the diffusion time is 150 s to 200 s, the pressure is 150 mtorr to 170 mtorr, the flow rate of the boron source is 200 sccm to 240 sccm, the flow rate of nitrogen is 2350 sccm to 2450 sccm, and the flow rate of oxygen is 560 sccm to 600 sccm; the temperature of the second diffusion is 855°C to 865°C, the diffusion time is 200 s to 250 s, the pressure is 150 mtorr to 170 mtorr, the flow rate of the boron source is 200 sccm to 240 sccm, the flow rate of nitrogen is 2350 sccm to 2450 sccm, and the flow rate of oxygen is 560 sccm to 600 sccm; and / or, the temperature of the push is 960°C to 980°C, the time is 500 s to 800 s, the pressure is 190 mtorr to 210 mtorr, and the nitrogen flow rate is 2900 sccm to 3100 sccm.

[0011] According to an embodiment of the present invention, the deposition temperatures of the first polysilicon layer, the tunneling layer, and the second polysilicon layer are the same and are 605°C to 615°C; the deposition time of the first polysilicon layer is 90 s to 150 s, and the thickness is 8 to 12 nm; the deposition time of the tunneling layer is 300 s to 500 s, and the thickness is 1 to 1.5 nm; the deposition time of the second polysilicon layer is 300 s to 500 s, and the thickness is 30 to 40 nm.

[0012] In another aspect of the present invention, the present invention provides a solar cell. According to an embodiment of the present invention, the solar cell includes: a silicon substrate having a front surface and a back surface disposed opposite to each other; a P-region passivation structure, the P-region passivation structure including the passivation contact structure described above, and the passivation contact structure is disposed on the surface of the back surface of the silicon substrate. Thus, the solar cell has a good passivation contact structure, improving its passivation quality and passivation uniformity, and improving the contact effect between the passivation contact structure and the gate line, which can reduce recombination and improve the carrier collection efficiency. Those skilled in the art can understand that the solar cell has all the features and advantages of the passivation contact structure described above, and will not be elaborated here too much.

[0013] According to an embodiment of the present invention, the solar cell further includes an N-region passivation structure, and the N-region passivation structure and the P-region passivation structure are disposed at intervals on the surface of the back surface.

[0014] In yet another aspect of the present invention, the present invention provides a method for manufacturing the solar cell described above. According to an embodiment of the present invention, the method for manufacturing the solar cell includes the method for manufacturing the passivation contact structure described above. Thereby, the solar cell has a good passivation contact structure, improving its passivation quality and passivation uniformity, as well as improving the contact effect between the passivation contact structure and the grid lines, which can reduce recombination and improve the carrier collection efficiency. Those skilled in the art can understand that the solar cell has all the features and advantages of the passivation contact structure described above, and will not be elaborated herein too much.

[0015] According to an embodiment of the present invention, the method for manufacturing the solar cell includes:

[0016] providing a silicon substrate having a front surface and a back surface disposed opposite to each other, the back surface including a P region and an N region, and a gap region located between the P region and the N region;

[0017] successively depositing and forming a first polysilicon layer, a first tunneling layer, a second polysilicon layer, a first amorphous silicon layer, and a second amorphous silicon layer on the silicon substrate, wherein the deposition temperature of the second amorphous silicon layer is lower than that of the first amorphous silicon layer;

[0018] crystallizing the first amorphous silicon layer and the second amorphous silicon layer to obtain a third polysilicon layer and a fourth polysilicon layer;

[0019] performing p-type impurity diffusion on the first polysilicon layer, the second polysilicon layer, the third polysilicon layer, and the fourth polysilicon layer, and driving and oxidizing to obtain the first p-type doped polysilicon layer, the second p-type doped polysilicon layer, the third p-type doped polysilicon layer, the fourth p-type doped polysilicon layer, and a first glass layer on the surface of the fourth p-type doped polysilicon layer;

[0020] patterning the first glass layer to retain the first glass layer in the P region;

[0021] using the first glass layer as a mask to remove the corresponding first p-type doped polysilicon layer, the first tunneling layer, the second p-type doped polysilicon layer, the third p-type doped polysilicon layer, and the fourth p-type doped polysilicon layer in the N region and the gap region;

[0022] successively depositing a second tunneling layer and a fifth polysilicon layer on the back surface;

[0023] performing n-type impurity diffusion on the fifth polysilicon layer, and driving and oxidizing to obtain the n-type doped polysilicon layer and a second glass layer on the surface of the n-type doped polysilicon layer;

[0024] Pattern the second glass layer, leaving the second glass layer in the N region;

[0025] Using the second glass layer as a mask, remove the corresponding n-type doped polysilicon layer and the second tunneling layer in the P region and the gap region to obtain an N-region passivation structure, and form a textured surface on the surface of the silicon substrate on the front side and the surface of the silicon substrate in the gap region;

[0026] Remove the first glass layer and the second glass layer;

[0027] Deposit a first passivation layer on both the front side and the back side;

[0028] Deposit an antireflection film on the side of the first passivation layer on the front side away from the silicon substrate;

[0029] Deposit a second passivation layer on the side of the first passivation layer on the back side away from the silicon substrate;

[0030] Form a first gate line and a second gate line on the back side, the first gate line being in contact connection with the fourth p-type doped polysilicon layer, and the second gate line being in contact connection with the n-type doped polysilicon layer.

[0031] In another aspect of the present invention, the present invention provides a photovoltaic module. According to an embodiment of the present invention, the photovoltaic module includes the solar cell described above, or a solar cell prepared by the method described above. Thus, the photovoltaic module has good photoelectric conversion efficiency.

[0032] Additional aspects and advantages of the present invention will be given in part in the following description, become apparent in part from the following description, or be learned through the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The above and / or additional aspects and advantages of the present invention will become apparent and be readily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0034] Figure 1 is a schematic structural diagram of a passivation contact structure in an embodiment of the present invention;

[0035] Figure 2 is a schematic structural diagram of preparing a passivation contact structure in another embodiment of the present invention;

[0036] Figure 3 is a schematic structural diagram of a solar cell in yet another embodiment of the present invention;

[0037] Figure 4 and Figure 5 is a structural flowchart of preparing a solar cell in yet another embodiment of the present invention.

[0038] Reference numerals: first p-type doped polysilicon layer 11; tunneling layer 12; second p-type doped polysilicon layer 13; third p-type doped polysilicon layer 14; fourth p-type doped polysilicon layer 15; first polysilicon layer 01; second polysilicon layer 02; first amorphous silicon layer 03; second amorphous silicon layer 04; third polysilicon layer 05; fourth polysilicon layer 06; silicon substrate 10; P-region passivation structure 100; N-region passivation structure 200; passivation layer 30; second tunneling layer 21; n-type doped polysilicon layer 22; first gate line 61; second gate line 62; front passivation layer 40; antireflection layer 50; first glass layer 16; fifth polysilicon layer 022; second glass layer 23. Detailed implementation manners

[0039] The solution of the present invention will be explained below in conjunction with embodiments. Those skilled in the art will understand that the following embodiments are only used to illustrate the present invention and should not be regarded as limiting the scope of the present invention. For those not specified in the embodiments regarding specific techniques or conditions, the techniques or conditions described in the literature in this field or according to the product specifications are followed. Those reagents or instruments without indicating the manufacturer can all be obtained as conventional products through commercial purchase.

[0040] The present invention will be described below with reference to specific embodiments. It should be noted that these embodiments are merely descriptive and do not limit the present invention in any way.

[0041] In one aspect of the present invention, the present invention provides a passivated contact structure. According to an embodiment of the present invention, referring to Figure 1 , in the stacking direction, the passivated contact structure includes a first p-type doped polysilicon layer 11, a tunneling layer 12, a second p-type doped polysilicon layer 13, a third p-type doped polysilicon layer 14, and a fourth p-type doped polysilicon layer 15 arranged in sequence, wherein the doping concentration of the fourth p-type doped polysilicon layer 15 is greater than that of the third p-type doped polysilicon layer 14.

[0042] Therefore, when the passivated contact structure is used in a solar cell, in the preparation processes of the third p-type doped polysilicon layer 14 and the fourth p-type doped polysilicon layer 15, the setting of the first p-type doped polysilicon layer 11 can play a role in blocking the inward diffusion of doping elements, that is, reducing the inward diffusion of doping elements into the silicon substrate, thereby improving the passivation effect; the first p-type doped polysilicon layer 11 adheres to the surface of the silicon substrate, which is beneficial to improving its surface flatness and the uniformity of subsequent film layers. The tunneling layer grows on the surface of the first p-type doped polysilicon layer 11, which can improve the growth efficiency and growth uniformity of the tunneling layer, improve the passivation effect and the carrier transport ability; moreover, the fourth p-type doped polysilicon layer 15 with a high doping concentration is located on the outside, which can further improve the passivation effect and at the same time improve the contact effect of the passivated contact structure; further, a high-low junction is formed between the fourth p-type doped polysilicon layer 15 and the third p-type doped polysilicon layer 14, which is beneficial to the transport and collection efficiency of carriers, reduces recombination, and is also beneficial to reducing interface defects and suppressing the inward diffusion of doping elements.

[0043] According to some embodiments of the present invention, the doping concentration of the third p-type doped polysilicon layer is greater than that of the second p-type doped polysilicon layer. Thus, the inward diffusion of doping elements can be further prevented. According to some embodiments of the present invention, the doping concentration of the second p-type doped polysilicon layer is greater than that of the first p-type doped polysilicon layer. Thus, the inward diffusion of doping elements can be further prevented.

[0044] According to some embodiments of the present invention, the thickness of the fourth p-type doped polysilicon layer is 95 nm to 100 nm (such as 95 nm, 96 nm, 97 nm, 98 nm, 99 nm, 100 nm, etc.), and the doping concentration is 4×10 19 cm -3 ~5×10 19 cm -3 (such as the doping concentration is 4×10 19 cm -3 、4.1×10 19 cm -3 、4.2×10 19 cm -3 、4.3×10 19 cm -3 、4.4×10 19 cm -3 、4.5×10 19 cm -3 、4.6×10 19 cm -3 、4.7×10 19 cm -3 、4.8×10 19 cm -3, 4.9*10 19 cm -3 , 5*10 19 cm -3 etc.); According to some embodiments of the present invention, the thickness of the third p-type doped polysilicon layer is 85 nm to 95 nm (such as 85 nm, 87 nm, 90 nm, 92 nm, 93 nm, 95 nm, etc.), and the doping concentration is 3*10 19 cm -3 ~4*10 19 cm -3 (such as the doping concentration is 3*10 19 cm -3 , 3.1*10 19 cm -3 , 3.2*10 19 cm -3 , 3.3*10 19 cm -3 , 3.4*10 19 cm -3 , 3.5*10 19 cm -3 , 3.6*10 19 cm -3 , 3.7*10 19 cm -3 , 3.8*10 19 cm -3 , 3.9*10 19 cm -3 , 4*10 19 cm -3 etc.). The above-mentioned fourth p-type doped polysilicon layer has a relatively high doping concentration, which can well improve its conductivity, and then improve the contact effect between it and the gate line, and further improve the carrier collection efficiency; moreover, the high-low junction of the above-mentioned concentration is more conducive to the transmission of carriers and the improvement of the carrier collection efficiency.

[0045] According to some embodiments of the present invention, the thickness of the second p-type doped polysilicon layer is 30 nm to 40 nm (such as 30 nm, 32 nm, 34 nm, 36 nm, 38 nm, 40 nm, etc.), and / or the doping concentration is 2*10 19 cm -3 ~3*10 19 cm -3 (such as the doping concentration is 2*10 19 cm -3 , 2.1*10 19 cm -3 , 2.2*10 19 cm -3 , 2.3*1019 cm -3 、2.4*10 19 cm -3 、2.5*10 19 cm -3 、2.6*10 19 cm -3 、2.7*10 19 cm -3 、2.8*10 19 cm -3 、2.9*10 19 cm -3 、3*10 19 cm -3 etc.). The above-mentioned second p-type doped polysilicon layer with a lower concentration and thickness can effectively block the inward diffusion of doping elements.

[0046] According to some embodiments of the present invention, the thickness of the first p-type doped polysilicon layer is 8 nm to 12 nm, such as 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, etc. The above-mentioned relatively thin first p-type doped polysilicon layer can provide a flatter surface for the growth of other film layers, and can also serve as a buffer layer or a barrier layer to further block the inward diffusion of doping elements, thereby helping to improve the passivation effect.

[0047] According to some embodiments of the present invention, the thickness of the tunneling layer is 1 nm to 1.5 nm, such as 1 nm, 1.1 nm, 1.2 nm, 1.3 nm, 1.4 nm, 1.5 nm, etc. Thus, the relatively thin tunneling layer can help to improve the carrier transport efficiency.

[0048] On the other hand of the present invention, the present invention provides a method for preparing a passivated contact structure. According to an embodiment of the present invention, referring to Figure 2 , the method for preparing a passivated contact structure includes:

[0049] S100: Sequentially deposit and form a first polysilicon layer 01, a tunneling layer 12, a second polysilicon layer 02, a first amorphous silicon layer 03, and a second amorphous silicon layer 04 on the silicon substrate 10.

[0050] The first polysilicon layer adheres to the surface of the silicon substrate, and a flatter surface can be formed. The tunneling layer grows on the surface of the first p-type doped polysilicon layer, which can improve the growth efficiency and growth uniformity of the tunneling layer, and improve the passivation effect and the carrier transport ability.

[0051] According to some embodiments of the present invention, the first polysilicon layer 01, the tunneling layer 12, the second polysilicon layer 02, the first amorphous silicon layer 03, and the second amorphous silicon layer 04 can be deposited by low-pressure chemical vapor deposition (LPCVD).

[0052] According to some embodiments of the present invention, the deposition temperatures of the first polysilicon layer, the tunneling layer, and the second polysilicon layer are the same, and are 605°C to 615°C, such as 605°C, 606°C, 607°C, 608°C, 609°C, 610°C, 611°C, 612°C, 613°C, 614°C, 615°C, etc. At the above temperatures, polysilicon and the tunneling layer with better quality can be deposited. Moreover, since the deposition temperatures of the three-layer structure remain unchanged, it is possible to avoid affecting their growth quality during the temperature change process, that is, keeping the deposition temperatures of the three-layer structure unchanged can help improve the growth quality of each layer structure.

[0053] In some embodiments, the deposition time of the first polysilicon layer is 90 s to 150 s, and the thickness is 8 to 12 nm. Thus, a relatively thin first polysilicon layer can effectively improve the surface flatness and effectively block the inward diffusion of doping elements, reducing the diffusion depth in the silicon substrate. In some embodiments, the deposition time of the tunneling layer is 300 s to 500 s, and the thickness is 1 to 1.5 nm. Thus, a relatively thin tunneling layer helps to improve the carrier transport efficiency. In some embodiments, the deposition time of the second polysilicon layer is 300 s to 500 s, and the thickness is 30 to 40 nm, such as 30 nm, 32 nm, 35 nm, 38 nm, 40 nm, etc.

[0054] According to the embodiments of the present invention, under the protection of the first polysilicon layer and the second polysilicon layer under the above conditions, the tunneling layer can be effectively protected during the subsequent crystallization process. Moreover, during the crystallization process, the growth amplitudes of the first polysilicon layer and the second polysilicon layer are small and will not damage the relatively thin tunneling layer; moreover, compared with the polysilicon layer obtained by first depositing amorphous silicon and then crystallizing and growing, the directly deposited first polysilicon layer and second polysilicon layer have a lower solid solubility for p-type doping elements (such as boron), and can more effectively reduce the inward diffusion depth after the doping elements diffuse through the film layer (such as the subsequent fourth polysilicon layer and third polysilicon layer), thereby improving the passivation effect.

[0055] According to some embodiments of the present invention, the deposition temperature of the second amorphous silicon layer is lower than that of the first amorphous silicon layer. Since the deposition temperature of the second amorphous silicon layer is lower than that of the first amorphous silicon layer, during the subsequent p-type impurity diffusion, a fourth p-type doped polysilicon layer with a high doping concentration and a third p-type doped polysilicon layer with a relatively low doping concentration will be formed, that is, the doping concentration of the fourth p-type doped polysilicon layer is greater than that of the third p-type doped polysilicon layer; moreover, the gradient cooling deposition of the first amorphous silicon layer and the second amorphous silicon layer will not damage the inner layer (such as the second polysilicon layer) structure during the crystallization growth process.

[0056] According to some embodiments of the present invention, the deposition temperature of the first amorphous silicon layer is 570°C to 590°C (such as 570°C, 575°C, 580°C, 585°C, 590°C, etc.), and the deposition time is 1000 s to 1200 s (such as 1000 s, 1050 s, 1100 s, 1150 s, 1200 s, etc.); the deposition temperature of the second amorphous silicon layer is 540°C to 560°C (such as 540°C, 545°C, 550°C, 555°C, 560°C, etc.), and the deposition time is 1300 s to 1700 s (such as 1300 s, 1400 s, 1500 s, 1600 s, 1700 s, etc.). Thus, under the above conditions, the first amorphous silicon layer and the second amorphous silicon layer with better quality and performance can be obtained, and for the above-described deposited amorphous silicon layer with decreasing temperature, a fourth p-type doped polysilicon layer with a high doping concentration and a third p-type doped polysilicon layer with a relatively low doping concentration can be obtained in subsequent processes.

[0057] S200: Crystallize the first amorphous silicon layer 03 and the second amorphous silicon layer 04 to obtain a third polysilicon layer 05 and a fourth polysilicon layer 06.

[0058] According to some embodiments of the present invention, the temperature of the crystallization treatment is 930°C to 970°C (such as 930°C, 940°C, 950°C, 960°C, 970°C, etc.), the crystallization pressure is 150 mtorr to 170 mtorr (such as 150 mtorr, 160 mtorr, 170 mtorr, etc.), and the time is 2000 s to 3000 s (such as 2000 s, 2200 s, 2500 s, 2800 s, 3000 s, etc.). Under the above conditions, the first amorphous silicon layer and the second amorphous silicon layer can grow to form a third polysilicon layer and a fourth polysilicon layer with better quality.

[0059] S300: Perform p-type impurity diffusion on the first polysilicon layer 01, the second polysilicon layer 02, the third polysilicon layer 05, and the fourth polysilicon layer 06, and push it forward to obtain a first p-type doped polysilicon layer 11, a second p-type doped polysilicon layer 13, a third p-type doped polysilicon layer 14, and a fourth p-type doped polysilicon layer 15.

[0060] In the above diffusion process, the setting of the first polysilicon layer can play a role in blocking the inward diffusion of doping elements, that is, reducing the inward diffusion of doping elements into the silicon substrate, thereby improving the passivation effect.

[0061] According to some embodiments of the present invention, the p-type impurity diffusion is boron diffusion, and the boron diffusion includes a first diffusion and a second diffusion performed in sequence. That is, the boron diffusion is completed through two diffusion steps, which is beneficial to improving the uniformity of boron diffusion.

[0062] In some embodiments, the temperature of the first diffusion is 835°C to 845°C (such as 835°C, 840°C, 845°C), the diffusion time is 150 s to 200 s (such as 150 s, 160 s, 170 s, 180 s, 190 s, 200 s, etc.), the pressure is 150 mtorr to 170 mtorr (such as 150 mtorr, 160 mtorr, 170 mtorr, etc.), the flow rate of the boron source is 200 sccm to 240 sccm (such as 200 sccm, 210 sccm, 220 sccm, 230 sccm, 240 sccm, etc.), the flow rate of nitrogen is 2350 sccm to 2450 sccm (such as 2350 sccm, 2400 sccm, 2450 sccm, etc.), and the flow rate of oxygen is 560 sccm to 600 sccm (such as 560 sccm, 570 sccm, 580 sccm, 590 sccm, 600 sccm, etc.).

[0063] In some embodiments, the temperature of the second diffusion is 855°C to 865°C (such as 855°C, 860°C, 865°C), the diffusion time is 200 s to 250 s (such as 200 s, 210 s, 220 s, 230 s, 240 s, 250 s, etc.), the pressure is 150 mtorr to 170 mtorr (such as 150 mtorr, 160 mtorr, 170 mtorr, etc.), the flow rate of the boron source is 200 sccm to 240 sccm (such as 200 sccm, 210 sccm, 220 sccm, 230 sccm, 240 sccm, etc.), the flow rate of nitrogen is 2350 sccm to 2450 sccm (such as 2350 sccm, 2400 sccm, 2450 sccm, etc.), and the flow rate of oxygen is 560 sccm to 600 sccm (such as 560 sccm, 570 sccm, 580 sccm, 590 sccm, 600 sccm, etc.).

[0064] In some embodiments, the temperature of the push is 960°C to 980°C (such as 960°C, 970°C, 980°C), the time is 500 s to 800 s (such as 500 s, 600 s, 700 s, 800 s, etc.), the pressure is 190 mtorr to 210 mtorr (such as 190 mtorr, 200 mtorr, 210 mtorr, etc.), and the nitrogen flow rate is 2900 sccm to 3100 sccm (such as 2900 sccm, 3000 sccm, 3100 sccm, etc.).

[0065] Under the above diffusion and promotion conditions, a first p-type doped polysilicon layer, a second p-type doped polysilicon layer, a third p-type doped polysilicon layer, and a fourth p-type doped polysilicon layer with uniform diffusion can be obtained. A high-low junction is formed between the fourth p-type doped polysilicon layer and the third p-type doped polysilicon layer, which is beneficial to the transport of carriers and the collection efficiency of carriers, reduces recombination, is also beneficial to reducing interface defects, and inhibits the inward diffusion of doping elements. Moreover, the fourth p-type doped polysilicon layer with a high doping concentration is located on the outside, which can further improve the passivation effect and at the same time improve the contact effect of the passivated contact structure.

[0066] In another aspect of the present invention, the present invention provides a solar cell. According to an embodiment of the present invention, referring to Figure 3 , the solar cell includes: a silicon substrate 10 having a front surface and a back surface disposed opposite to each other; a P-region passivation structure 100, the P-region passivation structure 100 including the passivated contact structure described above, and the passivated contact structure is disposed on the surface of the back surface of the silicon substrate. Thus, the solar cell has a good passivated contact structure, improves its passivation quality and passivation uniformity, and improves the contact effect between the passivated contact structure and the gate line, can reduce recombination, and improve the carrier collection efficiency. Those skilled in the art can understand that the solar cell has all the features and advantages of the passivated contact structure described above, and will not be elaborated here too much.

[0067] According to an embodiment of the present invention, referring to Figure 3 , the solar cell is a TBC cell. In some embodiments, as Figure 3 shows, the solar cell further includes an N-region passivation structure 200, and the N-region passivation structure 200 and the P-region passivation structure 100 are spaced apart and disposed on the surface of the back surface.

[0068] According to some embodiments of the present invention, referring to Figure 3 , the P-region passivation structure 100 may further include a passivation layer 30 on the side of the fourth p-type doped polysilicon layer away from the silicon substrate 10; in the direction away from the silicon substrate 10, the N-region passivation structure 200 includes a second tunneling layer 21, an n-type doped polysilicon layer 22, and a passivation layer 30; the solar cell further includes a first gate line 61 and a second gate line 62, the first gate line 61 is in contact connection with the fourth p-type doped polysilicon layer 15 of the P-region passivation structure, and the second gate line 62 is in contact connection with the n-type doped polysilicon layer 22 of the N-region passivation structure; it further includes a front passivation layer 40 and an antireflection layer 50 on the front surface of the silicon substrate 10.

[0069] In yet another aspect of the present invention, the present invention provides a method for fabricating the solar cell described above. According to an embodiment of the present invention, the method for fabricating the solar cell includes the method for fabricating the passivated contact structure described above. Thus, the solar cell has a good passivated contact structure, improving its passivation quality and passivation uniformity, as well as improving the contact effect between the passivated contact structure and the grid lines, which can reduce recombination and improve the carrier collection efficiency. Those skilled in the art can understand that the solar cell has all the features and advantages of the passivated contact structure described above, and will not be elaborated herein.

[0070] According to an embodiment of the present invention, the solar cell is a TBC cell. In some embodiments, referring to Figure 4 and Figure 5 , the method for fabricating the solar cell includes:

[0071] T110: Provide a silicon substrate 10, the silicon substrate 10 having a front side and a back side disposed opposite to each other, the back side including a P region and an N region, and a gap region located between the P region and the N region.

[0072] T120: Sequentially deposit and form a first polysilicon layer 01, a first tunneling layer (i.e., the tunneling layer 12 in the figure), a second polysilicon layer 02, a first amorphous silicon layer 03, and a second amorphous silicon layer 04 on the silicon substrate 10, wherein the deposition temperature of the second amorphous silicon layer 04 is lower than that of the first amorphous silicon layer 03.

[0073] T130: Crystallize the first amorphous silicon layer 03 and the second amorphous silicon layer 04 to obtain a third polysilicon layer 05 and a fourth polysilicon layer 06.

[0074] T140: Perform p-type impurity diffusion on the first polysilicon layer 01, the second polysilicon layer 02, the third polysilicon layer 05, and the fourth polysilicon layer 06, and then drive and oxidize to obtain a first p-type doped polysilicon layer 11, a second p-type doped polysilicon layer 13, a third p-type doped polysilicon layer 14, a fourth p-type doped polysilicon layer 15, and a first glass layer 16 on the surface of the fourth p-type doped polysilicon layer.

[0075] In some embodiments, the methods and requirements for fabricating the first p-type doped polysilicon layer 11, the second p-type doped polysilicon layer 13, the third p-type doped polysilicon layer 14, the fourth p-type doped polysilicon layer 15, and the tunneling layer 12 are the same as those described above, and will not be elaborated herein.

[0076] In some embodiments, the method of forming the first glass layer 16 by oxidizing the surface of the fourth p-type doped polysilicon layer 15 may include: after the push is completed, changing the nitrogen flow rate at the same temperature and introducing oxygen, thereby oxidizing the surface of the fourth p-type doped polysilicon layer 15 to form a glass layer 16, wherein the temperature is the same as the temperature of the push, the nitrogen flow rate is 900 sccm to 1100 sccm (such as 900 sccm, 1000 sccm, 1100 sccm, etc.), and the oxygen flow rate is 1400 sccm to 1600 sccm (such as 1400 sccm, 1500 sccm, 1600 sccm, etc.).

[0077] T150: Pattern the first glass layer 16 and retain the first glass layer 16 in the P region.

[0078] In some embodiments, the diffused impurity element is boron, and this first glass layer is a borosilicate glass (BSG) layer.

[0079] In some embodiments, the patterning method can be a laser method or a wet etching method. In some specific embodiments, the laser method is used for patterning, the laser power is 40 W - 50 W, the overlap rate is 50% - 60%, the frequency is 500 kHz - 600 kHz, and the pulse width is 0.8 μs - 1.2 μs.

[0080] In some embodiments, the first glass layer on the front and side can be further removed by acid cleaning. Specifically, it can be: pickling is performed using a wet chain machine, the tank body temperature of the wet acid tank chain machine is 20 - 50 °C, the overall process time is 50 - 80 s, and the chain machine has two acid tanks for cleaning respectively. The acid solution in the first acid tank is an acid solution composed of H2O and HF in a volume ratio of 2:5, and the acid solution in the second acid tank is an acid solution composed of H2O and HF in a volume ratio of 3:4.

[0081] T160: Using the first glass layer 16 as a mask, remove the corresponding first p-type doped polysilicon layer 11, the first tunneling layer, the second p-type doped polysilicon layer 13, the third p-type doped polysilicon layer 14, and the fourth p-type doped polysilicon layer 15 in the N region and the gap region (Gap region), and only retain the first p-type doped polysilicon layer 11, the tunneling layer 12, the second p-type doped polysilicon layer 13, the third p-type doped polysilicon layer 14, and the fourth p-type doped polysilicon layer 15 in the P region.

[0082] In some embodiments, the above-mentioned structures in the N region and the gap region can be removed by wet etching. In some specific embodiments, alkali cleaning is performed by a wet bench to remove the p-type doped polysilicon layers on the front side and the p-type doped polysilicon layers in the Gap region and the N region. Among them, the temperature of the tank body of the wet alkali polishing bench is 50-75 °C, the time is 200-300 s, and the alkali solution used for alkali cleaning is composed of H2O, NaOH and an additive in a volume ratio of 450:25:7.

[0083] T170: Deposit the second tunneling layer 21 and the fifth polysilicon layer 022 on the back side in sequence.

[0084] In some embodiments, it can be deposited by low-pressure chemical vapor deposition (LPCVD).

[0085] In some embodiments, the temperature for depositing the second tunneling layer is 590-630 °C, the time is 500-1200 s, and the thickness is 1.95 ± 0.3 nm.

[0086] In some embodiments, the time for depositing the fifth polysilicon layer is 3500-5000 s, the deposition temperature is 605-620 °C, and the thickness is 280 ± 30 nm.

[0087] T180: Perform n-type impurity diffusion on the fifth polysilicon layer 022, and then drive and oxidize to obtain an n-type doped polysilicon layer 22 and a second glass layer 23 on the surface of the n-type doped polysilicon layer 22.

[0088] In some embodiments, the diffusion temperature is 800-820 °C, the diffusion time is 1200-1500 s; the driving temperature is 870-890 °C, the driving time is 800-1200 s; the oxidation temperature is 910-930 °C, the oxidation time is 600-900 s, the thickness of the second glass layer is 50 ± 5 nm, and the sheet resistance is 25 ± 5. Further, when the n-type doped impurity is phosphorus, the second glass layer is phosphosilicate glass (PSG).

[0089] T190: Pattern the second glass layer 23, and retain the second glass layer 23 in the N region.

[0090] In some embodiments, the patterning method can be laser method or wet etching. In some specific embodiments, laser patterning is used, the laser power is 40W-50W, the overlap rate is 50%-60%, the frequency is 500kHz-600kHz, and the pulse width is 0.8μs-1.2μs.

[0091] In some embodiments, an acid solution can be further used to clean and remove the first glass layer on the front and side surfaces. Specifically, it can be as follows: pickling is performed using a wet chemical chain machine. The temperature of the tank body of the wet acid tank chain machine is 20 - 50 °C, and the overall process time is 30 - 60 s. The chain machine has a total of two acid tanks for cleaning respectively. The acid solution in the first acid tank is an acid solution composed of H2O and HF in a volume ratio of 2:5, and the acid solution in the second acid tank is an acid solution composed of H2O and HF in a volume ratio of 3:4.

[0092] T200: Using the second glass layer 23 as a mask, remove the corresponding n-type doped polysilicon layer 22 and the second tunneling layer 21 in the P region and the gap region to obtain an N-region passivation structure, and form a textured surface on the surface of the silicon substrate 10 on the front side and the surface of the silicon substrate in the gap region.

[0093] In some embodiments, a wet etching method can be used to remove the corresponding n-type doped polysilicon layer 22 and the second tunneling layer 21 in the P region and the gap region (Gap region). In some specific embodiments, alkaline cleaning is performed using a wet tank machine to remove the n-type doped polysilicon layer 22 and the N-region tunneling layer 21 on the front and side surfaces, as well as the n-type doped polysilicon layer 22 and the second tunneling layer 21 in the Gap region and the P region, and at the same time form a pyramid textured surface on the surface of the silicon substrate on the front side and the surface of the silicon substrate in the back gap region. Among them, the temperature of the tank body solution of the wet alkaline polishing tank machine is 70 - 80 °C, the time is 450 - 650 s, and the alkaline solution used for alkaline cleaning is composed of H2O, NaOH, and an additive in a volume ratio of 470:6:11.

[0094] T210: Remove the first glass layer 16 and the second glass layer 23.

[0095] In some embodiments, the remaining glass can be removed using a hydrofluoric acid solution.

[0096] T220: Deposit and form a front passivation layer 40 on the front side, and deposit and form a first passivation layer on the back side.

[0097] In some embodiments, atomic layer deposition (ALD) can be used to deposit and prepare the front passivation layer 40 and the first passivation layer. In a specific embodiment, the deposition temperature of ALD is 300 °C, the process time is 900 s, the thickness of the formed first passivation layer is 4.3 ± 1 nm, and the material can be alumina.

[0098] T230: Deposit an antireflection film 50 on the side of the front passivation layer 40 away from the silicon substrate 10.

[0099] In some embodiments, methods such as chemical vapor deposition (such as LPCVD or PECVD, etc.) or physical vapor deposition (such as magnetron sputtering) can be used to deposit an antireflection film. In some specific embodiments, the coating temperature is 540 °C, and it is divided into 6 layers of films. In the direction away from the silicon substrate 10, the deposition sequence from the inside out is silicon nitride 1, silicon nitride 2, silicon nitride 3, silicon oxynitride 1, silicon oxynitride 2, and silicon oxide. The thickness of each layer of film is between 10 - 25 nm, the overall thickness of the film layer is 75 ± 5 nm, and the refractive index is 2.10 ± 0.05.

[0100] T240: Deposit a second passivation layer on the side of the first passivation layer on the back surface away from the silicon substrate 10. The first passivation layer and the second passivation layer on the back surface together form the passivation layer 30 on the back surface.

[0101] In some embodiments, methods such as chemical vapor deposition (such as LPCVD or PECVD, etc.) or physical vapor deposition (such as magnetron sputtering) can be used to deposit an antireflection film. In some specific embodiments, the coating temperature is 530 °C, and it is divided into 3 layers of films. In the direction away from the silicon substrate 10, the deposition sequence from the inside out is silicon nitride 1, silicon nitride 2, and silicon nitride 3. The thickness of each layer of film is between 10 - 30 nm, the overall thickness of the film layer is 84 ± 6 nm, and the refractive index is 2.12 ± 0.05.

[0102] T250: Form a first grid line 61 and a second grid line 62 on the back surface. The first grid line 61 is in contact connection with the fourth p-type doped polysilicon layer 15, and the second grid line 62 is in contact connection with the n-type doped polysilicon layer 22.

[0103] In some embodiments, by means of screen printing, metal grid lines (including a first grid line and a second grid line, such as silver grid lines or copper grid lines) are formed on the back surface. After high-temperature sintering, an ohmic contact is formed between the metal and the semiconductor to collect current and conduct it out.

[0104] In another aspect of the present invention, the present invention provides a photovoltaic module. According to the embodiments of the present invention, the photovoltaic module includes the solar cell described above, or a solar cell prepared by the method described above. Thus, the photovoltaic module has good photoelectric conversion efficiency.

[0105] Embodiment

[0106] Embodiment 1

[0107] The method for preparing a TBC cell includes:

[0108] T100: Provide an N-type silicon substrate. The silicon substrate has a front side and a back side that are oppositely arranged. Perform the first double-sided polishing on the N-type silicon substrate in a wet alkaline polishing trough machine. The alkaline solution used is composed of H2O, NaOH, and a polishing additive mixed in a volume ratio of 450:30:5. The polishing time is 350 s, and the trough body temperature is 70 °C.

[0109] T120: Use the LPCVD method to sequentially deposit and form a first polysilicon layer, a tunneling layer, a second polysilicon layer, a first amorphous silicon layer, and a second amorphous silicon layer on the N-type silicon substrate. Among them, the deposition temperature of the first polysilicon layer is 610 °C, the deposition time is 120 s, and the deposition thickness is 10 nm; the deposition temperature of the tunneling layer is 610 °C, the deposition time is 400 s, and the deposition thickness is 1.2 nm; the deposition temperature of the second polysilicon layer is 610 °C, the deposition time is 400 s, and the deposition thickness is 35 nm; the deposition temperature of the first amorphous silicon layer is 580 °C, the deposition time is 1100 s, and the deposition thickness is 90 nm; the deposition temperature of the second amorphous silicon layer is 550 °C, the deposition time is 1300 s, and the deposition thickness is 100 nm.

[0110] T130: Crystallize the first amorphous silicon layer and the second amorphous silicon layer at 950 °C for 2000 s to obtain a third polysilicon layer and a fourth polysilicon layer.

[0111] T140: Perform boron diffusion on the first polysilicon layer, the second polysilicon layer, the third polysilicon layer, and the fourth polysilicon layer at 840 °C and 860 °C for 150 s and 200 s respectively, then raise the temperature to 970 °C and push for 600 s, and then oxidize at 970 °C for 1650 s to obtain a first p-type doped polysilicon layer, a second p-type doped polysilicon layer, a third p-type doped polysilicon layer, a fourth p-type doped polysilicon layer, and a 65-nm-thick borosilicate glass (BSG) layer on the surface of the fourth p-type doped polysilicon layer.

[0112] T150: Use a laser to remove the BSG layer in the back N region and the Gap region, and retain the BSG layer in the P region. The laser power is 45 W, the overlap rate is 55%, the frequency is 550 kHz, and the pulse width is 1 μs; then perform pickling through a wet chain machine to remove the BSG layer on the front side. The trough body temperature of the wet acid trough chain machine is 40 °C, the overall process time is 80 s, and the chain machine has a total of two acid troughs. The acid solution in the first acid trough is composed of H2O and HF mixed in a volume ratio of 2:5, and the acid solution in the second acid trough is composed of H2O and HF mixed in a volume ratio of 3:4.

[0113] T160: Using a borosilicate glass layer as a mask, perform alkali cleaning through a wet trough machine to remove the above-mentioned p-type doped polysilicon layers and tunneling layers on the front and side surfaces, as well as the p-type doped polysilicon layers and tunneling layers in the Gap region and N region. The trough temperature of the wet alkali polishing trough machine is 60°C, the process time is 250 s, and the alkali solution used for alkali cleaning is composed of H2O, NaOH, and an additive mixed in a volume ratio of 450:25:7.

[0114] T170: Use the LPCVD method to sequentially deposit a second tunneling layer and a fifth polysilicon layer on the back surface. Among them, the deposition time of the second tunneling layer is 800 s, the deposition temperature is 610°C, forming a silicon oxide tunneling layer with a thickness of 1.95 nm; the deposition time of the fifth polysilicon layer is 4000 s, the deposition temperature is 610°C, and the deposition thickness is 280 nm.

[0115] T180: Diffuse phosphorus in the fifth polysilicon layer at 810°C for 1400 s, then raise the temperature to 880°C and push for 1000 s, and then oxidize at 920°C for 750 s to obtain an n-type doped polysilicon layer and a phosphosilicate glass (PSG) layer on the surface of the n-type doped polysilicon layer.

[0116] T190: Use a laser to remove the PSG layer in the back P region and Gap region, and retain the PSG layer in the N region. The laser power is 45 W, the overlap rate is 55%, the frequency is 550 kHz, and the pulse width is 1 μs; then perform pickling through a wet chain machine to remove the PSG layer on the front and side surfaces. The trough temperature of the wet acid trough chain machine is 40°C, the overall process time is 50 s, and the chain machine has a total of two acid troughs. The acid solution in the first acid trough is composed of H2O and HF mixed in a volume ratio of 2:5, and the acid solution in the second acid trough is composed of H2O and HF mixed in a volume ratio of 3:4.

[0117] T200: Using the PSG layer as a mask, perform alkali cleaning through a wet trough machine to remove the above-mentioned n-type doped polysilicon layers and the second tunneling layer on the front and side surfaces, as well as the n-type doped polysilicon layers and the second tunneling layer in the Gap region and P region, and at the same time form a pyramid texture on the silicon substrate surface on the front side and the silicon substrate surface in the back Gap region. Among them, the trough temperature of the wet alkali polishing trough machine is 75°C, the process time is 500 s, and the alkali solution used for alkali cleaning and texturing is composed of H2O, NaOH, and an additive mixed in a volume ratio of 470:6:11.

[0118] T210: Use a hydrofluoric acid solution to remove the remaining PSG layer and BSG layer.

[0119] T220: Use the ALD method to deposit an aluminum oxide layer on both the front and back surfaces through a back-to-back double-insertion method. The ALD temperature is 300°C, the time is 900 s, and the thickness is 4.3 nm.

[0120] T230: On the side of the alumina layer on the front away from the silicon substrate, silicon nitride 1, silicon nitride 2, silicon nitride 3, silicon oxynitride 1, silicon oxynitride 2, and silicon oxide are sequentially deposited at 540 °C to obtain an antireflection film. Among them, the thickness of each layer of film is between 10 - 25 nm, the thickness of the overall film layer is 75 nm, and the refractive index is 2.10.

[0121] T240: On the side of the alumina layer on the back away from the silicon substrate, silicon nitride 1, silicon nitride 2, and silicon nitride 3 are sequentially deposited at 530 °C. Among them, the thickness of each layer of film is between 10 - 30 nm, the thickness of the overall film layer is 84 nm, and the refractive index is 2.12.

[0122] T250: A first silver grid line and a second silver grid line are formed on the back. The first silver grid line is in contact connection with the fourth p-type doped polysilicon layer, and the second silver grid line is in contact connection with the n-type doped polysilicon layer.

[0123] That is, the TBC cell is obtained.

[0124] Comparative Example 1

[0125] The method for preparing the TBC cell is basically the same as that in Example 1, except that: in step T120, the deposition temperatures of the first amorphous silicon layer and the second amorphous silicon layer are the same, both being 580 °C. The specific steps are as follows:

[0126] T120: Using the LPCVD method, a first polysilicon layer, a tunneling layer, a second polysilicon layer, a first amorphous silicon layer, and a second amorphous silicon layer are sequentially deposited on an N-type silicon substrate. Among them, the deposition temperature of the first polysilicon layer is 610 °C, the deposition time is 120 s, and the deposition thickness is 10 nm; the deposition temperature of the tunneling layer is 610 °C, the deposition time is 400 s, and the deposition thickness is 1.2 nm; the deposition temperature of the second polysilicon layer is 610 °C, the deposition time is 400 s, and the deposition thickness is 35 nm; the deposition temperature of the first amorphous silicon layer is 580 °C, the deposition time is 1100 s, and the deposition thickness is 90 nm; the deposition temperature of the second amorphous silicon layer is 580 °C, the deposition time is 1300 s, and the deposition thickness is 100 nm.

[0127] Comparative Example 2

[0128] The method for preparing the TBC cell is basically the same as that in Example 1, except that: in step T120, the first polysilicon layer is not deposited. The specific steps are as follows:

[0129] T120: The tunneling layer, the second polysilicon layer, the first amorphous silicon layer, and the second amorphous silicon layer are sequentially deposited on the N-type silicon substrate by the LPCVD method. Among them, the deposition temperature of the tunneling layer is 610 °C, the deposition time is 400 s, and the deposition thickness is 1.2 nm; the deposition temperature of the second polysilicon layer is 610 °C, the deposition time is 400 s, and the deposition thickness is 35 nm; the deposition temperature of the first amorphous silicon layer is 580 °C, the deposition time is 1100 s, and the deposition thickness is 90 nm; the deposition temperature of the second amorphous silicon layer is 550 °C, the deposition time is 1300 s, and the deposition thickness is 100 nm.

[0130] It can be understood that what is obtained in step T140 in this Comparative Example 2 is: the second p-type doped polysilicon layer, the third p-type doped polysilicon layer, the fourth p-type doped polysilicon layer, and a 65-nm-thick borosilicate glass (BSG) layer on the surface of the fourth p-type doped polysilicon layer.

[0131] Comparative Example 3

[0132] The method for preparing the TBC cell includes:

[0133] T110: Provide an N-type silicon substrate. The silicon substrate has a front side and a back side arranged oppositely. The N-type silicon substrate is subjected to the first double-sided polishing in a wet alkali polishing trough machine. The alkali solution used is composed of H2O, NaOH, and a polishing additive mixed in a volume ratio of 450:30:5. The polishing time is 350 s, and the trough temperature is 70 °C.

[0134] T120: The P-region tunneling layer and the amorphous silicon layer are sequentially deposited on the N-type silicon substrate by the LPCVD method. Among them, the deposition time of the tunneling layer is 2000 s, the deposition temperature is 610 °C, and a 2-nm-thick silicon oxide tunneling layer is formed; the deposition time of the non-polysilicon layer is 12000 s, the deposition temperature is 560 °C, and the deposition thickness is 300 nm.

[0135] T130: The amorphous silicon layer is crystallized at 970 °C for 2800 s to obtain a polysilicon layer.

[0136] T140: The polysilicon layer is subjected to boron diffusion at 840 °C for 450 s, then heated to 950 °C for 600 s for diffusion, then oxidized at 900 °C for 3300 s, and finally annealed at 960 °C to obtain a p-type doped polysilicon layer and a borosilicate glass (BSG) layer on the surface of the p-type doped polysilicon layer.

[0137] The remaining steps are basically the same as steps T150 to T250 in Example 1.

[0138] The TBC cells prepared in Examples 1 and 2 were subjected to performance tests. The test method was as follows: using a solar simulator and an I-V tester, under 1 standard solar irradiance, the electrical performance of the TBC cells obtained in the above examples and comparative examples was tested through steady-state power output tests. The test results can be seen in Table 1.

[0139] Table 1

[0140]

[0141] From the test results of Example 1 and Comparative Example 1, it can be seen that the formation of the fourth p-type doped polysilicon layer with a high doping concentration can improve the passivation effect, and at the same time improve the contact effect of the passivated contact structure. Moreover, a high-low junction is formed between the fourth p-type doped polysilicon layer and the third p-type doped polysilicon layer 14, which is beneficial to the transport of carriers and the collection efficiency of carriers, reduces recombination, and is also beneficial to reducing interface defects and suppressing the inward diffusion of doping elements, thereby improving the photoelectric conversion efficiency of the cell.

[0142] From the test results of Example 1 and Comparative Example 2, it can be seen that in Comparative Example 2, the first polysilicon layer was not deposited, that is, there was no first p-type doped polysilicon layer in the solar cell of Comparative Example 2. By comparison, it can be seen that the setting of the first p-type doped polysilicon layer in Example 1 can play a role in blocking the inward diffusion of doping elements, that is, reducing the inward diffusion of doping elements into the silicon substrate, thereby improving the passivation effect and thus improving the photoelectric conversion efficiency of the cell.

[0143] From the test results of Example 1 and Comparative Example 3, it can be seen that compared with the solar cells with common structures in the prior art, the solar cells of the present invention have better photoelectric conversion efficiency.

[0144] The terms "first" and "second" in the text are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present application, "a plurality" means two or more, unless otherwise specifically defined.

[0145] In the description of this specification, the description referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0146] Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention.

Claims

1. A passivated contact structure, characterized in that, In the stacking direction, it includes a first p-type doped polysilicon layer, a tunneling layer, a second p-type doped polysilicon layer, a third p-type doped polysilicon layer, and a fourth p-type doped polysilicon layer arranged in sequence, wherein the doping concentration of the fourth p-type doped polysilicon layer is greater than that of the third p-type doped polysilicon layer.

2. The passivation contact structure according to claim 1, wherein The doping concentration of the third p-type doped polysilicon layer is greater than that of the second p-type doped polysilicon layer, and / or the doping concentration of the second p-type doped polysilicon layer is greater than that of the first p-type doped polysilicon layer.

3. The passivation contact structure according to claim 1 or 2, characterized in that, The thickness of the fourth p-type doped polysilicon layer is 95 nm to 100 nm, and / or the doping concentration is 4*10 19 cm -3 ~5*10 19 cm -3 , The thickness of the third p-type doped polysilicon layer is 85 nm to 95 nm, and / or the doping concentration is 3*10 19 cm -3 ~4*10 19 cm -3 .

4. The passivation contact structure according to claim 2, wherein, It also satisfies at least one of the following conditions: The thickness of the second p-type doped polysilicon layer is 30 nm to 40 nm, and / or the doping concentration is 2*10 19 cm -3 ~3*10 19 cm -3 ; The thickness of the first p-type doped polysilicon layer is 8 nm to 12 nm; The thickness of the tunneling layer is 1 nm to 1.5 nm.

5. A method for preparing the passivated contact structure according to any one of claims 1 to 4, characterized in that, It includes: A first polysilicon layer, a tunneling layer, a second polysilicon layer, a first amorphous silicon layer, and a second amorphous silicon layer are sequentially deposited on a silicon substrate, wherein the deposition temperature of the second amorphous silicon layer is lower than that of the first amorphous silicon layer; The first amorphous silicon layer and the second amorphous silicon layer are subjected to crystallization treatment to obtain a third polysilicon layer and a fourth polysilicon layer; The first polysilicon layer, the second polysilicon layer, the third polysilicon layer, and the fourth polysilicon layer are subjected to p-type impurity diffusion and pushing to obtain a first p-type doped polysilicon layer, a second p-type doped polysilicon layer, a third p-type doped polysilicon layer, and a fourth p-type doped polysilicon layer.

6. The method according to claim 5, wherein The deposition temperature of the first amorphous silicon layer is 570 °C to 590 °C, and the deposition time is 1000 s to 1200 s; and / or the deposition temperature of the second amorphous silicon layer is 540 °C to 560 °C, and the deposition time is 1300 s to 1700 s; and / or the temperature of the crystallization treatment is 930 °C to 970 °C, the crystallization pressure is 150 mtorr to 170 mtorr, and the time is 2000 s to 3000 s.

7. The method according to claim 5 or 6, characterized in that, The p-type impurity diffusion is boron diffusion, and the boron diffusion includes a first diffusion and a second diffusion carried out in sequence. The temperature of the first diffusion is 835 °C to 845 °C, the diffusion time is 150 s to 200 s, the pressure is 150 mtorr to 170 mtorr, the flow rate of the boron source is 200 sccm to 240 sccm, the flow rate of nitrogen is 2350 sccm to 2450 sccm, and the flow rate of oxygen is 560 sccm to 600 sccm; the temperature of the second diffusion is 855 °C to 865 °C, the diffusion time is 200 s to 250 s, the pressure is 150 mtorr to 170 mtorr, the flow rate of the boron source is 200 sccm to 240 sccm, the flow rate of nitrogen is 2350 sccm to 2450 sccm, and the flow rate of oxygen is 560 sccm to 600 sccm; and / or the temperature of the pushing is 960 °C to 980 °C, the time is 500 s to 800 s, the pressure is 190 mtorr to 210 mtorr, and the nitrogen flow rate is 2900 sccm to 3100 sccm.

8. The method according to claim 5 or 6, characterized in that, The deposition temperatures of the first polysilicon layer, the tunneling layer, and the second polysilicon layer are the same, and are 605°C to 615°C; The deposition time of the first polysilicon layer is 90 s to 150 s, and the thickness is 8 to 12 nm; The deposition time of the tunneling layer is 300 s to 500 s, and the thickness is 1 to 1.5 nm; The deposition time of the second polysilicon layer is 300 s to 500 s, and the thickness is 30 to 40 nm.

9. A solar cell, characterized in that, Comprising: A silicon substrate having a front surface and a back surface disposed opposite to each other; A P-region passivation structure, the P-region passivation structure including the passivated contact structure according to any one of claims 1 to 4, the passivated contact structure being disposed on the surface of the back surface of the silicon substrate.

10. The solar cell according to claim 9, characterized in that, It further includes an N-region passivation structure, and the N-region passivation structure and the P-region passivation structure are spaced apart and disposed on the surface of the back surface.

11. A method for preparing the solar cell according to claim 9 or 10, characterized in that, Including the method for preparing a passivated contact structure according to any one of claims 5 to 9.

12. The method according to claim 11, wherein The method for preparing the solar cell includes: Providing a silicon substrate having a front surface and a back surface disposed opposite to each other, the back surface including a P region and an N region, and a gap region between the P region and the N region; Sequentially depositing and forming a first polysilicon layer, a first tunneling layer, a second polysilicon layer, a first amorphous silicon layer, and a second amorphous silicon layer on the silicon substrate, wherein the deposition temperature of the second amorphous silicon layer is lower than that of the first amorphous silicon layer; Performing crystallization treatment on the first amorphous silicon layer and the second amorphous silicon layer to obtain a third polysilicon layer and a fourth polysilicon layer; Performing p-type impurity diffusion on the first polysilicon layer, the second polysilicon layer, the third polysilicon layer, and the fourth polysilicon layer, and pushing and oxidizing to obtain the first p-type doped polysilicon layer, the second p-type doped polysilicon layer, the third p-type doped polysilicon layer, the fourth p-type doped polysilicon layer, and a first glass layer on the surface of the fourth p-type doped polysilicon layer; Patterning the first glass layer to retain the first glass layer in the P region; Using the first glass layer as a mask to remove the corresponding first p-type doped polysilicon layer, the first tunneling layer, the second p-type doped polysilicon layer, the third p-type doped polysilicon layer, and the fourth p-type doped polysilicon layer in the N region and the gap region; Sequentially depositing a second tunneling layer and a fifth polysilicon layer on the back surface; Performing n-type impurity diffusion on the fifth polysilicon layer, and pushing and oxidizing to obtain the n-type doped polysilicon layer and a second glass layer on the surface of the n-type doped polysilicon layer; Patterning the second glass layer to retain the second glass layer in the N region; Using the second glass layer as a mask to remove the corresponding n-type doped polysilicon layer and the second tunneling layer in the P region and the gap region to obtain an N-region passivation structure, and forming a textured surface on the surface of the silicon substrate on the front surface and the surface of the silicon substrate in the gap region; Removing the first glass layer and the second glass layer; Depositing and forming a first passivation layer on both the front surface and the back surface; Deposit an antireflection film on the side of the first passivation layer on the front surface away from the silicon substrate; Deposit a second passivation layer on the side of the first passivation layer on the back surface away from the silicon substrate; Form a first gate line and a second gate line on the back surface, the first gate line is in contact connection with the fourth p-type doped polysilicon layer, and the second gate line is in contact connection with the n-type doped polysilicon layer.

13. A photovoltaic module, characterized in that, Comprising the solar cell according to claim 9 or 10, or the solar cell prepared by the method according to claim 11 or 12.

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