Array substrate, charging method thereof and display panel

Abstract

The invention provides an array substrate, a charging method thereof and a display panel, and relates to the technical field of display, the array substrate comprises a display area and a first peripheral area located on one side of the display area, the display area comprises a plurality of sub-pixels arranged in an array and a plurality of data signal lines extending in the first direction, the data signal lines are arranged between two adjacent columns of sub-pixels; the plurality of sub-pixels comprise a first sub-pixel column, and the display colors of the sub-pixels in the first sub-pixel column are not completely the same; the same data signal line is electrically connected with the sub-pixels with the same display color in the at least two first sub-pixel columns respectively; the first direction is the direction in which the display area points to the first peripheral area. The array substrate is low in energy consumption and good in display effect.

Description

Technical Field

[0001] This application relates to the field of display technologies, and in particular, to an array substrate, a charging method thereof, and a display panel. Background Art

[0002] With the rapid development of OLED (Organic Light-Emitting Diode) display technology, people have higher and higher requirements for the characteristics of OLED display products. Based on the superiority of OLED display products, the diversity of their display refreshes, and the successive development of multi-frequency display products, OLED display technology is also continuously updated and iterated.

[0003] However, during the actual use of a display terminal, the power consumption of the screen, the power consumption of signal transmission (such as MIPI transmission), the power consumption of the terminal for rendering pictures, etc. are all relatively high. With the increasing requirement for the battery life of display products, it is urgent to improve the power consumption of display products to reduce power consumption. Summary of the Invention

[0004] The embodiments of this application adopt the following technical solutions:

[0005] In a first aspect, an embodiment of this application provides an array substrate, including a display area and a first peripheral area located on one side of the display area. The display area includes a plurality of sub-pixels arranged in an array and a plurality of data signal lines extending in a first direction. The data signal lines are disposed between two adjacent columns of the sub-pixels;

[0006] The plurality of sub-pixels include a first sub-pixel column, and the display colors of the sub-pixels in the first sub-pixel column are not completely the same; the same data signal line is electrically connected to the sub-pixels with the same display color in at least two of the first sub-pixel columns; the first direction is the direction from the display area to the first peripheral area.

[0007] In some array substrates provided by the embodiments of this application, the first peripheral area includes a multiplexing circuit, a plurality of bonding terminals, and a plurality of source signal lines. The data signal lines are electrically connected to the bonding terminals through the multiplexing circuit; the multiplexing circuit is configured to control the conduction and cut-off between the bonding terminals and the data signal lines;

[0008] Wherein, after two data signal lines connected to the sub-pixels with the same display color are connected together, they are electrically connected to the bonding terminal through the same source signal line.

[0009] In some array substrates provided by embodiments of the present application, the multiplexing circuit includes a first multiplexing unit and a second multiplexing unit. One of the two data signal lines connected to the same source signal line is electrically connected to the first multiplexing unit, and the other data signal line is electrically connected to the second multiplexing unit.

[0010] In some array substrates provided by embodiments of the present application, the same data signal line is electrically connected to sub-pixels with the same display color in two adjacent first sub-pixel columns respectively.

[0011] In some array substrates provided by embodiments of the present application, the plurality of sub-pixels further includes a second sub-pixel column. The second sub-pixel column is located between two adjacent first sub-pixel columns. The display colors of the sub-pixels in the second sub-pixel column are the same, and each sub-pixel in the second sub-pixel column is electrically connected to the same data signal line.

[0012] In some array substrates provided by embodiments of the present application, the first sub-pixel column includes first color sub-pixels and second color sub-pixels arranged alternately, and the second sub-pixel column includes third color sub-pixels; one second sub-pixel column is provided between any two adjacent first sub-pixel columns;

[0013] The first color sub-pixels in the first sub-pixel column of the first column and the first color sub-pixels in the first sub-pixel column of the second column are electrically connected to the first data signal line respectively. Each of the third color sub-pixels in the second sub-pixel column of the first column is electrically connected to the second data signal line. The second color sub-pixels in the first sub-pixel column of the first column and the second color sub-pixels in the first sub-pixel column of the second column are electrically connected to the third data signal line respectively. Each of the third color sub-pixels in the second sub-pixel column of the second column is electrically connected to the fourth data signal line.

[0014] The first color sub-pixels in the first sub-pixel column of the third column and the first color sub-pixels in the first sub-pixel column of the fourth column are electrically connected to the fifth data signal line respectively. Each of the third color sub-pixels in the second sub-pixel column of the third column is electrically connected to the sixth data signal line. The second color sub-pixels in the first sub-pixel column of the third column and the second color sub-pixels in the first sub-pixel column of the fourth column are electrically connected to the seventh data signal line respectively. Each of the third color sub-pixels in the second sub-pixel column of the fourth column is electrically connected to the eighth data signal line.

[0015] In some array substrates provided by the embodiments of the present application, the first multiplexing unit includes a first multiplexing signal line, a first switching transistor, a second switching transistor, a third switching transistor, and a sixth switching transistor, and the second multiplexing unit includes a second multiplexing signal line, a fourth switching transistor, a fifth switching transistor, a seventh switching transistor, and an eighth switching transistor;

[0016] The gates of the first switching transistor, the second switching transistor, the third switching transistor, and the sixth switching transistor are all electrically connected to the first multiplexing signal line, and the gates of the fourth switching transistor, the fifth switching transistor, the seventh switching transistor, and the eighth switching transistor are all electrically connected to the second multiplexing signal line;

[0017] The source of the first switching transistor is connected to the portion of the first data signal line in the display area, and the drain of the first switching transistor is connected to the portion of the first data signal line in the first peripheral area; the source of the second switching transistor is connected to the portion of the second data signal line in the display area, and the drain of the second switching transistor is connected to the portion of the second data signal line in the first peripheral area; the source of the third switching transistor is connected to the portion of the third data signal line in the display area, and the drain of the third switching transistor is connected to the portion of the third data signal line in the first peripheral area; the source of the fourth switching transistor is connected to the portion of the fourth data signal line in the display area, and the drain of the fourth switching transistor is connected to the portion of the fourth data signal line in the first peripheral area; the source of the fifth switching transistor is connected to the portion of the fifth data signal line in the display area, and the drain of the fifth switching transistor is connected to the portion of the fifth data signal line in the first peripheral area; the source of the sixth switching transistor is connected to the portion of the sixth data signal line in the display area, and the drain of the sixth switching transistor is connected to the portion of the sixth data signal line in the first peripheral area; the source of the seventh switching transistor is connected to the portion of the seventh data signal line in the display area, and the drain of the seventh switching transistor is connected to the portion of the seventh data signal line in the first peripheral area; the source of the eighth switching transistor is connected to the portion of the eighth data signal line in the display area, and the drain of the eighth switching transistor is connected to the portion of the eighth data signal line in the first peripheral area.

[0018] In some array substrates provided by the embodiments of the present application, the first color sub-pixel is a red sub-pixel, the second color sub-pixel is a blue sub-pixel, and the third color sub-pixel is a green sub-pixel.

[0019] In some array substrates provided by the embodiments of the present application, the first color sub-pixel is a blue sub-pixel, the second color sub-pixel is a red sub-pixel, and the third color sub-pixel is a green sub-pixel.

[0020] In some array substrates provided by the embodiments of the present application, the same data signal line is electrically connected to the sub-pixels with the same display color in three of the first sub-pixel columns respectively.

[0021] In some array substrates provided by the embodiments of the present application, the first sub-pixel column includes a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel. The first color sub-pixel, the second color sub-pixel, and the third color sub-pixel are sequentially and repeatedly arranged along the first direction. In the same row of sub-pixels, the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel are sequentially and repeatedly arranged perpendicular to the first direction.

[0022] In some array substrates provided by the embodiments of the present application, the first color sub-pixels in the 1st column, 2nd column, and 3rd column of the first sub-pixel columns are respectively electrically connected to the 1st data signal line, the second color sub-pixels in the 1st column, 2nd column, and 3rd column of the first sub-pixel columns are respectively electrically connected to the 2nd data signal line, and the third color sub-pixels in the 1st column, 2nd column, and 3rd column of the first sub-pixel columns are respectively electrically connected to the 3rd data signal line;

[0023] The first color sub-pixels in the 4th column, 5th column, and 6th column of the first sub-pixel columns are respectively electrically connected to the 4th data signal line, the second color sub-pixels in the 4th column, 5th column, and 6th column of the first sub-pixel columns are respectively electrically connected to the 5th data signal line, and the third color sub-pixels in the 4th column, 5th column, and 6th column of the first sub-pixel columns are respectively electrically connected to the 6th data signal line.

[0024] In some array substrates provided by the embodiments of the present application, the first multiplexing unit includes a first multiplexing signal line, a first switching transistor, a second switching transistor, and a third switching transistor. The second multiplexing unit includes a second multiplexing signal line, a fourth switching transistor, a fifth switching transistor, and a sixth switching transistor;

[0025] The gates of the first switching transistor, the second switching transistor, and the third switching transistor are respectively electrically connected to the first multiplexing signal line. The source of the first switching transistor is connected to the part of the 1st data signal line located in the display area, and the drain of the first switching transistor is connected to the part of the 1st data signal line located in the first peripheral area; the source of the second switching transistor is connected to the part of the 2nd data signal line located in the display area, and the drain of the second switching transistor is connected to the part of the 2nd data signal line located in the first peripheral area; the source of the third switching transistor is connected to the part of the 3rd data signal line located in the display area, and the drain of the third switching transistor is connected to the part of the 3rd data signal line located in the first peripheral area;

[0026] The gates of the fourth switching transistor, the fifth switching transistor, and the sixth switching transistor are respectively electrically connected to the second multiplexed signal line. The source of the fourth switching transistor is connected to the portion of the 4th data signal line located in the display area, and the drain of the fourth switching transistor is connected to the portion of the 4th data signal line located in the first peripheral area; the source of the fifth switching transistor is connected to the portion of the 5th data signal line located in the display area, and the drain of the fifth switching transistor is connected to the portion of the 5th data signal line located in the first peripheral area; the source of the sixth switching transistor is connected to the portion of the 6th data signal line located in the display area, and the drain of the sixth switching transistor is connected to the portion of the 6th data signal line located in the first peripheral area.

[0027] In some array substrates provided by the embodiments of the present application, one of the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel is a red sub-pixel, another is a green sub-pixel, and the other is a blue sub-pixel.

[0028] In some array substrates provided by the embodiments of the present application, the first multiplexed signal line is configured to transmit a first multiplexed signal, and the second multiplexed signal line is configured to transmit a second multiplexed signal;

[0029] The transistors electrically connected to the first multiplexed signal line and the transistors electrically connected to the second multiplexed signal line are not turned on simultaneously.

[0030] In some array substrates provided by the embodiments of the present application, the display area further includes a plurality of gate lines extending perpendicular to the first direction. The same gate line is connected to the sub-pixels in the same row. The gate line is configured to transmit a gate control signal to the sub-pixels, and the gate control signal is configured to control the charging time of the sub-pixels;

[0031] After the transistors electrically connected to the first multiplexed signal line are turned on and then turned off, the transistors electrically connected to the second multiplexed signal line are turned on;

[0032] After the transistors electrically connected to the second multiplexed signal line are turned on, the gate control signal is configured to control the sub-pixels to start charging.

[0033] In some array substrates provided by the embodiments of the present application, the transistors electrically connected to the first multiplexed signal line and the transistors electrically connected to the second multiplexed signal line are both P-type transistors.

[0034] Second aspect, an embodiment of the present application provides a charging method for an array substrate, which is applied to the array substrate described in any one of the first aspects. The charging method includes:

[0035] Input the first multiplexing signal of the first level to the first multiplexing signal line, and input the second multiplexing signal of the second level to the second multiplexing signal line;

[0036] Input the second multiplexing signal of the second level to the first multiplexing signal line, and input the first multiplexing signal of the first level to the second multiplexing signal line; wherein, the first level is less than the second level.

[0037] Input a gate control signal to the gate line, and the gate control signal partially overlaps with the second multiplexing signal.

[0038] Third aspect, an embodiment of the present application provides a display panel, including a driving chip and the array substrate described in the first aspect, and the bonding terminals on the driving chip and the array substrate are electrically connected.

[0039] The above description is only an overview of the technical solution of the present application. In order to be able to understand the technical means of the present application more clearly, it can be implemented according to the content of the description. And in order to make the above and other purposes, features and advantages of the present application more obvious and understandable, the specific embodiments of the present application are specifically given below. Description of the Drawings

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0041] Figure 1 It is a schematic structural diagram of a driving circuit of a first array substrate provided by an embodiment of the present application;

[0042] Figure 2 It is a schematic structural diagram of a driving circuit of a second array substrate provided by an embodiment of the present application;

[0043] Figure 3 It is a schematic structural diagram of a driving circuit of a third array substrate provided by an embodiment of the present application;

[0044] Figure 4 It is a timing signal diagram of a multiplexing circuit provided by an embodiment of the present application;

[0045] Figure 5A timing diagram of a multiplexed signal and a gate control signal provided by an embodiment of the present application;

[0046] Figure 6 A schematic structural diagram of a driving circuit of a fourth array substrate provided by an embodiment of the present application. Detailed implementation manners

[0047] Next, the technical solutions in the embodiments of the present application will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0048] Unless otherwise required by the context, throughout the specification and claims, the term "comprising" is interpreted in an open, inclusive sense, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "examples", "specific examples", or "some examples", etc., are intended to indicate that specific features, structures, materials, or characteristics related to the embodiment or example are included in at least one embodiment or example of the present application. The schematic representations of the above terms are not necessarily directed to the same embodiment or example. In addition, the specific features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0049] In the embodiments of the present application, the same items or similar items with basically the same functions and effects are partially named with words such as "first" and "second" only for clearly describing the technical solutions of the embodiments of the present application, and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features.

[0050] Features such as "parallel", "perpendicular", and "same" used in the embodiments of the present application include strict "parallel", "perpendicular", "same" and other features, as well as cases with certain errors such as "substantially parallel", "substantially perpendicular", and "substantially same". Considering measurement and errors related to the measurement of a specific quantity (for example, limitations of the measurement system), it means within the acceptable deviation range for a specific value determined by those of ordinary skill in the art. For example, "substantially" can mean within one or more standard deviations, or within 10% or 5% of the value. "At least one" means one or more, and "a plurality" means at least two.

[0051] In the embodiments of the present application, "same layer" refers to the relationship between multiple film layers formed from the same material after the same step (such as a single patterning process). Here, "same layer" does not always mean that the thicknesses of the multiple film layers are the same or that the heights of the multiple film layers in a cross-sectional view are the same. In this specification, polygons are not strictly defined and can be approximate triangles, parallelograms, trapezoids, pentagons, hexagons, etc., and there may be some small deformations caused by tolerances.

[0052] In this specification, "electrically connected" and "coupled" include cases where components are connected together through elements having a certain electrical effect. There are no particular limitations on the "elements having a certain electrical effect" as long as they can transfer electrical signals between the components to be connected. Examples of "elements having a certain electrical effect" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0053] With the continuous development of display technology, organic light-emitting diode display devices (OLEDs) have become a research focus and a technological development direction for major manufacturers due to their advantages such as wide color gamut, high contrast ratio, thin and light design, self-emission, and wide viewing angle. Currently, organic light-emitting diode display devices (OLEDs) have been widely applied to various electronic products, ranging from small electronic products such as smart bracelets, smart watches, smartphones, and tablet computers to large electronic products such as notebook computers, desktop computers, and televisions. Therefore, the market demand for active matrix organic light-emitting diode display devices is also increasing rapidly.

[0054] However, OLED technology still faces a power consumption bottleneck. When an OLED display terminal is actually in use, the power consumption of the screen, signal transmission power consumption (such as MIPI transmission), power consumption for the terminal to render pictures, etc. are all relatively high. With the increasing requirement for the battery life of display products, it is urgent to improve the power consumption of display products to reduce power consumption.

[0055] Based on this, embodiments of the present application provide an array substrate, a charging method thereof, and a display panel. The array substrate includes a display area and a first peripheral area located on one side of the display area. The display area includes a plurality of sub-pixels arranged in an array and a plurality of data signal lines extending in a first direction. The data signal lines are disposed between adjacent two columns of sub-pixels; the plurality of sub-pixels include a first sub-pixel column, and the display colors of the sub-pixels in the first sub-pixel column are not completely the same; the same data signal line is electrically connected to at least two sub-pixels with the same display color in the first sub-pixel column; the first direction is the direction from the display area to the first peripheral area.

[0056] Based on the requirement of reducing the power consumption of the Driver IC, this application optimizes the driving design of the sub-pixels in the array substrate, so that the same data signal line is electrically connected to the sub-pixels with the same display color in at least two first sub-pixel columns. In this way, it is ensured that the sub-pixels electrically connected to each source signal transmission channel (Source channel) of the later driver chip are all sub-pixels of the same color. For example, they are all red sub-pixels; or they are all green sub-pixels; or they are all blue sub-pixels. When the display panel displays a solid-color picture, the difference in the switching voltage (toggle voltage, or jump voltage) of each source signal transmission channel of the driver chip is very small, thus avoiding the large jump of the voltage signal transmitted by the source signal line when displaying solid-color pictures of different colors, and effectively reducing the power consumption of the driver chip. It is estimated that the effective power consumption can be reduced by about 20%, greatly improving the usage time of the display product.

[0057] Next, the array substrate, its charging method, and the display panel provided by the embodiments of the present application will be described in detail with reference to the accompanying drawings.

[0058] An embodiment of the present application provides an array substrate, as Figures 1 to 3 shown, including a display area AA and a first peripheral area B1 located on one side of the display area AA. The display area AA includes a plurality of sub-pixels PX arranged in an array and a plurality of data signal lines Data extending in a first direction (such as the OA direction). The data signal lines Data are arranged between adjacent two columns of sub-pixels PX;

[0059] The plurality of sub-pixels PX include a first sub-pixel column PXX1, and the display colors of the sub-pixels PX in the first sub-pixel column PXX1 are not all the same; the same data signal line Data is electrically connected to the sub-pixels PX with the same display color in at least two first sub-pixel columns PXX1; the first direction (such as the OA direction) is the direction from the display area AA to the first peripheral area B1.

[0060] The above-mentioned display area AA refers to the area of the array substrate for displaying pictures. The first peripheral area B1 may at least include a fan-out area (such as including the fan-out area, or including the fan-out area and the bonding area). Among them, various traces are arranged in the fan-out area to connect the signal lines in the display area AA and the bonding terminals (Pins) in the bonding area BD. A plurality of bonding terminals are arranged in the bonding area BD, and the bonding terminals in the bonding area BD can be bonded to the driver chip to input the signals transmitted by the driver chip into the traces in the fan-out area through the bonding terminals.

[0061] Exemplarily, the above-mentioned "first direction" may be the direction from the display area AA to the fan-out area Fan-out.

[0062] It should be noted that the first sub-pixel column PXX1 refers to a column of sub-pixels PX where the display colors of the sub-pixels are not completely the same. Among them, the situation where multiple sub-pixels PX include the first sub-pixel column PXX1 can be as follows:

[0063] First, multiple sub-pixels PX include the first sub-pixel column PXX1 and also include sub-pixel columns with other sub-pixel arrangement rules;

[0064] Second, multiple sub-pixels in the array substrate are arranged in the manner of the first sub-pixel column PXX1. It can be understood that each column of sub-pixels can be called the first sub-pixel column PXX1.

[0065] In addition, "the display colors are not completely the same" means that among the sub-pixels in the same column, the display colors of some sub-pixels are the same, and the display colors of some sub-pixels are different.

[0066] In some embodiments, the array substrate may include multiple types of sub-pixels with different display colors. For example, the array substrate may simultaneously include three types of sub-pixels that display red, blue, and green; for another example, the array substrate may simultaneously include four types of sub-pixels that display red, blue, green, and white.

[0067] Among them, the display colors of the sub-pixels PX in the first sub-pixel column PXX1 are not completely the same, and the number of sub-pixels with different display colors in the sub-pixel column is not limited. At this time, the first sub-pixel column PXX1 includes at least two types of sub-pixels with different display colors. For example, the first sub-pixel column PXX1 includes two types of sub-pixels with different display colors; for another example, the first sub-pixel column PXX1 includes three types of sub-pixels with different display colors; for another example, the first sub-pixel column PXX1 includes three types of sub-pixels with different display colors; of course, in some array substrates, the first sub-pixel column PXX1 may include four types of sub-pixels with different display colors.

[0068] In the embodiments of the present application, different from the driving method in the related art where a data signal line Data is electrically connected to sub-pixels in the same column, in the present application, the same data signal line Data is electrically connected to sub-pixels PX with the same display color in at least two first sub-pixel columns PXX1. Since the sub-pixels PX electrically connected by the same data signal line Data have the same display color, when the source signal transmission channel in the driving chip transmits a signal to the data signal line Data through the bonding terminals, in different display stages, the voltage jump in the same source signal transmission channel is small, and the difference in the voltage change of the signal in the same data signal line Data is small, avoiding power consumption loss caused by a large voltage jump.

[0069] Among them, the same data signal line Data being electrically connected to sub-pixels PX with the same display color in at least two first sub-pixel columns PXX1 may include the following situations:

[0070] First, the same data signal line Data is electrically connected to sub-pixels PX with the same display color in two first sub-pixel columns PXX1;

[0071] For example, the same data signal line Data is electrically connected to the first-color sub-pixels in the first first sub-pixel column PXX1 and the first-color sub-pixels in the second first sub-pixel column PXX1;

[0072] Another example, the same data signal line Data is electrically connected to the second-color sub-pixels in the first first sub-pixel column PXX1 and the second-color sub-pixels in the second first sub-pixel column PXX1;

[0073] Still another example, the same data signal line Data is electrically connected to the third-color sub-pixels in the first first sub-pixel column PXX1 and the third-color sub-pixels in the second first sub-pixel column PXX1.

[0074] Second, the same data signal line Data is electrically connected to sub-pixels PX with the same display color in three first sub-pixel columns PXX1;

[0075] For example, the same data signal line Data is electrically connected to the first-color sub-pixels in the first first sub-pixel column PXX1, the first-color sub-pixels in the second first sub-pixel column PXX1, and the first-color sub-pixels in the third first sub-pixel column PXX1;

[0076] For another example, the same data signal line Data is electrically connected to the second color sub-pixels in the first first sub-pixel column PXX1, the second color sub-pixels in the second first sub-pixel column PXX1, and the second color sub-pixels in the third first sub-pixel column PXX1 respectively;

[0077] For yet another example, the same data signal line Data is electrically connected to the third color sub-pixels in the first first sub-pixel column PXX1, the third color sub-pixels in the second first sub-pixel column PXX1, and the third color sub-pixels in the third first sub-pixel column PXX1 respectively.

[0078] In the embodiments of the present application, by providing multiple sub-pixels PX including a first sub-pixel column PXX1, the display colors of the sub-pixels PX in the first sub-pixel column PXX1 are not completely the same; the same data signal line Data is electrically connected to the sub-pixels PX with the same display color in at least two first sub-pixel columns PXX1 respectively; in this way, it can be ensured that the sub-pixels electrically connected to each source signal transmission channel (Source channel) of the later driving chip are sub-pixels of the same color. For example, they are all red sub-pixels; or all green sub-pixels; or all blue sub-pixels; when the display panel displays a pure color screen, the difference in the switching voltage (toggle voltage, or jump voltage) of each source signal transmission channel of the driving chip is very small, thereby avoiding the large-scale jump of the voltage signal transmitted by the source signal line when displaying pure color screens of different colors, and further effectively reducing the power consumption of the driving chip. It is estimated that the effective power consumption can be reduced by about 20%, greatly increasing the usage duration of the display product.

[0079] In some array substrates provided in the embodiments of the present application, as Figures 1 to 3 shown, the first peripheral area B1 includes a multiplexing circuit MUX, multiple bonding terminals Pin, and multiple source signal lines Source Line. The data signal line Data is electrically connected to the bonding terminal Pin through the multiplexing circuit MUX; the multiplexing circuit MUX is configured to control the conduction and cut-off between the bonding terminal Pin and the data signal line Data;

[0080] Among them, after two data signal lines Data connected to sub-pixels with the same display color are connected together, they are electrically connected to the bonding terminal Pin through the same source signal line Source Line.

[0081] The multiplexing circuit MUX is disposed at the lower end of the display area AA. One end of the multiplexing circuit MUX is electrically connected to each data signal line Data in the display area AA, and the other end is electrically connected to multiple source signal lines Source Line in the first peripheral area B1. The number of source signal lines Source Line is usually less than or equal to the number of data signal lines Data, and a certain proportional relationship can be satisfied between the two quantities.

[0082] Exemplarily, after two data signal lines Data with the same display color of the connected sub-pixels are connected together, they are electrically connected to the bonding terminal Pin through the same source signal line Source Line. At this time, the number of data signal lines Data is twice the number of source signal lines Source Line.

[0083] Multiple switching transistors are provided in the multiplexing circuit MUX, and each switching transistor controls whether the signal transmission between at least one data signal line Data and a bonding terminal Pin is allowed.

[0084] Here, the number and arrangement of the multiple bonding terminals Pin (for example, also called COP Pad) in the first peripheral area B1 are not limited. Since the bonding terminal Pin will be electrically connected to the driver chip (Driver IC) subsequently, the arrangement of the bonding terminal Pin is related to the setting position and arrangement of the pins in the selected driver chip.

[0085] Exemplarily, the multiple bonding terminals Pin can be arranged in at least one row. As Figure 1 shown, the bonding terminals S1, S2, S3, S4, S5, S6, S7, and S8 are arranged in the same row along the direction perpendicular to the display area AA and pointing to the first peripheral area B1. Among them, the Driver IC bonding area marked by the dotted rectangle in the figure is the area for bonding the driver chip subsequently.

[0086] In some embodiments, the multiple bonding terminals Pin further include dummy bonding terminals (Dummy Pin). Among them, the dummy bonding terminals (Dummy Pin) may not be electrically connected to the data signal lines Data in the display area AA, but are mainly used to improve the topographic flatness in the first peripheral area B1 and avoid the problem of increased bonding process difficulty caused by local unevenness.

[0087] In the array substrate provided by the embodiment of the present application, after two data signal lines Data with the same display color of the connected sub-pixels are connected together, they are electrically connected to the bonding terminal Pin through the same source signal line Source Line; on the one hand, the number of traces in the first peripheral area B1 can be reduced, and the space occupied by the design can be reduced; on the other hand, since the sub-pixels connected by the two data signal lines Data electrically connected to the same source signal line Source Line in the display area AA have the same display color, when the driving chip transmits a signal to the source signal line Source Line, the difference in the voltage signals transmitted by the source signal transmission channels (Source channel) in the driving chip is small, so that the power consumption of the driving chip can be greatly reduced.

[0088] In some array substrates provided by the embodiment of the present application, the multiplexing circuit MUX includes a first multiplexing unit MUX1 and a second multiplexing unit MUX2. Among the two data signal lines Data connected to the same source signal line Source Line, one of the data signal lines Data is electrically connected to the first multiplexing unit MUX1, and the other data signal line Data is electrically connected to the second multiplexing unit MUX2.

[0089] Since among the two data signal lines Data connected to the same source signal line Source Line, one of the data signal lines Data is electrically connected to the first multiplexing unit MUX1, and the other data signal line Data is electrically connected to the second multiplexing unit MUX2, in this way, the first multiplexing unit MUX1 can control whether the signal transmission between one of the two data signal lines Data connected to the same source signal line Source Line and the source signal line, and the second multiplexing unit MUX1 can control whether the signal transmission between the other data signal line Data of the two data signal lines Data connected to the same source signal line Source Line and the source signal line, so that the signal transmission of the two data signal lines Data connected to the same source signal line Source Line can be controlled in different time periods (for example, writing new signals or charging in different time periods).

[0090] In some array substrates provided by the embodiment of the present application, as Figure 1 and Figure 2 shown, the same data signal line Data is electrically connected to the sub-pixels with the same display color in two adjacent first sub-pixel columns PXX1 respectively.

[0091] In some array substrates provided by the embodiment of the present application, as Figure 1 and Figure 2As shown, the multiple sub-pixels PX further include a second sub-pixel column PXX2. The second sub-pixel column PXX2 (e.g., a green sub-pixel column) is located between two adjacent first sub-pixel columns PXX1. The display colors of the sub-pixels in the second sub-pixel column PXX2 are the same, and each sub-pixel in the second sub-pixel column PXX2 is electrically connected to the same data signal line Data.

[0092] In some array substrates provided in the embodiments of the present application, such as Figure 1 and Figure 2 As shown, the first sub-pixel column PXX1 includes first color sub-pixels and second color sub-pixels arranged alternately, and the second sub-pixel column PXX2 includes third color sub-pixels; one second sub-pixel column PXX2 is provided between any two adjacent first sub-pixel columns PXX1;

[0093] Wherein, one of the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel is a red sub-pixel, another is a green sub-pixel, and the other is a blue sub-pixel.

[0094] Such as Figure 1 and Figure 2 As shown, the first color sub-pixels in the first sub-pixel column PXX1 of the first column and the first color sub-pixels in the first sub-pixel column PXX1 of the second column are respectively electrically connected to the first data signal line Data. Each third color sub-pixel in the second sub-pixel column PXX2 of the first column is respectively electrically connected to the second data signal line Data. The second color sub-pixels in the first sub-pixel column PXX1 of the first column and the second color sub-pixels in the first sub-pixel column PXX1 of the second column are respectively electrically connected to the third data signal line Data. Each third color sub-pixel in the second sub-pixel column PXX2 of the second column is respectively electrically connected to the fourth data signal line Data;

[0095] Such as Figure 1 and Figure 2 As shown, the first color sub-pixels in the first sub-pixel column PXX1 of the third column and the first color sub-pixels in the first sub-pixel column PXX1 of the fourth column are respectively electrically connected to the fifth data signal line Data. Each third color sub-pixel in the second sub-pixel column PXX2 of the third column is respectively electrically connected to the sixth data signal line Data. The second color sub-pixels in the first sub-pixel column PXX1 of the third column and the second color sub-pixels in the first sub-pixel column PXX1 of the fourth column are respectively electrically connected to the seventh data signal line Data. Each third color sub-pixel in the second sub-pixel column PXX2 of the fourth column is respectively electrically connected to the eighth data signal line Data.

[0096] Such as Figure 1 and Figure 2As shown, the electrical connection manner between each subsequent column of sub-pixels and the data signal line Data is the same as that of the above eight columns of sub-pixels, and eight columns are used as a repeating unit and repeated in sequence cyclically.

[0097] Exemplarily, the first color sub-pixels in the first sub-pixel column PXX1 of the nth column and the first color sub-pixels in the first sub-pixel column PXX1 of the (n + 1)th column are respectively electrically connected to the nth data signal line Data, each third color sub-pixel in the second sub-pixel column PXX2 of the nth column is electrically connected to the (n + 1)th data signal line Data, the second color sub-pixels in the first sub-pixel column PXX1 of the nth column and the second color sub-pixels in the first sub-pixel column PXX1 of the (n + 1)th column are respectively electrically connected to the (n + 2)th data signal line Data, and each third color sub-pixel in the second sub-pixel column PXX2 of the (n + 1)th column is electrically connected to the (n + 3)th data signal line Data. The first color sub-pixels in the first sub-pixel column PXX1 of the (n + 2)th column and the first color sub-pixels in the first sub-pixel column PXX1 of the (n + 3)th column are respectively electrically connected to the (n + 4)th data signal line Data, each third color sub-pixel in the second sub-pixel column PXX2 of the (n + 2)th column is electrically connected to the (n + 5)th data signal line Data, the second color sub-pixels in the first sub-pixel column PXX1 of the (n + 2)th column and the second color sub-pixels in the first sub-pixel column PXX1 of the (n + 3)th column are respectively electrically connected to the (n + 6)th data signal line Data, and each third color sub-pixel in the second sub-pixel column PXX2 of the (n + 3)th column is electrically connected to the (n + 7)th data signal line Data; where n is a positive integer.

[0098] In some array substrates provided in the embodiments of the present application, such as Figure 1 and Figure 2 shown, the first multiplexing unit MUX1 includes a first multiplexing signal line ML1, a first switching transistor T1, a second switching transistor T2, a third switching transistor T3, and a sixth switching transistor T6, and the second multiplexing unit MUX2 includes a second multiplexing signal line ML2, a fourth switching transistor T4, a fifth switching transistor T5, a seventh switching transistor T7, and an eighth switching transistor T8; the gates of the first switching transistor T1, the second switching transistor T2, the third switching transistor T3, and the sixth switching transistor T6 are all electrically connected to the first multiplexing signal line ML1, and the gates of the fourth switching transistor T4, the fifth switching transistor T5, the seventh switching transistor T7, and the eighth switching transistor T8 are all electrically connected to the second multiplexing signal line ML2;

[0099] The source of the first switching transistor T1 is connected to the part of the first data signal line Data located in the display area AA, and the drain of the first switching transistor T1 is connected to the part of the first data signal line Data located in the first peripheral area B1; the source of the second switching transistor T2 is connected to the part of the second data signal line Data located in the display area AA, and the drain of the second switching transistor T2 is connected to the part of the second data signal line Data located in the first peripheral area B1; the source of the third switching transistor T3 is connected to the part of the third data signal line Data located in the display area AA, and the drain of the third switching transistor T4 is connected to the part of the third data signal line Data located in the first peripheral area B1; the source of the fourth switching transistor T4 is connected to the part of the fourth data signal line Data located in the display area AA, and the drain of the fourth switching transistor T4 is connected to the part of the fourth data signal line Data located in the first peripheral area B1; the source of the fifth switching transistor T5 is connected to the part of the fifth data signal line Data located in the display area AA, and the drain of the fifth switching transistor T5 is connected to the part of the fifth data signal line Data located in the first peripheral area B1; the source of the sixth switching transistor T6 is connected to the part of the sixth data signal line Data located in the display area AA, and the drain of the sixth switching transistor T6 is connected to the part of the sixth data signal line Data located in the first peripheral area B1; the source of the seventh switching transistor T7 is connected to the part of the seventh data signal line Data located in the display area AA, and the drain of the seventh switching transistor T7 is connected to the part of the seventh data signal line Data located in the first peripheral area B1; the source of the eighth switching transistor T8 is connected to the part of the eighth data signal line Data located in the display area AA, and the drain of the eighth switching transistor T8 is connected to the part of the eighth data signal line Data located in the first peripheral area B1.

[0100] Here, the types of the above-mentioned first switching transistor T1, second switching transistor T2, third switching transistor T3, and sixth switching transistor T6, as well as the fourth switching transistor T4, fifth switching transistor T5, seventh switching transistor T7, and eighth switching transistor T8 are not limited.

[0101] Exemplarily, the transistor types of the above-mentioned first switching transistor T1, second switching transistor T2, third switching transistor T3, and sixth switching transistor T6 are the same. For example, they are all N-type switching transistors; or they are all P-type switching transistors.

[0102] Exemplarily, the types of the above-mentioned fourth switching transistor T4, fifth switching transistor T5, seventh switching transistor T7, and eighth switching transistor T8 are the same. For example, they are all N-type switching transistors; or they are all P-type switching transistors.

[0103] Exemplarily, all of the above switching transistors can all be P-type thin film transistors; or all of the above switching transistors can all be N-type thin film transistors.

[0104] Of course, all of the above switching transistors may be P-type MOS transistors; alternatively, all of the above switching transistors may be N-type MOS transistors.

[0105] Among them, for an N-type transistor, the working level state is a high level state, and the non-working level state is a low level state; for a P-type transistor, the working level state is a low level state, and the non-working level state is a high level state. The working level state refers to the level state that can make the source and drain of the transistor conduct, and the non-working level state refers to the level state that can make the source and drain of the transistor disconnect.

[0106] In some array substrates provided by the embodiments of the present application, such as Figure 1 shown, the first color sub-pixel is a red sub-pixel R, the second color sub-pixel is a blue sub-pixel B, and the third color sub-pixel is a green sub-pixel G.

[0107] In some array substrates provided by the embodiments of the present application, such as Figure 2 shown, the first color sub-pixel is a blue sub-pixel B, the second color sub-pixel is a red sub-pixel R, and the third color sub-pixel is a green sub-pixel B.

[0108] In the embodiments of the present application, such as Figure 1 or Figure 2 shown, by setting the same data signal line Data to be electrically connected to the sub-pixels with the same display color in two first sub-pixel columns PXX1 respectively. In this way, it is ensured that the sub-pixels electrically connected to each source signal transmission channel (Source channel) of the later driving chip are sub-pixels of the same color. For example, they are all red sub-pixels; or they are all green sub-pixels; or they are all blue sub-pixels; when the display panel displays a pure color picture, the difference in the switching voltage (toggle voltage, or jump voltage) of each source signal transmission channel of the driving chip is very small, thereby avoiding the large amplitude jump of the voltage signal transmitted by the source signal line when displaying pure color pictures of different colors, and further effectively reducing the power consumption of the driving chip. It is estimated that the effective power consumption can be reduced by about 20%, greatly improving the usage duration of the display product.

[0109] Figure 1 and Figure 2 For the array substrates in , the sub-pixels of two colors, RG or GB, can be set as one pixel unit. In this way, it is beneficial to prepare a display product with a high PPI and improve the display effect.

[0110] In other embodiments, such as Figure 1 or Figure 2As shown, the four sub-pixels of RGBG can be set as the same pixel unit.

[0111] In an exemplary embodiment, the second multiplexing signal line ML2 can be set on the side of the first multiplexing signal line ML1 away from the display area AA, and the distance from each transistor (e.g., the first switching transistor T1, the second switching transistor T2, the third switching transistor T3, and the sixth switching transistor T6) electrically connected to the first multiplexing signal line ML1 to the display area AA is less than that of each transistor (e.g., the fourth switching transistor T4, the fifth switching transistor T5, the seventh switching transistor T7, and the eighth switching transistor T8) electrically connected to the second multiplexing signal line ML2.

[0112] It should be noted that the embodiments of the present application do not limit the shape of the sub-pixels. The shape of each sub-pixel can include polygons, arcs, or a combination of polygons and arcs; among them, polygons include quadrilaterals, pentagons, hexagons, etc.; arcs include circles, semi-circles, ellipses, and semi-ellipses; the combination of polygons and arcs refers to a figure formed by combining polygons and / or arcs, or a figure formed by removing some areas on the basis of polygons and arcs; the shapes of sub-pixels of different display colors can be the same, or the shapes of sub-pixels of different display colors can be different.

[0113] For convenience, the drawings provided in the embodiments of the present application are drawn with each sub-pixel being circular as an example, which does not represent a limitation on the shape of the sub-pixels of the present application.

[0114] The embodiments of the present application do not limit the size of the shape of the sub-pixels. Exemplarily, when the shapes of sub-pixels of different colors are the same, the lengths of their sides, diameters, or diagonals may not be exactly the same. In the drawings of the present application, for simplicity and to clearly show the electrical connection method, each sub-pixel is drawn as circular and of the same size as an example.

[0115] In some array substrates provided in the embodiments of the present application, as Figure 3 shown, the same data signal line Data is electrically connected to sub-pixels with the same display color in three first sub-pixel columns PXX1.

[0116] In some array substrates provided in the embodiments of the present application, as Figure 3 shown, the first sub-pixel column PXX1 includes first-color sub-pixels, second-color sub-pixels, and third-color sub-pixels. The first-color sub-pixels, second-color sub-pixels, and third-color sub-pixels are sequentially repeated along the first direction (e.g., the OA direction), and the first-color sub-pixels, second-color sub-pixels, and third-color sub-pixels in the same row of sub-pixels PX are sequentially repeated along a direction perpendicular to the first direction (e.g., the OA direction).

[0117] In the embodiments of the present application, by connecting sub-pixels of the same R sub-pixels / the same G sub-pixels / the same B sub-pixels in series on the same Source channel and finally driving them with the Source of the same Driver IC, the power consumption of the Driver IC caused by the voltage jump of the Source of the driving chip can be effectively reduced, and finally the power consumption of the screen can be reduced and the overall service life of the machine can be improved.

[0118] In some array substrates provided in the embodiments of the present application, such as Figure 3 shown, the first color sub-pixels in the first sub-pixel column PXX1 of the first, second, and third columns are respectively electrically connected to the first data signal line Data, the second color sub-pixels in the first sub-pixel column PXX1 of the first, second, and third columns are respectively electrically connected to the second data signal line Data, and the third color sub-pixels in the first sub-pixel column PXX1 of the first, second, and third columns are respectively electrically connected to the third data signal line Data; the first color sub-pixels in the first sub-pixel column PXX1 of the fourth, fifth, and sixth columns are respectively electrically connected to the fourth data signal line Data, the second color sub-pixels in the first sub-pixel column PXX1 of the fourth, fifth, and sixth columns are respectively electrically connected to the fifth data signal line Data, and the third color sub-pixels in the first sub-pixel column PXX1 of the fourth, fifth, and sixth columns are respectively electrically connected to the sixth data signal line Data.

[0119] Such as Figure 3 shown, the electrical connection manner between the subsequent columns of sub-pixels and the data signal line Data is the same as that of the above six columns of sub-pixels, and six columns are used as a repeating unit and repeated in sequence.

[0120] In some array substrates provided in the embodiments of the present application, such as Figure 3As shown, the first color sub-pixels in the first sub-pixel column PXX1 of the nth column, the (n + 1)th column, and the (n + 2)th column are respectively electrically connected to the nth data signal line Data. The second color sub-pixels in the first sub-pixel column PXX1 of the nth column, the (n + 1)th column, and the (n + 2)th column are respectively electrically connected to the (n + 1)th data signal line Data. The third color sub-pixels in the first sub-pixel column PXX1 of the nth column, the (n + 1)th column, and the (n + 2)th column are respectively electrically connected to the (n + 2)th data signal line Data. The first color sub-pixels in the first sub-pixel column PXX1 of the (n + 3)th column, the (n + 4)th column, and the (n + 5)th column are respectively electrically connected to the (n + 3)th data signal line Data. The second color sub-pixels in the first sub-pixel column PXX1 of the (n + 3)th column, the (n + 4)th column, and the (n + 5)th column are respectively electrically connected to the (n + 4)th data signal line Data. The third color sub-pixels in the first sub-pixel column PXX1 of the 4th column, the 5th column, and the 6th column are respectively electrically connected to the (n + 5)th data signal line Data. Wherein, n is a positive integer.

[0121] In some array substrates provided in the embodiments of the present application, as Figure 3 shown, the first multiplexing unit MUX1 includes a first multiplexing signal line ML1, a first switching transistor T1, a second switching transistor T2, and a third switching transistor T3. The second multiplexing unit MUX2 includes a second multiplexing signal line ML2, a fourth switching transistor T4, a fifth switching transistor T5, and a sixth switching transistor T6;

[0122] The gates of the first switching transistor T1, the second switching transistor T2, and the third switching transistor T3 are respectively electrically connected to the first multiplexing signal line ML1. The source of the first switching transistor T1 is connected to the part of the first data signal line Data located in the display area AA, and the drain of the first switching transistor T1 is connected to the part of the first data signal line Data located in the first peripheral area B1. The source of the second switching transistor is connected to the part of the second data signal line Data located in the display area AA, and the drain of the second switching transistor T2 is connected to the part of the second data signal line Data located in the first peripheral area B1. The source of the third switching transistor T3 is connected to the part of the third data signal line Data located in the display area AA, and the drain of the third switching transistor T3 is connected to the part of the third data signal line Data located in the first peripheral area B1;

[0123] The gates of the fourth switching transistor T4, the fifth switching transistor T5, and the sixth switching transistor T6 are respectively electrically connected to the second multiplexing signal line ML2. The source of the fourth switching transistor T4 is connected to the part of the 4th data signal line Data located in the display area AA, and the drain of the fourth switching transistor T4 is connected to the part of the 4th data signal line Data located in the first peripheral area B1. The source of the fifth switching transistor T5 is connected to the part of the 5th data signal line Data located in the display area AA, and the drain of the fifth switching transistor T5 is connected to the part of the 5th data signal line Data located in the first peripheral area B1. The source of the sixth switching transistor T6 is connected to the part of the 6th data signal line Data located in the display area AA, and the drain of the sixth switching transistor T6 is connected to the part of the 6th data signal line Data located in the first peripheral area B1.

[0124] Here, the types of the first switching transistor T1, the second switching transistor T2, and the third switching transistor T3, as well as the fourth switching transistor T4, the fifth switching transistor T5, and the sixth switching transistor T6, are not limited.

[0125] Exemplarily, the transistor types of the first switching transistor T1, the second switching transistor T2, and the third switching transistor T3 are the same. For example, they are all N-type switching transistors; or they are all P-type switching transistors.

[0126] Exemplarily, the types of the fourth switching transistor T4, the fifth switching transistor T5, and the sixth switching transistor T6 are the same. For example, they are all N-type switching transistors; or they are all P-type switching transistors.

[0127] Exemplarily, all of the above switching transistors can be P-type thin film transistors; or all of the above switching transistors can be N-type thin film transistors.

[0128] Of course, all of the above switching transistors can be P-type MOS transistors; or all of the above switching transistors can be N-type MOS transistors.

[0129] The embodiments of the present application provide the timing as shown in Figure 4 by taking each transistor as a P-type transistor as an example.

[0130] In some array substrates provided by the embodiments of the present application, as Figure 3 shown, one of the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel is a red sub-pixel, another is a green sub-pixel, and the other is a blue sub-pixel.

[0131] Exemplarily, as Figure 3 shown, the first color sub-pixel can be a red sub-pixel, the second color sub-pixel can be a green sub-pixel, and the third color sub-pixel can be a blue sub-pixel.

[0132] In some array substrates provided by the embodiments of the present application, inFigures 1 to 3 Among them, the first multiplexed signal line ML1 is configured to transmit a first multiplexed signal, and the second multiplexed signal line ML2 is configured to transmit a second multiplexed signal; the transistors electrically connected to the first multiplexed signal line and the transistors electrically connected to the second multiplexed signal line are not turned on simultaneously.

[0133] The first multiplexed signal and the second multiplexed signal are not simultaneously a first-level signal; wherein, the first-level signal is an effective signal for turning on each transistor in the MUX circuit. For example, when all the above-mentioned transistors are P-type transistors, the first multiplexed signal and the second multiplexed signal are not simultaneously a low-level signal, so that the transistors electrically connected to the first multiplexed signal line ML1 and the transistors electrically connected to the second multiplexed signal line ML2 are not turned on simultaneously.

[0134] In an embodiment of the present application, by setting that the transistors electrically connected to the first multiplexed signal line ML1 and the transistors electrically connected to the second multiplexed signal line ML2 are not turned on simultaneously, in this way, for two data signal lines Data connected to the same source signal line Source, the driving chip can be controlled by the MUX circuit to transmit signals to the two data signal lines Data connected to the same source signal line Source in different time periods, so that different signals can be transmitted to these two data signal lines Data.

[0135] In some array substrates provided by the embodiments of the present application, such as Figure 6 shown, the display area AA further includes a plurality of gate lines GL (including GL1, GL2, GL3...) extending along a direction perpendicular to the first direction (for example, the first direction OA). The same gate line GL is connected to the same row of sub-pixels PX. The gate line GL is configured to transmit a gate control signal (also called a gate signal Gout) to the sub-pixel PX. The gate control signal is configured to control the charging time of the sub-pixel PX;

[0136] Combined with the timing signal as Figure 5 shown, after the transistors electrically connected to the first multiplexed signal line ML1 are turned on and then turned off, the transistors electrically connected to the second multiplexed signal line ML1 are turned on; after the transistors electrically connected to the second multiplexed signal line ML2 are turned on, the gate control signal is configured to control the sub-pixel PX to start charging.

[0137] In an exemplary embodiment, when the second multiplexed signal line ML2 is disposed on a side of the first multiplexed signal line ML1 away from the display area AA, and the distances from each transistor (e.g., the first switching transistor T1, the second switching transistor T2, the third switching transistor T3, and the sixth switching transistor T6) electrically connected to the first multiplexed signal line ML1 to the display area AA are less than those of each transistor (e.g., the fourth switching transistor T4, the fifth switching transistor T5, the seventh switching transistor T7, and the eighth switching transistor T8) electrically connected to the second multiplexed signal line ML2, when the four sub-pixels RGBG are of the same pixel unit, as Figure 1 or Figure 2 shown, taking the first column of pixel units as an example, since the first multiplexed signal line ML1 controls the first switching transistor T1, the second switching transistor T2, the third switching transistor T3, and the sixth switching transistor T6 to turn on, the data signal lines Data corresponding to the first column of sub-pixels (R and B), the second column of sub-pixels (G), and the third column of sub-pixels (R and B) in the first column of pixel units start to be charged first, while the data signal line Data corresponding to the fourth column of sub-pixels (G) in the first column of pixel units is not charged; after each transistor electrically connected to the first multiplexed signal line ML1 is turned off, each transistor electrically connected to the second multiplexed signal line ML2 is turned on, and then the data signal line Data corresponding to the fourth column of sub-pixels (G) in the first column of pixel units starts to be charged; in this way, even if the gate control signal controls each data signal line to turn on simultaneously to charge the sub-pixels, at this time, due to the shorter charging time of the data signal line Data corresponding to the fourth column of sub-pixels (G), the charging degree of the fourth column of sub-pixels (G) is actually lower than that of the first column of sub-pixels (R and B), the second column of sub-pixels (G), and the third column of sub-pixels (R and B); the actual display brightness of the fourth column of sub-pixels (G) is lower than that of the second column of sub-pixels (G), so for this pixel unit of the four sub-pixels RGBG, the problem of the display screen being greenish caused by the too high brightness of the green sub-pixels can be improved to a great extent.

[0138] Similarly, for the second column of pixel units, the two green sub-pixels are respectively controlled by the sixth transistor and the eighth transistor, as Figure 1 or Figure 2 shown, in the second column of pixel units, the two green sub-pixels are respectively controlled by the first multiplexed signal line ML1 and the second multiplexed signal line ML2. Due to the timing difference, the actual charging rate of one of the green sub-pixels is lower, and the problem of the display screen being greenish caused by the too high brightness of the green sub-pixels can be improved to a great extent.

[0139] In some array substrates provided in the embodiments of the present application, each transistor electrically connected to the first multiplexed signal line ML1 and each transistor electrically connected to the second multiplexed signal line ML2 are all P-type transistors.

[0140] It should be noted that the above array substrate may further include other structures and components. This specification only describes the structures and components related to the inventive points, and other structures and components can refer to the introductions in the related technologies.

[0141] An embodiment of the present application provides a charging method for an array substrate, which is applied to the array substrate described in any one of the foregoing paragraphs, and in combination with Figure 4 and Figure 5 as shown, the charging method includes:

[0142] S01, The first step, input a first multiplexing signal with a first level to the first multiplexing signal line ML1, and input a second multiplexing signal with a second level to the second multiplexing signal line ML2;

[0143] S02, The second step, input a first multiplexing signal with a second level to the first multiplexing signal line ML1, and input a second multiplexing signal with a first level to the second multiplexing signal line ML2; wherein, the first level is less than the second level;

[0144] S03, The third step, input a gate control signal to the gate line GL, and the gate control signal Gout partially overlaps with the second multiplexing signal Mux2.

[0145] It should be noted that during the above charging process, the second step starts to be executed after the first step is executed, and the third step can start to be executed when the second step starts to be executed and has not ended.

[0146] The following takes charging the first row of sub-pixels as an example to illustrate the charging method for the array substrate:

[0147] Step 1, input a first multiplexing signal with a first level (such as a low level) to the first multiplexing signal line ML1, and input a second multiplexing signal with a second level (such as a high level) to the second multiplexing signal line ML2; the first multiplexing signal line ML1 controls the transistors electrically connected thereto to conduct, and the second multiplexing signal line ML2 controls the transistors electrically connected thereto to turn off, and charges the signal provided by the source signal transmission channel (Source channel) of the driving chip into the corresponding data signal line Data in the first row of sub-pixels;

[0148] Step 2: Input a first multiplexed signal of a second level (e.g., high level) to the first multiplexed signal line ML1, and input a second multiplexed signal of a first level (e.g., low level) to the second multiplexed signal line ML2; the first multiplexed signal line ML1 controls the transistor electrically connected thereto to turn off, and the second multiplexed signal line ML2 controls the transistor electrically connected thereto to turn on, charging the signal provided by the source signal transmission channel (Source channel) of the driving chip into the data signal line Data corresponding to the first row of sub-pixels;

[0149] Step 3: Input a gate control signal (e.g., low level) to the gate line GL, and the gate line GL electrically connected to the first row of sub-pixels PX controls the transistor in the pixel driving circuit in the first row of sub-pixels PX to turn on. The data signal line Data controlled by the first multiplexed signal line ML1 and the data signal line Data controlled by the second multiplexed signal line ML2 respectively start to charge the sub-pixels electrically connected thereto.

[0150] Among them, combined with Figure 5 the timing in it, it can be seen that the falling edge of the Gout1 signal appears after the falling edge of the Mux2 signal, and there is a time overlap between these two signals, so it can be known that Step 3 can start before the end of Step 2.

[0151] The charging process of other rows of sub-pixels is the same as that of the first row. By controlling the gate control signals of different rows, the array substrate completes the charging process row by row.

[0152] Exemplarily, taking the refresh time of one row as H, the on-time t of each mux (e.g., the first multiplexing unit MUX1 or the second multiplexing unit MUX2) ranges approximately from 0.1*H to 0.45*H, and the specific time can be determined according to the product design.

[0153] Since the charging time of the sub-pixels is controlled by the gate control signal provided by the gate line GL, therefore, the charging times of the sub-pixels electrically connected to the first multiplexed signal line ML1 and the sub-pixels electrically connected to the second multiplexed signal line ML2 are the same, and the brightness uniformity is better, thereby enabling the display panel to have a good display effect.

[0154] In an embodiment of the present application, by setting that a plurality of sub-pixels PX include a first sub-pixel column PXX1, the display colors of the sub-pixels PX in the first sub-pixel column PXX1 are not completely the same; the same data signal line Data is electrically connected to the sub-pixels PX with the same display color in at least two first sub-pixel columns PXX1 respectively; in this way, it can be ensured that during the process of charging the sub-pixels of the driving substrate later, the sub-pixels electrically connected to each source signal transmission channel (Source channel) of the driving chip are sub-pixels of the same color. For example, they are all red sub-pixels; or they are all green sub-pixels; or they are all blue sub-pixels; in the case where the display panel displays a pure color screen, the difference in the switching voltage (toggle voltage, or also called jump voltage) of each source signal transmission channel (Source channel) of the driving chip is very small, thereby avoiding a large jump in the voltage signal transmitted by the source signal line when displaying pure color screens of different colors, and further effectively reducing the power consumption of the driving chip. It is estimated that the effective power consumption can be reduced by about 20%, greatly improving the usage duration of the display product.

[0155] An embodiment of the present application provides a display panel, including a driving chip and an array substrate as described in the foregoing, and the driving chip is electrically connected to the bonding terminals Pin on the array substrate.

[0156] In an exemplary embodiment, the above display panel may be a Light-emitting Diode (LED), an Organic light-emitting Diode (OLED), a Micro LED (Micro light Emitting Diode), or a Mini LED (Mini light Emitting Diode) display panel.

[0157] Among them, the above display panel may also be a silicon-based display panel, or it may also be a glass-based display panel. The silicon-based display panel means that the driving circuit of the display panel is arranged on a silicon-based substrate, and the driving circuit is prepared by MOS process. The glass-based display panel means that the driving circuit of the display panel is arranged on a glass-based substrate, and the driving circuit is prepared by TFT process.

[0158] Exemplarily, the above display panel may be a Touch and Display Driver Integration (TDDI) display panel.

[0159] The size of the above display panel is not limited, and it can be applied to large-size or extra-large-size (e.g., 86 inches) UHD (Ultra High Definition) display devices or HD (High Definition) display devices, or it can also be applied to small-size (e.g., 23.6 inches) UHD display devices or HD display devices.

[0160] In an exemplary embodiment, the display panel of the present application can also be used in virtual reality devices or augmented display devices, etc. The display panel can include, but is not limited to: mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo frames, navigators, or any product or component with a display function.

[0161] In the display panel provided by the embodiment of the present application, by setting that a plurality of sub-pixels PX include a first sub-pixel column PXX1, the display colors of the sub-pixels PX in the first sub-pixel column PXX1 are not completely the same; the same data signal line Data is electrically connected to the sub-pixels PX with the same display color in at least two first sub-pixel columns PXX1 respectively; in this way, it can be ensured that the sub-pixels electrically connected to each source signal transmission channel (Source channel) of the later driving chip are sub-pixels of the same color. For example, they are all red sub-pixels; or they are all green sub-pixels; or they are all blue sub-pixels; when the display panel displays a pure color screen, the difference in the switching voltage (toggle voltage, or also called jump voltage) of each source signal transmission channel of the driving chip is very small, thereby avoiding the large amplitude jump of the voltage signal transmitted by the source signal line when displaying pure color screens of different colors, and further effectively reducing the power consumption of the driving chip. It is estimated that the effective power consumption can be reduced by about 20%, greatly improving the usage duration of the display product.

[0162] As described above, the above are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. An array substrate, wherein, It includes a display area and a first peripheral area located on one side of the display area. The display area includes a plurality of sub-pixels arranged in an array and a plurality of data signal lines extending in a first direction. The data signal lines are disposed between two adjacent columns of the sub-pixels. The plurality of sub-pixels includes a first sub-pixel column, and the display colors of the sub-pixels in the first sub-pixel column are not completely the same. The same data signal line is electrically connected to the sub-pixels with the same display color in at least two of the first sub-pixel columns respectively. The first direction is the direction from the display area to the first peripheral area.

2. The array substrate according to claim 1, wherein, The first peripheral area includes a multiplexing circuit, a plurality of bonding terminals, and a plurality of source signal lines. The data signal lines are electrically connected to the bonding terminals through the multiplexing circuit. The multiplexing circuit is configured to control the conduction and cut-off between the bonding terminals and the data signal lines. Among them, after two data signal lines connected to sub-pixels with the same display color are connected together, they are electrically connected to the bonding terminal through the same source signal line.

3. The array substrate according to claim 2, wherein, The multiplexing circuit includes a first multiplexing unit and a second multiplexing unit. One of the two data signal lines connected to the same source signal line is electrically connected to the first multiplexing unit, and the other data signal line is electrically connected to the second multiplexing unit.

4. The array substrate according to claim 3, wherein, The same data signal line is electrically connected to the sub-pixels with the same display color in two adjacent first sub-pixel columns respectively.

5. The array substrate according to claim 4, wherein, The plurality of sub-pixels further includes a second sub-pixel column, which is located between two adjacent first sub-pixel columns. The display colors of the sub-pixels in the second sub-pixel column are all the same, and each of the sub-pixels in the second sub-pixel column is electrically connected to the same data signal line.

6. The array substrate according to claim 5, wherein The first sub-pixel column includes first-color sub-pixels and second-color sub-pixels arranged alternately. The second sub-pixel column includes third-color sub-pixels. One second sub-pixel column is provided between any two adjacent first sub-pixel columns. The first-color sub-pixels in the first column of the first sub-pixel column and the first-color sub-pixels in the second column of the first sub-pixel column are electrically connected to the first data signal line respectively. Each of the third-color sub-pixels in the first column of the second sub-pixel column is electrically connected to the second data signal line. The second-color sub-pixels in the first column of the first sub-pixel column and the second-color sub-pixels in the second column of the first sub-pixel column are electrically connected to the third data signal line respectively. Each of the third-color sub-pixels in the second column of the second sub-pixel column is electrically connected to the fourth data signal line. The first color sub-pixels in the first sub-pixel column of the third column and the first color sub-pixels in the first sub-pixel column of the fourth column are respectively electrically connected to the data signal line described in Article 5. Each of the third color sub-pixels in the second sub-pixel column of the third column is electrically connected to the data signal line described in Article 6. The second color sub-pixels in the first sub-pixel column of the third column and the second color sub-pixels in the first sub-pixel column of the fourth column are respectively electrically connected to the data signal line described in Article 7. Each of the third color sub-pixels in the second sub-pixel column of the fourth column is electrically connected to the data signal line described in Article 8.

7. The array substrate according to claim 6, wherein, The first multiplexing unit includes a first multiplexing signal line, a first switching transistor, a second switching transistor, a third switching transistor, and a sixth switching transistor. The second multiplexing unit includes a second multiplexing signal line, a fourth switching transistor, a fifth switching transistor, a seventh switching transistor, and an eighth switching transistor. The gates of the first switching transistor, the second switching transistor, the third switching transistor, and the sixth switching transistor are all electrically connected to the first multiplexing signal line. The gates of the fourth switching transistor, the fifth switching transistor, the seventh switching transistor, and the eighth switching transistor are all electrically connected to the second multiplexing signal line. The source of the first switching transistor is connected to the part of the first data signal line located in the display area, and the drain of the first switching transistor is connected to the part of the first data signal line located in the first peripheral area. The source of the second switching transistor is connected to the part of the second data signal line located in the display area, and the drain of the second switching transistor is connected to the part of the second data signal line located in the first peripheral area. The source of the third switching transistor is connected to the part of the third data signal line located in the display area, and the drain of the third switching transistor is connected to the part of the third data signal line located in the first peripheral area. The source of the fourth switching transistor is connected to the part of the fourth data signal line located in the display area, and the drain of the fourth switching transistor is connected to the part of the fourth data signal line located in the first peripheral area. The source of the fifth switching transistor is connected to the part of the fifth data signal line located in the display area, and the drain of the fifth switching transistor is connected to the part of the fifth data signal line located in the first peripheral area. The source of the sixth switching transistor is connected to the part of the sixth data signal line located in the display area, and the drain of the sixth switching transistor is connected to the part of the sixth data signal line located in the first peripheral area. The source of the seventh switching transistor is connected to the part of the seventh data signal line located in the display area, and the drain of the seventh switching transistor is connected to the part of the seventh data signal line located in the first peripheral area. The source of the eighth switching transistor is connected to the part of the eighth data signal line located in the display area, and the drain of the eighth switching transistor is connected to the part of the eighth data signal line located in the first peripheral area.

8. The array substrate according to claim 7, wherein, The first color sub-pixel is a red sub-pixel, the second color sub-pixel is a blue sub-pixel, and the third color sub-pixel is a green sub-pixel.

9. The array substrate according to claim 7, wherein, The first color sub-pixel is a blue sub-pixel, the second color sub-pixel is a red sub-pixel, and the third color sub-pixel is a green sub-pixel.

10. The array substrate according to claim 3, wherein, The same data signal line is electrically connected to the sub-pixels with the same display color in three of the first sub-pixel columns respectively.

11. The array substrate according to claim 10, wherein, The first sub-pixel column includes a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel. The first color sub-pixel, the second color sub-pixel, and the third color sub-pixel are sequentially and repeatedly arranged along the first direction. In the same row of sub-pixels, the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel are sequentially and repeatedly arranged perpendicular to the first direction.

12. The array substrate according to claim 11, wherein, The first color sub-pixels in the 1st, 2nd, and 3rd first sub-pixel columns are respectively electrically connected to the 1st data signal line, the second color sub-pixels in the 1st, 2nd, and 3rd first sub-pixel columns are respectively electrically connected to the 2nd data signal line, and the third color sub-pixels in the 1st, 2nd, and 3rd first sub-pixel columns are respectively electrically connected to the 3rd data signal line; The first color sub-pixels in the 4th, 5th, and 6th first sub-pixel columns are respectively electrically connected to the 4th data signal line, the second color sub-pixels in the 4th, 5th, and 6th first sub-pixel columns are respectively electrically connected to the 5th data signal line, and the third color sub-pixels in the 4th, 5th, and 6th first sub-pixel columns are respectively electrically connected to the 6th data signal line.

13. The array substrate according to claim 12, wherein, The first multiplexing unit includes a first multiplexing signal line, a first switching transistor, a second switching transistor, and a third switching transistor. The second multiplexing unit includes a second multiplexing signal line, a fourth switching transistor, a fifth switching transistor, and a sixth switching transistor; The gates of the first switching transistor, the second switching transistor, and the third switching transistor are respectively electrically connected to the first multiplexing signal line. The source of the first switching transistor is connected to the part of the 1st data signal line located in the display area, and the drain of the first switching transistor is connected to the part of the 1st data signal line located in the first peripheral area. The source of the second switching transistor is connected to the part of the 2nd data signal line located in the display area, and the drain of the second switching transistor is connected to the part of the 2nd data signal line located in the first peripheral area. The source of the third switching transistor is connected to the part of the 3rd data signal line located in the display area, and the drain of the third switching transistor is connected to the part of the 3rd data signal line located in the first peripheral area; The gates of the fourth switching transistor, the fifth switching transistor, and the sixth switching transistor are respectively electrically connected to the second multiplexing signal line. The source of the fourth switching transistor is connected to the portion of the fourth data signal line located in the display area, and the drain of the fourth switching transistor is connected to the portion of the fourth data signal line located in the first peripheral area. The source of the fifth switching transistor is connected to the portion of the fifth data signal line located in the display area, and the drain of the fifth switching transistor is connected to the portion of the fifth data signal line located in the first peripheral area. The source of the sixth switching transistor is connected to the portion of the sixth data signal line located in the display area, and the drain of the sixth switching transistor is connected to the portion of the sixth data signal line located in the first peripheral area.

14. The array substrate according to claim 13, wherein, One of the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel is a red sub-pixel, another is a green sub-pixel, and the remaining one is a blue sub-pixel.

15. The array substrate according to any one of claims 7 to 9 and 13 to 14, wherein, The first multiplexing signal line is configured to transmit a first multiplexing signal, and the second multiplexing signal line is configured to transmit a second multiplexing signal; The transistors electrically connected to the first multiplexing signal line and the transistors electrically connected to the second multiplexing signal line are not turned on simultaneously.

16. The array substrate according to claim 15, wherein, The display area further includes a plurality of gate lines extending perpendicular to the first direction. The same gate line is connected to the sub-pixels in the same row. The gate line is configured to transmit a gate control signal to the sub-pixels, and the gate control signal is configured to control the charging time of the sub-pixels; After the transistors electrically connected to the first multiplexing signal line are turned on and then turned off, the transistors electrically connected to the second multiplexing signal line are turned on; After the transistors electrically connected to the second multiplexing signal line are turned on, the gate control signal is configured to control the sub-pixels to start charging.

17. The array substrate according to claim 16, wherein, The transistors electrically connected to the first multiplexing signal line and the transistors electrically connected to the second multiplexing signal line are all P-type transistors.

18. A charging method for an array substrate, wherein, Applied to the array substrate according to any one of claims 1 to 17, the charging method includes: Inputting the first multiplexing signal of the first level to the first multiplexing signal line, and inputting the second multiplexing signal of the second level to the second multiplexing signal line; Inputting the second multiplexing signal of the second level to the first multiplexing signal line, and inputting the first multiplexing signal of the first level to the second multiplexing signal line; wherein, the first level is less than the second level; Inputting a gate control signal to the gate line, and the gate control signal partially overlaps with the second multiplexing signal.

19. A display panel, wherein, Including a driving chip and the array substrate according to any one of claims 2 to 17, and the driving chip is electrically connected to the bonding terminals on the array substrate.

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