Efficient processing of multiple non-overlapping layer images in display processing unit

Abstract

Efficient processing of multiple non-overlapping layer images in a display processing unit is disclosed herein. In this regard, in some exemplary aspects, a display processing unit is provided that includes a plurality of memory access pipeline circuits and a layer mixer circuit. For each non-overlapping layer image of the plurality of non-overlapping layer images, the memory access pipeline circuitry obtains image configuration data for the non-overlapping layer image and extracts the non-overlapping layer image from the image data storage device based on the image configuration data. The memory access pipeline circuitry then outputs each pixel of the non-overlapping layer image as part of an intermediate premixed image data stream based on the image configuration data. The layer mixer circuit mixes the intermediate premixed image data stream and a background layer image data stream including a background layer image as a display data stream, and outputs the display data stream to a display device.

Description

[0001] Priority Application

[0002] This application claims priority to U.S. Patent Application Serial No. 18 / 066,034, filed on December 14, 2022, entitled "EFFICIENTLY PROCESSING MULTIPLE NON - OVERLAPPING LAYER IMAGES IN DISPLAY PROCESSING UNITS", the entire disclosure of which is incorporated herein by reference. Background

[0003] I. Technical Field

[0004] The technology of the present disclosure generally relates to display processing units in processor - based devices and, more particularly, to processing and blending layer images for display.

[0005] II. Background Art

[0006] Modern processor - based devices may include a dedicated processing unit, referred to as a display processing unit, to handle operations for extracting, processing, and blending image data for display on a display device. Conventional display processing units include multiple memory access pipelines, each of which includes, for example, extraction circuitry for retrieving image data from a memory or other image data storage device, and a pixel processing unit for performing image processing on the image data (e.g., color correction operations, zoom operations, scaling operations, etc.). The image data is then fed by each memory access pipeline to a layer mixer circuit that performs the blending of multiple layer images, and further fed to a pixel processing unit that performs display - specific image processing operations. Finally, the blended and processed image data is transmitted to the display device for display to the user.

[0007] One task often performed by a display processing unit is to extract multiple non - overlapping layer images and blend the multiple non - overlapping layer images with a background layer image. In a conventional display processing unit, each memory access pipeline is configured to extract a single non - overlapping layer image. Thus, blending multiple non - overlapping layer images with a background layer image requires the use of multiple memory access pipelines, one for the background layer image and one for each non - overlapping layer image. Therefore, the number of non - overlapping images that can be blended by the display processing unit is limited by the number of memory access pipelines provided by the display processing unit. Summary of the Invention

[0008] Aspects disclosed in the detailed description include efficiently processing multiple non-overlapping layer images in a display processing unit. Related apparatuses, methods, and computer-readable media are also disclosed. In this regard, in some exemplary aspects disclosed herein, the display processing unit provides a plurality of memory access pipeline circuits and a layer mixer circuit. The first memory access pipeline circuit is configured to extract multiple non-overlapping layer images (i.e., layer images whose positions and dimensions do not overlap) and pre-mix them into an intermediate pre-mixed image, which is then mixed by the layer mixer circuit with a background layer image extracted by the second memory access pipeline. To generate the intermediate pre-mixed image, the first memory access pipeline performs a series of operations on each of the non-overlapping layer images. The first memory access pipeline first obtains image configuration data for the non-overlapping layer images and then extracts the non-overlapping layer images from an image data storage device based on the image configuration data. The first memory access pipeline then outputs each pixel of the non-overlapping layer images as part of the intermediate pre-mixed image to an intermediate pre-mixed image data stream based on the image configuration data. When receiving the intermediate pre-mixed image data stream from the first memory access pipeline and the background image data stream from the second memory access pipeline, the layer mixer circuit mixes the intermediate pre-mixed image data stream with the background layer image data stream as a display data stream. The display data stream can then be sent to a display device for display to a user.

[0009] In some aspects, the first memory access pipeline circuit may include a plurality of image configuration registers that may receive image configuration data from, for example, a running software process and may be used to populate an image configuration queue. The first memory access pipeline circuit may then obtain the image configuration data for each non-overlapping layer image from the top entry in the image configuration queue (e.g., by "popping" the image configuration for each non-overlapping layer image from the image configuration queue). According to some aspects, the first memory access pipeline circuit may calculate a set of position coordinates and dimensions of the intermediate pre-mixed image to be generated based on the image configuration data received for the multiple non-overlapping layer images. The first memory access pipeline circuit may then send the set of position coordinates and dimensions of the intermediate pre-mixed image to the layer mixer circuit for mixing the intermediate pre-mixed image data stream and the background layer image data stream. In some aspects, the first memory access pipeline circuit may include two (2) image configuration queues such that the first memory access pipeline circuit may obtain image configuration data from the first image configuration queue while concurrently receiving the image configuration data for the next set of non-overlapping layer images into the second image configuration queue.

[0010] In some aspects, as part of outputting each pixel of the non-overlapping layer image to the intermediate pre-blended image data stream, the first memory access pipeline circuit may output blend bypass pixels (e.g., pixels with a pre-specified color value) for each pixel of the intermediate pre-blended image that does not correspond to a pixel of the non-overlapping layer image. When the layer mixer circuit subsequently blends the intermediate pre-blended image data stream and the background layer image data stream, the layer mixer circuit may blend each pixel of the intermediate pre-blended image data stream that corresponds to the non-overlapping layer with the corresponding pixel of the background layer image. The layer mixer circuit may also output the corresponding pixel of the background layer image for each blend bypass pixel of the intermediate pre-blended image data stream.

[0011] In some aspects, the layer mixer circuit may employ multiple blending stages to blend images from multiple memory access pipeline circuits. According to such aspects, each blending stage corresponds to a memory access pipeline circuit among the multiple memory access pipeline circuits, and the layer mixer circuit outputs the display data stream of each blending stage prior to the final blending stage as the background layer image data stream to the subsequent blending stage. The layer mixer circuit then outputs the display data stream of the final blending stage to the display device. Some such aspects may enable the first memory access pipeline circuit to transfer image data to one or more blending stages by providing a layer mixer configuration queue, and the layer mixer circuit will receive the memory access pipeline identifier and the blending stage indication for the first memory access pipeline circuit in the layer mixer configuration queue. The layer mixer circuit assigns a label corresponding to the layer mixer configuration queue to the first memory access pipeline circuit based on the memory access pipeline identifier, thereby associating the layer mixer configuration queue with the first memory access pipeline. When receiving the intermediate pre-blended image data stream from the first memory access pipeline circuit, the layer mixer circuit obtains the memory access pipeline identifier and the blending stage indication from the layer mixer configuration queue based on the label, and blends the intermediate pre-blended image data stream and the background layer image data stream in the appropriate blending stage based on the blending stage indication.

[0012] In another aspect, a display processing unit is provided. The display processing unit includes a plurality of memory access pipeline circuits and a layer mixer circuit. A first memory access pipeline circuit among the plurality of memory access pipeline circuits is configured to obtain, for each of a plurality of non-overlapping layer images, image configuration data for the non-overlapping layer image. The first memory access pipeline circuit is further configured to extract the non-overlapping layer image from an image data storage device based on the image configuration data. The first memory access pipeline circuit is also configured to output, based on the image configuration data, each pixel of the non-overlapping layer image as part of an intermediate pre-mixed image to an intermediate pre-mixed image data stream. The layer mixer circuit is configured to mix the intermediate pre-mixed image data stream and a background layer image data stream including a background layer image as a display data stream. The layer mixer circuit is further configured to output the display data stream to a display device.

[0013] In another aspect, a display processing unit is provided. The display processing unit includes components for performing the following operations: obtaining, for each of a plurality of non-overlapping layer images, image configuration data for the non-overlapping layer image; extracting the non-overlapping layer image from an image data storage device based on the image configuration data; and outputting, based on the image configuration data, each pixel of the non-overlapping layer image as part of an intermediate pre-mixed image to an intermediate pre-mixed image data stream. The display processing unit further includes components for mixing the intermediate pre-mixed image data stream and a background layer image data stream including a background layer image as a display data stream. The display processing unit further includes components for outputting the display data stream to a display device.

[0014] In another aspect, a method for efficiently processing a plurality of non-overlapping layer images is provided. The method includes: obtaining, for each of a plurality of non-overlapping layer images, by a first memory access pipeline circuit of a display processing unit, image configuration data for the non-overlapping layer image. The method further includes extracting, by the first memory access pipeline circuit, the non-overlapping layer image from an image data storage device based on the image configuration data. The method further includes outputting, by the first memory access pipeline circuit, based on the image configuration data, each pixel of the non-overlapping layer image as part of an intermediate pre-mixed image to an intermediate pre-mixed image data stream. The method further includes mixing, by a layer mixer circuit of the display processing unit, the intermediate pre-mixed image data stream and a background layer image data stream as a display data stream. The method further includes outputting, by the layer mixer circuit, the display data stream to a display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a block diagram of an exemplary processor-based device according to some aspects, the processor-based device including a display processing unit configured to efficiently process a plurality of non-overlapping layer images;

[0016] Figure 2 is a diagram illustrating the use of multiple display pipelines in a conventional display processing unit to blend multiple non - overlapping layer images and a background layer image according to some aspects;

[0017] Figure 3 is an illustration of, according to some aspects, when blending Figure 2 the multiple non - overlapping layer images and the background layer image, the processing timeline of a conventional display processing unit;

[0018] Figure 4 is a more detailed block diagram illustrating, according to some aspects, the memory access pipeline circuit and the layer mixer circuit of a display processing unit for efficiently processing multiple non - overlapping layer images Figure 1 ;

[0019] Figure 5 is an illustration of, according to some aspects, using Figure 1 and Figure 4 in a display processing unit to blend multiple non - overlapping layer images into an intermediate pre - blended image, which is then blended with the background layer image;

[0020] Figure 6 is an illustration of, according to some aspects, when blending Figure 5 the multiple non - overlapping layer images and the background layer image, Figure 1 and Figure 4 the processing timeline of a display processing unit;

[0021] Figure 7 is an illustration of, according to some aspects, the mixing levels used by a display processing unit when blending images provided by multiple memory access pipeline circuits Figure 1 and Figure 4 ;

[0022] Figures 8A to 8C provides a flowchart illustrating exemplary operations for efficiently processing multiple non - overlapping layer images according to some aspects;

[0023] Figure 9A and Figure 9B provides a flowchart illustrating exemplary operations performed by the layer mixer circuit of Figure 1 and Figure 4 to blend images from multiple memory access pipeline circuits using mixing levels; and

[0024] Figure 10 is a block diagram of an exemplary processor - based device that may include Figure 1 and Figure 4 a display processing unit. Detailed implementation manners

[0025] Referring now to the drawings, several exemplary aspects of the present disclosure are described. The term "exemplary" is used herein to mean "serving as an example, instance, or illustration". Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or having an advantage over other aspects.

[0026] Aspects disclosed in the detailed description include efficiently processing multiple non - overlapping layer images in a display processing unit. Related apparatuses, methods, and computer - readable media are also disclosed. In this regard, in some exemplary aspects disclosed herein, the display processing unit provides a plurality of memory access pipeline circuits and layer mixer circuits. The first memory access pipeline circuit is configured to extract multiple non - overlapping layer images (i.e., layer images whose positions and dimensions do not overlap) and pre - mix them into an intermediate pre - mixed image, which is then mixed by the layer mixer circuit with a background layer image extracted by the second memory access pipeline. To generate the intermediate pre - mixed image, the first memory access pipeline performs a series of operations on each of the non - overlapping layer images. The first memory access pipeline first obtains image configuration data for the non - overlapping layer image and then extracts the non - overlapping layer image from the image data storage device based on the image configuration data. The first memory access pipeline then outputs each pixel of the non - overlapping layer image as part of the intermediate pre - mixed image to the intermediate pre - mixed image data stream based on the image configuration data. When receiving the intermediate pre - mixed image data stream from the first memory access pipeline and the background image data stream from the second memory access pipeline, the layer mixer circuit mixes the intermediate pre - mixed image data stream with the background layer image data stream as a display data stream. The display data stream can then be sent to a display device for display to the user.

[0027] In some aspects, the first memory access pipeline circuit may include a plurality of image configuration registers that may receive image configuration data from, for example, a software process being executed and may be used to populate an image configuration queue. The first memory access pipeline circuit may then obtain image configuration data for each non-overlapping layer image from the top entry in the image configuration queue (e.g., by "popping" the image configuration for each non-overlapping layer image from the image configuration queue). According to some aspects, the first memory access pipeline circuit may calculate a set of position coordinates and dimensions of an intermediate pre-blended image to be generated based on the image configuration data received for the plurality of non-overlapping layer images. The first memory access pipeline circuit may then send the set of position coordinates and dimensions of the intermediate pre-blended image to a layer mixer circuit for mixing the intermediate pre-blended image data stream and the background layer image data stream. In some aspects, the first memory access pipeline circuit may include two (2) image configuration queues such that the first memory access pipeline circuit may obtain image configuration data from a first image configuration queue while concurrently receiving image configuration data for the next set of non-overlapping layer images into a second image configuration queue.

[0028] Some aspects may provide that, as part of outputting each pixel of a non-overlapping layer image to the intermediate pre-blended image data stream, the first memory access pipeline circuit may output blend bypass pixels (e.g., pixels having a pre-specified color value) for each pixel of the intermediate pre-blended image that does not correspond to a pixel of the non-overlapping layer image. When the layer mixer circuit subsequently mixes the intermediate pre-blended image data stream and the background layer image data stream, the layer mixer circuit may blend each pixel of the intermediate pre-blended image data stream that corresponds to a non-overlapping layer with the corresponding pixel of the background layer image. The layer mixer circuit may also output the corresponding pixel of the background layer image for each blend bypass pixel of the intermediate pre-blended image data stream.

[0029] In some aspects, a layer mixer circuit may employ multiple mixing stages to mix images from multiple memory access pipeline circuits. According to such aspects, each mixing stage corresponds to a memory access pipeline circuit among the multiple memory access pipeline circuits, and the layer mixer circuit outputs the display data stream of each mixing stage before the final mixing stage as a background layer image data stream to a subsequent mixing stage. The layer mixer circuit then outputs the display data stream of the final mixing stage to a display device. Some such aspects may enable a first memory access pipeline circuit to transfer image data to one or more mixing stages by providing a layer mixer configuration queue, and the layer mixer circuit receives a memory access pipeline identifier and a mixing stage indication for the first memory access pipeline circuit in the layer mixer configuration queue. The layer mixer circuit assigns a tag corresponding to the layer mixer configuration queue to the first memory access pipeline circuit based on the memory access pipeline identifier, thereby associating the layer mixer configuration queue with the first memory access pipeline. When receiving an intermediate pre-mixed image data stream from the first memory access pipeline circuit, the layer mixer circuit obtains the memory access pipeline identifier and the mixing stage indication from the layer mixer configuration queue based on the tag, and mixes the intermediate pre-mixed image data stream and the background layer image data stream in an appropriate mixing stage based on the mixing stage indication.

[0030] In this regard, Figure 1 is a diagram of an exemplary processor-based device 100 that includes an image data storage device 102, a display processing unit 104, and a display device 106. As a non-limiting example, the image data storage device 102 may include any data storage device on which image data is stored, and in some aspects may include a double data rate (DDR) memory. In some aspects, the image data storage device 102 may be communicatively coupled to the display processing unit 104 via a network-on-chip (NOC), which is not shown in Figure 1 for clarity. The display processing unit 104 of the processor-based device 100 is configured to handle operations for extracting, processing, and mixing image data for display on the display device 106. The display device 106 according to some aspects may include any type of display, including but not limited to a cathode ray tube (CRT) device, a liquid crystal display (LCD) device, a plasma display device, etc. It will be understood that although the display device 106 is illustrated as an integrated element of the processor-based device 100 in Figure 1 some aspects may provide that the display device 106 includes a peripheral device communicatively coupled to the processor-based device 100 but separate from the processor-based device.

[0031] Figure 1The display processing unit 104 includes a plurality of memory access pipeline circuits 108(0) to 108(M), each of the plurality of memory access pipeline circuits being configured to extract image data (not shown) from the image data storage device 102, perform image processing operations on the image data, and provide the processed image data to the layer mixer circuit 118 for mixing and blending. The memory access pipeline circuits 108(0) to 108(M) include corresponding extraction circuits (labeled "FETCH" in Figure 1 ), 110(0) to 110(M), buffers (labeled "BUFFER" in Figure 1 ), 112(0) to 112(M), unpacking circuits (labeled "UNPACK" in Figure 1 ), 114(0) to 114(M), and pixel processing circuits (labeled "PIXELPROC" in Figure 1 ), 116(0) to 116(M). In normal operation, the extraction circuits 110(0) to 110(M) are configured to retrieve the image data for an image from the image data storage device 102 and store the retrieved image data in the corresponding buffers 112(0) to 112(M). The unpacking circuits 114(0) to 114(M) are configured to receive the image data stream from the corresponding buffers 112(0) to 112(M) and process the image data stream to obtain information such as the rows and columns of each image and the alpha / red / green / blue (ARGB) data for each pixel of each image. As a non-limiting example, the pixel processing circuits 116(0) to 116(M) are configured to then perform additional processing on the image data stream, such as color correction, zooming, magnifying / shrinking, and the like. The layer mixer circuit 118 is configured to receive the image data stream from the pixel processing circuits 116(0) to 116(M) and blend the image data stream into a single display data stream. The resulting display data stream is then transmitted to the pixel processing circuit 120 for additional display-specific processing and ultimately transmitted to the display device 106 for display.

[0032] Figure 1 The processor-based device 100 may encompass any of the known digital logic elements, semiconductor circuits, processing cores, and / or memory structures, as well as other elements or combinations thereof. The aspects described herein are not limited to any particular arrangement of elements, and the disclosed techniques can be readily extended to various structures and layouts on a semiconductor die or package. It will be understood that some aspects of the processor-based device 100 may include elements in addition to those Figure 1 illustrated, and / or may include Figure 1More or fewer components as illustrated. For example, the processor-based device 100 may also include one or more buffers, caches, controllers, and / or communication buses, which are omitted in Figure 1 for clarity.

[0033] As described above, a task often performed by a conventional display processing unit is to extract multiple non-overlapping layer images and blend them with a background layer image. Since the memory access pipelines in a conventional display processing unit are each configured to extract a single non-overlapping layer image, the blending of multiple non-overlapping layer images with the background layer image requires the use of multiple memory access pipelines (i.e., one memory access pipeline for the background layer image and one memory access pipeline for each non-overlapping layer image). Thus, the number of non-overlapping images that can be blended is limited by the number of memory access pipelines provided by the display processing unit.

[0034] Accordingly, to efficiently process multiple non-overlapping layer images, Figure 1 the memory access pipeline circuits 108(0) to 108(M) of the display processing unit 104 are each configured to retrieve multiple non-overlapping layer images and generate an intermediate pre-blended layer image that includes the multiple non-overlapping layer images. Specifically, each of the extraction circuits 110(0) to 110(M) is configured to dynamically extract multiple non-overlapping layer images from the image data storage device 102 based on, for example, image configuration data provided by a software process (not shown) being executed. Additionally, each memory access pipeline circuit 108(0) to 108(M) further provides a corresponding pre-blending circuit (labeled "pre-blend" in Figure 1 ) 122(0) to 122(M), which is configured to combine the non-overlapping layer images into an intermediate pre-blended layer image that can then be transmitted to the layer mixer circuit 118 for blending with the background layer image. The operations performed by Figure 4 the memory access pipeline circuits 108(0) to 108(M) and the layer mixer circuit 118 for efficiently processing multiple non-overlapping layer images are discussed in more detail below for Figure 1 .

[0035] Before describing in more detail Figure 1 the memory access pipeline circuits 108(0) to 108(M) and the layer mixer circuit 118, for purposes of comparison, first describe the use of multiple display pipelines in a conventional display processing unit to blend multiple non-overlapping layer images and a background layer image. In this regard, Figure 2 illustrates a background layer image 200 and four (4) non-overlapping layer images 202(0) to 202(3), which are to be combined into a final blended image 204 for use in, for example, Figure 1displayed on the display device 106 of the display device. Assume that Figure 1 the display processing unit 104 operates in a conventional manner, and each of the background layer image 200 and the non-overlapping layer images 202(0) to 202(3) will be Figure 1 extracted by a separate memory access pipeline circuit among the memory access pipeline circuits 108(0) to 108(M) (assuming M≥4). Therefore, in Figure 1 the example of, the background layer image 200 is extracted and processed by the memory access pipeline circuit 108(0), the non-overlapping layer image 202(0) is extracted by the memory access pipeline circuit 108(1), the non-overlapping layer image 202(1) is extracted by the memory access pipeline circuit 108(2) ( Figure 1 not shown in), the non-overlapping layer image 202(2) is extracted by the memory access pipeline circuit 108(3) ( Figure 1 not shown in), and the non-overlapping layer image 202(3) is extracted by the memory access pipeline circuit 108(4) ( Figure 1 not shown in). The image data streams for the background layer image 200 and the non-overlapping layer images 202(0) to 202(3) are then transmitted to the layer mixer circuit 118, which mixes the image data streams into the final mixed image 204.

[0036] The operation of a conventional display processing unit when mixing multiple non-overlapping layer images and a background layer image as described in Figure 2 results in all the memory access pipeline circuits 108(0)-108(4) being employed during the duration of generating the final mixed image 204, even though each of the memory access pipeline circuits 108(1)-108(4) only supplies a small portion of the final mixed image 204. This is illustrated by Figure 3 the processing timeline 300 shown. The processing timeline 300 shows the activities of the memory access pipeline circuits 108(0) to 108(4) and the layer mixer circuit 118 operating in a conventional manner as described above for Figure 2 during one display screen refresh cycle. Figure 1

[0037] In Figure 3 , the annotation "VSYNC" indicates the start of vertical synchronization, while the annotations "VBLANK" and "BLANKING" indicate the time periods during which image data is not sent by the layer mixer circuit 118 (e.g., via Figure 1 the pixel processing circuit 120) to the display device 106. Figure 3The annotation "prefill" in indicates the period during which each of the memory access pipeline circuits 108(0) to 108(4) is extracting and filling the corresponding buffers 112(0) to 112(4), while the annotation "idle" indicates the period during which each of the memory access pipeline circuits 108(0) to 108(4) is waiting to send the image data stream to the layer mixer circuit 118. Finally, in Figure 3 the annotation "active" indicates the period during which each of the memory access pipeline circuits 108(0) to 108(4) is actively processing the image data stream and sending it to the layer mixer circuit 118, and the annotation "mixing active data" indicates the period during which the layer mixer circuit 118 is mixing the image data stream and sending the display data stream to the display device 106.

[0038] As Figure 3 seen, during the entire time that the layer mixer circuit 118 is mixing the image data stream and sending the display data stream to the display device 106, the memory access pipeline circuit 108(0) that is processing and sending the background layer image data stream for the Figure 2 background layer image 200 is active. However, each of the memory access pipeline circuits 108(1) to 108(4) is active only during a relatively short period that roughly corresponds in position and duration to the Figure 2 position and size of the associated non-overlapping layer images 202(0) to 202(3). Thus, the conventional processing of multiple non-overlapping layer images can be considered inefficient because each of the memory access pipeline circuits can extract only a single layer image (i.e., the background layer image or a single non-overlapping layer image), and also because each of the memory access pipeline circuits that processes the non-overlapping layer images is used only for a small fraction of the total time required to generate the final display data stream.

[0039] Therefore, Figure 4 more particularly illustrates the memory access pipeline circuits 108(0) and 108(1) and the layer mixer circuit 118 for efficiently processing multiple non-overlapping layer images according to some aspects. Figure 1 Figure 4 shows Figure 1 the processor-based device 100, which includes an image data storage device 102, a display processing unit 104, and a display device 106. Figure 4 Also shown in Figure 1 are the memory access pipeline circuits 108(0) and 108(1) and the layer mixer circuit 118. For clarity, Figure 4 the other elements of the processor-based device 100 are omitted in

[0040] Figure 4 The memory access pipeline circuit 108(1) is configured to extract and pre-mix a plurality of non-overlapping layer images, such as Figure 2 the non-overlapping layer images 202(0) to 202(3). The memory access pipeline circuit 108(1) then uses the pre-mixing circuit 122(1) to mix the non-overlapping layer images 202(0) to 202(3) into an intermediate pre-mixed image data stream 400 that is provided to the layer mixer circuit 118. Figure 4 The memory access pipeline circuit 108(0) is configured to extract a background layer image (such as, Figure 2 the background layer image 200), and provide the background layer image data stream 402 to the layer mixer circuit 118. The layer mixer circuit 118 then mixes the background layer image data stream 402 and the intermediate pre-mixed image data stream 400 into a display data stream 404, which is then transmitted to the display device 106 for display. Examples of intermediate pre-mixed images that can be generated and transmitted as the intermediate pre-mixed image data stream 400 are shown and discussed in more detail below for Figure 6 an intermediate pre-mixed image data stream 400.

[0041] To generate the intermediate pre-mixed image data stream 400, in some aspects, the memory access pipeline circuit 108(1) may first obtain image configuration data (labeled "image configuration" in Figure 4 for each of the non-overlapping layer images 202(0) to 202(3). As a non-limiting example, the image configuration data 406 may include a source image size, an output image size, a set of source image position coordinates, a set of output image position coordinates, a source address, a stride value, an image format, and / or an unpacking mode value for the corresponding non-overlapping layer images 202(0) to 202(3). The image configuration data 406 for each of the non-overlapping layer images 202(0) to 202(3) may be provided by a software process (not shown), such as a driver process. In some aspects, the image configuration data 406 may be placed into a plurality of image configuration registers (labeled "image configuration registers" in Figure 4 408(0) to 408(C), which may then be used to push the image configuration data 406 into a plurality of image configuration queue entries (labeled "image configuration queue" in Figure 4 of the image configuration queue 412(0) (labeled "image configuration queue entry" in Figure 4in one of the entries labeled "entry") 410(0) to 410(Q). For example, the image configuration data 406 for each of the non-overlapping layer images 202(0) to 202(3) can be pushed into the image configuration queue 412(0) in an order that reflects the vertical position of each of the non-overlapping layer images 202(0) to 202(3) (e.g., in ascending order of Y coordinate). The memory access pipeline circuit 108(1) can then obtain the image configuration data 406 for each of the non-overlapping layer images 202(0) to 202(3) from the top entry (e.g., Figure 4 the image configuration queue entry 410(0)) in the image configuration queue 412(0) by "popping" the image configuration queue entry 410(0) from the image configuration queue 412(0).

[0042] Some aspects may provide that when the memory access pipeline circuit 108(1) receives the image configuration data 406 for each of the non-overlapping layer images 202(0) to 202(3), the memory access pipeline circuit 108(1) can calculate a set of position coordinates (in Figure 4 labeled "position") 414 and dimensions 416 of the intermediate pre-mixed image to be generated based on the image configuration data 406 received for the multiple non-overlapping layer images 202(0) to 202(3). For example, the relative dimensions and positions of the non-overlapping layer images 202(0) to 202(3) can be used by the memory access pipeline circuit 108(1) to determine the dimensions and position of the intermediate pre-mixed image that encompasses all of the non-overlapping layer images 202(0) to 202(3). The memory access pipeline circuit 108(1) can then send this set of position coordinates 414 and dimensions 416 of the intermediate pre-mixed image to the layer mixer circuit 118 for mixing the intermediate pre-mixed image data stream 400 and the background layer image data stream 402.

[0043] In some aspects, the memory access pipeline circuit 108(1) can provide two (2) image configuration queues 412(0) and 412(1). In such aspects, the memory access pipeline circuit 108(1) is configured to obtain the image configuration data 406 from, for example, the image configuration queue 412(0), while concurrently receiving the image configuration data 406 for the next set of non-overlapping layer images (not shown) into the multiple image configuration queue entries (in Figure 4 labeled "entry") 418(0) to 418(Q) of the image configuration queue 412(1). Selecting the image configuration queue 412(0) or the image configuration queue 412(1) as the "active" queue from which to read the image configuration data 406 can be done using, for example, one of the image configuration registers 408(0) to 408(C).

[0044] Exemplary image configuration registers 408(0) to 408(C) according to some aspects may include the registers described in Table 1 below:

[0045] Configuration Register Description Multi-Layer Configuration Enable Used to enable the multi-layer configuration mode Multi-Layer Push Push all configuration data into the configuration queue Multi-Layer Configuration Set Swap Used to swap the active image configuration queue

[0046] Table 1

[0047] After obtaining image configuration data 406 for a non-overlapping layer image (such as non-overlapping layer image 202(0)) from the image configuration queue 412(0), the memory access pipeline circuit 108(1) then outputs each pixel of the non-overlapping layer image 202(0) as part of an intermediate pre-mixed image to the intermediate pre-mixed image data stream 400 using the pre-mixing circuit 122(1) based on the image configuration data 406 for the non-overlapping layer image 202(0). In some aspects, the operation of outputting each pixel of the non-overlapping layer image 202(0) to the intermediate pre-mixed image data stream 400 involves outputting a mixed bypass pixel (e.g., a pixel with a pre-specified color value) for each pixel of the intermediate pre-mixed image that does not correspond to a pixel of the non-overlapping layer image 202(0), where the mixed bypass pixel information includes the coordinates (e.g., X position and Y position) of the intermediate pre-mixed image.

[0048] The pre-mixing circuit 122(1) uses the image configuration data to determine the target coordinates for the non-overlapping layer image 202(0) in the intermediate pre-mixed image and tracks the output pixel positions. When processing for the non-overlapping layer image 202(0) is complete, the memory access pipeline circuit 108(1) then obtains image configuration data 406 for the next non-overlapping layer image (e.g., non-overlapping layer image 202(1)) from the image configuration queue 412(0) and begins processing the image data for the non-overlapping layer image 202(1).

[0049] The layer mixer circuit 118 then mixes the intermediate pre-mixed image data stream 400 with the background layer image data stream 402 into a display data stream 404 by mixing each pixel of the intermediate pre-mixed image data stream 400 corresponding to one of the non-overlapping layer images 202(0) to 202(3) with the corresponding pixel of the background layer image 200. In some aspects, each of the non-overlapping layer images 202(0) to 202(3) may be associated with different alpha mode data (not shown) and / or different alpha value data (not shown), which is used by the layer mixer circuit 118 when mixing each pixel of the intermediate pre-mixed image data stream 400 corresponding to one of the non-overlapping layer images 202(0) to 202(3) with the corresponding pixel of the background layer image 200. In some aspects, the alpha mode data and / or alpha value data may be stored in software-configurable read-write registers provided for each mixing stage, which will be discussed in more detail below. The layer mixer circuit 118 also outputs the corresponding pixel of the background layer image 200 to the display data stream 404 for each mixing bypass pixel of the intermediate pre-mixed image data stream 400.

[0050] Some aspects of the layer mixer circuit 118 may provide that the non-overlapping layer images 202(0) to 202(3) within the intermediate pre-mixed image data stream 400 may each be processed within a separate mixing stage of a plurality of mixing stages, as discussed in more detail below for Figure 7 For example, in some such aspects, the background layer image data stream 402 and the intermediate pre-mixed image data stream 400 may be mixed by the layer mixer circuit 118 in a first mixing stage. The resulting display data stream 404 may then be used as the background layer image data stream to be combined with another intermediate pre-mixed image data stream from another memory access pipeline circuit in a second mixing stage, where the display data stream from the second mixing stage is transmitted to the display device 106 for display. This functionality may enable, for example, the generation of a final display data stream using multiple memory access pipeline circuits that support the extraction of multiple non-overlapping layer images.

[0051] To support the functionality for providing mixing stages, in some aspects, the layer mixer circuit 118 provides a plurality of layer mixer configuration queues (labeled "layer mixer configuration queue" in Figure 4 ), 420(0) to 420(L), each of which includes a plurality of layer mixer configuration queue entries (labeled "entry" in Figure 4 ), 422(0) to 422(M), 424(0) to 424(M). Some aspects may provide that the number of layer mixer configuration queues 420(0) to 420(L) is the same as Figure 1The number of memory access pipeline circuits 108(0) to 108(M) is the same, such that each memory access pipeline circuit 108(0) to 108(M) that supports fetching multiple non-overlapping layer images is associated with one of the layer mixer configuration queues 420(0) to 420(L). In some aspects, there may be fewer layer mixer configuration queues 420(0) to 420(L) than memory access pipeline circuits 108(0) to 108(M). In such aspects, each layer mixer configuration queue 420(0) to 420(L) is associated with a corresponding tag 426(0) to 426(L), which can be assigned to one of the memory access pipeline circuits 108(0) to 108(M) to indicate the configuration data stored therein that will be accessed when processing data from the memory access pipeline circuits 108(0) to 108(M). In this way, the layer mixer configuration queues 420(0) to 420(L) can be reassigned to different ones of the memory access pipeline circuits 108(0) to 108(M), which in turn enables the memory access pipeline circuits 108(0) to 108(M) to transfer image data to different mixing levels.

[0052] The layer mixer configuration queues 420(0) to 420(L) can be filled, for example, by a software process such as a driver process using layer mixer configuration registers (labeled "layer mixer configuration registers" in Figure 4 ). The exemplary layer mixer configuration registers 428(0) to 428(F) according to some aspects may include the registers described in Table 2 below:

[0053]

[0054] Table 2

[0055] When the layer mixer circuit 118 receives an intermediate pre-mixed data stream from a memory access pipeline circuit (such as memory access pipeline circuit 108(1)) or an end-of-line (EOL) indication when bypass_Y is detected, the layer mixer circuit 118 obtains a memory access pipeline identifier (not shown) and a mixing level indication (not shown) from the layer mixer configuration queue 420(0) to 420(L) identified by the tag associated with the memory access pipeline circuit 108(1) (e.g., by popping the top layer mixer configuration queue entry 422(0) from the layer mixer configuration queue 420(0)). The layer mixer circuit 118 then mixes the intermediate pre-mixed image data stream (e.g., intermediate pre-mixed image data stream 400) and the background layer image data stream (e.g., background layer image data stream 402) at the appropriate mixing level based on the mixing level indication. Examples of using the mixing level in this way are discussed in more detail below for Figure 7 an example.

[0056] Figure 5 The above for Figure 4 is shown in the exemplary results of the operations described. In Figure 5 it is shown that the background layer image 200 extracted and processed by the memory access pipeline circuit 108(0) of Figure 1 and Figure 4 . As seen in Figure 5 , the non-overlapping layer images 202(0) to 202(3) have been combined into an intermediate pre-mixed image 500, where the black pixel areas are used to represent bypass pixels for pixels that do not correspond to any of the non-overlapping layer images 202(0) to 202(3). The layer mixer circuit 118 then mixes the background layer image 200 received as the background layer image data stream 402 of Figure 4 and the intermediate pre-mixed image 500 received as the intermediate pre-mixed image data stream 400 of Figure 4 from the memory access pipeline circuit 108(1) of Figure 1 and Figure 4 into a final mixed image 502, which is transmitted as the display data stream 404 of Figure 4 to the display device 106 of Figure 1 and Figure 4 . In the example of Figure 4 and Figure 5 , the generation of the final mixed image 502 requires only two (2) memory access pipeline circuits, rather than the five (5) memory access pipeline circuits required in the example of Figure 2 .

[0057] Figure 6 shows a processing timeline 600, which illustrates the activities of the memory access pipeline circuits 108(0) and 108(1) and the layer mixer circuit 118 during one display screen refresh cycle for the operations described above for Figure 4 . In Figure 4 , the annotation "VSYNC" indicates the start of vertical synchronization, while the annotations "VBLANK" and "BLANKING" indicate the time periods during which image data is not sent by the layer mixer circuit 118 to the display device 106. Figure 6 The annotation "prefill" in Figure 6 indicates the time periods during which each of the memory access pipeline circuits 108(0) and 108(1) is extracting and filling the corresponding buffers 112(0) and 112(1), while the annotation "idle" indicates the time periods during which each of the memory access pipeline circuits 108(0) and 108(1) is waiting to send the image data stream to the layer mixer circuit 118. Finally, in Figure 6Among them, the annotation "active" indicates the time period during which each of the memory access pipeline circuits 108(0) and 108(1) is actively processing the image data stream and sending it to the layer mixer circuit 118, and the annotation "mixed active data" indicates the time period during which the layer mixer circuit 118 is mixing the image data stream and sending the display data stream to the display device 106.

[0058] As Figure 6 As can be seen, during the entire time that the layer mixer circuit 118 is mixing the image data stream and sending the display data stream to the display device 106, the memory access pipeline circuit 108(0) that is processing and sending the background layer image data stream for the background layer image 200 is active. In addition, the memory access pipeline circuit 108(0) that extracts and pre-mixes the non-overlapping layer images 202(0) to 202(3) also accounts for most of the total time required to generate the final display data stream.

[0059] As described above for Figure 4 discussed, the layer mixer circuit 118 can employ multiple mixing stages to mix the images received from multiple memory access pipeline circuits. To illustrate such use of multiple mixing stages within the layer mixer circuit 118, Figure 7 is provided. As Figure 7 As can be seen, three (3) memory access pipeline circuits 108(0) to 108(2) are providing image data that will be processed using four (4) mixing stages 700(0) to 700(3). In this example, the memory access pipeline circuit 108(0) provides the background layer image data stream 702, and the memory access pipeline circuit 108(1) provides the first intermediate pre-mixed data stream 704. The layer mixer circuit 118 processes the background layer image data stream 702 and the first intermediate pre-mixed data stream 704 into the display data stream 706, which is then used as the background layer image data stream 706 entering the next mixing stage 700(1). For the mixing stage 700(1), the memory access pipeline circuit 108(1) provides the second intermediate pre-mixed data stream 708, and the layer mixer circuit 118 mixes the second intermediate pre-mixed data stream with the background layer image data stream 706 into the display data stream 710. The display data stream 710 is then used as the background layer image data stream 710 entering the mixing stage 700(2).

[0060] The memory access pipeline circuit 108(2) then provides the first intermediate pre-mixed data stream 712 to the mixing stage 700(2), where the layer mixer circuit 118 mixes the first intermediate pre-mixed data stream with the background layer image data stream 710 to generate the display data stream 714. The display data stream 714 is then provided as the background layer image data stream 714 to the final mixing stage 700(3). The memory access pipeline circuit 108(2) provides the second intermediate pre-mixed data stream 716 to the final mixing stage 700(3), where the second intermediate pre-mixed data stream is mixed with the background layer image data stream 714 to form the display data stream 718. The display data stream 718 is then output to the display device 106 for display.

[0061] For illustration Figure 1 and Figure 4 the display processing unit 104 for exemplary operations of efficiently processing multiple non-overlapping layer images, Figures 8A to 8C a flowchart illustrating exemplary operation 800 is provided. For clarity, reference is made to Figures 8A to 8C when describing Figure 1 、 Figure 2 as well as Figures 4 to 6 the elements of. In some aspects, exemplary operation 800 begins in Figure 8A a first memory access pipeline circuit of a display processing unit (such as Figure 1 and Figure 4 the display processing unit 104) for each non-overlapping layer image of multiple non-overlapping layer images (e.g., Figure 1 and Figure 4 the memory access pipeline circuit 108(1)) from multiple image configuration registers (e.g., Figure 2 the image configuration registers 408(0) to 408(C) of) the image configuration data (e.g., Figure 4 the image configuration data 406 of) is received into an image configuration queue (such as Figure 4 the image configuration queue 412(0) of) (block 802). In some aspects, the memory access pipeline circuit 108(1) may calculate a set of position coordinates (e.g., Figure 4 the set of position coordinates 414 of) and dimensions (e.g., Figure 5 the intermediate pre-mixed image 500 of) of an intermediate pre-mixed image (such as Figure 4 based on the image configuration data 406 for the multiple non-overlapping layer images 202(0) to 202(3). Figure 4dimensions 416) (box 804). In such aspects, the memory access pipeline circuit 108(1) may then send the set of position coordinates 414 and dimensions 416 of the intermediate pre-mixed image 500 to a layer mixer circuit of the display processing unit 104 (e.g., Figure 1 and Figure 4 the layer mixer circuit 118) (box 806). Exemplary operation 800 then continues at Figure 8B box 808.

[0062] Now referring to Figure 8B , a series of operations (box 808) are performed for each of the plurality of non-overlapping layer images 202(0) to 202(3). The memory access pipeline circuit 108(1) obtains image configuration data 406 for the non-overlapping layer image 202(0) (box 810). In some aspects, the operation of box 810 for obtaining the image configuration data 406 may include the memory access pipeline circuit 108(1) obtaining the image configuration data 406 from the top entry of the image configuration queue 412(0) (e.g., Figure 4 the image configuration queue entry 410(0)) (box 812). The memory access pipeline circuit 108(1) then extracts the non-overlapping layer image 202(0) from the image data storage device (e.g., Figure 1 and Figure 4 the image data storage device 102) based on the image configuration data 406 (box 814).

[0063] The memory access pipeline circuit 108(1) then outputs each pixel of the non-overlapping layer image 202(0) as part of the intermediate pre-mixed image 500 to an intermediate pre-mixed image data stream (e.g., Figure 4 the intermediate pre-mixed image data stream 400) (box 816). According to some aspects, the operation of box 816 for outputting each pixel of the non-overlapping layer image 202(0) as part of the intermediate pre-mixed image 500 to the intermediate pre-mixed image data stream 400 may include outputting blend bypass pixels for each pixel of the intermediate pre-mixed image 500 that does not correspond to a pixel of the non-overlapping layer image 202(0) (box 818). Exemplary operation 800 then continues at Figure 8C box 820.

[0064] Now turning to Figure 8C , some aspects may provide that the layer mixer circuit 118 receives the intermediate pre-mixed image data stream 400 from the memory access pipeline circuit 108(1) (box 820). The layer mixer circuit 118 may also receive from a second memory access pipeline circuit of the display processing unit 104 (such as Figure 1 and Figure 4The memory access pipeline circuit 108(0) receives the background layer image data stream (e.g., Figure 4 of the background layer image data stream 402) (block 822). The layer mixer circuit 118 then mixes the intermediate pre-mixed image data stream 400 and the background layer image data stream 402 including the background layer image (e.g., Figure 2 and Figure 5 of the background layer image 200) as the display data stream (e.g., Figure 4 of the display data stream 404) (block 824). In some aspects, the operation of block 824 for mixing the intermediate pre-mixed image data stream 400 and the background layer image data stream 402 may be based on the set of position coordinates 414 and dimensions 416 of the intermediate pre-mixed image 500 (block 826). Some aspects may provide that the operation of block 824 for mixing the intermediate pre-mixed image data stream 400 and the background layer image data stream 402 may include the layer mixer circuit 118 outputting the mixture of each pixel of the intermediate pre-mixed image data stream 400 corresponding to the non-overlapping layer image 202(0) among the multiple non-overlapping layer images 202(0) to 202(3) with the corresponding pixel of the background layer image 200 to the display data stream 404 (block 828). According to some aspects, the operation of block 824 for mixing the intermediate pre-mixed image data stream 400 and the background layer image data stream 402 may include the layer mixer circuit 118 outputting the corresponding pixel of the background layer image 200 to the display data stream 404 for each mixed bypass pixel of the intermediate pre-mixed image data stream 400 (block 830). The layer mixer circuit 118 then outputs the display data stream 404 to the display device 106 (block 832).

[0065] Figure 9A and Figure 9B provides a flowchart of an exemplary operation 900 performed by the Figure 1 and Figure 4 layer mixer circuit for mixing images from multiple memory access pipeline circuits using mixing levels. For clarity, reference is made to the Figure 9A and Figure 9B elements of Figure 1 , Figure 4 and Figure 7 when describing Figure 9A . In Figure 4Multiple layer mixer configuration queues 420(0)-420(L), in the layer mixer configuration queue 420(0) (box 902). The layer mixer circuit 118 assigns a tag corresponding to the layer mixer configuration queue 420(0) (e.g., Figure 4 tag 426(0)) to the memory access pipeline circuit 108(1) based on the memory access pipeline identifier (box 904).

[0066] Subsequently, when the layer mixer circuit 118 receives the intermediate pre-mixed image data stream 400 from the memory access pipeline circuit 108(1), the layer mixer circuit 118 obtains the memory access pipeline identifier and the mixing stage indication from the top entry of the layer mixer configuration queue 420(0) (e.g., Figure 4 layer mixer configuration queue entry 422(0)) based on the tag 426(0) (box 906). The layer mixer circuit 118 then mixes the intermediate pre-mixed image data stream 400 with the background layer image data stream 402 as the display data stream 404 within a mixing stage (e.g., Figure 7 mixing stage 700(1) of the multiple mixing stages 700(0) to 700(3)), where each mixing stage corresponds to a memory access pipeline circuit among the multiple memory access pipeline circuits 108(0) to 108(M) (box 908). In some aspects, the operation of box 908 for mixing the intermediate pre-mixed image data stream 400 and the background layer image data stream 402 as the display data stream 404 within the mixing stage 700(1) is based on the mixing stage indication (box 910). It will be understood that in some aspects, the operations of boxes 908 and 910 may correspond to Figure 8C the operation of box 824. The exemplary operation 900 then continues at Figure 9B box 912.

[0067] Now referring to Figure 9B , the exemplary operation 900 continues, where the layer mixer circuit 118 outputs the display data stream (e.g., Figure 7 display data stream 706) of each mixing stage before the final mixing stage (e.g., Figure 7 mixing stage 700(3)) among the multiple mixing stages 700(0) to 700(3) as the background layer image data stream (e.g., Figure 7 background layer image data stream 702) to the consecutive mixing stage (e.g., Figure 7 mixing stage 700(1)) (box 912). The layer mixer circuit 118 then outputs the display data stream of the final mixing stage 700(3) among the multiple mixing stages 700(0) to 700(3) (e.g., Figure 7The display data stream 718) is output to the display device 106 (block 914). It will be appreciated that, in some aspects, the operations of blocks 912 and 914 may correspond to Figure 8C the operations of block 832.

[0068] Efficiently processing multiple non-overlapping layer images according to aspects disclosed herein can be provided in or integrated into any processor-based device. Non-limiting examples include: set-top boxes, entertainment units, navigation devices, communication devices, fixed-location data units, mobile-location data units, Global Positioning System (GPS) devices, mobile phones, cellular phones, smart phones, Session Initiation Protocol (SIP) phones, tablet computers, phablets, servers, computers, portable computers, mobile computing devices, laptop computers, wearable computing devices (e.g., smart watches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, motor vehicles, vehicle components, avionics systems, drones, and multi-rotor aircraft.

[0069] In this regard, Figure 10 FIG. illustrates an example of a processor-based device 1000, which may include Figure 1 the illustrated display processing unit 104. In this example, the processor-based device 1000 includes a processor 1002, which includes one or more central processing units (labeled "CPU" in Figure 10 ), which may also be referred to as CPU cores or processor cores. The processor 1002 may have a cache memory 1006 coupled to the processor 1002 for fast access to temporarily stored data. The processor 1002 is coupled to a system bus 1008 and may couple master and slave devices included in the processor-based device 1000 to each other. As is well known, the processor 1002 communicates with these other devices by exchanging address, control, and data information on the system bus 1008. For example, the processor 1002 may convey bus transaction requests to a memory controller 1010, which is an example of a slave device. Although not illustrated in Figure 10 , multiple system buses 1008 may be provided, where each system bus 1008 constitutes a different architecture.

[0070] Other master and slave devices may be connected to the system bus 1008. As Figure 10Illustrated by way of example, these devices may include a memory system 1012 (which includes a memory controller 1010 and a memory array 1014), one or more input devices 1016, one or more output devices 1018, one or more network interface devices 1020, and one or more display controllers 1022. The input devices 1016 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. The output devices 1018 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. The network interface device 1020 may be any device configured to permit data exchange to and from a network 1024. The network 1024 may be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), Bluetooth TM networks, and the Internet. The network interface device 1020 may be configured to support any type of communication protocol desired.

[0071] The processor 1002 may also be configured to access the display controller 1022 via the system bus 1008 to control the information transmitted to one or more displays 1026. The display controller 1022 transmits the information to be displayed to the displays 1026 via one or more video processors 1028, and the one or more video processors process the information to be displayed into a format suitable for the displays 1026. The displays 1026 may include any type of display, including but not limited to cathode ray tubes (CRTs), liquid crystal displays (LCDs), plasma displays, etc.

[0072] Those skilled in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein may be implemented as electronic hardware, instructions stored in memory or other computer-readable medium and executed by a processor or other processing device, or combinations of both. The memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate such interchangeability, the functionality of the various illustrative components, blocks, modules, circuits, and steps has been described generally above. How such functionality is implemented depends on the particular application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each particular application, but such specific implementation decisions should not be construed as causing a departure from the scope of the present disclosure.

[0073] The various illustrative logical blocks, modules, and circuits described in connection with the aspects disclosed herein can be implemented or performed with a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic components, discrete hardware components, or any combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors cooperating with a DSP core, or any other such configuration).

[0074] Aspects disclosed herein may be embodied in hardware and instructions stored in hardware, and may reside in, for example, random access memory (RAM), flash memory, read only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer readable medium known in the art. The exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. In the alternative, the processor and the storage medium may reside as discrete components in a remote station, a base station, or a server.

[0075] It is also noted that the operational steps described in any of the exemplary aspects herein are described for purposes of providing examples and discussion. The described operations may be performed in numerous different orders other than the illustrated order. Further, the operations described in a single operational step may actually be performed in multiple different steps. Additionally, one or more of the operational steps discussed in the exemplary aspects may be combined. It will be understood that, as will be apparent to those of ordinary skill in the art, numerous different modifications may be made to the operational steps illustrated in the flowcharts. Those of ordinary skill in the art will also understand that any of a variety of different technologies and processes may be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof.

[0076] The foregoing description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0077] Specific embodiments are described in the following numbered clauses:

[0078] 1. A display processing unit, the display processing unit comprising:

[0079] A plurality of memory access pipeline circuits;

[0080] A layer mixer circuit;

[0081] A first memory access pipeline circuit among the plurality of memory access pipeline circuits is configured to, for each non-overlapping layer image among a plurality of non-overlapping layer images:

[0082] Obtain image configuration data for the non-overlapping layer image;

[0083] Extract the non-overlapping layer image from an image data storage device based on the image configuration data; and output each pixel of the non-overlapping layer image as part of an intermediate pre-mixed image to an intermediate pre-mixed image data stream based on the image configuration data; and

[0084] The layer mixer circuit is configured to:

[0085] Mix the intermediate pre-mixed image data stream and a background layer image data stream including a background layer image as a display data stream; and

[0086] Output the display data stream to a display device.

[0087] 2. The display processing unit according to clause 1, wherein the layer mixer circuit is further configured to:

[0088] Receive the intermediate pre-mixed image data stream from the first memory access pipeline circuit; and receive the background layer image data stream from a second memory access pipeline circuit among the plurality of memory access pipeline circuits.

[0089] 3. The display processing unit according to any one of clauses 1 to 2, wherein the image configuration data for each non-overlapping layer image among the plurality of non-overlapping layer images includes one or more of the following: source image size, output image size, a set of source image position coordinates, a set of output image position coordinates, source address, stride value, image format, and unpacking mode value.

[0090] 4. The display processing unit according to any one of clauses 1 to 3, wherein:

[0091] The first memory access pipeline circuit further includes an image configuration queue;

[0092] The first memory access pipeline circuit is further configured to: for each non-overlapping layer image among the plurality of non-overlapping layer images, receive the image configuration data from a plurality of image configuration registers into the image configuration queue; and

[0093] The first memory access pipeline circuit is configured to: for each non-overlapping layer image among the plurality of non-overlapping layer images, obtain the image configuration data from the top entry of the image configuration queue.

[0094] 5. The display processing unit according to clause 4, wherein:

[0095] The first memory access pipeline circuit is further configured to:

[0096] Calculate a set of position coordinates and dimensions of the intermediate pre-mixed image based on the image configuration data for the plurality of non-overlapping layer images; and

[0097] Send the set of position coordinates and the dimensions of the intermediate pre-mixed image to the layer mixer circuit; and

[0098] The layer mixer circuit is configured to mix the intermediate pre-mixed image data stream and the background layer image data stream as the display data stream based on the set of position coordinates and the dimensions of the intermediate pre-mixed image.

[0099] 6. The display processing unit according to any one of clauses 4 to 5, wherein:

[0100] The first memory access pipeline circuit includes a first optional image configuration queue and a second optional image configuration queue;

[0101] The first memory access pipeline circuit is further configured to: for each non-overlapping layer image among the plurality of non-overlapping layer images, receive the image configuration data from a plurality of image configuration registers into the first optional image configuration queue;

[0102] The first memory access pipeline circuit is configured to: for each non-overlapping layer image among the plurality of non-overlapping layer images, obtain the image configuration data from the top entry of the first optional image configuration queue; and

[0103] The first memory access pipeline circuit is further configured to: in parallel with obtaining the image configuration data from the top entry of the first optional image configuration queue, for each of the next plurality of non-overlapping layer images, receive next image configuration data from the plurality of image configuration registers into the second optional image configuration queue.

[0104] 7. The display processing unit according to any one of clauses 1 to 6, wherein the layer mixer circuit is configured to mix the intermediate pre-mixed image data stream and the background layer image data stream as the display data stream by being configured to output, for each pixel of the intermediate pre-mixed image data stream corresponding to a non-overlapping layer image among the plurality of non-overlapping layer images, a mixture of the pixel and the corresponding pixel of the background layer image to the display data stream.

[0105] 8. The display processing unit according to clause 7, wherein:

[0106] The first memory access pipeline circuit is further configured to: for each of the plurality of non-overlapping layer images, output a mixed bypass pixel to the intermediate pre-mixed image data stream for each pixel of the intermediate pre-mixed image that does not correspond to the non-overlapping layer image; and

[0107] The layer mixer circuit is configured to mix the intermediate pre-mixed image data stream and the background layer image data stream as the display data stream by being configured to output, for each mixed bypass pixel of the intermediate pre-mixed image data stream, the corresponding pixel of the background layer image to the display data stream.

[0108] 9. The display processing unit according to clause 8, wherein the mixed bypass pixels include pixels having a pre-specified color value.

[0109] 10. The display processing unit according to any one of clauses 2 to 9, wherein:

[0110] The layer mixer circuit is configured to mix the intermediate pre-mixed image data stream and the background layer image data stream as the display data stream by being configured to perform the following operations:

[0111] Mix the intermediate pre-mixed image data stream and the background layer image data stream as the display data stream at a mixing level within a plurality of mixing levels, wherein each mixing level corresponds to a memory access pipeline circuit among the plurality of memory access pipeline circuits; and

[0112] outputting the display data stream of each mixing stage before the final mixing stage among the plurality of mixing stages as the background layer image data stream to a subsequent mixing stage; and

[0113] The layer mixer circuit is configured to output the display data stream to the display device by being configured to output the display data stream of the final mixing stage of the plurality of mixing stages to the display device.

[0114] 11. A display processing unit according to clause 10, wherein:

[0115] The layer mixer circuit also includes a plurality of layer mixer configuration queues;

[0116] The layer mixer circuit is further configured as:

[0117] receiving a memory access pipeline identifier and a mixing stage indication for the first memory access pipeline circuit into a layer mixer configuration queue of the plurality of layer mixer configuration queues;

[0118] assigning a tag corresponding to the layer mixer configuration queue to the first memory access pipeline circuit based on the memory access pipeline identifier; and

[0119] in response to receiving the intermediate pre-mixed image data stream from the first memory access pipeline circuit, obtaining the memory access pipeline identifier and the blending stage indication from a top entry of the layer mixer configuration queue based on the tag; and

[0120] The layer mixer circuit is configured to adjust the mixing among the plurality of mixing stages based on the mixing level indication.

[0121] The intermediate premixed image data stream and the background layer image data stream are mixed as the display data stream in the display processing unit. 12. A display processing unit according to any one of clauses 1 to 11, wherein the display processing unit is integrated into a display processing unit selected from the following items:

[0122] Among the devices of the group consisting of: set-top box; entertainment unit; navigation device; communication device; fixed position data unit; mobile position data unit; Global Positioning System (GPS) device; mobile phone; cellular phone; smart phone; Session Initiation Protocol (SIP) phone; tablet computer; phablet; server; computer; portable computer; mobile computing device; wearable computing device; desktop computer; personal digital assistant (PDA); monitor; computer monitor; television; tuner; radio; satellite radio; music player; digital music player; portable music player; digital video player; video player; digital video disc (DVD) player; portable digital video player; automobile; vehicle component; avionics system; drone; and multi-rotor aircraft.

[0123] 13. A display processing unit, the display processing unit comprising:

[0124] Components for performing the following operations for each of a plurality of non-overlapping layer images:

[0125] Obtain image configuration data for the non-overlapping layer image;

[0126] Extract the non-overlapping layer image from an image data storage device based on the image configuration data; and output each pixel of the non-overlapping layer image as part of an intermediate pre-mixed image to an intermediate pre-mixed image data stream based on the image configuration data;

[0127] Components for mixing the intermediate pre-mixed image data stream and a background layer image data stream including a background layer image as a display data stream; and

[0128] Components for outputting the display data stream to a display device.

[0129] 14. A method for efficiently processing a plurality of non-overlapping layer images, the method comprising:

[0130] Perform the following operations for each of a plurality of non-overlapping layer images:

[0131] Obtain, by a first memory access pipeline circuit among a plurality of memory access pipeline circuits of a display processing unit, image configuration data for the non-overlapping layer image;

[0132] Extract, by the first memory access pipeline circuit, the non-overlapping layer image from an image data storage device based on the image configuration data; and

[0133] Each pixel of the non-overlapping layer image is output as part of an intermediate pre-blended image to an intermediate pre-blended image data stream by the first memory access pipeline circuit based on the image configuration data;

[0134] The intermediate pre-blended image data stream and the background layer image data stream are mixed by the layer mixer circuit of the display processing unit as a display data stream; and

[0135] The display data stream is output by the layer mixer circuit to a display device.

[0136] 15. The method according to clause 14, the method further comprising:

[0137] The intermediate pre-blended image data stream is received by the layer mixer circuit from the first memory access pipeline circuit; and

[0138] The background layer image data stream including the background layer image is received by the layer mixer circuit from a second memory access pipeline circuit among the plurality of memory access pipeline circuits.

[0139] 16. The method according to any one of clauses 14 to 15, wherein the image configuration data for each non-overlapping layer image among the plurality of non-overlapping layer images includes one or more of the following: source image size, output image size, a set of source image position coordinates, a set of output image position coordinates, source address, stride value, image format, and unpacking mode value.

[0140] 17. The method according to any one of clauses 14 to 16, the method further comprising: for each non-overlapping layer image among the plurality of non-overlapping layer images, the first memory access pipeline circuit receives the image configuration data from a plurality of image configuration registers into an image configuration queue of the first memory access pipeline circuit;

[0141] wherein, for each non-overlapping layer image among the plurality of non-overlapping layer images, obtaining the image configuration data for the non-overlapping layer image includes obtaining the image configuration data from the top entry of the image configuration queue.

[0142] 18. The method according to clause 17, the method further comprising:

[0143] The first memory access pipeline circuit calculates a set of position coordinates and a size of the intermediate pre-blended image based on the image configuration data for the plurality of non-overlapping layer images; and

[0144] The first memory access pipeline circuit sends the set of position coordinates and the size of the intermediate pre-blended image to the layer mixer circuit;

[0145] Wherein, the intermediate pre-mixed image data stream and the background layer image data stream are mixed as the display data stream based on the set of position coordinates and the size of the intermediate pre-mixed image.

[0146] 19. The method according to any one of clauses 17 to 18, the method further comprising: for each non-overlapping layer image among the plurality of non-overlapping layer images, receiving, by the first memory access pipeline circuit, the image configuration data from a plurality of image configuration registers into a first selectable image configuration queue;

[0147] Wherein:

[0148] For each non-overlapping layer image among the plurality of non-overlapping layer images, obtaining the image configuration data includes obtaining the image configuration data from the top entry of the first selectable image configuration queue; and

[0149] The method further comprising: in parallel with obtaining the image configuration data from the top entry of the first selectable image configuration queue, for each non-overlapping layer image among the next plurality of non-overlapping layer images, receiving, by the first memory access pipeline circuit, next image configuration data from the plurality of image configuration registers into a second selectable image configuration queue.

[0150] 20. The method according to any one of clauses 15 to 19, wherein mixing the intermediate pre-mixed image data stream and the background layer image data stream as the display data stream includes: for each pixel of the intermediate pre-mixed image data stream corresponding to a non-overlapping layer image among the plurality of non-overlapping layer images, outputting, by the layer mixer circuit, a mixture of the pixel and the corresponding pixel of the background layer image to the display data stream.

[0151] 21. The method according to any one of clauses 15 to 20, the method further comprising: for each non-overlapping layer image among the plurality of non-overlapping layer images, outputting, by the first memory access pipeline circuit, mixed bypass pixels to the intermediate pre-mixed image data stream for each pixel of the intermediate pre-mixed image that does not correspond to the non-overlapping layer image;

[0152] Wherein mixing the intermediate pre-mixed image data stream and the background layer image data stream as the display data stream includes: for each mixed bypass pixel of the intermediate pre-mixed image data stream, outputting, by the layer mixer circuit, the corresponding pixel of the background layer image to the display data stream.

[0153] 22. The method according to clause 21, wherein the mixed bypass pixels include pixels having a pre-specified color value.

[0154] 23. The method according to any one of clauses 15 to 22, wherein:

[0155] Mixing the intermediate pre-mixed image data stream and the background layer image data stream as the display data stream includes:

[0156] Mixing, by the layer mixer circuit, the intermediate pre-mixed image data stream and the background layer image data stream as the display data stream within a mixing stage among a plurality of mixing stages, where each mixing stage corresponds to a memory access pipeline circuit among the plurality of memory access pipeline circuits; and

[0157] Outputting, by the layer mixer circuit, the display data stream of each mixing stage before the final mixing stage among the plurality of mixing stages as the background layer image data stream to a subsequent mixing stage; and

[0158] Outputting the display data stream to the display device includes: outputting, by the layer mixer circuit, the display data stream of the final mixing stage among the plurality of mixing stages to the display device.

[0159] 24. The method according to clause 23, the method further comprising:

[0160] Receiving, by the layer mixer circuit, a memory access pipeline identifier and a mixing stage indication for the first memory access pipeline circuit in a layer mixer configuration queue among a plurality of layer mixer configuration queues;

[0161] Assigning, by the layer mixer circuit, a tag corresponding to the layer mixer configuration queue to the first memory access pipeline circuit based on the memory access pipeline identifier; and

[0162] In response to receiving the intermediate pre-mixed image data stream from the first memory access pipeline circuit, obtaining, by the layer mixer circuit, the memory access pipeline identifier and the mixing stage indication from the top entry of the layer mixer configuration queue based on the tag;

[0163] wherein mixing the intermediate pre-mixed image data stream and the background layer image data stream as the display data stream within the mixing stage among the plurality of mixing stages is based on the mixing stage indication.

Claims

1. A display processing unit, the display processing unit comprising: A plurality of memory access pipeline circuits; A layer mixer circuit; The first memory access pipeline circuit among the plurality of memory access pipeline circuits is configured to, for each non-overlapping layer image among a plurality of non-overlapping layer images: Obtain image configuration data for the non-overlapping layer image; Extract the non-overlapping layer image from an image data storage device based on the image configuration data; And Output each pixel of the non-overlapping layer image as part of an intermediate pre-mixed image to an intermediate pre-mixed image data stream based on the image configuration data; and The layer mixer circuit is configured to: Mix the intermediate pre-mixed image data stream and a background layer image data stream including a background layer image as a display data stream; and Output the display data stream to a display device.

2. The display processing unit according to claim 1, wherein the layer mixer circuit is further configured to: Receive the intermediate pre-mixed image data stream from the first memory access pipeline circuit; and Receive the background layer image data stream from a second memory access pipeline circuit among the plurality of memory access pipeline circuits.

3. The display processing unit according to claim 1, wherein the image configuration data for each non-overlapping layer image among the plurality of non-overlapping layer images includes one or more of the following: source image size, output image size, a set of source image position coordinates, a set of output image position coordinates, source address, stride value, image format, and unpacking mode value.

4. The display processing unit according to claim 1, wherein: The first memory access pipeline circuit further includes an image configuration queue; The first memory access pipeline circuit is further configured to: for each non-overlapping layer image among the plurality of non-overlapping layer images, receive the image configuration data from a plurality of image configuration registers into the image configuration queue; and The first memory access pipeline circuit is configured to: for each non-overlapping layer image among the plurality of non-overlapping layer images, obtain the image configuration data from the top entry of the image configuration queue.

5. The display processing unit according to claim 4, wherein: The first memory access pipeline circuit is further configured to: Calculate a set of position coordinates and a size of the intermediate pre-mixed image based on the image configuration data for the plurality of non-overlapping layer images; and Send the set of position coordinates and the size of the intermediate pre-mixed image to the layer mixer circuit; And The layer mixer circuit is configured to mix the intermediate pre-mixed image data stream and the background layer image data stream as the display data stream based on the set of position coordinates and the size of the intermediate pre-mixed image.

6. The display processing unit according to claim 4, wherein: The first memory access pipeline circuit includes a first optional image configuration queue and a second optional image configuration queue; The first memory access pipeline circuit is further configured to: for each of the plurality of non-overlapping layer images, receive the image configuration data from a plurality of image configuration registers into the first optional image configuration queue; The first memory access pipeline circuit is configured to: for each of the plurality of non-overlapping layer images, obtain the image configuration data from the top entry of the first optional image configuration queue; and The first memory access pipeline circuit is further configured to: in parallel with obtaining the image configuration data from the top entry of the first optional image configuration queue, for each of the next plurality of non-overlapping layer images, receive next image configuration data from the plurality of image configuration registers into the second optional image configuration queue.

7. The display processing unit according to claim 1, wherein the layer mixer circuit is configured to mix the intermediate pre-mixed image data stream and the background layer image data stream as the display data stream by being configured to output, for each pixel of the intermediate pre-mixed image data stream corresponding to a non-overlapping layer image of the plurality of non-overlapping layer images, a mixture of the pixel and a corresponding pixel of the background layer image to the display data stream.

8. The display processing unit according to claim 7, wherein: The first memory access pipeline circuit is further configured to: for each of the plurality of non-overlapping layer images, output a mixed bypass pixel to the intermediate pre-mixed image data stream for each pixel of the intermediate pre-mixed image that does not correspond to a pixel of the non-overlapping layer image; and The layer mixer circuit is configured to mix the intermediate pre-mixed image data stream and the background layer image data stream as the display data stream by being configured to output, for each mixed bypass pixel of the intermediate pre-mixed image data stream, a corresponding pixel of the background layer image to the display data stream.

9. The display processing unit according to claim 8, wherein the mixed bypass pixels include pixels having a pre-specified color value.

10. The display processing unit according to claim 2, wherein: The layer mixer circuit is configured to mix the intermediate pre-mixed image data stream and the background layer image data stream as the display data stream by being configured to perform the following operations: Mix the intermediate pre-mixed image data stream and the background layer image data stream as the display data stream at a mixing level within a plurality of mixing levels, wherein each mixing level corresponds to a memory access pipeline circuit of the plurality of memory access pipeline circuits; And Output the display data stream of each mixing level before a final mixing level of the plurality of mixing levels as the background layer image data stream to a subsequent mixing level; and The layer mixer circuit is configured to output the display data stream to the display device by being configured to output the display data stream of the final mixing level of the plurality of mixing levels to the display device.

11. The display processing unit according to claim 10, wherein: The layer mixer circuit further includes a plurality of layer mixer configuration queues; The layer mixer circuit is further configured to: Receive the memory access pipeline identifier and the mixing level indication for the first memory access pipeline circuit into the layer mixer configuration queue in the plurality of layer mixer configuration queues; Assign a tag corresponding to the layer mixer configuration queue to the first memory access pipeline circuit based on the memory access pipeline identifier; And In response to receiving the intermediate pre-mixed image data stream from the first memory access pipeline circuit, obtain the memory access pipeline identifier and the mixing level indication from the top entry of the layer mixer configuration queue based on the tag; and The layer mixer circuit is configured to mix the intermediate pre-mixed image data stream and the background layer image data stream within the mixing level among the plurality of mixing levels as the display data stream based on the mixing level indication.

12. The display processing unit according to claim 1, wherein the display processing unit is integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communication device; a fixed position data unit; a mobile position data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet computer; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; an avionics system; a drone; and a multi-rotor aircraft.

13. A display processing unit, the display processing unit includes: Components for performing the following operations for each of a plurality of non-overlapping layer images: Obtain image configuration data for the non-overlapping layer image; Extract the non-overlapping layer image from an image data storage device based on the image configuration data; And Output each pixel of the non-overlapping layer image as part of an intermediate pre-mixed image to an intermediate pre-mixed image data stream based on the image configuration data; Components for mixing the intermediate pre-mixed image data stream and a background layer image data stream including a background layer image as a display data stream; And Components for outputting the display data stream to a display device.

14. A method for efficiently processing a plurality of non-overlapping layer images, the method includes: Performing the following operations for each of a plurality of non-overlapping layer images: Obtain, by a first memory access pipeline circuit among a plurality of memory access pipeline circuits of a display processing unit, image configuration data for the non-overlapping layer image; The first memory access pipeline circuit extracts the non-overlapping layer images from the image data storage device based on the image configuration data; and the first memory access pipeline circuit outputs each pixel of the non-overlapping layer images as part of an intermediate pre-blended image to an intermediate pre-blended image data stream based on the image configuration data; the layer mixer circuit of the display processing unit mixes the intermediate pre-blended image data stream and the background layer image data stream as a display data stream; and the layer mixer circuit outputs the display data stream to a display device.

15. The method according to claim 14, the method further comprising: the layer mixer circuit receiving the intermediate pre-blended image data stream from the first memory access pipeline circuit; and the layer mixer circuit receiving the background layer image data stream including the background layer image from a second memory access pipeline circuit among the plurality of memory access pipeline circuits.

16. The method according to claim 14, wherein the image configuration data for each non-overlapping layer image among the plurality of non-overlapping layer images includes one or more of the following: source image size, output image size, a set of source image position coordinates, a set of output image position coordinates, source address, stride value, image format, and unpacking mode value.

17. The method according to claim 14, the method further comprising: For each non-overlapping layer image among the plurality of non-overlapping layer images, the first memory access pipeline circuit receives the image configuration data from a plurality of image configuration registers into an image configuration queue of the first memory access pipeline circuit; wherein, for each non-overlapping layer image among the plurality of non-overlapping layer images, obtaining the image configuration data for the non-overlapping layer image includes obtaining the image configuration data from the top entry of the image configuration queue.

18. The method according to claim 17, the method further comprising: the first memory access pipeline circuit calculating a set of position coordinates and a size of the intermediate pre-blended image based on the image configuration data for the plurality of non-overlapping layer images; and the first memory access pipeline circuit sending the set of position coordinates and the size of the intermediate pre-blended image to the layer mixer circuit; wherein mixing the intermediate pre-blended image data stream and the background layer image data stream as the display data stream is based on the set of position coordinates and the size of the intermediate pre-blended image.

19. The method according to claim 17, the method further comprising: For each non-overlapping layer image among the plurality of non-overlapping layer images, the first memory access pipeline circuit receives the image configuration data from a plurality of image configuration registers into a first selectable image configuration queue; wherein: for each non-overlapping layer image among the plurality of non-overlapping layer images, obtaining the image configuration data includes obtaining the image configuration data from the top entry of the first selectable image configuration queue; and The method further includes: in parallel with obtaining the image configuration data from the top entry of the first optional image configuration queue, for each of the next plurality of non-overlapping layer images, receiving, by the first memory access pipeline circuit, next image configuration data from the plurality of image configuration registers into a second optional image configuration queue.

20. The method according to claim 15, wherein mixing the intermediate pre-mixed image data stream and the background layer image data stream as the display data stream comprises: For each pixel of the intermediate pre-mixed image data stream corresponding to a non-overlapping layer image among the plurality of non-overlapping layer images, output, by the layer mixer circuit, a mixture of the pixel and a corresponding pixel of the background layer image to the display data stream.

21. The method according to claim 15, the method further comprising: For each of the plurality of non-overlapping layer images, output, by the first memory access pipeline circuit, a mixed bypass pixel to the intermediate pre-mixed image data stream for each pixel of the intermediate pre-mixed image that does not correspond to the non-overlapping layer image; Wherein mixing the intermediate pre-mixed image data stream and the background layer image data stream as the display data stream includes: for each mixed bypass pixel of the intermediate pre-mixed image data stream, output, by the layer mixer circuit, the corresponding pixel of the background layer image to the display data stream.

22. The method according to claim 21, wherein the mixed bypass pixels include pixels having a pre-specified color value.

23. The method according to claim 15, wherein: Mixing the intermediate pre-mixed image data stream and the background layer image data stream as the display data stream includes: Mixing, by the layer mixer circuit, the intermediate pre-mixed image data stream and the background layer image data stream as the display data stream within a mixing stage among a plurality of mixing stages, wherein each mixing stage corresponds to a memory access pipeline circuit among the plurality of memory access pipeline circuits; and Outputting, by the layer mixer circuit, the display data stream of each mixing stage before the final mixing stage among the plurality of mixing stages as the background layer image data stream to a subsequent mixing stage; and Outputting the display data stream to the display device includes: outputting, by the layer mixer circuit, the display data stream of the final mixing stage among the plurality of mixing stages to the display device.

24. The method according to claim 23, the method further includes: Receiving, by the layer mixer circuit, a memory access pipeline identifier and a mixing stage indication for the first memory access pipeline circuit into a layer mixer configuration queue among a plurality of layer mixer configuration queues; Assigning, by the layer mixer circuit, a tag corresponding to the layer mixer configuration queue to the first memory access pipeline circuit based on the memory access pipeline identifier; and And In response to receiving the intermediate pre-mixed image data stream from the first memory access pipeline circuit, obtaining, by the layer mixer circuit, the memory access pipeline identifier and the mixing stage indication from the top entry of the layer mixer configuration queue based on the tag; Wherein, within the mixing stage among the plurality of mixing stages, the intermediate pre-mixed image data stream and the background layer image data stream are mixed as the display data stream based on the mixing stage indication.

Images